Commit | Line | Data |
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bdcd8170 KV |
1 | |
2 | /* | |
3 | * Copyright (c) 2011 Atheros Communications Inc. | |
1b2df407 | 4 | * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. |
bdcd8170 KV |
5 | * |
6 | * Permission to use, copy, modify, and/or distribute this software for any | |
7 | * purpose with or without fee is hereby granted, provided that the above | |
8 | * copyright notice and this permission notice appear in all copies. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
17 | */ | |
18 | ||
c6efe578 | 19 | #include <linux/moduleparam.h> |
f7830202 | 20 | #include <linux/errno.h> |
d6a434d6 | 21 | #include <linux/export.h> |
92ecbff4 | 22 | #include <linux/of.h> |
bdcd8170 | 23 | #include <linux/mmc/sdio_func.h> |
d6a434d6 | 24 | |
bdcd8170 KV |
25 | #include "core.h" |
26 | #include "cfg80211.h" | |
27 | #include "target.h" | |
28 | #include "debug.h" | |
29 | #include "hif-ops.h" | |
30 | ||
856f4b31 KV |
31 | static const struct ath6kl_hw hw_list[] = { |
32 | { | |
0d0192ba | 33 | .id = AR6003_HW_2_0_VERSION, |
293badf4 | 34 | .name = "ar6003 hw 2.0", |
856f4b31 KV |
35 | .dataset_patch_addr = 0x57e884, |
36 | .app_load_addr = 0x543180, | |
37 | .board_ext_data_addr = 0x57e500, | |
38 | .reserved_ram_size = 6912, | |
39586bf2 RH |
39 | .refclk_hz = 26000000, |
40 | .uarttx_pin = 8, | |
856f4b31 KV |
41 | |
42 | /* hw2.0 needs override address hardcoded */ | |
43 | .app_start_override_addr = 0x944C00, | |
d1a9421d | 44 | |
c0038972 KV |
45 | .fw = { |
46 | .dir = AR6003_HW_2_0_FW_DIR, | |
47 | .otp = AR6003_HW_2_0_OTP_FILE, | |
48 | .fw = AR6003_HW_2_0_FIRMWARE_FILE, | |
49 | .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE, | |
50 | .patch = AR6003_HW_2_0_PATCH_FILE, | |
c0038972 KV |
51 | }, |
52 | ||
d1a9421d KV |
53 | .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE, |
54 | .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE, | |
856f4b31 KV |
55 | }, |
56 | { | |
0d0192ba | 57 | .id = AR6003_HW_2_1_1_VERSION, |
293badf4 | 58 | .name = "ar6003 hw 2.1.1", |
856f4b31 KV |
59 | .dataset_patch_addr = 0x57ff74, |
60 | .app_load_addr = 0x1234, | |
61 | .board_ext_data_addr = 0x542330, | |
62 | .reserved_ram_size = 512, | |
39586bf2 RH |
63 | .refclk_hz = 26000000, |
64 | .uarttx_pin = 8, | |
cd23c1c9 | 65 | .testscript_addr = 0x57ef74, |
d1a9421d | 66 | |
c0038972 KV |
67 | .fw = { |
68 | .dir = AR6003_HW_2_1_1_FW_DIR, | |
69 | .otp = AR6003_HW_2_1_1_OTP_FILE, | |
70 | .fw = AR6003_HW_2_1_1_FIRMWARE_FILE, | |
71 | .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE, | |
72 | .patch = AR6003_HW_2_1_1_PATCH_FILE, | |
cd23c1c9 AY |
73 | .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE, |
74 | .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE, | |
c0038972 KV |
75 | }, |
76 | ||
d1a9421d KV |
77 | .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, |
78 | .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, | |
856f4b31 KV |
79 | }, |
80 | { | |
0d0192ba | 81 | .id = AR6004_HW_1_0_VERSION, |
293badf4 | 82 | .name = "ar6004 hw 1.0", |
856f4b31 KV |
83 | .dataset_patch_addr = 0x57e884, |
84 | .app_load_addr = 0x1234, | |
85 | .board_ext_data_addr = 0x437000, | |
86 | .reserved_ram_size = 19456, | |
0d4d72bf | 87 | .board_addr = 0x433900, |
39586bf2 RH |
88 | .refclk_hz = 26000000, |
89 | .uarttx_pin = 11, | |
d1a9421d | 90 | |
c0038972 KV |
91 | .fw = { |
92 | .dir = AR6004_HW_1_0_FW_DIR, | |
93 | .fw = AR6004_HW_1_0_FIRMWARE_FILE, | |
c0038972 KV |
94 | }, |
95 | ||
d1a9421d KV |
96 | .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE, |
97 | .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE, | |
856f4b31 KV |
98 | }, |
99 | { | |
0d0192ba | 100 | .id = AR6004_HW_1_1_VERSION, |
293badf4 | 101 | .name = "ar6004 hw 1.1", |
856f4b31 KV |
102 | .dataset_patch_addr = 0x57e884, |
103 | .app_load_addr = 0x1234, | |
104 | .board_ext_data_addr = 0x437000, | |
105 | .reserved_ram_size = 11264, | |
0d4d72bf | 106 | .board_addr = 0x43d400, |
39586bf2 RH |
107 | .refclk_hz = 40000000, |
108 | .uarttx_pin = 11, | |
d1a9421d | 109 | |
c0038972 KV |
110 | .fw = { |
111 | .dir = AR6004_HW_1_1_FW_DIR, | |
112 | .fw = AR6004_HW_1_1_FIRMWARE_FILE, | |
c0038972 KV |
113 | }, |
114 | ||
d1a9421d KV |
115 | .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE, |
116 | .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE, | |
856f4b31 KV |
117 | }, |
118 | }; | |
119 | ||
bdcd8170 KV |
120 | /* |
121 | * Include definitions here that can be used to tune the WLAN module | |
122 | * behavior. Different customers can tune the behavior as per their needs, | |
123 | * here. | |
124 | */ | |
125 | ||
126 | /* | |
127 | * This configuration item enable/disable keepalive support. | |
128 | * Keepalive support: In the absence of any data traffic to AP, null | |
129 | * frames will be sent to the AP at periodic interval, to keep the association | |
130 | * active. This configuration item defines the periodic interval. | |
131 | * Use value of zero to disable keepalive support | |
132 | * Default: 60 seconds | |
133 | */ | |
134 | #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 | |
135 | ||
136 | /* | |
137 | * This configuration item sets the value of disconnect timeout | |
138 | * Firmware delays sending the disconnec event to the host for this | |
139 | * timeout after is gets disconnected from the current AP. | |
140 | * If the firmware successly roams within the disconnect timeout | |
141 | * it sends a new connect event | |
142 | */ | |
143 | #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 | |
144 | ||
bdcd8170 | 145 | |
bdcd8170 KV |
146 | #define ATH6KL_DATA_OFFSET 64 |
147 | struct sk_buff *ath6kl_buf_alloc(int size) | |
148 | { | |
149 | struct sk_buff *skb; | |
150 | u16 reserved; | |
151 | ||
152 | /* Add chacheline space at front and back of buffer */ | |
153 | reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + | |
1df94a85 | 154 | sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; |
bdcd8170 KV |
155 | skb = dev_alloc_skb(size + reserved); |
156 | ||
157 | if (skb) | |
158 | skb_reserve(skb, reserved - L1_CACHE_BYTES); | |
159 | return skb; | |
160 | } | |
161 | ||
e29f25f5 | 162 | void ath6kl_init_profile_info(struct ath6kl_vif *vif) |
bdcd8170 | 163 | { |
3450334f VT |
164 | vif->ssid_len = 0; |
165 | memset(vif->ssid, 0, sizeof(vif->ssid)); | |
166 | ||
167 | vif->dot11_auth_mode = OPEN_AUTH; | |
168 | vif->auth_mode = NONE_AUTH; | |
169 | vif->prwise_crypto = NONE_CRYPT; | |
170 | vif->prwise_crypto_len = 0; | |
171 | vif->grp_crypto = NONE_CRYPT; | |
172 | vif->grp_crypto_len = 0; | |
6f2a73f9 | 173 | memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); |
8c8b65e3 VT |
174 | memset(vif->req_bssid, 0, sizeof(vif->req_bssid)); |
175 | memset(vif->bssid, 0, sizeof(vif->bssid)); | |
f74bac54 | 176 | vif->bss_ch = 0; |
bdcd8170 KV |
177 | } |
178 | ||
bdcd8170 KV |
179 | static int ath6kl_set_host_app_area(struct ath6kl *ar) |
180 | { | |
181 | u32 address, data; | |
182 | struct host_app_area host_app_area; | |
183 | ||
184 | /* Fetch the address of the host_app_area_s | |
185 | * instance in the host interest area */ | |
186 | address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); | |
31024d99 | 187 | address = TARG_VTOP(ar->target_type, address); |
bdcd8170 | 188 | |
addb44be | 189 | if (ath6kl_diag_read32(ar, address, &data)) |
bdcd8170 KV |
190 | return -EIO; |
191 | ||
31024d99 | 192 | address = TARG_VTOP(ar->target_type, data); |
cbf49a6f | 193 | host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION); |
addb44be KV |
194 | if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area, |
195 | sizeof(struct host_app_area))) | |
bdcd8170 KV |
196 | return -EIO; |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | static inline void set_ac2_ep_map(struct ath6kl *ar, | |
202 | u8 ac, | |
203 | enum htc_endpoint_id ep) | |
204 | { | |
205 | ar->ac2ep_map[ac] = ep; | |
206 | ar->ep2ac_map[ep] = ac; | |
207 | } | |
208 | ||
209 | /* connect to a service */ | |
210 | static int ath6kl_connectservice(struct ath6kl *ar, | |
211 | struct htc_service_connect_req *con_req, | |
212 | char *desc) | |
213 | { | |
214 | int status; | |
215 | struct htc_service_connect_resp response; | |
216 | ||
217 | memset(&response, 0, sizeof(response)); | |
218 | ||
ad226ec2 | 219 | status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); |
bdcd8170 KV |
220 | if (status) { |
221 | ath6kl_err("failed to connect to %s service status:%d\n", | |
222 | desc, status); | |
223 | return status; | |
224 | } | |
225 | ||
226 | switch (con_req->svc_id) { | |
227 | case WMI_CONTROL_SVC: | |
228 | if (test_bit(WMI_ENABLED, &ar->flag)) | |
229 | ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); | |
230 | ar->ctrl_ep = response.endpoint; | |
231 | break; | |
232 | case WMI_DATA_BE_SVC: | |
233 | set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); | |
234 | break; | |
235 | case WMI_DATA_BK_SVC: | |
236 | set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); | |
237 | break; | |
238 | case WMI_DATA_VI_SVC: | |
239 | set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); | |
240 | break; | |
241 | case WMI_DATA_VO_SVC: | |
242 | set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); | |
243 | break; | |
244 | default: | |
245 | ath6kl_err("service id is not mapped %d\n", con_req->svc_id); | |
246 | return -EINVAL; | |
247 | } | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | static int ath6kl_init_service_ep(struct ath6kl *ar) | |
253 | { | |
254 | struct htc_service_connect_req connect; | |
255 | ||
256 | memset(&connect, 0, sizeof(connect)); | |
257 | ||
258 | /* these fields are the same for all service endpoints */ | |
259 | connect.ep_cb.rx = ath6kl_rx; | |
260 | connect.ep_cb.rx_refill = ath6kl_rx_refill; | |
261 | connect.ep_cb.tx_full = ath6kl_tx_queue_full; | |
262 | ||
263 | /* | |
264 | * Set the max queue depth so that our ath6kl_tx_queue_full handler | |
265 | * gets called. | |
266 | */ | |
267 | connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; | |
268 | connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; | |
269 | if (!connect.ep_cb.rx_refill_thresh) | |
270 | connect.ep_cb.rx_refill_thresh++; | |
271 | ||
272 | /* connect to control service */ | |
273 | connect.svc_id = WMI_CONTROL_SVC; | |
274 | if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) | |
275 | return -EIO; | |
276 | ||
277 | connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; | |
278 | ||
279 | /* | |
280 | * Limit the HTC message size on the send path, although e can | |
281 | * receive A-MSDU frames of 4K, we will only send ethernet-sized | |
282 | * (802.3) frames on the send path. | |
283 | */ | |
284 | connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; | |
285 | ||
286 | /* | |
287 | * To reduce the amount of committed memory for larger A_MSDU | |
288 | * frames, use the recv-alloc threshold mechanism for larger | |
289 | * packets. | |
290 | */ | |
291 | connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; | |
292 | connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; | |
293 | ||
294 | /* | |
295 | * For the remaining data services set the connection flag to | |
296 | * reduce dribbling, if configured to do so. | |
297 | */ | |
298 | connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; | |
299 | connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; | |
300 | connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; | |
301 | ||
302 | connect.svc_id = WMI_DATA_BE_SVC; | |
303 | ||
304 | if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) | |
305 | return -EIO; | |
306 | ||
307 | /* connect to back-ground map this to WMI LOW_PRI */ | |
308 | connect.svc_id = WMI_DATA_BK_SVC; | |
309 | if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) | |
310 | return -EIO; | |
311 | ||
312 | /* connect to Video service, map this to to HI PRI */ | |
313 | connect.svc_id = WMI_DATA_VI_SVC; | |
314 | if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) | |
315 | return -EIO; | |
316 | ||
317 | /* | |
318 | * Connect to VO service, this is currently not mapped to a WMI | |
319 | * priority stream due to historical reasons. WMI originally | |
320 | * defined 3 priorities over 3 mailboxes We can change this when | |
321 | * WMI is reworked so that priorities are not dependent on | |
322 | * mailboxes. | |
323 | */ | |
324 | connect.svc_id = WMI_DATA_VO_SVC; | |
325 | if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) | |
326 | return -EIO; | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
e29f25f5 | 331 | void ath6kl_init_control_info(struct ath6kl_vif *vif) |
bdcd8170 | 332 | { |
e29f25f5 | 333 | ath6kl_init_profile_info(vif); |
3450334f | 334 | vif->def_txkey_index = 0; |
6f2a73f9 | 335 | memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); |
f74bac54 | 336 | vif->ch_hint = 0; |
bdcd8170 KV |
337 | } |
338 | ||
339 | /* | |
340 | * Set HTC/Mbox operational parameters, this can only be called when the | |
341 | * target is in the BMI phase. | |
342 | */ | |
343 | static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, | |
344 | u8 htc_ctrl_buf) | |
345 | { | |
346 | int status; | |
347 | u32 blk_size; | |
348 | ||
349 | blk_size = ar->mbox_info.block_size; | |
350 | ||
351 | if (htc_ctrl_buf) | |
352 | blk_size |= ((u32)htc_ctrl_buf) << 16; | |
353 | ||
354 | /* set the host interest area for the block size */ | |
355 | status = ath6kl_bmi_write(ar, | |
356 | ath6kl_get_hi_item_addr(ar, | |
357 | HI_ITEM(hi_mbox_io_block_sz)), | |
358 | (u8 *)&blk_size, | |
359 | 4); | |
360 | if (status) { | |
361 | ath6kl_err("bmi_write_memory for IO block size failed\n"); | |
362 | goto out; | |
363 | } | |
364 | ||
365 | ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", | |
366 | blk_size, | |
367 | ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); | |
368 | ||
369 | if (mbox_isr_yield_val) { | |
370 | /* set the host interest area for the mbox ISR yield limit */ | |
371 | status = ath6kl_bmi_write(ar, | |
372 | ath6kl_get_hi_item_addr(ar, | |
373 | HI_ITEM(hi_mbox_isr_yield_limit)), | |
374 | (u8 *)&mbox_isr_yield_val, | |
375 | 4); | |
376 | if (status) { | |
377 | ath6kl_err("bmi_write_memory for yield limit failed\n"); | |
378 | goto out; | |
379 | } | |
380 | } | |
381 | ||
382 | out: | |
383 | return status; | |
384 | } | |
385 | ||
0ce59445 | 386 | static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) |
bdcd8170 KV |
387 | { |
388 | int status = 0; | |
4dea08e0 | 389 | int ret; |
bdcd8170 KV |
390 | |
391 | /* | |
392 | * Configure the device for rx dot11 header rules. "0,0" are the | |
393 | * default values. Required if checksum offload is needed. Set | |
394 | * RxMetaVersion to 2. | |
395 | */ | |
0ce59445 | 396 | if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, |
bdcd8170 KV |
397 | ar->rx_meta_ver, 0, 0)) { |
398 | ath6kl_err("unable to set the rx frame format\n"); | |
399 | status = -EIO; | |
400 | } | |
401 | ||
402 | if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) | |
0ce59445 | 403 | if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, |
bdcd8170 KV |
404 | IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) { |
405 | ath6kl_err("unable to set power save fail event policy\n"); | |
406 | status = -EIO; | |
407 | } | |
408 | ||
409 | if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) | |
0ce59445 | 410 | if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, |
bdcd8170 KV |
411 | WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) { |
412 | ath6kl_err("unable to set barker preamble policy\n"); | |
413 | status = -EIO; | |
414 | } | |
415 | ||
0ce59445 | 416 | if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, |
bdcd8170 KV |
417 | WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) { |
418 | ath6kl_err("unable to set keep alive interval\n"); | |
419 | status = -EIO; | |
420 | } | |
421 | ||
0ce59445 | 422 | if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, |
bdcd8170 KV |
423 | WLAN_CONFIG_DISCONNECT_TIMEOUT)) { |
424 | ath6kl_err("unable to set disconnect timeout\n"); | |
425 | status = -EIO; | |
426 | } | |
427 | ||
428 | if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) | |
0ce59445 | 429 | if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) { |
bdcd8170 KV |
430 | ath6kl_err("unable to set txop bursting\n"); |
431 | status = -EIO; | |
432 | } | |
433 | ||
b64de356 | 434 | if (ar->p2p && (ar->vif_max == 1 || idx)) { |
0ce59445 | 435 | ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, |
6bbc7c35 JM |
436 | P2P_FLAG_CAPABILITIES_REQ | |
437 | P2P_FLAG_MACADDR_REQ | | |
438 | P2P_FLAG_HMODEL_REQ); | |
439 | if (ret) { | |
440 | ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P " | |
441 | "capabilities (%d) - assuming P2P not " | |
442 | "supported\n", ret); | |
3db1cd5c | 443 | ar->p2p = false; |
6bbc7c35 JM |
444 | } |
445 | } | |
446 | ||
b64de356 | 447 | if (ar->p2p && (ar->vif_max == 1 || idx)) { |
6bbc7c35 | 448 | /* Enable Probe Request reporting for P2P */ |
0ce59445 | 449 | ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true); |
6bbc7c35 JM |
450 | if (ret) { |
451 | ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe " | |
452 | "Request reporting (%d)\n", ret); | |
453 | } | |
4dea08e0 JM |
454 | } |
455 | ||
bdcd8170 KV |
456 | return status; |
457 | } | |
458 | ||
459 | int ath6kl_configure_target(struct ath6kl *ar) | |
460 | { | |
461 | u32 param, ram_reserved_size; | |
3226f68a | 462 | u8 fw_iftype, fw_mode = 0, fw_submode = 0; |
39586bf2 | 463 | int i, status; |
bdcd8170 | 464 | |
f29af978 | 465 | param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG); |
a10e2f2f VT |
466 | if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, |
467 | HI_ITEM(hi_serial_enable)), (u8 *)¶m, 4)) { | |
468 | ath6kl_err("bmi_write_memory for uart debug failed\n"); | |
469 | return -EIO; | |
470 | } | |
471 | ||
7b85832d VT |
472 | /* |
473 | * Note: Even though the firmware interface type is | |
474 | * chosen as BSS_STA for all three interfaces, can | |
475 | * be configured to IBSS/AP as long as the fw submode | |
476 | * remains normal mode (0 - AP, STA and IBSS). But | |
477 | * due to an target assert in firmware only one interface is | |
478 | * configured for now. | |
479 | */ | |
dd3751f7 | 480 | fw_iftype = HI_OPTION_FW_MODE_BSS_STA; |
bdcd8170 | 481 | |
71f96ee6 | 482 | for (i = 0; i < ar->vif_max; i++) |
7b85832d VT |
483 | fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS); |
484 | ||
485 | /* | |
3226f68a VT |
486 | * By default, submodes : |
487 | * vif[0] - AP/STA/IBSS | |
488 | * vif[1] - "P2P dev"/"P2P GO"/"P2P Client" | |
489 | * vif[2] - "P2P dev"/"P2P GO"/"P2P Client" | |
7b85832d | 490 | */ |
3226f68a VT |
491 | |
492 | for (i = 0; i < ar->max_norm_iface; i++) | |
493 | fw_submode |= HI_OPTION_FW_SUBMODE_NONE << | |
494 | (i * HI_OPTION_FW_SUBMODE_BITS); | |
495 | ||
71f96ee6 | 496 | for (i = ar->max_norm_iface; i < ar->vif_max; i++) |
3226f68a VT |
497 | fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << |
498 | (i * HI_OPTION_FW_SUBMODE_BITS); | |
7b85832d | 499 | |
b64de356 | 500 | if (ar->p2p && ar->vif_max == 1) |
7b85832d | 501 | fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; |
7b85832d | 502 | |
bdcd8170 KV |
503 | param = HTC_PROTOCOL_VERSION; |
504 | if (ath6kl_bmi_write(ar, | |
505 | ath6kl_get_hi_item_addr(ar, | |
506 | HI_ITEM(hi_app_host_interest)), | |
507 | (u8 *)¶m, 4) != 0) { | |
508 | ath6kl_err("bmi_write_memory for htc version failed\n"); | |
509 | return -EIO; | |
510 | } | |
511 | ||
512 | /* set the firmware mode to STA/IBSS/AP */ | |
513 | param = 0; | |
514 | ||
515 | if (ath6kl_bmi_read(ar, | |
516 | ath6kl_get_hi_item_addr(ar, | |
517 | HI_ITEM(hi_option_flag)), | |
518 | (u8 *)¶m, 4) != 0) { | |
519 | ath6kl_err("bmi_read_memory for setting fwmode failed\n"); | |
520 | return -EIO; | |
521 | } | |
522 | ||
71f96ee6 | 523 | param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT); |
7b85832d VT |
524 | param |= fw_mode << HI_OPTION_FW_MODE_SHIFT; |
525 | param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT; | |
526 | ||
bdcd8170 KV |
527 | param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); |
528 | param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); | |
529 | ||
530 | if (ath6kl_bmi_write(ar, | |
531 | ath6kl_get_hi_item_addr(ar, | |
532 | HI_ITEM(hi_option_flag)), | |
533 | (u8 *)¶m, | |
534 | 4) != 0) { | |
535 | ath6kl_err("bmi_write_memory for setting fwmode failed\n"); | |
536 | return -EIO; | |
537 | } | |
538 | ||
539 | ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); | |
540 | ||
541 | /* | |
542 | * Hardcode the address use for the extended board data | |
543 | * Ideally this should be pre-allocate by the OS at boot time | |
544 | * But since it is a new feature and board data is loaded | |
545 | * at init time, we have to workaround this from host. | |
546 | * It is difficult to patch the firmware boot code, | |
547 | * but possible in theory. | |
548 | */ | |
549 | ||
991b27ea KV |
550 | param = ar->hw.board_ext_data_addr; |
551 | ram_reserved_size = ar->hw.reserved_ram_size; | |
bdcd8170 | 552 | |
991b27ea KV |
553 | if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, |
554 | HI_ITEM(hi_board_ext_data)), | |
555 | (u8 *)¶m, 4) != 0) { | |
556 | ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); | |
557 | return -EIO; | |
558 | } | |
559 | ||
560 | if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, | |
561 | HI_ITEM(hi_end_ram_reserve_sz)), | |
562 | (u8 *)&ram_reserved_size, 4) != 0) { | |
563 | ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); | |
564 | return -EIO; | |
bdcd8170 KV |
565 | } |
566 | ||
567 | /* set the block size for the target */ | |
568 | if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) | |
569 | /* use default number of control buffers */ | |
570 | return -EIO; | |
571 | ||
39586bf2 RH |
572 | /* Configure GPIO AR600x UART */ |
573 | param = ar->hw.uarttx_pin; | |
574 | status = ath6kl_bmi_write(ar, | |
575 | ath6kl_get_hi_item_addr(ar, | |
576 | HI_ITEM(hi_dbg_uart_txpin)), | |
577 | (u8 *)¶m, 4); | |
578 | if (status) | |
579 | return status; | |
580 | ||
581 | /* Configure target refclk_hz */ | |
582 | param = ar->hw.refclk_hz; | |
583 | status = ath6kl_bmi_write(ar, | |
584 | ath6kl_get_hi_item_addr(ar, | |
585 | HI_ITEM(hi_refclk_hz)), | |
586 | (u8 *)¶m, 4); | |
587 | if (status) | |
588 | return status; | |
589 | ||
bdcd8170 KV |
590 | return 0; |
591 | } | |
592 | ||
bdcd8170 | 593 | /* firmware upload */ |
bdcd8170 KV |
594 | static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, |
595 | u8 **fw, size_t *fw_len) | |
596 | { | |
597 | const struct firmware *fw_entry; | |
598 | int ret; | |
599 | ||
600 | ret = request_firmware(&fw_entry, filename, ar->dev); | |
601 | if (ret) | |
602 | return ret; | |
603 | ||
604 | *fw_len = fw_entry->size; | |
605 | *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); | |
606 | ||
607 | if (*fw == NULL) | |
608 | ret = -ENOMEM; | |
609 | ||
610 | release_firmware(fw_entry); | |
611 | ||
612 | return ret; | |
613 | } | |
614 | ||
92ecbff4 | 615 | #ifdef CONFIG_OF |
92ecbff4 SL |
616 | /* |
617 | * Check the device tree for a board-id and use it to construct | |
618 | * the pathname to the firmware file. Used (for now) to find a | |
619 | * fallback to the "bdata.bin" file--typically a symlink to the | |
620 | * appropriate board-specific file. | |
621 | */ | |
622 | static bool check_device_tree(struct ath6kl *ar) | |
623 | { | |
624 | static const char *board_id_prop = "atheros,board-id"; | |
625 | struct device_node *node; | |
626 | char board_filename[64]; | |
627 | const char *board_id; | |
628 | int ret; | |
629 | ||
630 | for_each_compatible_node(node, NULL, "atheros,ath6kl") { | |
631 | board_id = of_get_property(node, board_id_prop, NULL); | |
632 | if (board_id == NULL) { | |
633 | ath6kl_warn("No \"%s\" property on %s node.\n", | |
634 | board_id_prop, node->name); | |
635 | continue; | |
636 | } | |
637 | snprintf(board_filename, sizeof(board_filename), | |
c0038972 | 638 | "%s/bdata.%s.bin", ar->hw.fw.dir, board_id); |
92ecbff4 SL |
639 | |
640 | ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board, | |
641 | &ar->fw_board_len); | |
642 | if (ret) { | |
643 | ath6kl_err("Failed to get DT board file %s: %d\n", | |
644 | board_filename, ret); | |
645 | continue; | |
646 | } | |
647 | return true; | |
648 | } | |
649 | return false; | |
650 | } | |
651 | #else | |
652 | static bool check_device_tree(struct ath6kl *ar) | |
653 | { | |
654 | return false; | |
655 | } | |
656 | #endif /* CONFIG_OF */ | |
657 | ||
bdcd8170 KV |
658 | static int ath6kl_fetch_board_file(struct ath6kl *ar) |
659 | { | |
660 | const char *filename; | |
661 | int ret; | |
662 | ||
772c31ee KV |
663 | if (ar->fw_board != NULL) |
664 | return 0; | |
665 | ||
d1a9421d KV |
666 | if (WARN_ON(ar->hw.fw_board == NULL)) |
667 | return -EINVAL; | |
668 | ||
669 | filename = ar->hw.fw_board; | |
bdcd8170 KV |
670 | |
671 | ret = ath6kl_get_fw(ar, filename, &ar->fw_board, | |
672 | &ar->fw_board_len); | |
673 | if (ret == 0) { | |
674 | /* managed to get proper board file */ | |
675 | return 0; | |
676 | } | |
677 | ||
92ecbff4 SL |
678 | if (check_device_tree(ar)) { |
679 | /* got board file from device tree */ | |
680 | return 0; | |
681 | } | |
682 | ||
bdcd8170 KV |
683 | /* there was no proper board file, try to use default instead */ |
684 | ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", | |
685 | filename, ret); | |
686 | ||
d1a9421d | 687 | filename = ar->hw.fw_default_board; |
bdcd8170 KV |
688 | |
689 | ret = ath6kl_get_fw(ar, filename, &ar->fw_board, | |
690 | &ar->fw_board_len); | |
691 | if (ret) { | |
692 | ath6kl_err("Failed to get default board file %s: %d\n", | |
693 | filename, ret); | |
694 | return ret; | |
695 | } | |
696 | ||
697 | ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); | |
698 | ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); | |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
772c31ee KV |
703 | static int ath6kl_fetch_otp_file(struct ath6kl *ar) |
704 | { | |
c0038972 | 705 | char filename[100]; |
772c31ee KV |
706 | int ret; |
707 | ||
708 | if (ar->fw_otp != NULL) | |
709 | return 0; | |
710 | ||
c0038972 | 711 | if (ar->hw.fw.otp == NULL) { |
d1a9421d KV |
712 | ath6kl_dbg(ATH6KL_DBG_BOOT, |
713 | "no OTP file configured for this hw\n"); | |
772c31ee | 714 | return 0; |
772c31ee KV |
715 | } |
716 | ||
c0038972 KV |
717 | snprintf(filename, sizeof(filename), "%s/%s", |
718 | ar->hw.fw.dir, ar->hw.fw.otp); | |
d1a9421d | 719 | |
772c31ee KV |
720 | ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, |
721 | &ar->fw_otp_len); | |
722 | if (ret) { | |
723 | ath6kl_err("Failed to get OTP file %s: %d\n", | |
724 | filename, ret); | |
725 | return ret; | |
726 | } | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
5f1127ff | 731 | static int ath6kl_fetch_testmode_file(struct ath6kl *ar) |
772c31ee | 732 | { |
c0038972 | 733 | char filename[100]; |
772c31ee KV |
734 | int ret; |
735 | ||
5f1127ff | 736 | if (ar->testmode == 0) |
772c31ee KV |
737 | return 0; |
738 | ||
5f1127ff | 739 | ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode); |
772c31ee | 740 | |
5f1127ff KV |
741 | if (ar->testmode == 2) { |
742 | if (ar->hw.fw.utf == NULL) { | |
743 | ath6kl_warn("testmode 2 not supported\n"); | |
744 | return -EOPNOTSUPP; | |
745 | } | |
d1a9421d | 746 | |
5f1127ff KV |
747 | snprintf(filename, sizeof(filename), "%s/%s", |
748 | ar->hw.fw.dir, ar->hw.fw.utf); | |
749 | } else { | |
750 | if (ar->hw.fw.tcmd == NULL) { | |
751 | ath6kl_warn("testmode 1 not supported\n"); | |
752 | return -EOPNOTSUPP; | |
cd23c1c9 | 753 | } |
772c31ee | 754 | |
5f1127ff KV |
755 | snprintf(filename, sizeof(filename), "%s/%s", |
756 | ar->hw.fw.dir, ar->hw.fw.tcmd); | |
772c31ee KV |
757 | } |
758 | ||
5f1127ff KV |
759 | set_bit(TESTMODE, &ar->flag); |
760 | ||
761 | ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); | |
762 | if (ret) { | |
763 | ath6kl_err("Failed to get testmode %d firmware file %s: %d\n", | |
764 | ar->testmode, filename, ret); | |
765 | return ret; | |
766 | } | |
767 | ||
768 | return 0; | |
769 | } | |
770 | ||
771 | static int ath6kl_fetch_fw_file(struct ath6kl *ar) | |
772 | { | |
773 | char filename[100]; | |
774 | int ret; | |
775 | ||
776 | if (ar->fw != NULL) | |
777 | return 0; | |
778 | ||
c0038972 KV |
779 | /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */ |
780 | if (WARN_ON(ar->hw.fw.fw == NULL)) | |
d1a9421d KV |
781 | return -EINVAL; |
782 | ||
c0038972 KV |
783 | snprintf(filename, sizeof(filename), "%s/%s", |
784 | ar->hw.fw.dir, ar->hw.fw.fw); | |
772c31ee | 785 | |
772c31ee KV |
786 | ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); |
787 | if (ret) { | |
788 | ath6kl_err("Failed to get firmware file %s: %d\n", | |
789 | filename, ret); | |
790 | return ret; | |
791 | } | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static int ath6kl_fetch_patch_file(struct ath6kl *ar) | |
797 | { | |
c0038972 | 798 | char filename[100]; |
772c31ee KV |
799 | int ret; |
800 | ||
d1a9421d | 801 | if (ar->fw_patch != NULL) |
772c31ee | 802 | return 0; |
772c31ee | 803 | |
c0038972 | 804 | if (ar->hw.fw.patch == NULL) |
d1a9421d KV |
805 | return 0; |
806 | ||
c0038972 KV |
807 | snprintf(filename, sizeof(filename), "%s/%s", |
808 | ar->hw.fw.dir, ar->hw.fw.patch); | |
d1a9421d KV |
809 | |
810 | ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, | |
811 | &ar->fw_patch_len); | |
812 | if (ret) { | |
813 | ath6kl_err("Failed to get patch file %s: %d\n", | |
814 | filename, ret); | |
815 | return ret; | |
772c31ee KV |
816 | } |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
cd23c1c9 AY |
821 | static int ath6kl_fetch_testscript_file(struct ath6kl *ar) |
822 | { | |
823 | char filename[100]; | |
824 | int ret; | |
825 | ||
5f1127ff | 826 | if (ar->testmode != 2) |
cd23c1c9 AY |
827 | return 0; |
828 | ||
829 | if (ar->fw_testscript != NULL) | |
830 | return 0; | |
831 | ||
832 | if (ar->hw.fw.testscript == NULL) | |
833 | return 0; | |
834 | ||
835 | snprintf(filename, sizeof(filename), "%s/%s", | |
836 | ar->hw.fw.dir, ar->hw.fw.testscript); | |
837 | ||
838 | ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript, | |
839 | &ar->fw_testscript_len); | |
840 | if (ret) { | |
841 | ath6kl_err("Failed to get testscript file %s: %d\n", | |
842 | filename, ret); | |
843 | return ret; | |
844 | } | |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
50d41234 | 849 | static int ath6kl_fetch_fw_api1(struct ath6kl *ar) |
772c31ee KV |
850 | { |
851 | int ret; | |
852 | ||
772c31ee KV |
853 | ret = ath6kl_fetch_otp_file(ar); |
854 | if (ret) | |
855 | return ret; | |
856 | ||
857 | ret = ath6kl_fetch_fw_file(ar); | |
858 | if (ret) | |
859 | return ret; | |
860 | ||
861 | ret = ath6kl_fetch_patch_file(ar); | |
862 | if (ret) | |
863 | return ret; | |
864 | ||
cd23c1c9 AY |
865 | ret = ath6kl_fetch_testscript_file(ar); |
866 | if (ret) | |
867 | return ret; | |
868 | ||
772c31ee KV |
869 | return 0; |
870 | } | |
bdcd8170 | 871 | |
65a8b4cc | 872 | static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name) |
50d41234 KV |
873 | { |
874 | size_t magic_len, len, ie_len; | |
875 | const struct firmware *fw; | |
876 | struct ath6kl_fw_ie *hdr; | |
c0038972 | 877 | char filename[100]; |
50d41234 | 878 | const u8 *data; |
97e0496d | 879 | int ret, ie_id, i, index, bit; |
8a137480 | 880 | __le32 *val; |
50d41234 | 881 | |
65a8b4cc | 882 | snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name); |
50d41234 KV |
883 | |
884 | ret = request_firmware(&fw, filename, ar->dev); | |
885 | if (ret) | |
886 | return ret; | |
887 | ||
888 | data = fw->data; | |
889 | len = fw->size; | |
890 | ||
891 | /* magic also includes the null byte, check that as well */ | |
892 | magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1; | |
893 | ||
894 | if (len < magic_len) { | |
895 | ret = -EINVAL; | |
896 | goto out; | |
897 | } | |
898 | ||
899 | if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) { | |
900 | ret = -EINVAL; | |
901 | goto out; | |
902 | } | |
903 | ||
904 | len -= magic_len; | |
905 | data += magic_len; | |
906 | ||
907 | /* loop elements */ | |
908 | while (len > sizeof(struct ath6kl_fw_ie)) { | |
909 | /* hdr is unaligned! */ | |
910 | hdr = (struct ath6kl_fw_ie *) data; | |
911 | ||
912 | ie_id = le32_to_cpup(&hdr->id); | |
913 | ie_len = le32_to_cpup(&hdr->len); | |
914 | ||
915 | len -= sizeof(*hdr); | |
916 | data += sizeof(*hdr); | |
917 | ||
918 | if (len < ie_len) { | |
919 | ret = -EINVAL; | |
920 | goto out; | |
921 | } | |
922 | ||
923 | switch (ie_id) { | |
924 | case ATH6KL_FW_IE_OTP_IMAGE: | |
ef548626 | 925 | ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", |
6bc36431 KV |
926 | ie_len); |
927 | ||
50d41234 KV |
928 | ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); |
929 | ||
930 | if (ar->fw_otp == NULL) { | |
931 | ret = -ENOMEM; | |
932 | goto out; | |
933 | } | |
934 | ||
935 | ar->fw_otp_len = ie_len; | |
936 | break; | |
937 | case ATH6KL_FW_IE_FW_IMAGE: | |
ef548626 | 938 | ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", |
6bc36431 KV |
939 | ie_len); |
940 | ||
5f1127ff KV |
941 | /* in testmode we already might have a fw file */ |
942 | if (ar->fw != NULL) | |
943 | break; | |
944 | ||
50d41234 KV |
945 | ar->fw = kmemdup(data, ie_len, GFP_KERNEL); |
946 | ||
947 | if (ar->fw == NULL) { | |
948 | ret = -ENOMEM; | |
949 | goto out; | |
950 | } | |
951 | ||
952 | ar->fw_len = ie_len; | |
953 | break; | |
954 | case ATH6KL_FW_IE_PATCH_IMAGE: | |
ef548626 | 955 | ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", |
6bc36431 KV |
956 | ie_len); |
957 | ||
50d41234 KV |
958 | ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); |
959 | ||
960 | if (ar->fw_patch == NULL) { | |
961 | ret = -ENOMEM; | |
962 | goto out; | |
963 | } | |
964 | ||
965 | ar->fw_patch_len = ie_len; | |
966 | break; | |
8a137480 KV |
967 | case ATH6KL_FW_IE_RESERVED_RAM_SIZE: |
968 | val = (__le32 *) data; | |
969 | ar->hw.reserved_ram_size = le32_to_cpup(val); | |
6bc36431 KV |
970 | |
971 | ath6kl_dbg(ATH6KL_DBG_BOOT, | |
972 | "found reserved ram size ie 0x%d\n", | |
973 | ar->hw.reserved_ram_size); | |
8a137480 | 974 | break; |
97e0496d | 975 | case ATH6KL_FW_IE_CAPABILITIES: |
277d90f4 KV |
976 | if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8)) |
977 | break; | |
978 | ||
6bc36431 | 979 | ath6kl_dbg(ATH6KL_DBG_BOOT, |
ef548626 | 980 | "found firmware capabilities ie (%zd B)\n", |
6bc36431 KV |
981 | ie_len); |
982 | ||
97e0496d | 983 | for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) { |
277d90f4 | 984 | index = i / 8; |
97e0496d KV |
985 | bit = i % 8; |
986 | ||
987 | if (data[index] & (1 << bit)) | |
988 | __set_bit(i, ar->fw_capabilities); | |
989 | } | |
6bc36431 KV |
990 | |
991 | ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "", | |
992 | ar->fw_capabilities, | |
993 | sizeof(ar->fw_capabilities)); | |
97e0496d | 994 | break; |
1b4304da KV |
995 | case ATH6KL_FW_IE_PATCH_ADDR: |
996 | if (ie_len != sizeof(*val)) | |
997 | break; | |
998 | ||
999 | val = (__le32 *) data; | |
1000 | ar->hw.dataset_patch_addr = le32_to_cpup(val); | |
6bc36431 KV |
1001 | |
1002 | ath6kl_dbg(ATH6KL_DBG_BOOT, | |
03ef0250 | 1003 | "found patch address ie 0x%x\n", |
6bc36431 | 1004 | ar->hw.dataset_patch_addr); |
1b4304da | 1005 | break; |
03ef0250 KV |
1006 | case ATH6KL_FW_IE_BOARD_ADDR: |
1007 | if (ie_len != sizeof(*val)) | |
1008 | break; | |
1009 | ||
1010 | val = (__le32 *) data; | |
1011 | ar->hw.board_addr = le32_to_cpup(val); | |
1012 | ||
1013 | ath6kl_dbg(ATH6KL_DBG_BOOT, | |
1014 | "found board address ie 0x%x\n", | |
1015 | ar->hw.board_addr); | |
1016 | break; | |
368b1b0f KV |
1017 | case ATH6KL_FW_IE_VIF_MAX: |
1018 | if (ie_len != sizeof(*val)) | |
1019 | break; | |
1020 | ||
1021 | val = (__le32 *) data; | |
1022 | ar->vif_max = min_t(unsigned int, le32_to_cpup(val), | |
1023 | ATH6KL_VIF_MAX); | |
1024 | ||
f143379d VT |
1025 | if (ar->vif_max > 1 && !ar->p2p) |
1026 | ar->max_norm_iface = 2; | |
1027 | ||
368b1b0f KV |
1028 | ath6kl_dbg(ATH6KL_DBG_BOOT, |
1029 | "found vif max ie %d\n", ar->vif_max); | |
1030 | break; | |
50d41234 | 1031 | default: |
6bc36431 | 1032 | ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n", |
50d41234 KV |
1033 | le32_to_cpup(&hdr->id)); |
1034 | break; | |
1035 | } | |
1036 | ||
1037 | len -= ie_len; | |
1038 | data += ie_len; | |
1039 | }; | |
1040 | ||
1041 | ret = 0; | |
1042 | out: | |
1043 | release_firmware(fw); | |
1044 | ||
1045 | return ret; | |
1046 | } | |
1047 | ||
45eaa78f | 1048 | int ath6kl_init_fetch_firmwares(struct ath6kl *ar) |
50d41234 KV |
1049 | { |
1050 | int ret; | |
1051 | ||
1052 | ret = ath6kl_fetch_board_file(ar); | |
1053 | if (ret) | |
1054 | return ret; | |
1055 | ||
5f1127ff KV |
1056 | ret = ath6kl_fetch_testmode_file(ar); |
1057 | if (ret) | |
1058 | return ret; | |
1059 | ||
65a8b4cc | 1060 | ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE); |
6bc36431 | 1061 | if (ret == 0) { |
65a8b4cc KV |
1062 | ar->fw_api = 3; |
1063 | goto out; | |
1064 | } | |
1065 | ||
1066 | ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE); | |
1067 | if (ret == 0) { | |
1068 | ar->fw_api = 2; | |
1069 | goto out; | |
6bc36431 | 1070 | } |
50d41234 KV |
1071 | |
1072 | ret = ath6kl_fetch_fw_api1(ar); | |
1073 | if (ret) | |
1074 | return ret; | |
1075 | ||
65a8b4cc KV |
1076 | ar->fw_api = 1; |
1077 | ||
1078 | out: | |
1079 | ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api); | |
6bc36431 | 1080 | |
50d41234 KV |
1081 | return 0; |
1082 | } | |
1083 | ||
bdcd8170 KV |
1084 | static int ath6kl_upload_board_file(struct ath6kl *ar) |
1085 | { | |
1086 | u32 board_address, board_ext_address, param; | |
31024d99 | 1087 | u32 board_data_size, board_ext_data_size; |
bdcd8170 KV |
1088 | int ret; |
1089 | ||
772c31ee KV |
1090 | if (WARN_ON(ar->fw_board == NULL)) |
1091 | return -ENOENT; | |
bdcd8170 | 1092 | |
31024d99 KF |
1093 | /* |
1094 | * Determine where in Target RAM to write Board Data. | |
1095 | * For AR6004, host determine Target RAM address for | |
1096 | * writing board data. | |
1097 | */ | |
0d4d72bf KV |
1098 | if (ar->hw.board_addr != 0) { |
1099 | board_address = ar->hw.board_addr; | |
31024d99 KF |
1100 | ath6kl_bmi_write(ar, |
1101 | ath6kl_get_hi_item_addr(ar, | |
1102 | HI_ITEM(hi_board_data)), | |
1103 | (u8 *) &board_address, 4); | |
1104 | } else { | |
1105 | ath6kl_bmi_read(ar, | |
1106 | ath6kl_get_hi_item_addr(ar, | |
1107 | HI_ITEM(hi_board_data)), | |
1108 | (u8 *) &board_address, 4); | |
1109 | } | |
1110 | ||
bdcd8170 KV |
1111 | /* determine where in target ram to write extended board data */ |
1112 | ath6kl_bmi_read(ar, | |
1113 | ath6kl_get_hi_item_addr(ar, | |
1114 | HI_ITEM(hi_board_ext_data)), | |
1115 | (u8 *) &board_ext_address, 4); | |
1116 | ||
50e2740b KV |
1117 | if (ar->target_type == TARGET_TYPE_AR6003 && |
1118 | board_ext_address == 0) { | |
bdcd8170 KV |
1119 | ath6kl_err("Failed to get board file target address.\n"); |
1120 | return -EINVAL; | |
1121 | } | |
1122 | ||
31024d99 KF |
1123 | switch (ar->target_type) { |
1124 | case TARGET_TYPE_AR6003: | |
1125 | board_data_size = AR6003_BOARD_DATA_SZ; | |
1126 | board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; | |
1127 | break; | |
1128 | case TARGET_TYPE_AR6004: | |
1129 | board_data_size = AR6004_BOARD_DATA_SZ; | |
1130 | board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; | |
1131 | break; | |
1132 | default: | |
1133 | WARN_ON(1); | |
1134 | return -EINVAL; | |
1135 | break; | |
1136 | } | |
1137 | ||
50e2740b KV |
1138 | if (board_ext_address && |
1139 | ar->fw_board_len == (board_data_size + board_ext_data_size)) { | |
31024d99 | 1140 | |
bdcd8170 | 1141 | /* write extended board data */ |
6bc36431 KV |
1142 | ath6kl_dbg(ATH6KL_DBG_BOOT, |
1143 | "writing extended board data to 0x%x (%d B)\n", | |
1144 | board_ext_address, board_ext_data_size); | |
1145 | ||
bdcd8170 | 1146 | ret = ath6kl_bmi_write(ar, board_ext_address, |
31024d99 KF |
1147 | ar->fw_board + board_data_size, |
1148 | board_ext_data_size); | |
bdcd8170 KV |
1149 | if (ret) { |
1150 | ath6kl_err("Failed to write extended board data: %d\n", | |
1151 | ret); | |
1152 | return ret; | |
1153 | } | |
1154 | ||
1155 | /* record that extended board data is initialized */ | |
31024d99 KF |
1156 | param = (board_ext_data_size << 16) | 1; |
1157 | ||
bdcd8170 KV |
1158 | ath6kl_bmi_write(ar, |
1159 | ath6kl_get_hi_item_addr(ar, | |
1160 | HI_ITEM(hi_board_ext_data_config)), | |
1161 | (unsigned char *) ¶m, 4); | |
1162 | } | |
1163 | ||
31024d99 | 1164 | if (ar->fw_board_len < board_data_size) { |
bdcd8170 KV |
1165 | ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); |
1166 | ret = -EINVAL; | |
1167 | return ret; | |
1168 | } | |
1169 | ||
6bc36431 KV |
1170 | ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n", |
1171 | board_address, board_data_size); | |
1172 | ||
bdcd8170 | 1173 | ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, |
31024d99 | 1174 | board_data_size); |
bdcd8170 KV |
1175 | |
1176 | if (ret) { | |
1177 | ath6kl_err("Board file bmi write failed: %d\n", ret); | |
1178 | return ret; | |
1179 | } | |
1180 | ||
1181 | /* record the fact that Board Data IS initialized */ | |
1182 | param = 1; | |
1183 | ath6kl_bmi_write(ar, | |
1184 | ath6kl_get_hi_item_addr(ar, | |
1185 | HI_ITEM(hi_board_data_initialized)), | |
1186 | (u8 *)¶m, 4); | |
1187 | ||
1188 | return ret; | |
1189 | } | |
1190 | ||
1191 | static int ath6kl_upload_otp(struct ath6kl *ar) | |
1192 | { | |
bdcd8170 | 1193 | u32 address, param; |
bef26a7f | 1194 | bool from_hw = false; |
bdcd8170 KV |
1195 | int ret; |
1196 | ||
50e2740b KV |
1197 | if (ar->fw_otp == NULL) |
1198 | return 0; | |
bdcd8170 | 1199 | |
a01ac414 | 1200 | address = ar->hw.app_load_addr; |
bdcd8170 | 1201 | |
ef548626 | 1202 | ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address, |
6bc36431 KV |
1203 | ar->fw_otp_len); |
1204 | ||
bdcd8170 KV |
1205 | ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, |
1206 | ar->fw_otp_len); | |
1207 | if (ret) { | |
1208 | ath6kl_err("Failed to upload OTP file: %d\n", ret); | |
1209 | return ret; | |
1210 | } | |
1211 | ||
639d0b89 KV |
1212 | /* read firmware start address */ |
1213 | ret = ath6kl_bmi_read(ar, | |
1214 | ath6kl_get_hi_item_addr(ar, | |
1215 | HI_ITEM(hi_app_start)), | |
1216 | (u8 *) &address, sizeof(address)); | |
1217 | ||
1218 | if (ret) { | |
1219 | ath6kl_err("Failed to read hi_app_start: %d\n", ret); | |
1220 | return ret; | |
1221 | } | |
1222 | ||
bef26a7f KV |
1223 | if (ar->hw.app_start_override_addr == 0) { |
1224 | ar->hw.app_start_override_addr = address; | |
1225 | from_hw = true; | |
1226 | } | |
639d0b89 | 1227 | |
bef26a7f KV |
1228 | ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n", |
1229 | from_hw ? " (from hw)" : "", | |
6bc36431 KV |
1230 | ar->hw.app_start_override_addr); |
1231 | ||
bdcd8170 | 1232 | /* execute the OTP code */ |
bef26a7f KV |
1233 | ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n", |
1234 | ar->hw.app_start_override_addr); | |
bdcd8170 | 1235 | param = 0; |
bef26a7f | 1236 | ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m); |
bdcd8170 KV |
1237 | |
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | static int ath6kl_upload_firmware(struct ath6kl *ar) | |
1242 | { | |
bdcd8170 KV |
1243 | u32 address; |
1244 | int ret; | |
1245 | ||
772c31ee | 1246 | if (WARN_ON(ar->fw == NULL)) |
50e2740b | 1247 | return 0; |
bdcd8170 | 1248 | |
a01ac414 | 1249 | address = ar->hw.app_load_addr; |
bdcd8170 | 1250 | |
ef548626 | 1251 | ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n", |
6bc36431 KV |
1252 | address, ar->fw_len); |
1253 | ||
bdcd8170 KV |
1254 | ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); |
1255 | ||
1256 | if (ret) { | |
1257 | ath6kl_err("Failed to write firmware: %d\n", ret); | |
1258 | return ret; | |
1259 | } | |
1260 | ||
31024d99 KF |
1261 | /* |
1262 | * Set starting address for firmware | |
1263 | * Don't need to setup app_start override addr on AR6004 | |
1264 | */ | |
1265 | if (ar->target_type != TARGET_TYPE_AR6004) { | |
a01ac414 | 1266 | address = ar->hw.app_start_override_addr; |
31024d99 KF |
1267 | ath6kl_bmi_set_app_start(ar, address); |
1268 | } | |
bdcd8170 KV |
1269 | return ret; |
1270 | } | |
1271 | ||
1272 | static int ath6kl_upload_patch(struct ath6kl *ar) | |
1273 | { | |
bdcd8170 KV |
1274 | u32 address, param; |
1275 | int ret; | |
1276 | ||
50e2740b KV |
1277 | if (ar->fw_patch == NULL) |
1278 | return 0; | |
bdcd8170 | 1279 | |
a01ac414 | 1280 | address = ar->hw.dataset_patch_addr; |
bdcd8170 | 1281 | |
ef548626 | 1282 | ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n", |
6bc36431 KV |
1283 | address, ar->fw_patch_len); |
1284 | ||
bdcd8170 KV |
1285 | ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); |
1286 | if (ret) { | |
1287 | ath6kl_err("Failed to write patch file: %d\n", ret); | |
1288 | return ret; | |
1289 | } | |
1290 | ||
1291 | param = address; | |
1292 | ath6kl_bmi_write(ar, | |
1293 | ath6kl_get_hi_item_addr(ar, | |
1294 | HI_ITEM(hi_dset_list_head)), | |
1295 | (unsigned char *) ¶m, 4); | |
1296 | ||
1297 | return 0; | |
1298 | } | |
1299 | ||
cd23c1c9 AY |
1300 | static int ath6kl_upload_testscript(struct ath6kl *ar) |
1301 | { | |
1302 | u32 address, param; | |
1303 | int ret; | |
1304 | ||
5f1127ff | 1305 | if (ar->testmode != 2) |
cd23c1c9 AY |
1306 | return 0; |
1307 | ||
1308 | if (ar->fw_testscript == NULL) | |
1309 | return 0; | |
1310 | ||
1311 | address = ar->hw.testscript_addr; | |
1312 | ||
1313 | ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n", | |
1314 | address, ar->fw_testscript_len); | |
1315 | ||
1316 | ret = ath6kl_bmi_write(ar, address, ar->fw_testscript, | |
1317 | ar->fw_testscript_len); | |
1318 | if (ret) { | |
1319 | ath6kl_err("Failed to write testscript file: %d\n", ret); | |
1320 | return ret; | |
1321 | } | |
1322 | ||
1323 | param = address; | |
1324 | ath6kl_bmi_write(ar, | |
1325 | ath6kl_get_hi_item_addr(ar, | |
1326 | HI_ITEM(hi_ota_testscript)), | |
1327 | (unsigned char *) ¶m, 4); | |
1328 | ||
1329 | param = 4096; | |
1330 | ath6kl_bmi_write(ar, | |
1331 | ath6kl_get_hi_item_addr(ar, | |
1332 | HI_ITEM(hi_end_ram_reserve_sz)), | |
1333 | (unsigned char *) ¶m, 4); | |
1334 | ||
1335 | param = 1; | |
1336 | ath6kl_bmi_write(ar, | |
1337 | ath6kl_get_hi_item_addr(ar, | |
1338 | HI_ITEM(hi_test_apps_related)), | |
1339 | (unsigned char *) ¶m, 4); | |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
bdcd8170 KV |
1344 | static int ath6kl_init_upload(struct ath6kl *ar) |
1345 | { | |
1346 | u32 param, options, sleep, address; | |
1347 | int status = 0; | |
1348 | ||
31024d99 KF |
1349 | if (ar->target_type != TARGET_TYPE_AR6003 && |
1350 | ar->target_type != TARGET_TYPE_AR6004) | |
bdcd8170 KV |
1351 | return -EINVAL; |
1352 | ||
1353 | /* temporarily disable system sleep */ | |
1354 | address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; | |
1355 | status = ath6kl_bmi_reg_read(ar, address, ¶m); | |
1356 | if (status) | |
1357 | return status; | |
1358 | ||
1359 | options = param; | |
1360 | ||
1361 | param |= ATH6KL_OPTION_SLEEP_DISABLE; | |
1362 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1363 | if (status) | |
1364 | return status; | |
1365 | ||
1366 | address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; | |
1367 | status = ath6kl_bmi_reg_read(ar, address, ¶m); | |
1368 | if (status) | |
1369 | return status; | |
1370 | ||
1371 | sleep = param; | |
1372 | ||
1373 | param |= SM(SYSTEM_SLEEP_DISABLE, 1); | |
1374 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1375 | if (status) | |
1376 | return status; | |
1377 | ||
1378 | ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", | |
1379 | options, sleep); | |
1380 | ||
1381 | /* program analog PLL register */ | |
31024d99 KF |
1382 | /* no need to control 40/44MHz clock on AR6004 */ |
1383 | if (ar->target_type != TARGET_TYPE_AR6004) { | |
1384 | status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, | |
1385 | 0xF9104001); | |
bdcd8170 | 1386 | |
31024d99 KF |
1387 | if (status) |
1388 | return status; | |
bdcd8170 | 1389 | |
31024d99 KF |
1390 | /* Run at 80/88MHz by default */ |
1391 | param = SM(CPU_CLOCK_STANDARD, 1); | |
1392 | ||
1393 | address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; | |
1394 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1395 | if (status) | |
1396 | return status; | |
1397 | } | |
bdcd8170 KV |
1398 | |
1399 | param = 0; | |
1400 | address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; | |
1401 | param = SM(LPO_CAL_ENABLE, 1); | |
1402 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1403 | if (status) | |
1404 | return status; | |
1405 | ||
1406 | /* WAR to avoid SDIO CRC err */ | |
0d0192ba | 1407 | if (ar->version.target_ver == AR6003_HW_2_0_VERSION) { |
bdcd8170 KV |
1408 | ath6kl_err("temporary war to avoid sdio crc error\n"); |
1409 | ||
1410 | param = 0x20; | |
1411 | ||
1412 | address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; | |
1413 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1414 | if (status) | |
1415 | return status; | |
1416 | ||
1417 | address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; | |
1418 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1419 | if (status) | |
1420 | return status; | |
1421 | ||
1422 | address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; | |
1423 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1424 | if (status) | |
1425 | return status; | |
1426 | ||
1427 | address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; | |
1428 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1429 | if (status) | |
1430 | return status; | |
1431 | } | |
1432 | ||
1433 | /* write EEPROM data to Target RAM */ | |
1434 | status = ath6kl_upload_board_file(ar); | |
1435 | if (status) | |
1436 | return status; | |
1437 | ||
1438 | /* transfer One time Programmable data */ | |
1439 | status = ath6kl_upload_otp(ar); | |
1440 | if (status) | |
1441 | return status; | |
1442 | ||
1443 | /* Download Target firmware */ | |
1444 | status = ath6kl_upload_firmware(ar); | |
1445 | if (status) | |
1446 | return status; | |
1447 | ||
1448 | status = ath6kl_upload_patch(ar); | |
1449 | if (status) | |
1450 | return status; | |
1451 | ||
cd23c1c9 AY |
1452 | /* Download the test script */ |
1453 | status = ath6kl_upload_testscript(ar); | |
1454 | if (status) | |
1455 | return status; | |
1456 | ||
bdcd8170 KV |
1457 | /* Restore system sleep */ |
1458 | address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; | |
1459 | status = ath6kl_bmi_reg_write(ar, address, sleep); | |
1460 | if (status) | |
1461 | return status; | |
1462 | ||
1463 | address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; | |
1464 | param = options | 0x20; | |
1465 | status = ath6kl_bmi_reg_write(ar, address, param); | |
1466 | if (status) | |
1467 | return status; | |
1468 | ||
bdcd8170 KV |
1469 | return status; |
1470 | } | |
1471 | ||
45eaa78f | 1472 | int ath6kl_init_hw_params(struct ath6kl *ar) |
a01ac414 | 1473 | { |
1b46dc04 | 1474 | const struct ath6kl_hw *uninitialized_var(hw); |
856f4b31 | 1475 | int i; |
bef26a7f | 1476 | |
856f4b31 KV |
1477 | for (i = 0; i < ARRAY_SIZE(hw_list); i++) { |
1478 | hw = &hw_list[i]; | |
bef26a7f | 1479 | |
856f4b31 KV |
1480 | if (hw->id == ar->version.target_ver) |
1481 | break; | |
1482 | } | |
1483 | ||
1484 | if (i == ARRAY_SIZE(hw_list)) { | |
a01ac414 KV |
1485 | ath6kl_err("Unsupported hardware version: 0x%x\n", |
1486 | ar->version.target_ver); | |
1487 | return -EINVAL; | |
1488 | } | |
1489 | ||
856f4b31 KV |
1490 | ar->hw = *hw; |
1491 | ||
6bc36431 KV |
1492 | ath6kl_dbg(ATH6KL_DBG_BOOT, |
1493 | "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n", | |
1494 | ar->version.target_ver, ar->target_type, | |
1495 | ar->hw.dataset_patch_addr, ar->hw.app_load_addr); | |
1496 | ath6kl_dbg(ATH6KL_DBG_BOOT, | |
1497 | "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x", | |
1498 | ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr, | |
1499 | ar->hw.reserved_ram_size); | |
39586bf2 RH |
1500 | ath6kl_dbg(ATH6KL_DBG_BOOT, |
1501 | "refclk_hz %d uarttx_pin %d", | |
1502 | ar->hw.refclk_hz, ar->hw.uarttx_pin); | |
6bc36431 | 1503 | |
a01ac414 KV |
1504 | return 0; |
1505 | } | |
1506 | ||
293badf4 KV |
1507 | static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type) |
1508 | { | |
1509 | switch (type) { | |
1510 | case ATH6KL_HIF_TYPE_SDIO: | |
1511 | return "sdio"; | |
1512 | case ATH6KL_HIF_TYPE_USB: | |
1513 | return "usb"; | |
1514 | } | |
1515 | ||
1516 | return NULL; | |
1517 | } | |
1518 | ||
5fe4dffb | 1519 | int ath6kl_init_hw_start(struct ath6kl *ar) |
20459ee2 KV |
1520 | { |
1521 | long timeleft; | |
1522 | int ret, i; | |
1523 | ||
5fe4dffb KV |
1524 | ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n"); |
1525 | ||
20459ee2 KV |
1526 | ret = ath6kl_hif_power_on(ar); |
1527 | if (ret) | |
1528 | return ret; | |
1529 | ||
1530 | ret = ath6kl_configure_target(ar); | |
1531 | if (ret) | |
1532 | goto err_power_off; | |
1533 | ||
1534 | ret = ath6kl_init_upload(ar); | |
1535 | if (ret) | |
1536 | goto err_power_off; | |
1537 | ||
1538 | /* Do we need to finish the BMI phase */ | |
1539 | /* FIXME: return error from ath6kl_bmi_done() */ | |
1540 | if (ath6kl_bmi_done(ar)) { | |
1541 | ret = -EIO; | |
1542 | goto err_power_off; | |
1543 | } | |
1544 | ||
1545 | /* | |
1546 | * The reason we have to wait for the target here is that the | |
1547 | * driver layer has to init BMI in order to set the host block | |
1548 | * size. | |
1549 | */ | |
1550 | if (ath6kl_htc_wait_target(ar->htc_target)) { | |
1551 | ret = -EIO; | |
1552 | goto err_power_off; | |
1553 | } | |
1554 | ||
1555 | if (ath6kl_init_service_ep(ar)) { | |
1556 | ret = -EIO; | |
1557 | goto err_cleanup_scatter; | |
1558 | } | |
1559 | ||
1560 | /* setup credit distribution */ | |
1561 | ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info); | |
1562 | ||
1563 | /* start HTC */ | |
1564 | ret = ath6kl_htc_start(ar->htc_target); | |
1565 | if (ret) { | |
1566 | /* FIXME: call this */ | |
1567 | ath6kl_cookie_cleanup(ar); | |
1568 | goto err_cleanup_scatter; | |
1569 | } | |
1570 | ||
1571 | /* Wait for Wmi event to be ready */ | |
1572 | timeleft = wait_event_interruptible_timeout(ar->event_wq, | |
1573 | test_bit(WMI_READY, | |
1574 | &ar->flag), | |
1575 | WMI_TIMEOUT); | |
1576 | ||
1577 | ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n"); | |
1578 | ||
293badf4 KV |
1579 | |
1580 | if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) { | |
65a8b4cc | 1581 | ath6kl_info("%s %s fw %s api %d%s\n", |
293badf4 KV |
1582 | ar->hw.name, |
1583 | ath6kl_init_get_hif_name(ar->hif_type), | |
1584 | ar->wiphy->fw_version, | |
65a8b4cc | 1585 | ar->fw_api, |
293badf4 KV |
1586 | test_bit(TESTMODE, &ar->flag) ? " testmode" : ""); |
1587 | } | |
1588 | ||
20459ee2 KV |
1589 | if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { |
1590 | ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", | |
1591 | ATH6KL_ABI_VERSION, ar->version.abi_ver); | |
1592 | ret = -EIO; | |
1593 | goto err_htc_stop; | |
1594 | } | |
1595 | ||
1596 | if (!timeleft || signal_pending(current)) { | |
1597 | ath6kl_err("wmi is not ready or wait was interrupted\n"); | |
1598 | ret = -EIO; | |
1599 | goto err_htc_stop; | |
1600 | } | |
1601 | ||
1602 | ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); | |
1603 | ||
1604 | /* communicate the wmi protocol verision to the target */ | |
1605 | /* FIXME: return error */ | |
1606 | if ((ath6kl_set_host_app_area(ar)) != 0) | |
1607 | ath6kl_err("unable to set the host app area\n"); | |
1608 | ||
71f96ee6 | 1609 | for (i = 0; i < ar->vif_max; i++) { |
20459ee2 KV |
1610 | ret = ath6kl_target_config_wlan_params(ar, i); |
1611 | if (ret) | |
1612 | goto err_htc_stop; | |
1613 | } | |
1614 | ||
76a9fbe2 KV |
1615 | ar->state = ATH6KL_STATE_ON; |
1616 | ||
20459ee2 KV |
1617 | return 0; |
1618 | ||
1619 | err_htc_stop: | |
1620 | ath6kl_htc_stop(ar->htc_target); | |
1621 | err_cleanup_scatter: | |
1622 | ath6kl_hif_cleanup_scatter(ar); | |
1623 | err_power_off: | |
1624 | ath6kl_hif_power_off(ar); | |
1625 | ||
1626 | return ret; | |
1627 | } | |
1628 | ||
5fe4dffb KV |
1629 | int ath6kl_init_hw_stop(struct ath6kl *ar) |
1630 | { | |
1631 | int ret; | |
1632 | ||
1633 | ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n"); | |
1634 | ||
1635 | ath6kl_htc_stop(ar->htc_target); | |
1636 | ||
1637 | ath6kl_hif_stop(ar); | |
1638 | ||
1639 | ath6kl_bmi_reset(ar); | |
1640 | ||
1641 | ret = ath6kl_hif_power_off(ar); | |
1642 | if (ret) | |
1643 | ath6kl_warn("failed to power off hif: %d\n", ret); | |
1644 | ||
76a9fbe2 KV |
1645 | ar->state = ATH6KL_STATE_OFF; |
1646 | ||
5fe4dffb KV |
1647 | return 0; |
1648 | } | |
1649 | ||
c25889e8 | 1650 | /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */ |
55055976 | 1651 | void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready) |
6db8fa53 VT |
1652 | { |
1653 | static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | |
1654 | bool discon_issued; | |
1655 | ||
1656 | netif_stop_queue(vif->ndev); | |
1657 | ||
1658 | clear_bit(WLAN_ENABLED, &vif->flags); | |
1659 | ||
1660 | if (wmi_ready) { | |
1661 | discon_issued = test_bit(CONNECTED, &vif->flags) || | |
1662 | test_bit(CONNECT_PEND, &vif->flags); | |
1663 | ath6kl_disconnect(vif); | |
1664 | del_timer(&vif->disconnect_timer); | |
1665 | ||
1666 | if (discon_issued) | |
1667 | ath6kl_disconnect_event(vif, DISCONNECT_CMD, | |
1668 | (vif->nw_type & AP_NETWORK) ? | |
1669 | bcast_mac : vif->bssid, | |
1670 | 0, NULL, 0); | |
1671 | } | |
1672 | ||
1673 | if (vif->scan_req) { | |
1674 | cfg80211_scan_done(vif->scan_req, true); | |
1675 | vif->scan_req = NULL; | |
1676 | } | |
6db8fa53 VT |
1677 | } |
1678 | ||
bdcd8170 KV |
1679 | void ath6kl_stop_txrx(struct ath6kl *ar) |
1680 | { | |
990bd915 | 1681 | struct ath6kl_vif *vif, *tmp_vif; |
1d2a4456 | 1682 | int i; |
bdcd8170 KV |
1683 | |
1684 | set_bit(DESTROY_IN_PROGRESS, &ar->flag); | |
1685 | ||
1686 | if (down_interruptible(&ar->sem)) { | |
1687 | ath6kl_err("down_interruptible failed\n"); | |
1688 | return; | |
1689 | } | |
1690 | ||
1d2a4456 VT |
1691 | for (i = 0; i < AP_MAX_NUM_STA; i++) |
1692 | aggr_reset_state(ar->sta_list[i].aggr_conn); | |
1693 | ||
11f6e40d | 1694 | spin_lock_bh(&ar->list_lock); |
990bd915 VT |
1695 | list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) { |
1696 | list_del(&vif->list); | |
11f6e40d | 1697 | spin_unlock_bh(&ar->list_lock); |
990bd915 | 1698 | ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag)); |
27929723 | 1699 | rtnl_lock(); |
c25889e8 | 1700 | ath6kl_cfg80211_vif_cleanup(vif); |
27929723 | 1701 | rtnl_unlock(); |
11f6e40d | 1702 | spin_lock_bh(&ar->list_lock); |
990bd915 | 1703 | } |
11f6e40d | 1704 | spin_unlock_bh(&ar->list_lock); |
bdcd8170 | 1705 | |
6db8fa53 | 1706 | clear_bit(WMI_READY, &ar->flag); |
bdcd8170 | 1707 | |
6db8fa53 VT |
1708 | /* |
1709 | * After wmi_shudown all WMI events will be dropped. We | |
1710 | * need to cleanup the buffers allocated in AP mode and | |
1711 | * give disconnect notification to stack, which usually | |
1712 | * happens in the disconnect_event. Simulate the disconnect | |
1713 | * event by calling the function directly. Sometimes | |
1714 | * disconnect_event will be received when the debug logs | |
1715 | * are collected. | |
1716 | */ | |
1717 | ath6kl_wmi_shutdown(ar->wmi); | |
bdcd8170 | 1718 | |
6db8fa53 VT |
1719 | clear_bit(WMI_ENABLED, &ar->flag); |
1720 | if (ar->htc_target) { | |
1721 | ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__); | |
1722 | ath6kl_htc_stop(ar->htc_target); | |
bdcd8170 KV |
1723 | } |
1724 | ||
6db8fa53 VT |
1725 | /* |
1726 | * Try to reset the device if we can. The driver may have been | |
1727 | * configure NOT to reset the target during a debug session. | |
1728 | */ | |
1729 | ath6kl_dbg(ATH6KL_DBG_TRC, | |
1730 | "attempting to reset target on instance destroy\n"); | |
1731 | ath6kl_reset_device(ar, ar->target_type, true, true); | |
19703573 | 1732 | |
6db8fa53 | 1733 | clear_bit(WLAN_ENABLED, &ar->flag); |
bdcd8170 | 1734 | } |
d6a434d6 | 1735 | EXPORT_SYMBOL(ath6kl_stop_txrx); |