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ath6kl: Update license header
[deliverable/linux.git] / drivers / net / wireless / ath / ath6kl / sdio.c
CommitLineData
bdcd8170
KV		 1/*
2 * Copyright (c) 2004-2011 Atheros Communications Inc.
1b2df407 3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
bdcd8170
KV		 4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
9d9779e7 18#include <linux/module.h>
bdcd8170
KV		 19#include <linux/mmc/card.h>
20#include <linux/mmc/mmc.h>
21#include <linux/mmc/host.h>
22#include <linux/mmc/sdio_func.h>
23#include <linux/mmc/sdio_ids.h>
24#include <linux/mmc/sdio.h>
25#include <linux/mmc/sd.h>
2e1cb23c 26#include "hif.h"
bdcd8170
KV		 27#include "hif-ops.h"
28#include "target.h"
29#include "debug.h"
9df337a1 30#include "cfg80211.h"
bdcd8170
KV		 31
32struct ath6kl_sdio {
33 struct sdio_func *func;
34
35 spinlock_t lock;
36
37 /* free list */
38 struct list_head bus_req_freeq;
39
40 /* available bus requests */
41 struct bus_request bus_req[BUS_REQUEST_MAX_NUM];
42
43 struct ath6kl *ar;
fdb28589 44
bdcd8170
KV		 45 u8 *dma_buffer;
46
fdb28589
RM		 47 /* protects access to dma_buffer */
48 struct mutex dma_buffer_mutex;
49
bdcd8170
KV		 50 /* scatter request list head */
51 struct list_head scat_req;
52
9d82682d
VT		 53 /* Avoids disabling irq while the interrupts being handled */
54 struct mutex mtx_irq;
55
bdcd8170 56 spinlock_t scat_lock;
32a07e44
KV		 57 bool scatter_enabled;
58
bdcd8170 59 bool is_disabled;
bdcd8170
KV		 60 const struct sdio_device_id *id;
61 struct work_struct wr_async_work;
62 struct list_head wr_asyncq;
63 spinlock_t wr_async_lock;
64};
65
66#define CMD53_ARG_READ 0
67#define CMD53_ARG_WRITE 1
68#define CMD53_ARG_BLOCK_BASIS 1
69#define CMD53_ARG_FIXED_ADDRESS 0
70#define CMD53_ARG_INCR_ADDRESS 1
71
72static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar)
73{
74 return ar->hif_priv;
75}
76
77/*
78 * Macro to check if DMA buffer is WORD-aligned and DMA-able.
79 * Most host controllers assume the buffer is DMA'able and will
80 * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid
81 * check fails on stack memory.
82 */
83static inline bool buf_needs_bounce(u8 *buf)
84{
85 return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
86}
87
88static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar)
89{
90 struct ath6kl_mbox_info *mbox_info = &ar->mbox_info;
91
92 /* EP1 has an extended range */
93 mbox_info->htc_addr = HIF_MBOX_BASE_ADDR;
94 mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR;
95 mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH;
96 mbox_info->block_size = HIF_MBOX_BLOCK_SIZE;
97 mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR;
98 mbox_info->gmbox_sz = HIF_GMBOX_WIDTH;
99}
100
101static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
102 u8 mode, u8 opcode, u32 addr,
103 u16 blksz)
104{
105 *arg = (((rw & 1) << 31) |
106 ((func & 0x7) << 28) |
107 ((mode & 1) << 27) |
108 ((opcode & 1) << 26) |
109 ((addr & 0x1FFFF) << 9) |
110 (blksz & 0x1FF));
111}
112
113static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
114 unsigned int address,
115 unsigned char val)
116{
117 const u8 func = 0;
118
119 *arg = ((write & 1) << 31) |
120 ((func & 0x7) << 28) |
121 ((raw & 1) << 27) |
122 (1 << 26) |
123 ((address & 0x1FFFF) << 9) |
124 (1 << 8) |
125 (val & 0xFF);
126}
127
128static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
129 unsigned int address,
130 unsigned char byte)
131{
132 struct mmc_command io_cmd;
133
134 memset(&io_cmd, 0, sizeof(io_cmd));
135 ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
136 io_cmd.opcode = SD_IO_RW_DIRECT;
137 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
138
139 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
140}
141
da220695
VT		 142static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr,
143 u8 *buf, u32 len)
144{
145 int ret = 0;
146
861dd058
VT		 147 sdio_claim_host(func);
148
da220695 149 if (request & HIF_WRITE) {
f7325b85 150 /* FIXME: looks like ugly workaround for something */
da220695
VT		 151 if (addr >= HIF_MBOX_BASE_ADDR &&
152 addr <= HIF_MBOX_END_ADDR)
153 addr += (HIF_MBOX_WIDTH - len);
154
f7325b85 155 /* FIXME: this also looks like ugly workaround */
da220695
VT		 156 if (addr == HIF_MBOX0_EXT_BASE_ADDR)
157 addr += HIF_MBOX0_EXT_WIDTH - len;
158
159 if (request & HIF_FIXED_ADDRESS)
160 ret = sdio_writesb(func, addr, buf, len);
161 else
162 ret = sdio_memcpy_toio(func, addr, buf, len);
163 } else {
164 if (request & HIF_FIXED_ADDRESS)
165 ret = sdio_readsb(func, buf, addr, len);
166 else
167 ret = sdio_memcpy_fromio(func, buf, addr, len);
168 }
169
861dd058
VT		 170 sdio_release_host(func);
171
f7325b85
KV		 172 ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n",
173 request & HIF_WRITE ? "wr" : "rd", addr,
174 request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len);
175 ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len);
176
da220695
VT		 177 return ret;
178}
179
bdcd8170
KV		 180static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio)
181{
182 struct bus_request *bus_req;
bdcd8170 183
151bd30b 184 spin_lock_bh(&ar_sdio->lock);
bdcd8170
KV		 185
186 if (list_empty(&ar_sdio->bus_req_freeq)) {
151bd30b 187 spin_unlock_bh(&ar_sdio->lock);
bdcd8170
KV		 188 return NULL;
189 }
190
191 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
192 struct bus_request, list);
193 list_del(&bus_req->list);
194
151bd30b 195 spin_unlock_bh(&ar_sdio->lock);
f7325b85
KV		 196 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
197 __func__, bus_req);
bdcd8170
KV		 198
199 return bus_req;
200}
201
202static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio,
203 struct bus_request *bus_req)
204{
f7325b85
KV		 205 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
206 __func__, bus_req);
bdcd8170 207
151bd30b 208 spin_lock_bh(&ar_sdio->lock);
bdcd8170 209 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
151bd30b 210 spin_unlock_bh(&ar_sdio->lock);
bdcd8170
KV		 211}
212
213static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req,
bdcd8170
KV		 214 struct mmc_data *data)
215{
216 struct scatterlist *sg;
217 int i;
218
219 data->blksz = HIF_MBOX_BLOCK_SIZE;
220 data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE;
221
222 ath6kl_dbg(ATH6KL_DBG_SCATTER,
223 "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
224 (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr,
225 data->blksz, data->blocks, scat_req->len,
226 scat_req->scat_entries);
227
228 data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE :
229 MMC_DATA_READ;
230
231 /* fill SG entries */
d4df7890 232 sg = scat_req->sgentries;
bdcd8170
KV		 233 sg_init_table(sg, scat_req->scat_entries);
234
235 /* assemble SG list */
236 for (i = 0; i < scat_req->scat_entries; i++, sg++) {
bdcd8170
KV		 237 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n",
238 i, scat_req->scat_list[i].buf,
239 scat_req->scat_list[i].len);
240
241 sg_set_buf(sg, scat_req->scat_list[i].buf,
242 scat_req->scat_list[i].len);
243 }
244
245 /* set scatter-gather table for request */
d4df7890 246 data->sg = scat_req->sgentries;
bdcd8170
KV		 247 data->sg_len = scat_req->scat_entries;
248}
249
250static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio,
251 struct bus_request *req)
252{
253 struct mmc_request mmc_req;
254 struct mmc_command cmd;
255 struct mmc_data data;
256 struct hif_scatter_req *scat_req;
257 u8 opcode, rw;
348a8fbc 258 int status, len;
bdcd8170
KV		 259
260 scat_req = req->scat_req;
261
348a8fbc
VT		 262 if (scat_req->virt_scat) {
263 len = scat_req->len;
264 if (scat_req->req & HIF_BLOCK_BASIS)
265 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
266
267 status = ath6kl_sdio_io(ar_sdio->func, scat_req->req,
268 scat_req->addr, scat_req->virt_dma_buf,
269 len);
270 goto scat_complete;
271 }
272
bdcd8170
KV		 273 memset(&mmc_req, 0, sizeof(struct mmc_request));
274 memset(&cmd, 0, sizeof(struct mmc_command));
275 memset(&data, 0, sizeof(struct mmc_data));
276
d4df7890 277 ath6kl_sdio_setup_scat_data(scat_req, &data);
bdcd8170
KV		 278
279 opcode = (scat_req->req & HIF_FIXED_ADDRESS) ?
280 CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS;
281
282 rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
283
284 /* Fixup the address so that the last byte will fall on MBOX EOM */
285 if (scat_req->req & HIF_WRITE) {
286 if (scat_req->addr == HIF_MBOX_BASE_ADDR)
287 scat_req->addr += HIF_MBOX_WIDTH - scat_req->len;
288 else
289 /* Uses extended address range */
290 scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len;
291 }
292
293 /* set command argument */
294 ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num,
295 CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr,
296 data.blocks);
297
298 cmd.opcode = SD_IO_RW_EXTENDED;
299 cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
300
301 mmc_req.cmd = &cmd;
302 mmc_req.data = &data;
303
861dd058
VT		 304 sdio_claim_host(ar_sdio->func);
305
bdcd8170
KV		 306 mmc_set_data_timeout(&data, ar_sdio->func->card);
307 /* synchronous call to process request */
308 mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req);
309
861dd058
VT		 310 sdio_release_host(ar_sdio->func);
311
bdcd8170 312 status = cmd.error ? cmd.error : data.error;
348a8fbc
VT		 313
314scat_complete:
bdcd8170
KV		 315 scat_req->status = status;
316
317 if (scat_req->status)
318 ath6kl_err("Scatter write request failed:%d\n",
319 scat_req->status);
320
321 if (scat_req->req & HIF_ASYNCHRONOUS)
e041c7f9 322 scat_req->complete(ar_sdio->ar->htc_target, scat_req);
bdcd8170
KV		 323
324 return status;
325}
326
3df505ad
VT		 327static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio,
328 int n_scat_entry, int n_scat_req,
329 bool virt_scat)
330{
331 struct hif_scatter_req *s_req;
332 struct bus_request *bus_req;
cfeab10b
VT		 333 int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz;
334 u8 *virt_buf;
3df505ad
VT		 335
336 scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item);
337 scat_req_sz = sizeof(*s_req) + scat_list_sz;
338
339 if (!virt_scat)
340 sg_sz = sizeof(struct scatterlist) * n_scat_entry;
cfeab10b
VT		 341 else
342 buf_sz = 2 * L1_CACHE_BYTES +
343 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
3df505ad
VT		 344
345 for (i = 0; i < n_scat_req; i++) {
346 /* allocate the scatter request */
347 s_req = kzalloc(scat_req_sz, GFP_KERNEL);
348 if (!s_req)
349 return -ENOMEM;
350
cfeab10b
VT		 351 if (virt_scat) {
352 virt_buf = kzalloc(buf_sz, GFP_KERNEL);
353 if (!virt_buf) {
354 kfree(s_req);
355 return -ENOMEM;
356 }
357
358 s_req->virt_dma_buf =
359 (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf);
360 } else {
3df505ad
VT		 361 /* allocate sglist */
362 s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL);
363
364 if (!s_req->sgentries) {
365 kfree(s_req);
366 return -ENOMEM;
367 }
368 }
369
370 /* allocate a bus request for this scatter request */
371 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
372 if (!bus_req) {
373 kfree(s_req->sgentries);
cfeab10b 374 kfree(s_req->virt_dma_buf);
3df505ad
VT		 375 kfree(s_req);
376 return -ENOMEM;
377 }
378
379 /* assign the scatter request to this bus request */
380 bus_req->scat_req = s_req;
381 s_req->busrequest = bus_req;
382
4a005c3e
VT		 383 s_req->virt_scat = virt_scat;
384
3df505ad
VT		 385 /* add it to the scatter pool */
386 hif_scatter_req_add(ar_sdio->ar, s_req);
387 }
388
389 return 0;
390}
391
bdcd8170
KV		 392static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf,
393 u32 len, u32 request)
394{
395 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
396 u8 *tbuf = NULL;
397 int ret;
398 bool bounced = false;
399
400 if (request & HIF_BLOCK_BASIS)
401 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
402
403 if (buf_needs_bounce(buf)) {
404 if (!ar_sdio->dma_buffer)
405 return -ENOMEM;
fdb28589 406 mutex_lock(&ar_sdio->dma_buffer_mutex);
bdcd8170
KV		 407 tbuf = ar_sdio->dma_buffer;
408 memcpy(tbuf, buf, len);
409 bounced = true;
410 } else
411 tbuf = buf;
412
da220695
VT		 413 ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len);
414 if ((request & HIF_READ) && bounced)
415 memcpy(buf, tbuf, len);
bdcd8170 416
fdb28589
RM		 417 if (bounced)
418 mutex_unlock(&ar_sdio->dma_buffer_mutex);
419
bdcd8170
KV		 420 return ret;
421}
422
423static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio,
424 struct bus_request *req)
425{
426 if (req->scat_req)
427 ath6kl_sdio_scat_rw(ar_sdio, req);
428 else {
429 void *context;
430 int status;
431
432 status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address,
433 req->buffer, req->length,
434 req->request);
435 context = req->packet;
436 ath6kl_sdio_free_bus_req(ar_sdio, req);
8e8ddb2b 437 ath6kl_hif_rw_comp_handler(context, status);
bdcd8170
KV		 438 }
439}
440
441static void ath6kl_sdio_write_async_work(struct work_struct *work)
442{
443 struct ath6kl_sdio *ar_sdio;
bdcd8170
KV		 444 struct bus_request *req, *tmp_req;
445
446 ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work);
bdcd8170 447
151bd30b 448 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 449 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
450 list_del(&req->list);
151bd30b 451 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170 452 __ath6kl_sdio_write_async(ar_sdio, req);
151bd30b 453 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170 454 }
151bd30b 455 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 456}
457
458static void ath6kl_sdio_irq_handler(struct sdio_func *func)
459{
460 int status;
461 struct ath6kl_sdio *ar_sdio;
462
f7325b85
KV		 463 ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n");
464
bdcd8170 465 ar_sdio = sdio_get_drvdata(func);
9d82682d 466 mutex_lock(&ar_sdio->mtx_irq);
bdcd8170
KV		 467 /*
468 * Release the host during interrups so we can pick it back up when
469 * we process commands.
470 */
471 sdio_release_host(ar_sdio->func);
472
8e8ddb2b 473 status = ath6kl_hif_intr_bh_handler(ar_sdio->ar);
bdcd8170 474 sdio_claim_host(ar_sdio->func);
9d82682d 475 mutex_unlock(&ar_sdio->mtx_irq);
bdcd8170
KV		 476 WARN_ON(status && status != -ECANCELED);
477}
478
b2e75698 479static int ath6kl_sdio_power_on(struct ath6kl *ar)
bdcd8170 480{
b2e75698 481 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170
KV		 482 struct sdio_func *func = ar_sdio->func;
483 int ret = 0;
484
485 if (!ar_sdio->is_disabled)
486 return 0;
487
3ef987be
KV		 488 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n");
489
bdcd8170
KV		 490 sdio_claim_host(func);
491
492 ret = sdio_enable_func(func);
493 if (ret) {
494 ath6kl_err("Unable to enable sdio func: %d)\n", ret);
495 sdio_release_host(func);
496 return ret;
497 }
498
499 sdio_release_host(func);
500
501 /*
502 * Wait for hardware to initialise. It should take a lot less than
503 * 10 ms but let's be conservative here.
504 */
505 msleep(10);
506
507 ar_sdio->is_disabled = false;
508
509 return ret;
510}
511
b2e75698 512static int ath6kl_sdio_power_off(struct ath6kl *ar)
bdcd8170 513{
b2e75698 514 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170
KV		 515 int ret;
516
517 if (ar_sdio->is_disabled)
518 return 0;
519
3ef987be
KV		 520 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n");
521
bdcd8170
KV		 522 /* Disable the card */
523 sdio_claim_host(ar_sdio->func);
524 ret = sdio_disable_func(ar_sdio->func);
525 sdio_release_host(ar_sdio->func);
526
527 if (ret)
528 return ret;
529
530 ar_sdio->is_disabled = true;
531
532 return ret;
533}
534
535static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer,
536 u32 length, u32 request,
537 struct htc_packet *packet)
538{
539 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
540 struct bus_request *bus_req;
bdcd8170
KV		 541
542 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
543
544 if (!bus_req)
545 return -ENOMEM;
546
547 bus_req->address = address;
548 bus_req->buffer = buffer;
549 bus_req->length = length;
550 bus_req->request = request;
551 bus_req->packet = packet;
552
151bd30b 553 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170 554 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
151bd30b 555 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 556 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
557
558 return 0;
559}
560
561static void ath6kl_sdio_irq_enable(struct ath6kl *ar)
562{
563 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
564 int ret;
565
566 sdio_claim_host(ar_sdio->func);
567
568 /* Register the isr */
569 ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler);
570 if (ret)
571 ath6kl_err("Failed to claim sdio irq: %d\n", ret);
572
573 sdio_release_host(ar_sdio->func);
574}
575
576static void ath6kl_sdio_irq_disable(struct ath6kl *ar)
577{
578 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
579 int ret;
580
581 sdio_claim_host(ar_sdio->func);
582
9d82682d 583 mutex_lock(&ar_sdio->mtx_irq);
bdcd8170
KV		 584
585 ret = sdio_release_irq(ar_sdio->func);
586 if (ret)
587 ath6kl_err("Failed to release sdio irq: %d\n", ret);
588
9d82682d
VT		 589 mutex_unlock(&ar_sdio->mtx_irq);
590
bdcd8170
KV		 591 sdio_release_host(ar_sdio->func);
592}
593
594static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar)
595{
596 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
597 struct hif_scatter_req *node = NULL;
bdcd8170 598
151bd30b 599 spin_lock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 600
601 if (!list_empty(&ar_sdio->scat_req)) {
602 node = list_first_entry(&ar_sdio->scat_req,
603 struct hif_scatter_req, list);
604 list_del(&node->list);
605 }
606
151bd30b 607 spin_unlock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 608
609 return node;
610}
611
612static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar,
613 struct hif_scatter_req *s_req)
614{
615 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170 616
151bd30b 617 spin_lock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 618
619 list_add_tail(&s_req->list, &ar_sdio->scat_req);
620
151bd30b 621 spin_unlock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 622
623}
624
c630d18a
VT		 625/* scatter gather read write request */
626static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar,
627 struct hif_scatter_req *scat_req)
628{
629 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
c630d18a
VT		 630 u32 request = scat_req->req;
631 int status = 0;
c630d18a
VT		 632
633 if (!scat_req->len)
634 return -EINVAL;
635
636 ath6kl_dbg(ATH6KL_DBG_SCATTER,
637 "hif-scatter: total len: %d scatter entries: %d\n",
638 scat_req->len, scat_req->scat_entries);
639
861dd058 640 if (request & HIF_SYNCHRONOUS)
d4df7890 641 status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest);
861dd058 642 else {
151bd30b 643 spin_lock_bh(&ar_sdio->wr_async_lock);
d4df7890 644 list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq);
151bd30b 645 spin_unlock_bh(&ar_sdio->wr_async_lock);
c630d18a
VT		 646 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
647 }
648
649 return status;
650}
651
18a0f93e
VT		 652/* clean up scatter support */
653static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar)
654{
655 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
656 struct hif_scatter_req *s_req, *tmp_req;
18a0f93e
VT		 657
658 /* empty the free list */
151bd30b 659 spin_lock_bh(&ar_sdio->scat_lock);
18a0f93e
VT		 660 list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) {
661 list_del(&s_req->list);
151bd30b 662 spin_unlock_bh(&ar_sdio->scat_lock);
18a0f93e 663
32a07e44
KV		 664 /*
665 * FIXME: should we also call completion handler with
666 * ath6kl_hif_rw_comp_handler() with status -ECANCELED so
667 * that the packet is properly freed?
668 */
18a0f93e
VT		 669 if (s_req->busrequest)
670 ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest);
671 kfree(s_req->virt_dma_buf);
672 kfree(s_req->sgentries);
673 kfree(s_req);
674
151bd30b 675 spin_lock_bh(&ar_sdio->scat_lock);
18a0f93e 676 }
151bd30b 677 spin_unlock_bh(&ar_sdio->scat_lock);
18a0f93e
VT		 678}
679
680/* setup of HIF scatter resources */
50745af7 681static int ath6kl_sdio_enable_scatter(struct ath6kl *ar)
18a0f93e
VT		 682{
683 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
50745af7 684 struct htc_target *target = ar->htc_target;
cfeab10b
VT		 685 int ret;
686 bool virt_scat = false;
18a0f93e 687
32a07e44
KV		 688 if (ar_sdio->scatter_enabled)
689 return 0;
690
691 ar_sdio->scatter_enabled = true;
692
18a0f93e
VT		 693 /* check if host supports scatter and it meets our requirements */
694 if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
cfeab10b 695 ath6kl_err("host only supports scatter of :%d entries, need: %d\n",
18a0f93e
VT		 696 ar_sdio->func->card->host->max_segs,
697 MAX_SCATTER_ENTRIES_PER_REQ);
cfeab10b 698 virt_scat = true;
18a0f93e
VT		 699 }
700
cfeab10b
VT		 701 if (!virt_scat) {
702 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
703 MAX_SCATTER_ENTRIES_PER_REQ,
704 MAX_SCATTER_REQUESTS, virt_scat);
705
706 if (!ret) {
3ef987be
KV		 707 ath6kl_dbg(ATH6KL_DBG_BOOT,
708 "hif-scatter enabled requests %d entries %d\n",
cfeab10b
VT		 709 MAX_SCATTER_REQUESTS,
710 MAX_SCATTER_ENTRIES_PER_REQ);
711
50745af7
VT		 712 target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ;
713 target->max_xfer_szper_scatreq =
cfeab10b
VT		 714 MAX_SCATTER_REQ_TRANSFER_SIZE;
715 } else {
716 ath6kl_sdio_cleanup_scatter(ar);
717 ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n");
718 }
719 }
18a0f93e 720
cfeab10b
VT		 721 if (virt_scat || ret) {
722 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
723 ATH6KL_SCATTER_ENTRIES_PER_REQ,
724 ATH6KL_SCATTER_REQS, virt_scat);
725
726 if (ret) {
727 ath6kl_err("failed to alloc virtual scatter resources !\n");
728 ath6kl_sdio_cleanup_scatter(ar);
729 return ret;
730 }
731
3ef987be
KV		 732 ath6kl_dbg(ATH6KL_DBG_BOOT,
733 "virtual scatter enabled requests %d entries %d\n",
cfeab10b
VT		 734 ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ);
735
50745af7
VT		 736 target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ;
737 target->max_xfer_szper_scatreq =
cfeab10b 738 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
18a0f93e
VT		 739 }
740
18a0f93e
VT		 741 return 0;
742}
743
e28e8104
KV		 744static int ath6kl_sdio_config(struct ath6kl *ar)
745{
746 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
747 struct sdio_func *func = ar_sdio->func;
748 int ret;
749
750 sdio_claim_host(func);
751
752 if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >=
753 MANUFACTURER_ID_AR6003_BASE) {
754 /* enable 4-bit ASYNC interrupt on AR6003 or later */
755 ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card,
756 CCCR_SDIO_IRQ_MODE_REG,
757 SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
758 if (ret) {
759 ath6kl_err("Failed to enable 4-bit async irq mode %d\n",
760 ret);
761 goto out;
762 }
763
764 ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n");
765 }
766
767 /* give us some time to enable, in ms */
768 func->enable_timeout = 100;
769
770 ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
771 if (ret) {
772 ath6kl_err("Set sdio block size %d failed: %d)\n",
773 HIF_MBOX_BLOCK_SIZE, ret);
e28e8104
KV		 774 goto out;
775 }
776
777out:
778 sdio_release_host(func);
779
780 return ret;
781}
782
e390af77 783static int ath6kl_set_sdio_pm_caps(struct ath6kl *ar)
abcb344b
KV		 784{
785 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
786 struct sdio_func *func = ar_sdio->func;
787 mmc_pm_flag_t flags;
788 int ret;
789
790 flags = sdio_get_host_pm_caps(func);
791
b4b2a0b1
KV		 792 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags);
793
e390af77
RM		 794 if (!(flags & MMC_PM_WAKE_SDIO_IRQ) ||
795 !(flags & MMC_PM_KEEP_POWER))
796 return -EINVAL;
abcb344b
KV		 797
798 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
799 if (ret) {
e390af77 800 ath6kl_err("set sdio keep pwr flag failed: %d\n", ret);
abcb344b
KV		 801 return ret;
802 }
803
10509f90 804 /* sdio irq wakes up host */
e390af77
RM		 805 ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ);
806 if (ret)
807 ath6kl_err("set sdio wake irq flag failed: %d\n", ret);
808
809 return ret;
810}
811
812static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow)
813{
814 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
815 struct sdio_func *func = ar_sdio->func;
816 mmc_pm_flag_t flags;
817 int ret;
10509f90
KV		 818
819 if (ar->state == ATH6KL_STATE_SCHED_SCAN) {
e390af77
RM		 820 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sched scan is in progress\n");
821
822 ret = ath6kl_set_sdio_pm_caps(ar);
823 if (ret)
824 goto cut_pwr;
825
10509f90
KV		 826 ret = ath6kl_cfg80211_suspend(ar,
827 ATH6KL_CFG_SUSPEND_SCHED_SCAN,
828 NULL);
10509f90 829 if (ret)
e390af77 830 goto cut_pwr;
10509f90 831
e390af77 832 return 0;
10509f90
KV		 833 }
834
e390af77
RM		 835 if (ar->suspend_mode == WLAN_POWER_STATE_WOW ||
836 (!ar->suspend_mode && wow)) {
837
838 ret = ath6kl_set_sdio_pm_caps(ar);
839 if (ret)
840 goto cut_pwr;
841
d7c44e0b
RM		 842 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow);
843 if (ret)
e390af77
RM		 844 goto cut_pwr;
845
846 return 0;
847 }
848
849 if (ar->suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP ||
850 !ar->suspend_mode) {
d7c44e0b 851
e390af77
RM		 852 flags = sdio_get_host_pm_caps(func);
853 if (!(flags & MMC_PM_KEEP_POWER))
854 goto cut_pwr;
855
856 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
d7c44e0b 857 if (ret)
e390af77 858 goto cut_pwr;
d7c44e0b 859
cca4d5ad
SS		 860 /*
861 * Workaround to support Deep Sleep with MSM, set the host pm
862 * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable
863 * the sdc2_clock and internally allows MSM to enter
864 * TCXO shutdown properly.
865 */
866 if ((flags & MMC_PM_WAKE_SDIO_IRQ)) {
867 ret = sdio_set_host_pm_flags(func,
868 MMC_PM_WAKE_SDIO_IRQ);
869 if (ret)
870 goto cut_pwr;
871 }
872
e390af77
RM		 873 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP,
874 NULL);
875 if (ret)
876 goto cut_pwr;
877
878 return 0;
d7c44e0b
RM		 879 }
880
e390af77
RM		 881cut_pwr:
882 return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, NULL);
abcb344b
KV		 883}
884
aa6cffc1
CN		 885static int ath6kl_sdio_resume(struct ath6kl *ar)
886{
b4b2a0b1
KV		 887 switch (ar->state) {
888 case ATH6KL_STATE_OFF:
889 case ATH6KL_STATE_CUTPOWER:
890 ath6kl_dbg(ATH6KL_DBG_SUSPEND,
891 "sdio resume configuring sdio\n");
892
893 /* need to set sdio settings after power is cut from sdio */
894 ath6kl_sdio_config(ar);
895 break;
896
897 case ATH6KL_STATE_ON:
b4b2a0b1
KV		 898 break;
899
900 case ATH6KL_STATE_DEEPSLEEP:
901 break;
d7c44e0b
RM		 902
903 case ATH6KL_STATE_WOW:
904 break;
10509f90
KV		 905 case ATH6KL_STATE_SCHED_SCAN:
906 break;
b4b2a0b1
KV		 907 }
908
52d81a68 909 ath6kl_cfg80211_resume(ar);
aa6cffc1
CN		 910
911 return 0;
912}
913
c7111495
KV		 914/* set the window address register (using 4-byte register access ). */
915static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
916{
917 int status;
918 u8 addr_val[4];
919 s32 i;
920
921 /*
922 * Write bytes 1,2,3 of the register to set the upper address bytes,
923 * the LSB is written last to initiate the access cycle
924 */
925
926 for (i = 1; i <= 3; i++) {
927 /*
928 * Fill the buffer with the address byte value we want to
929 * hit 4 times.
930 */
931 memset(addr_val, ((u8 *)&addr)[i], 4);
932
933 /*
934 * Hit each byte of the register address with a 4-byte
935 * write operation to the same address, this is a harmless
936 * operation.
937 */
938 status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val,
939 4, HIF_WR_SYNC_BYTE_FIX);
940 if (status)
941 break;
942 }
943
944 if (status) {
945 ath6kl_err("%s: failed to write initial bytes of 0x%x "
946 "to window reg: 0x%X\n", __func__,
947 addr, reg_addr);
948 return status;
949 }
950
951 /*
952 * Write the address register again, this time write the whole
953 * 4-byte value. The effect here is that the LSB write causes the
954 * cycle to start, the extra 3 byte write to bytes 1,2,3 has no
955 * effect since we are writing the same values again
956 */
957 status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr),
958 4, HIF_WR_SYNC_BYTE_INC);
959
960 if (status) {
961 ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n",
962 __func__, addr, reg_addr);
963 return status;
964 }
965
966 return 0;
967}
968
969static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data)
970{
971 int status;
972
973 /* set window register to start read cycle */
974 status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS,
975 address);
976
977 if (status)
978 return status;
979
980 /* read the data */
981 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
982 (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC);
983 if (status) {
984 ath6kl_err("%s: failed to read from window data addr\n",
985 __func__);
986 return status;
987 }
988
989 return status;
990}
991
992static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address,
993 __le32 data)
994{
995 int status;
996 u32 val = (__force u32) data;
997
998 /* set write data */
999 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
1000 (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC);
1001 if (status) {
1002 ath6kl_err("%s: failed to write 0x%x to window data addr\n",
1003 __func__, data);
1004 return status;
1005 }
1006
1007 /* set window register, which starts the write cycle */
1008 return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS,
1009 address);
1010}
1011
66b693c3
KV		 1012static int ath6kl_sdio_bmi_credits(struct ath6kl *ar)
1013{
1014 u32 addr;
1015 unsigned long timeout;
1016 int ret;
1017
1018 ar->bmi.cmd_credits = 0;
1019
1020 /* Read the counter register to get the command credits */
1021 addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
1022
1023 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
1024 while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) {
1025
1026 /*
1027 * Hit the credit counter with a 4-byte access, the first byte
1028 * read will hit the counter and cause a decrement, while the
1029 * remaining 3 bytes has no effect. The rationale behind this
1030 * is to make all HIF accesses 4-byte aligned.
1031 */
1032 ret = ath6kl_sdio_read_write_sync(ar, addr,
1033 (u8 *)&ar->bmi.cmd_credits, 4,
1034 HIF_RD_SYNC_BYTE_INC);
1035 if (ret) {
1036 ath6kl_err("Unable to decrement the command credit "
1037 "count register: %d\n", ret);
1038 return ret;
1039 }
1040
1041 /* The counter is only 8 bits.
1042 * Ignore anything in the upper 3 bytes
1043 */
1044 ar->bmi.cmd_credits &= 0xFF;
1045 }
1046
1047 if (!ar->bmi.cmd_credits) {
1048 ath6kl_err("bmi communication timeout\n");
1049 return -ETIMEDOUT;
1050 }
1051
1052 return 0;
1053}
1054
1055static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar)
1056{
1057 unsigned long timeout;
1058 u32 rx_word = 0;
1059 int ret = 0;
1060
1061 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
1062 while ((time_before(jiffies, timeout)) && !rx_word) {
1063 ret = ath6kl_sdio_read_write_sync(ar,
1064 RX_LOOKAHEAD_VALID_ADDRESS,
1065 (u8 *)&rx_word, sizeof(rx_word),
1066 HIF_RD_SYNC_BYTE_INC);
1067 if (ret) {
1068 ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n");
1069 return ret;
1070 }
1071
1072 /* all we really want is one bit */
1073 rx_word &= (1 << ENDPOINT1);
1074 }
1075
1076 if (!rx_word) {
1077 ath6kl_err("bmi_recv_buf FIFO empty\n");
1078 return -EINVAL;
1079 }
1080
1081 return ret;
1082}
1083
1084static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len)
1085{
1086 int ret;
1087 u32 addr;
1088
1089 ret = ath6kl_sdio_bmi_credits(ar);
1090 if (ret)
1091 return ret;
1092
1093 addr = ar->mbox_info.htc_addr;
1094
1095 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1096 HIF_WR_SYNC_BYTE_INC);
1097 if (ret)
1098 ath6kl_err("unable to send the bmi data to the device\n");
1099
1100 return ret;
1101}
1102
1103static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len)
1104{
1105 int ret;
1106 u32 addr;
1107
1108 /*
1109 * During normal bootup, small reads may be required.
1110 * Rather than issue an HIF Read and then wait as the Target
1111 * adds successive bytes to the FIFO, we wait here until
1112 * we know that response data is available.
1113 *
1114 * This allows us to cleanly timeout on an unexpected
1115 * Target failure rather than risk problems at the HIF level.
1116 * In particular, this avoids SDIO timeouts and possibly garbage
1117 * data on some host controllers. And on an interconnect
1118 * such as Compact Flash (as well as some SDIO masters) which
1119 * does not provide any indication on data timeout, it avoids
1120 * a potential hang or garbage response.
1121 *
1122 * Synchronization is more difficult for reads larger than the
1123 * size of the MBOX FIFO (128B), because the Target is unable
1124 * to push the 129th byte of data until AFTER the Host posts an
1125 * HIF Read and removes some FIFO data. So for large reads the
1126 * Host proceeds to post an HIF Read BEFORE all the data is
1127 * actually available to read. Fortunately, large BMI reads do
1128 * not occur in practice -- they're supported for debug/development.
1129 *
1130 * So Host/Target BMI synchronization is divided into these cases:
1131 * CASE 1: length < 4
1132 * Should not happen
1133 *
1134 * CASE 2: 4 <= length <= 128
1135 * Wait for first 4 bytes to be in FIFO
1136 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1137 * a BMI command credit, which indicates that the ENTIRE
1138 * response is available in the the FIFO
1139 *
1140 * CASE 3: length > 128
1141 * Wait for the first 4 bytes to be in FIFO
1142 *
1143 * For most uses, a small timeout should be sufficient and we will
1144 * usually see a response quickly; but there may be some unusual
1145 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1146 * For now, we use an unbounded busy loop while waiting for
1147 * BMI_EXECUTE.
1148 *
1149 * If BMI_EXECUTE ever needs to support longer-latency execution,
1150 * especially in production, this code needs to be enhanced to sleep
1151 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1152 * a function of Host processor speed.
1153 */
1154 if (len >= 4) { /* NB: Currently, always true */
1155 ret = ath6kl_bmi_get_rx_lkahd(ar);
1156 if (ret)
1157 return ret;
1158 }
1159
1160 addr = ar->mbox_info.htc_addr;
1161 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1162 HIF_RD_SYNC_BYTE_INC);
1163 if (ret) {
1164 ath6kl_err("Unable to read the bmi data from the device: %d\n",
1165 ret);
1166 return ret;
1167 }
1168
1169 return 0;
1170}
1171
32a07e44
KV		 1172static void ath6kl_sdio_stop(struct ath6kl *ar)
1173{
1174 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
1175 struct bus_request *req, *tmp_req;
1176 void *context;
1177
1178 /* FIXME: make sure that wq is not queued again */
1179
1180 cancel_work_sync(&ar_sdio->wr_async_work);
1181
1182 spin_lock_bh(&ar_sdio->wr_async_lock);
1183
1184 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1185 list_del(&req->list);
1186
1187 if (req->scat_req) {
1188 /* this is a scatter gather request */
1189 req->scat_req->status = -ECANCELED;
1190 req->scat_req->complete(ar_sdio->ar->htc_target,
1191 req->scat_req);
1192 } else {
1193 context = req->packet;
1194 ath6kl_sdio_free_bus_req(ar_sdio, req);
1195 ath6kl_hif_rw_comp_handler(context, -ECANCELED);
1196 }
1197 }
1198
1199 spin_unlock_bh(&ar_sdio->wr_async_lock);
1200
1201 WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4);
1202}
1203
bdcd8170
KV		 1204static const struct ath6kl_hif_ops ath6kl_sdio_ops = {
1205 .read_write_sync = ath6kl_sdio_read_write_sync,
1206 .write_async = ath6kl_sdio_write_async,
1207 .irq_enable = ath6kl_sdio_irq_enable,
1208 .irq_disable = ath6kl_sdio_irq_disable,
1209 .scatter_req_get = ath6kl_sdio_scatter_req_get,
1210 .scatter_req_add = ath6kl_sdio_scatter_req_add,
1211 .enable_scatter = ath6kl_sdio_enable_scatter,
f74a7361 1212 .scat_req_rw = ath6kl_sdio_async_rw_scatter,
bdcd8170 1213 .cleanup_scatter = ath6kl_sdio_cleanup_scatter,
abcb344b 1214 .suspend = ath6kl_sdio_suspend,
aa6cffc1 1215 .resume = ath6kl_sdio_resume,
c7111495
KV		 1216 .diag_read32 = ath6kl_sdio_diag_read32,
1217 .diag_write32 = ath6kl_sdio_diag_write32,
66b693c3
KV		 1218 .bmi_read = ath6kl_sdio_bmi_read,
1219 .bmi_write = ath6kl_sdio_bmi_write,
b2e75698
KV		 1220 .power_on = ath6kl_sdio_power_on,
1221 .power_off = ath6kl_sdio_power_off,
32a07e44 1222 .stop = ath6kl_sdio_stop,
bdcd8170
KV		 1223};
1224
b4b2a0b1
KV		 1225#ifdef CONFIG_PM_SLEEP
1226
1227/*
1228 * Empty handlers so that mmc subsystem doesn't remove us entirely during
1229 * suspend. We instead follow cfg80211 suspend/resume handlers.
1230 */
1231static int ath6kl_sdio_pm_suspend(struct device *device)
1232{
1233 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n");
1234
1235 return 0;
1236}
1237
1238static int ath6kl_sdio_pm_resume(struct device *device)
1239{
1240 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n");
1241
1242 return 0;
1243}
1244
1245static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend,
1246 ath6kl_sdio_pm_resume);
1247
1248#define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops)
1249
1250#else
1251
1252#define ATH6KL_SDIO_PM_OPS NULL
1253
1254#endif /* CONFIG_PM_SLEEP */
1255
bdcd8170
KV		 1256static int ath6kl_sdio_probe(struct sdio_func *func,
1257 const struct sdio_device_id *id)
1258{
1259 int ret;
1260 struct ath6kl_sdio *ar_sdio;
1261 struct ath6kl *ar;
1262 int count;
1263
3ef987be
KV		 1264 ath6kl_dbg(ATH6KL_DBG_BOOT,
1265 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
f7325b85
KV		 1266 func->num, func->vendor, func->device,
1267 func->max_blksize, func->cur_blksize);
bdcd8170
KV		 1268
1269 ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL);
1270 if (!ar_sdio)
1271 return -ENOMEM;
1272
1273 ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
1274 if (!ar_sdio->dma_buffer) {
1275 ret = -ENOMEM;
1276 goto err_hif;
1277 }
1278
1279 ar_sdio->func = func;
1280 sdio_set_drvdata(func, ar_sdio);
1281
1282 ar_sdio->id = id;
1283 ar_sdio->is_disabled = true;
1284
1285 spin_lock_init(&ar_sdio->lock);
1286 spin_lock_init(&ar_sdio->scat_lock);
1287 spin_lock_init(&ar_sdio->wr_async_lock);
fdb28589 1288 mutex_init(&ar_sdio->dma_buffer_mutex);
9d82682d 1289 mutex_init(&ar_sdio->mtx_irq);
bdcd8170
KV		 1290
1291 INIT_LIST_HEAD(&ar_sdio->scat_req);
1292 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
1293 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
1294
1295 INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work);
1296
1297 for (count = 0; count < BUS_REQUEST_MAX_NUM; count++)
1298 ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]);
1299
45eaa78f 1300 ar = ath6kl_core_create(&ar_sdio->func->dev);
bdcd8170
KV		 1301 if (!ar) {
1302 ath6kl_err("Failed to alloc ath6kl core\n");
1303 ret = -ENOMEM;
1304 goto err_dma;
1305 }
1306
1307 ar_sdio->ar = ar;
77eab1e9 1308 ar->hif_type = ATH6KL_HIF_TYPE_SDIO;
bdcd8170
KV		 1309 ar->hif_priv = ar_sdio;
1310 ar->hif_ops = &ath6kl_sdio_ops;
1f4c894d 1311 ar->bmi.max_data_size = 256;
bdcd8170
KV		 1312
1313 ath6kl_sdio_set_mbox_info(ar);
1314
e28e8104 1315 ret = ath6kl_sdio_config(ar);
bdcd8170 1316 if (ret) {
e28e8104
KV		 1317 ath6kl_err("Failed to config sdio: %d\n", ret);
1318 goto err_core_alloc;
bdcd8170
KV		 1319 }
1320
bdcd8170
KV		 1321 ret = ath6kl_core_init(ar);
1322 if (ret) {
1323 ath6kl_err("Failed to init ath6kl core\n");
e28e8104 1324 goto err_core_alloc;
bdcd8170
KV		 1325 }
1326
1327 return ret;
1328
8dafb70e 1329err_core_alloc:
45eaa78f 1330 ath6kl_core_destroy(ar_sdio->ar);
bdcd8170
KV		 1331err_dma:
1332 kfree(ar_sdio->dma_buffer);
1333err_hif:
1334 kfree(ar_sdio);
1335
1336 return ret;
1337}
1338
1339static void ath6kl_sdio_remove(struct sdio_func *func)
1340{
1341 struct ath6kl_sdio *ar_sdio;
1342
3ef987be
KV		 1343 ath6kl_dbg(ATH6KL_DBG_BOOT,
1344 "sdio removed func %d vendor 0x%x device 0x%x\n",
f7325b85
KV		 1345 func->num, func->vendor, func->device);
1346
bdcd8170
KV		 1347 ar_sdio = sdio_get_drvdata(func);
1348
1349 ath6kl_stop_txrx(ar_sdio->ar);
1350 cancel_work_sync(&ar_sdio->wr_async_work);
1351
6db8fa53 1352 ath6kl_core_cleanup(ar_sdio->ar);
0e7de662 1353 ath6kl_core_destroy(ar_sdio->ar);
bdcd8170 1354
bdcd8170
KV		 1355 kfree(ar_sdio->dma_buffer);
1356 kfree(ar_sdio);
1357}
1358
1359static const struct sdio_device_id ath6kl_sdio_devices[] = {
1360 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))},
1361 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))},
d93e2c2f
NG		 1362 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))},
1363 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))},
bdcd8170
KV		 1364 {},
1365};
1366
1367MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices);
1368
1369static struct sdio_driver ath6kl_sdio_driver = {
241b128b 1370 .name = "ath6kl_sdio",
bdcd8170
KV		 1371 .id_table = ath6kl_sdio_devices,
1372 .probe = ath6kl_sdio_probe,
1373 .remove = ath6kl_sdio_remove,
b4b2a0b1 1374 .drv.pm = ATH6KL_SDIO_PM_OPS,
bdcd8170
KV		 1375};
1376
1377static int __init ath6kl_sdio_init(void)
1378{
1379 int ret;
1380
1381 ret = sdio_register_driver(&ath6kl_sdio_driver);
1382 if (ret)
1383 ath6kl_err("sdio driver registration failed: %d\n", ret);
1384
1385 return ret;
1386}
1387
1388static void __exit ath6kl_sdio_exit(void)
1389{
1390 sdio_unregister_driver(&ath6kl_sdio_driver);
1391}
1392
1393module_init(ath6kl_sdio_init);
1394module_exit(ath6kl_sdio_exit);
1395
1396MODULE_AUTHOR("Atheros Communications, Inc.");
1397MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices");
1398MODULE_LICENSE("Dual BSD/GPL");
1399
c0038972
KV		 1400MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_OTP_FILE);
1401MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_FIRMWARE_FILE);
1402MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_PATCH_FILE);
0d0192ba
KV		 1403MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE);
1404MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE);
c0038972
KV		 1405MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_OTP_FILE);
1406MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_FIRMWARE_FILE);
1407MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_PATCH_FILE);
0d0192ba
KV		 1408MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE);
1409MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE);
c0038972 1410MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR "/" AR6004_HW_1_0_FIRMWARE_FILE);
f0ea5d58
KV		 1411MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE);
1412MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE);
c0038972 1413MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR "/" AR6004_HW_1_1_FIRMWARE_FILE);
f0ea5d58
KV		 1414MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE);
1415MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE);
Linux kernel - Deliverables
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