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ath6kl: firmware boot fixes for ar6004
[deliverable/linux.git] / drivers / net / wireless / ath / ath6kl / sdio.c
CommitLineData
bdcd8170
KV		 1/*
2 * Copyright (c) 2004-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/mmc/card.h>
18#include <linux/mmc/mmc.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/sdio_func.h>
21#include <linux/mmc/sdio_ids.h>
22#include <linux/mmc/sdio.h>
23#include <linux/mmc/sd.h>
2e1cb23c 24#include "hif.h"
bdcd8170
KV		 25#include "hif-ops.h"
26#include "target.h"
27#include "debug.h"
9df337a1 28#include "cfg80211.h"
bdcd8170
KV		 29
30struct ath6kl_sdio {
31 struct sdio_func *func;
32
33 spinlock_t lock;
34
35 /* free list */
36 struct list_head bus_req_freeq;
37
38 /* available bus requests */
39 struct bus_request bus_req[BUS_REQUEST_MAX_NUM];
40
41 struct ath6kl *ar;
42 u8 *dma_buffer;
43
44 /* scatter request list head */
45 struct list_head scat_req;
46
47 spinlock_t scat_lock;
32a07e44
KV		 48 bool scatter_enabled;
49
bdcd8170
KV		 50 bool is_disabled;
51 atomic_t irq_handling;
52 const struct sdio_device_id *id;
53 struct work_struct wr_async_work;
54 struct list_head wr_asyncq;
55 spinlock_t wr_async_lock;
56};
57
58#define CMD53_ARG_READ 0
59#define CMD53_ARG_WRITE 1
60#define CMD53_ARG_BLOCK_BASIS 1
61#define CMD53_ARG_FIXED_ADDRESS 0
62#define CMD53_ARG_INCR_ADDRESS 1
63
64static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar)
65{
66 return ar->hif_priv;
67}
68
69/*
70 * Macro to check if DMA buffer is WORD-aligned and DMA-able.
71 * Most host controllers assume the buffer is DMA'able and will
72 * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid
73 * check fails on stack memory.
74 */
75static inline bool buf_needs_bounce(u8 *buf)
76{
77 return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
78}
79
80static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar)
81{
82 struct ath6kl_mbox_info *mbox_info = &ar->mbox_info;
83
84 /* EP1 has an extended range */
85 mbox_info->htc_addr = HIF_MBOX_BASE_ADDR;
86 mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR;
87 mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH;
88 mbox_info->block_size = HIF_MBOX_BLOCK_SIZE;
89 mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR;
90 mbox_info->gmbox_sz = HIF_GMBOX_WIDTH;
91}
92
93static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
94 u8 mode, u8 opcode, u32 addr,
95 u16 blksz)
96{
97 *arg = (((rw & 1) << 31) |
98 ((func & 0x7) << 28) |
99 ((mode & 1) << 27) |
100 ((opcode & 1) << 26) |
101 ((addr & 0x1FFFF) << 9) |
102 (blksz & 0x1FF));
103}
104
105static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
106 unsigned int address,
107 unsigned char val)
108{
109 const u8 func = 0;
110
111 *arg = ((write & 1) << 31) |
112 ((func & 0x7) << 28) |
113 ((raw & 1) << 27) |
114 (1 << 26) |
115 ((address & 0x1FFFF) << 9) |
116 (1 << 8) |
117 (val & 0xFF);
118}
119
120static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
121 unsigned int address,
122 unsigned char byte)
123{
124 struct mmc_command io_cmd;
125
126 memset(&io_cmd, 0, sizeof(io_cmd));
127 ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
128 io_cmd.opcode = SD_IO_RW_DIRECT;
129 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
130
131 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
132}
133
da220695
VT		 134static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr,
135 u8 *buf, u32 len)
136{
137 int ret = 0;
138
861dd058
VT		 139 sdio_claim_host(func);
140
da220695 141 if (request & HIF_WRITE) {
f7325b85 142 /* FIXME: looks like ugly workaround for something */
da220695
VT		 143 if (addr >= HIF_MBOX_BASE_ADDR &&
144 addr <= HIF_MBOX_END_ADDR)
145 addr += (HIF_MBOX_WIDTH - len);
146
f7325b85 147 /* FIXME: this also looks like ugly workaround */
da220695
VT		 148 if (addr == HIF_MBOX0_EXT_BASE_ADDR)
149 addr += HIF_MBOX0_EXT_WIDTH - len;
150
151 if (request & HIF_FIXED_ADDRESS)
152 ret = sdio_writesb(func, addr, buf, len);
153 else
154 ret = sdio_memcpy_toio(func, addr, buf, len);
155 } else {
156 if (request & HIF_FIXED_ADDRESS)
157 ret = sdio_readsb(func, buf, addr, len);
158 else
159 ret = sdio_memcpy_fromio(func, buf, addr, len);
160 }
161
861dd058
VT		 162 sdio_release_host(func);
163
f7325b85
KV		 164 ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n",
165 request & HIF_WRITE ? "wr" : "rd", addr,
166 request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len);
167 ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len);
168
da220695
VT		 169 return ret;
170}
171
bdcd8170
KV		 172static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio)
173{
174 struct bus_request *bus_req;
bdcd8170 175
151bd30b 176 spin_lock_bh(&ar_sdio->lock);
bdcd8170
KV		 177
178 if (list_empty(&ar_sdio->bus_req_freeq)) {
151bd30b 179 spin_unlock_bh(&ar_sdio->lock);
bdcd8170
KV		 180 return NULL;
181 }
182
183 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
184 struct bus_request, list);
185 list_del(&bus_req->list);
186
151bd30b 187 spin_unlock_bh(&ar_sdio->lock);
f7325b85
KV		 188 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
189 __func__, bus_req);
bdcd8170
KV		 190
191 return bus_req;
192}
193
194static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio,
195 struct bus_request *bus_req)
196{
f7325b85
KV		 197 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
198 __func__, bus_req);
bdcd8170 199
151bd30b 200 spin_lock_bh(&ar_sdio->lock);
bdcd8170 201 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
151bd30b 202 spin_unlock_bh(&ar_sdio->lock);
bdcd8170
KV		 203}
204
205static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req,
bdcd8170
KV		 206 struct mmc_data *data)
207{
208 struct scatterlist *sg;
209 int i;
210
211 data->blksz = HIF_MBOX_BLOCK_SIZE;
212 data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE;
213
214 ath6kl_dbg(ATH6KL_DBG_SCATTER,
215 "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
216 (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr,
217 data->blksz, data->blocks, scat_req->len,
218 scat_req->scat_entries);
219
220 data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE :
221 MMC_DATA_READ;
222
223 /* fill SG entries */
d4df7890 224 sg = scat_req->sgentries;
bdcd8170
KV		 225 sg_init_table(sg, scat_req->scat_entries);
226
227 /* assemble SG list */
228 for (i = 0; i < scat_req->scat_entries; i++, sg++) {
bdcd8170
KV		 229 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n",
230 i, scat_req->scat_list[i].buf,
231 scat_req->scat_list[i].len);
232
233 sg_set_buf(sg, scat_req->scat_list[i].buf,
234 scat_req->scat_list[i].len);
235 }
236
237 /* set scatter-gather table for request */
d4df7890 238 data->sg = scat_req->sgentries;
bdcd8170
KV		 239 data->sg_len = scat_req->scat_entries;
240}
241
242static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio,
243 struct bus_request *req)
244{
245 struct mmc_request mmc_req;
246 struct mmc_command cmd;
247 struct mmc_data data;
248 struct hif_scatter_req *scat_req;
249 u8 opcode, rw;
348a8fbc 250 int status, len;
bdcd8170
KV		 251
252 scat_req = req->scat_req;
253
348a8fbc
VT		 254 if (scat_req->virt_scat) {
255 len = scat_req->len;
256 if (scat_req->req & HIF_BLOCK_BASIS)
257 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
258
259 status = ath6kl_sdio_io(ar_sdio->func, scat_req->req,
260 scat_req->addr, scat_req->virt_dma_buf,
261 len);
262 goto scat_complete;
263 }
264
bdcd8170
KV		 265 memset(&mmc_req, 0, sizeof(struct mmc_request));
266 memset(&cmd, 0, sizeof(struct mmc_command));
267 memset(&data, 0, sizeof(struct mmc_data));
268
d4df7890 269 ath6kl_sdio_setup_scat_data(scat_req, &data);
bdcd8170
KV		 270
271 opcode = (scat_req->req & HIF_FIXED_ADDRESS) ?
272 CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS;
273
274 rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
275
276 /* Fixup the address so that the last byte will fall on MBOX EOM */
277 if (scat_req->req & HIF_WRITE) {
278 if (scat_req->addr == HIF_MBOX_BASE_ADDR)
279 scat_req->addr += HIF_MBOX_WIDTH - scat_req->len;
280 else
281 /* Uses extended address range */
282 scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len;
283 }
284
285 /* set command argument */
286 ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num,
287 CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr,
288 data.blocks);
289
290 cmd.opcode = SD_IO_RW_EXTENDED;
291 cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
292
293 mmc_req.cmd = &cmd;
294 mmc_req.data = &data;
295
861dd058
VT		 296 sdio_claim_host(ar_sdio->func);
297
bdcd8170
KV		 298 mmc_set_data_timeout(&data, ar_sdio->func->card);
299 /* synchronous call to process request */
300 mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req);
301
861dd058
VT		 302 sdio_release_host(ar_sdio->func);
303
bdcd8170 304 status = cmd.error ? cmd.error : data.error;
348a8fbc
VT		 305
306scat_complete:
bdcd8170
KV		 307 scat_req->status = status;
308
309 if (scat_req->status)
310 ath6kl_err("Scatter write request failed:%d\n",
311 scat_req->status);
312
313 if (scat_req->req & HIF_ASYNCHRONOUS)
e041c7f9 314 scat_req->complete(ar_sdio->ar->htc_target, scat_req);
bdcd8170
KV		 315
316 return status;
317}
318
3df505ad
VT		 319static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio,
320 int n_scat_entry, int n_scat_req,
321 bool virt_scat)
322{
323 struct hif_scatter_req *s_req;
324 struct bus_request *bus_req;
cfeab10b
VT		 325 int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz;
326 u8 *virt_buf;
3df505ad
VT		 327
328 scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item);
329 scat_req_sz = sizeof(*s_req) + scat_list_sz;
330
331 if (!virt_scat)
332 sg_sz = sizeof(struct scatterlist) * n_scat_entry;
cfeab10b
VT		 333 else
334 buf_sz = 2 * L1_CACHE_BYTES +
335 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
3df505ad
VT		 336
337 for (i = 0; i < n_scat_req; i++) {
338 /* allocate the scatter request */
339 s_req = kzalloc(scat_req_sz, GFP_KERNEL);
340 if (!s_req)
341 return -ENOMEM;
342
cfeab10b
VT		 343 if (virt_scat) {
344 virt_buf = kzalloc(buf_sz, GFP_KERNEL);
345 if (!virt_buf) {
346 kfree(s_req);
347 return -ENOMEM;
348 }
349
350 s_req->virt_dma_buf =
351 (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf);
352 } else {
3df505ad
VT		 353 /* allocate sglist */
354 s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL);
355
356 if (!s_req->sgentries) {
357 kfree(s_req);
358 return -ENOMEM;
359 }
360 }
361
362 /* allocate a bus request for this scatter request */
363 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
364 if (!bus_req) {
365 kfree(s_req->sgentries);
cfeab10b 366 kfree(s_req->virt_dma_buf);
3df505ad
VT		 367 kfree(s_req);
368 return -ENOMEM;
369 }
370
371 /* assign the scatter request to this bus request */
372 bus_req->scat_req = s_req;
373 s_req->busrequest = bus_req;
374
4a005c3e
VT		 375 s_req->virt_scat = virt_scat;
376
3df505ad
VT		 377 /* add it to the scatter pool */
378 hif_scatter_req_add(ar_sdio->ar, s_req);
379 }
380
381 return 0;
382}
383
bdcd8170
KV		 384static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf,
385 u32 len, u32 request)
386{
387 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
388 u8 *tbuf = NULL;
389 int ret;
390 bool bounced = false;
391
392 if (request & HIF_BLOCK_BASIS)
393 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
394
395 if (buf_needs_bounce(buf)) {
396 if (!ar_sdio->dma_buffer)
397 return -ENOMEM;
398 tbuf = ar_sdio->dma_buffer;
399 memcpy(tbuf, buf, len);
400 bounced = true;
401 } else
402 tbuf = buf;
403
da220695
VT		 404 ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len);
405 if ((request & HIF_READ) && bounced)
406 memcpy(buf, tbuf, len);
bdcd8170
KV		 407
408 return ret;
409}
410
411static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio,
412 struct bus_request *req)
413{
414 if (req->scat_req)
415 ath6kl_sdio_scat_rw(ar_sdio, req);
416 else {
417 void *context;
418 int status;
419
420 status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address,
421 req->buffer, req->length,
422 req->request);
423 context = req->packet;
424 ath6kl_sdio_free_bus_req(ar_sdio, req);
8e8ddb2b 425 ath6kl_hif_rw_comp_handler(context, status);
bdcd8170
KV		 426 }
427}
428
429static void ath6kl_sdio_write_async_work(struct work_struct *work)
430{
431 struct ath6kl_sdio *ar_sdio;
bdcd8170
KV		 432 struct bus_request *req, *tmp_req;
433
434 ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work);
bdcd8170 435
151bd30b 436 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 437 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
438 list_del(&req->list);
151bd30b 439 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170 440 __ath6kl_sdio_write_async(ar_sdio, req);
151bd30b 441 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170 442 }
151bd30b 443 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 444}
445
446static void ath6kl_sdio_irq_handler(struct sdio_func *func)
447{
448 int status;
449 struct ath6kl_sdio *ar_sdio;
450
f7325b85
KV		 451 ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n");
452
bdcd8170
KV		 453 ar_sdio = sdio_get_drvdata(func);
454 atomic_set(&ar_sdio->irq_handling, 1);
455
456 /*
457 * Release the host during interrups so we can pick it back up when
458 * we process commands.
459 */
460 sdio_release_host(ar_sdio->func);
461
8e8ddb2b 462 status = ath6kl_hif_intr_bh_handler(ar_sdio->ar);
bdcd8170
KV		 463 sdio_claim_host(ar_sdio->func);
464 atomic_set(&ar_sdio->irq_handling, 0);
465 WARN_ON(status && status != -ECANCELED);
466}
467
b2e75698 468static int ath6kl_sdio_power_on(struct ath6kl *ar)
bdcd8170 469{
b2e75698 470 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170
KV		 471 struct sdio_func *func = ar_sdio->func;
472 int ret = 0;
473
474 if (!ar_sdio->is_disabled)
475 return 0;
476
3ef987be
KV		 477 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n");
478
bdcd8170
KV		 479 sdio_claim_host(func);
480
481 ret = sdio_enable_func(func);
482 if (ret) {
483 ath6kl_err("Unable to enable sdio func: %d)\n", ret);
484 sdio_release_host(func);
485 return ret;
486 }
487
488 sdio_release_host(func);
489
490 /*
491 * Wait for hardware to initialise. It should take a lot less than
492 * 10 ms but let's be conservative here.
493 */
494 msleep(10);
495
496 ar_sdio->is_disabled = false;
497
498 return ret;
499}
500
b2e75698 501static int ath6kl_sdio_power_off(struct ath6kl *ar)
bdcd8170 502{
b2e75698 503 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170
KV		 504 int ret;
505
506 if (ar_sdio->is_disabled)
507 return 0;
508
3ef987be
KV		 509 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n");
510
bdcd8170
KV		 511 /* Disable the card */
512 sdio_claim_host(ar_sdio->func);
513 ret = sdio_disable_func(ar_sdio->func);
514 sdio_release_host(ar_sdio->func);
515
516 if (ret)
517 return ret;
518
519 ar_sdio->is_disabled = true;
520
521 return ret;
522}
523
524static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer,
525 u32 length, u32 request,
526 struct htc_packet *packet)
527{
528 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
529 struct bus_request *bus_req;
bdcd8170
KV		 530
531 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
532
533 if (!bus_req)
534 return -ENOMEM;
535
536 bus_req->address = address;
537 bus_req->buffer = buffer;
538 bus_req->length = length;
539 bus_req->request = request;
540 bus_req->packet = packet;
541
151bd30b 542 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170 543 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
151bd30b 544 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 545 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
546
547 return 0;
548}
549
550static void ath6kl_sdio_irq_enable(struct ath6kl *ar)
551{
552 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
553 int ret;
554
555 sdio_claim_host(ar_sdio->func);
556
557 /* Register the isr */
558 ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler);
559 if (ret)
560 ath6kl_err("Failed to claim sdio irq: %d\n", ret);
561
562 sdio_release_host(ar_sdio->func);
563}
564
565static void ath6kl_sdio_irq_disable(struct ath6kl *ar)
566{
567 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
568 int ret;
569
570 sdio_claim_host(ar_sdio->func);
571
572 /* Mask our function IRQ */
573 while (atomic_read(&ar_sdio->irq_handling)) {
574 sdio_release_host(ar_sdio->func);
575 schedule_timeout(HZ / 10);
576 sdio_claim_host(ar_sdio->func);
577 }
578
579 ret = sdio_release_irq(ar_sdio->func);
580 if (ret)
581 ath6kl_err("Failed to release sdio irq: %d\n", ret);
582
583 sdio_release_host(ar_sdio->func);
584}
585
586static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar)
587{
588 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
589 struct hif_scatter_req *node = NULL;
bdcd8170 590
151bd30b 591 spin_lock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 592
593 if (!list_empty(&ar_sdio->scat_req)) {
594 node = list_first_entry(&ar_sdio->scat_req,
595 struct hif_scatter_req, list);
596 list_del(&node->list);
597 }
598
151bd30b 599 spin_unlock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 600
601 return node;
602}
603
604static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar,
605 struct hif_scatter_req *s_req)
606{
607 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170 608
151bd30b 609 spin_lock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 610
611 list_add_tail(&s_req->list, &ar_sdio->scat_req);
612
151bd30b 613 spin_unlock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 614
615}
616
c630d18a
VT		 617/* scatter gather read write request */
618static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar,
619 struct hif_scatter_req *scat_req)
620{
621 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
c630d18a
VT		 622 u32 request = scat_req->req;
623 int status = 0;
c630d18a
VT		 624
625 if (!scat_req->len)
626 return -EINVAL;
627
628 ath6kl_dbg(ATH6KL_DBG_SCATTER,
629 "hif-scatter: total len: %d scatter entries: %d\n",
630 scat_req->len, scat_req->scat_entries);
631
861dd058 632 if (request & HIF_SYNCHRONOUS)
d4df7890 633 status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest);
861dd058 634 else {
151bd30b 635 spin_lock_bh(&ar_sdio->wr_async_lock);
d4df7890 636 list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq);
151bd30b 637 spin_unlock_bh(&ar_sdio->wr_async_lock);
c630d18a
VT		 638 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
639 }
640
641 return status;
642}
643
18a0f93e
VT		 644/* clean up scatter support */
645static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar)
646{
647 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
648 struct hif_scatter_req *s_req, *tmp_req;
18a0f93e
VT		 649
650 /* empty the free list */
151bd30b 651 spin_lock_bh(&ar_sdio->scat_lock);
18a0f93e
VT		 652 list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) {
653 list_del(&s_req->list);
151bd30b 654 spin_unlock_bh(&ar_sdio->scat_lock);
18a0f93e 655
32a07e44
KV		 656 /*
657 * FIXME: should we also call completion handler with
658 * ath6kl_hif_rw_comp_handler() with status -ECANCELED so
659 * that the packet is properly freed?
660 */
18a0f93e
VT		 661 if (s_req->busrequest)
662 ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest);
663 kfree(s_req->virt_dma_buf);
664 kfree(s_req->sgentries);
665 kfree(s_req);
666
151bd30b 667 spin_lock_bh(&ar_sdio->scat_lock);
18a0f93e 668 }
151bd30b 669 spin_unlock_bh(&ar_sdio->scat_lock);
18a0f93e
VT		 670}
671
672/* setup of HIF scatter resources */
50745af7 673static int ath6kl_sdio_enable_scatter(struct ath6kl *ar)
18a0f93e
VT		 674{
675 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
50745af7 676 struct htc_target *target = ar->htc_target;
cfeab10b
VT		 677 int ret;
678 bool virt_scat = false;
18a0f93e 679
32a07e44
KV		 680 if (ar_sdio->scatter_enabled)
681 return 0;
682
683 ar_sdio->scatter_enabled = true;
684
18a0f93e
VT		 685 /* check if host supports scatter and it meets our requirements */
686 if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
cfeab10b 687 ath6kl_err("host only supports scatter of :%d entries, need: %d\n",
18a0f93e
VT		 688 ar_sdio->func->card->host->max_segs,
689 MAX_SCATTER_ENTRIES_PER_REQ);
cfeab10b 690 virt_scat = true;
18a0f93e
VT		 691 }
692
cfeab10b
VT		 693 if (!virt_scat) {
694 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
695 MAX_SCATTER_ENTRIES_PER_REQ,
696 MAX_SCATTER_REQUESTS, virt_scat);
697
698 if (!ret) {
3ef987be
KV		 699 ath6kl_dbg(ATH6KL_DBG_BOOT,
700 "hif-scatter enabled requests %d entries %d\n",
cfeab10b
VT		 701 MAX_SCATTER_REQUESTS,
702 MAX_SCATTER_ENTRIES_PER_REQ);
703
50745af7
VT		 704 target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ;
705 target->max_xfer_szper_scatreq =
cfeab10b
VT		 706 MAX_SCATTER_REQ_TRANSFER_SIZE;
707 } else {
708 ath6kl_sdio_cleanup_scatter(ar);
709 ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n");
710 }
711 }
18a0f93e 712
cfeab10b
VT		 713 if (virt_scat || ret) {
714 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
715 ATH6KL_SCATTER_ENTRIES_PER_REQ,
716 ATH6KL_SCATTER_REQS, virt_scat);
717
718 if (ret) {
719 ath6kl_err("failed to alloc virtual scatter resources !\n");
720 ath6kl_sdio_cleanup_scatter(ar);
721 return ret;
722 }
723
3ef987be
KV		 724 ath6kl_dbg(ATH6KL_DBG_BOOT,
725 "virtual scatter enabled requests %d entries %d\n",
cfeab10b
VT		 726 ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ);
727
50745af7
VT		 728 target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ;
729 target->max_xfer_szper_scatreq =
cfeab10b 730 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
18a0f93e
VT		 731 }
732
18a0f93e
VT		 733 return 0;
734}
735
e28e8104
KV		 736static int ath6kl_sdio_config(struct ath6kl *ar)
737{
738 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
739 struct sdio_func *func = ar_sdio->func;
740 int ret;
741
742 sdio_claim_host(func);
743
744 if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >=
745 MANUFACTURER_ID_AR6003_BASE) {
746 /* enable 4-bit ASYNC interrupt on AR6003 or later */
747 ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card,
748 CCCR_SDIO_IRQ_MODE_REG,
749 SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
750 if (ret) {
751 ath6kl_err("Failed to enable 4-bit async irq mode %d\n",
752 ret);
753 goto out;
754 }
755
756 ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n");
757 }
758
759 /* give us some time to enable, in ms */
760 func->enable_timeout = 100;
761
762 ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
763 if (ret) {
764 ath6kl_err("Set sdio block size %d failed: %d)\n",
765 HIF_MBOX_BLOCK_SIZE, ret);
766 sdio_release_host(func);
767 goto out;
768 }
769
770out:
771 sdio_release_host(func);
772
773 return ret;
774}
775
0f60e9f4 776static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow)
abcb344b
KV		 777{
778 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
779 struct sdio_func *func = ar_sdio->func;
780 mmc_pm_flag_t flags;
781 int ret;
782
783 flags = sdio_get_host_pm_caps(func);
784
b4b2a0b1
KV		 785 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags);
786
8277de15
KV		 787 if (!(flags & MMC_PM_KEEP_POWER) ||
788 (ar->conf_flags & ATH6KL_CONF_SUSPEND_CUTPOWER)) {
b4b2a0b1 789 /* as host doesn't support keep power we need to cut power */
0f60e9f4
RM		 790 return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER,
791 NULL);
17380859 792 }
abcb344b
KV		 793
794 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
795 if (ret) {
796 printk(KERN_ERR "ath6kl: set sdio pm flags failed: %d\n",
797 ret);
798 return ret;
799 }
800
d7c44e0b
RM		 801 if ((flags & MMC_PM_WAKE_SDIO_IRQ) && wow) {
802 /*
803 * The host sdio controller is capable of keep power and
804 * sdio irq wake up at this point. It's fine to continue
805 * wow suspend operation.
806 */
807 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow);
808 if (ret)
809 return ret;
810
811 ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ);
812 if (ret)
813 ath6kl_err("set sdio wake irq flag failed: %d\n", ret);
814
815 return ret;
816 }
817
0f60e9f4 818 return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP, NULL);
abcb344b
KV		 819}
820
aa6cffc1
CN		 821static int ath6kl_sdio_resume(struct ath6kl *ar)
822{
b4b2a0b1
KV		 823 switch (ar->state) {
824 case ATH6KL_STATE_OFF:
825 case ATH6KL_STATE_CUTPOWER:
826 ath6kl_dbg(ATH6KL_DBG_SUSPEND,
827 "sdio resume configuring sdio\n");
828
829 /* need to set sdio settings after power is cut from sdio */
830 ath6kl_sdio_config(ar);
831 break;
832
833 case ATH6KL_STATE_ON:
b4b2a0b1
KV		 834 break;
835
836 case ATH6KL_STATE_DEEPSLEEP:
837 break;
d7c44e0b
RM		 838
839 case ATH6KL_STATE_WOW:
840 break;
b4b2a0b1
KV		 841 }
842
52d81a68 843 ath6kl_cfg80211_resume(ar);
aa6cffc1
CN		 844
845 return 0;
846}
847
c7111495
KV		 848/* set the window address register (using 4-byte register access ). */
849static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
850{
851 int status;
852 u8 addr_val[4];
853 s32 i;
854
855 /*
856 * Write bytes 1,2,3 of the register to set the upper address bytes,
857 * the LSB is written last to initiate the access cycle
858 */
859
860 for (i = 1; i <= 3; i++) {
861 /*
862 * Fill the buffer with the address byte value we want to
863 * hit 4 times.
864 */
865 memset(addr_val, ((u8 *)&addr)[i], 4);
866
867 /*
868 * Hit each byte of the register address with a 4-byte
869 * write operation to the same address, this is a harmless
870 * operation.
871 */
872 status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val,
873 4, HIF_WR_SYNC_BYTE_FIX);
874 if (status)
875 break;
876 }
877
878 if (status) {
879 ath6kl_err("%s: failed to write initial bytes of 0x%x "
880 "to window reg: 0x%X\n", __func__,
881 addr, reg_addr);
882 return status;
883 }
884
885 /*
886 * Write the address register again, this time write the whole
887 * 4-byte value. The effect here is that the LSB write causes the
888 * cycle to start, the extra 3 byte write to bytes 1,2,3 has no
889 * effect since we are writing the same values again
890 */
891 status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr),
892 4, HIF_WR_SYNC_BYTE_INC);
893
894 if (status) {
895 ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n",
896 __func__, addr, reg_addr);
897 return status;
898 }
899
900 return 0;
901}
902
903static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data)
904{
905 int status;
906
907 /* set window register to start read cycle */
908 status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS,
909 address);
910
911 if (status)
912 return status;
913
914 /* read the data */
915 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
916 (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC);
917 if (status) {
918 ath6kl_err("%s: failed to read from window data addr\n",
919 __func__);
920 return status;
921 }
922
923 return status;
924}
925
926static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address,
927 __le32 data)
928{
929 int status;
930 u32 val = (__force u32) data;
931
932 /* set write data */
933 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
934 (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC);
935 if (status) {
936 ath6kl_err("%s: failed to write 0x%x to window data addr\n",
937 __func__, data);
938 return status;
939 }
940
941 /* set window register, which starts the write cycle */
942 return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS,
943 address);
944}
945
66b693c3
KV		 946static int ath6kl_sdio_bmi_credits(struct ath6kl *ar)
947{
948 u32 addr;
949 unsigned long timeout;
950 int ret;
951
952 ar->bmi.cmd_credits = 0;
953
954 /* Read the counter register to get the command credits */
955 addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
956
957 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
958 while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) {
959
960 /*
961 * Hit the credit counter with a 4-byte access, the first byte
962 * read will hit the counter and cause a decrement, while the
963 * remaining 3 bytes has no effect. The rationale behind this
964 * is to make all HIF accesses 4-byte aligned.
965 */
966 ret = ath6kl_sdio_read_write_sync(ar, addr,
967 (u8 *)&ar->bmi.cmd_credits, 4,
968 HIF_RD_SYNC_BYTE_INC);
969 if (ret) {
970 ath6kl_err("Unable to decrement the command credit "
971 "count register: %d\n", ret);
972 return ret;
973 }
974
975 /* The counter is only 8 bits.
976 * Ignore anything in the upper 3 bytes
977 */
978 ar->bmi.cmd_credits &= 0xFF;
979 }
980
981 if (!ar->bmi.cmd_credits) {
982 ath6kl_err("bmi communication timeout\n");
983 return -ETIMEDOUT;
984 }
985
986 return 0;
987}
988
989static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar)
990{
991 unsigned long timeout;
992 u32 rx_word = 0;
993 int ret = 0;
994
995 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
996 while ((time_before(jiffies, timeout)) && !rx_word) {
997 ret = ath6kl_sdio_read_write_sync(ar,
998 RX_LOOKAHEAD_VALID_ADDRESS,
999 (u8 *)&rx_word, sizeof(rx_word),
1000 HIF_RD_SYNC_BYTE_INC);
1001 if (ret) {
1002 ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n");
1003 return ret;
1004 }
1005
1006 /* all we really want is one bit */
1007 rx_word &= (1 << ENDPOINT1);
1008 }
1009
1010 if (!rx_word) {
1011 ath6kl_err("bmi_recv_buf FIFO empty\n");
1012 return -EINVAL;
1013 }
1014
1015 return ret;
1016}
1017
1018static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len)
1019{
1020 int ret;
1021 u32 addr;
1022
1023 ret = ath6kl_sdio_bmi_credits(ar);
1024 if (ret)
1025 return ret;
1026
1027 addr = ar->mbox_info.htc_addr;
1028
1029 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1030 HIF_WR_SYNC_BYTE_INC);
1031 if (ret)
1032 ath6kl_err("unable to send the bmi data to the device\n");
1033
1034 return ret;
1035}
1036
1037static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len)
1038{
1039 int ret;
1040 u32 addr;
1041
1042 /*
1043 * During normal bootup, small reads may be required.
1044 * Rather than issue an HIF Read and then wait as the Target
1045 * adds successive bytes to the FIFO, we wait here until
1046 * we know that response data is available.
1047 *
1048 * This allows us to cleanly timeout on an unexpected
1049 * Target failure rather than risk problems at the HIF level.
1050 * In particular, this avoids SDIO timeouts and possibly garbage
1051 * data on some host controllers. And on an interconnect
1052 * such as Compact Flash (as well as some SDIO masters) which
1053 * does not provide any indication on data timeout, it avoids
1054 * a potential hang or garbage response.
1055 *
1056 * Synchronization is more difficult for reads larger than the
1057 * size of the MBOX FIFO (128B), because the Target is unable
1058 * to push the 129th byte of data until AFTER the Host posts an
1059 * HIF Read and removes some FIFO data. So for large reads the
1060 * Host proceeds to post an HIF Read BEFORE all the data is
1061 * actually available to read. Fortunately, large BMI reads do
1062 * not occur in practice -- they're supported for debug/development.
1063 *
1064 * So Host/Target BMI synchronization is divided into these cases:
1065 * CASE 1: length < 4
1066 * Should not happen
1067 *
1068 * CASE 2: 4 <= length <= 128
1069 * Wait for first 4 bytes to be in FIFO
1070 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1071 * a BMI command credit, which indicates that the ENTIRE
1072 * response is available in the the FIFO
1073 *
1074 * CASE 3: length > 128
1075 * Wait for the first 4 bytes to be in FIFO
1076 *
1077 * For most uses, a small timeout should be sufficient and we will
1078 * usually see a response quickly; but there may be some unusual
1079 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1080 * For now, we use an unbounded busy loop while waiting for
1081 * BMI_EXECUTE.
1082 *
1083 * If BMI_EXECUTE ever needs to support longer-latency execution,
1084 * especially in production, this code needs to be enhanced to sleep
1085 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1086 * a function of Host processor speed.
1087 */
1088 if (len >= 4) { /* NB: Currently, always true */
1089 ret = ath6kl_bmi_get_rx_lkahd(ar);
1090 if (ret)
1091 return ret;
1092 }
1093
1094 addr = ar->mbox_info.htc_addr;
1095 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1096 HIF_RD_SYNC_BYTE_INC);
1097 if (ret) {
1098 ath6kl_err("Unable to read the bmi data from the device: %d\n",
1099 ret);
1100 return ret;
1101 }
1102
1103 return 0;
1104}
1105
32a07e44
KV		 1106static void ath6kl_sdio_stop(struct ath6kl *ar)
1107{
1108 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
1109 struct bus_request *req, *tmp_req;
1110 void *context;
1111
1112 /* FIXME: make sure that wq is not queued again */
1113
1114 cancel_work_sync(&ar_sdio->wr_async_work);
1115
1116 spin_lock_bh(&ar_sdio->wr_async_lock);
1117
1118 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1119 list_del(&req->list);
1120
1121 if (req->scat_req) {
1122 /* this is a scatter gather request */
1123 req->scat_req->status = -ECANCELED;
1124 req->scat_req->complete(ar_sdio->ar->htc_target,
1125 req->scat_req);
1126 } else {
1127 context = req->packet;
1128 ath6kl_sdio_free_bus_req(ar_sdio, req);
1129 ath6kl_hif_rw_comp_handler(context, -ECANCELED);
1130 }
1131 }
1132
1133 spin_unlock_bh(&ar_sdio->wr_async_lock);
1134
1135 WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4);
1136}
1137
bdcd8170
KV		 1138static const struct ath6kl_hif_ops ath6kl_sdio_ops = {
1139 .read_write_sync = ath6kl_sdio_read_write_sync,
1140 .write_async = ath6kl_sdio_write_async,
1141 .irq_enable = ath6kl_sdio_irq_enable,
1142 .irq_disable = ath6kl_sdio_irq_disable,
1143 .scatter_req_get = ath6kl_sdio_scatter_req_get,
1144 .scatter_req_add = ath6kl_sdio_scatter_req_add,
1145 .enable_scatter = ath6kl_sdio_enable_scatter,
f74a7361 1146 .scat_req_rw = ath6kl_sdio_async_rw_scatter,
bdcd8170 1147 .cleanup_scatter = ath6kl_sdio_cleanup_scatter,
abcb344b 1148 .suspend = ath6kl_sdio_suspend,
aa6cffc1 1149 .resume = ath6kl_sdio_resume,
c7111495
KV		 1150 .diag_read32 = ath6kl_sdio_diag_read32,
1151 .diag_write32 = ath6kl_sdio_diag_write32,
66b693c3
KV		 1152 .bmi_read = ath6kl_sdio_bmi_read,
1153 .bmi_write = ath6kl_sdio_bmi_write,
b2e75698
KV		 1154 .power_on = ath6kl_sdio_power_on,
1155 .power_off = ath6kl_sdio_power_off,
32a07e44 1156 .stop = ath6kl_sdio_stop,
bdcd8170
KV		 1157};
1158
b4b2a0b1
KV		 1159#ifdef CONFIG_PM_SLEEP
1160
1161/*
1162 * Empty handlers so that mmc subsystem doesn't remove us entirely during
1163 * suspend. We instead follow cfg80211 suspend/resume handlers.
1164 */
1165static int ath6kl_sdio_pm_suspend(struct device *device)
1166{
1167 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n");
1168
1169 return 0;
1170}
1171
1172static int ath6kl_sdio_pm_resume(struct device *device)
1173{
1174 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n");
1175
1176 return 0;
1177}
1178
1179static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend,
1180 ath6kl_sdio_pm_resume);
1181
1182#define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops)
1183
1184#else
1185
1186#define ATH6KL_SDIO_PM_OPS NULL
1187
1188#endif /* CONFIG_PM_SLEEP */
1189
bdcd8170
KV		 1190static int ath6kl_sdio_probe(struct sdio_func *func,
1191 const struct sdio_device_id *id)
1192{
1193 int ret;
1194 struct ath6kl_sdio *ar_sdio;
1195 struct ath6kl *ar;
1196 int count;
1197
3ef987be
KV		 1198 ath6kl_dbg(ATH6KL_DBG_BOOT,
1199 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
f7325b85
KV		 1200 func->num, func->vendor, func->device,
1201 func->max_blksize, func->cur_blksize);
bdcd8170
KV		 1202
1203 ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL);
1204 if (!ar_sdio)
1205 return -ENOMEM;
1206
1207 ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
1208 if (!ar_sdio->dma_buffer) {
1209 ret = -ENOMEM;
1210 goto err_hif;
1211 }
1212
1213 ar_sdio->func = func;
1214 sdio_set_drvdata(func, ar_sdio);
1215
1216 ar_sdio->id = id;
1217 ar_sdio->is_disabled = true;
1218
1219 spin_lock_init(&ar_sdio->lock);
1220 spin_lock_init(&ar_sdio->scat_lock);
1221 spin_lock_init(&ar_sdio->wr_async_lock);
1222
1223 INIT_LIST_HEAD(&ar_sdio->scat_req);
1224 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
1225 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
1226
1227 INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work);
1228
1229 for (count = 0; count < BUS_REQUEST_MAX_NUM; count++)
1230 ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]);
1231
1232 ar = ath6kl_core_alloc(&ar_sdio->func->dev);
1233 if (!ar) {
1234 ath6kl_err("Failed to alloc ath6kl core\n");
1235 ret = -ENOMEM;
1236 goto err_dma;
1237 }
1238
1239 ar_sdio->ar = ar;
1240 ar->hif_priv = ar_sdio;
1241 ar->hif_ops = &ath6kl_sdio_ops;
1f4c894d 1242 ar->bmi.max_data_size = 256;
bdcd8170
KV		 1243
1244 ath6kl_sdio_set_mbox_info(ar);
1245
e28e8104 1246 ret = ath6kl_sdio_config(ar);
bdcd8170 1247 if (ret) {
e28e8104
KV		 1248 ath6kl_err("Failed to config sdio: %d\n", ret);
1249 goto err_core_alloc;
bdcd8170
KV		 1250 }
1251
bdcd8170
KV		 1252 ret = ath6kl_core_init(ar);
1253 if (ret) {
1254 ath6kl_err("Failed to init ath6kl core\n");
e28e8104 1255 goto err_core_alloc;
bdcd8170
KV		 1256 }
1257
1258 return ret;
1259
8dafb70e
VT		 1260err_core_alloc:
1261 ath6kl_core_free(ar_sdio->ar);
bdcd8170
KV		 1262err_dma:
1263 kfree(ar_sdio->dma_buffer);
1264err_hif:
1265 kfree(ar_sdio);
1266
1267 return ret;
1268}
1269
1270static void ath6kl_sdio_remove(struct sdio_func *func)
1271{
1272 struct ath6kl_sdio *ar_sdio;
1273
3ef987be
KV		 1274 ath6kl_dbg(ATH6KL_DBG_BOOT,
1275 "sdio removed func %d vendor 0x%x device 0x%x\n",
f7325b85
KV		 1276 func->num, func->vendor, func->device);
1277
bdcd8170
KV		 1278 ar_sdio = sdio_get_drvdata(func);
1279
1280 ath6kl_stop_txrx(ar_sdio->ar);
1281 cancel_work_sync(&ar_sdio->wr_async_work);
1282
6db8fa53 1283 ath6kl_core_cleanup(ar_sdio->ar);
bdcd8170 1284
bdcd8170
KV		 1285 kfree(ar_sdio->dma_buffer);
1286 kfree(ar_sdio);
1287}
1288
1289static const struct sdio_device_id ath6kl_sdio_devices[] = {
1290 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))},
1291 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))},
1292 {},
1293};
1294
1295MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices);
1296
1297static struct sdio_driver ath6kl_sdio_driver = {
cd4b8b85 1298 .name = "ath6kl",
bdcd8170
KV		 1299 .id_table = ath6kl_sdio_devices,
1300 .probe = ath6kl_sdio_probe,
1301 .remove = ath6kl_sdio_remove,
b4b2a0b1 1302 .drv.pm = ATH6KL_SDIO_PM_OPS,
bdcd8170
KV		 1303};
1304
1305static int __init ath6kl_sdio_init(void)
1306{
1307 int ret;
1308
1309 ret = sdio_register_driver(&ath6kl_sdio_driver);
1310 if (ret)
1311 ath6kl_err("sdio driver registration failed: %d\n", ret);
1312
1313 return ret;
1314}
1315
1316static void __exit ath6kl_sdio_exit(void)
1317{
1318 sdio_unregister_driver(&ath6kl_sdio_driver);
1319}
1320
1321module_init(ath6kl_sdio_init);
1322module_exit(ath6kl_sdio_exit);
1323
1324MODULE_AUTHOR("Atheros Communications, Inc.");
1325MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices");
1326MODULE_LICENSE("Dual BSD/GPL");
1327
1328MODULE_FIRMWARE(AR6003_REV2_OTP_FILE);
1329MODULE_FIRMWARE(AR6003_REV2_FIRMWARE_FILE);
1330MODULE_FIRMWARE(AR6003_REV2_PATCH_FILE);
1331MODULE_FIRMWARE(AR6003_REV2_BOARD_DATA_FILE);
1332MODULE_FIRMWARE(AR6003_REV2_DEFAULT_BOARD_DATA_FILE);
1333MODULE_FIRMWARE(AR6003_REV3_OTP_FILE);
1334MODULE_FIRMWARE(AR6003_REV3_FIRMWARE_FILE);
1335MODULE_FIRMWARE(AR6003_REV3_PATCH_FILE);
1336MODULE_FIRMWARE(AR6003_REV3_BOARD_DATA_FILE);
1337MODULE_FIRMWARE(AR6003_REV3_DEFAULT_BOARD_DATA_FILE);
Linux kernel - Deliverables
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