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ath6kl: Send own IP addr to the firmware during WOW suspend
[deliverable/linux.git] / drivers / net / wireless / ath / ath6kl / sdio.c
CommitLineData
bdcd8170
KV		 1/*
2 * Copyright (c) 2004-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
9d9779e7 17#include <linux/module.h>
bdcd8170
KV		 18#include <linux/mmc/card.h>
19#include <linux/mmc/mmc.h>
20#include <linux/mmc/host.h>
21#include <linux/mmc/sdio_func.h>
22#include <linux/mmc/sdio_ids.h>
23#include <linux/mmc/sdio.h>
24#include <linux/mmc/sd.h>
2e1cb23c 25#include "hif.h"
bdcd8170
KV		 26#include "hif-ops.h"
27#include "target.h"
28#include "debug.h"
9df337a1 29#include "cfg80211.h"
bdcd8170
KV		 30
31struct ath6kl_sdio {
32 struct sdio_func *func;
33
34 spinlock_t lock;
35
36 /* free list */
37 struct list_head bus_req_freeq;
38
39 /* available bus requests */
40 struct bus_request bus_req[BUS_REQUEST_MAX_NUM];
41
42 struct ath6kl *ar;
fdb28589 43
bdcd8170
KV		 44 u8 *dma_buffer;
45
fdb28589
RM		 46 /* protects access to dma_buffer */
47 struct mutex dma_buffer_mutex;
48
bdcd8170
KV		 49 /* scatter request list head */
50 struct list_head scat_req;
51
52 spinlock_t scat_lock;
32a07e44
KV		 53 bool scatter_enabled;
54
bdcd8170
KV		 55 bool is_disabled;
56 atomic_t irq_handling;
57 const struct sdio_device_id *id;
58 struct work_struct wr_async_work;
59 struct list_head wr_asyncq;
60 spinlock_t wr_async_lock;
61};
62
63#define CMD53_ARG_READ 0
64#define CMD53_ARG_WRITE 1
65#define CMD53_ARG_BLOCK_BASIS 1
66#define CMD53_ARG_FIXED_ADDRESS 0
67#define CMD53_ARG_INCR_ADDRESS 1
68
69static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar)
70{
71 return ar->hif_priv;
72}
73
74/*
75 * Macro to check if DMA buffer is WORD-aligned and DMA-able.
76 * Most host controllers assume the buffer is DMA'able and will
77 * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid
78 * check fails on stack memory.
79 */
80static inline bool buf_needs_bounce(u8 *buf)
81{
82 return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
83}
84
85static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar)
86{
87 struct ath6kl_mbox_info *mbox_info = &ar->mbox_info;
88
89 /* EP1 has an extended range */
90 mbox_info->htc_addr = HIF_MBOX_BASE_ADDR;
91 mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR;
92 mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH;
93 mbox_info->block_size = HIF_MBOX_BLOCK_SIZE;
94 mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR;
95 mbox_info->gmbox_sz = HIF_GMBOX_WIDTH;
96}
97
98static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
99 u8 mode, u8 opcode, u32 addr,
100 u16 blksz)
101{
102 *arg = (((rw & 1) << 31) |
103 ((func & 0x7) << 28) |
104 ((mode & 1) << 27) |
105 ((opcode & 1) << 26) |
106 ((addr & 0x1FFFF) << 9) |
107 (blksz & 0x1FF));
108}
109
110static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
111 unsigned int address,
112 unsigned char val)
113{
114 const u8 func = 0;
115
116 *arg = ((write & 1) << 31) |
117 ((func & 0x7) << 28) |
118 ((raw & 1) << 27) |
119 (1 << 26) |
120 ((address & 0x1FFFF) << 9) |
121 (1 << 8) |
122 (val & 0xFF);
123}
124
125static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
126 unsigned int address,
127 unsigned char byte)
128{
129 struct mmc_command io_cmd;
130
131 memset(&io_cmd, 0, sizeof(io_cmd));
132 ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
133 io_cmd.opcode = SD_IO_RW_DIRECT;
134 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
135
136 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
137}
138
da220695
VT		 139static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr,
140 u8 *buf, u32 len)
141{
142 int ret = 0;
143
861dd058
VT		 144 sdio_claim_host(func);
145
da220695 146 if (request & HIF_WRITE) {
f7325b85 147 /* FIXME: looks like ugly workaround for something */
da220695
VT		 148 if (addr >= HIF_MBOX_BASE_ADDR &&
149 addr <= HIF_MBOX_END_ADDR)
150 addr += (HIF_MBOX_WIDTH - len);
151
f7325b85 152 /* FIXME: this also looks like ugly workaround */
da220695
VT		 153 if (addr == HIF_MBOX0_EXT_BASE_ADDR)
154 addr += HIF_MBOX0_EXT_WIDTH - len;
155
156 if (request & HIF_FIXED_ADDRESS)
157 ret = sdio_writesb(func, addr, buf, len);
158 else
159 ret = sdio_memcpy_toio(func, addr, buf, len);
160 } else {
161 if (request & HIF_FIXED_ADDRESS)
162 ret = sdio_readsb(func, buf, addr, len);
163 else
164 ret = sdio_memcpy_fromio(func, buf, addr, len);
165 }
166
861dd058
VT		 167 sdio_release_host(func);
168
f7325b85
KV		 169 ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n",
170 request & HIF_WRITE ? "wr" : "rd", addr,
171 request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len);
172 ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len);
173
da220695
VT		 174 return ret;
175}
176
bdcd8170
KV		 177static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio)
178{
179 struct bus_request *bus_req;
bdcd8170 180
151bd30b 181 spin_lock_bh(&ar_sdio->lock);
bdcd8170
KV		 182
183 if (list_empty(&ar_sdio->bus_req_freeq)) {
151bd30b 184 spin_unlock_bh(&ar_sdio->lock);
bdcd8170
KV		 185 return NULL;
186 }
187
188 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
189 struct bus_request, list);
190 list_del(&bus_req->list);
191
151bd30b 192 spin_unlock_bh(&ar_sdio->lock);
f7325b85
KV		 193 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
194 __func__, bus_req);
bdcd8170
KV		 195
196 return bus_req;
197}
198
199static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio,
200 struct bus_request *bus_req)
201{
f7325b85
KV		 202 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
203 __func__, bus_req);
bdcd8170 204
151bd30b 205 spin_lock_bh(&ar_sdio->lock);
bdcd8170 206 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
151bd30b 207 spin_unlock_bh(&ar_sdio->lock);
bdcd8170
KV		 208}
209
210static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req,
bdcd8170
KV		 211 struct mmc_data *data)
212{
213 struct scatterlist *sg;
214 int i;
215
216 data->blksz = HIF_MBOX_BLOCK_SIZE;
217 data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE;
218
219 ath6kl_dbg(ATH6KL_DBG_SCATTER,
220 "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
221 (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr,
222 data->blksz, data->blocks, scat_req->len,
223 scat_req->scat_entries);
224
225 data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE :
226 MMC_DATA_READ;
227
228 /* fill SG entries */
d4df7890 229 sg = scat_req->sgentries;
bdcd8170
KV		 230 sg_init_table(sg, scat_req->scat_entries);
231
232 /* assemble SG list */
233 for (i = 0; i < scat_req->scat_entries; i++, sg++) {
bdcd8170
KV		 234 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n",
235 i, scat_req->scat_list[i].buf,
236 scat_req->scat_list[i].len);
237
238 sg_set_buf(sg, scat_req->scat_list[i].buf,
239 scat_req->scat_list[i].len);
240 }
241
242 /* set scatter-gather table for request */
d4df7890 243 data->sg = scat_req->sgentries;
bdcd8170
KV		 244 data->sg_len = scat_req->scat_entries;
245}
246
247static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio,
248 struct bus_request *req)
249{
250 struct mmc_request mmc_req;
251 struct mmc_command cmd;
252 struct mmc_data data;
253 struct hif_scatter_req *scat_req;
254 u8 opcode, rw;
348a8fbc 255 int status, len;
bdcd8170
KV		 256
257 scat_req = req->scat_req;
258
348a8fbc
VT		 259 if (scat_req->virt_scat) {
260 len = scat_req->len;
261 if (scat_req->req & HIF_BLOCK_BASIS)
262 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
263
264 status = ath6kl_sdio_io(ar_sdio->func, scat_req->req,
265 scat_req->addr, scat_req->virt_dma_buf,
266 len);
267 goto scat_complete;
268 }
269
bdcd8170
KV		 270 memset(&mmc_req, 0, sizeof(struct mmc_request));
271 memset(&cmd, 0, sizeof(struct mmc_command));
272 memset(&data, 0, sizeof(struct mmc_data));
273
d4df7890 274 ath6kl_sdio_setup_scat_data(scat_req, &data);
bdcd8170
KV		 275
276 opcode = (scat_req->req & HIF_FIXED_ADDRESS) ?
277 CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS;
278
279 rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
280
281 /* Fixup the address so that the last byte will fall on MBOX EOM */
282 if (scat_req->req & HIF_WRITE) {
283 if (scat_req->addr == HIF_MBOX_BASE_ADDR)
284 scat_req->addr += HIF_MBOX_WIDTH - scat_req->len;
285 else
286 /* Uses extended address range */
287 scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len;
288 }
289
290 /* set command argument */
291 ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num,
292 CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr,
293 data.blocks);
294
295 cmd.opcode = SD_IO_RW_EXTENDED;
296 cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
297
298 mmc_req.cmd = &cmd;
299 mmc_req.data = &data;
300
861dd058
VT		 301 sdio_claim_host(ar_sdio->func);
302
bdcd8170
KV		 303 mmc_set_data_timeout(&data, ar_sdio->func->card);
304 /* synchronous call to process request */
305 mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req);
306
861dd058
VT		 307 sdio_release_host(ar_sdio->func);
308
bdcd8170 309 status = cmd.error ? cmd.error : data.error;
348a8fbc
VT		 310
311scat_complete:
bdcd8170
KV		 312 scat_req->status = status;
313
314 if (scat_req->status)
315 ath6kl_err("Scatter write request failed:%d\n",
316 scat_req->status);
317
318 if (scat_req->req & HIF_ASYNCHRONOUS)
e041c7f9 319 scat_req->complete(ar_sdio->ar->htc_target, scat_req);
bdcd8170
KV		 320
321 return status;
322}
323
3df505ad
VT		 324static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio,
325 int n_scat_entry, int n_scat_req,
326 bool virt_scat)
327{
328 struct hif_scatter_req *s_req;
329 struct bus_request *bus_req;
cfeab10b
VT		 330 int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz;
331 u8 *virt_buf;
3df505ad
VT		 332
333 scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item);
334 scat_req_sz = sizeof(*s_req) + scat_list_sz;
335
336 if (!virt_scat)
337 sg_sz = sizeof(struct scatterlist) * n_scat_entry;
cfeab10b
VT		 338 else
339 buf_sz = 2 * L1_CACHE_BYTES +
340 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
3df505ad
VT		 341
342 for (i = 0; i < n_scat_req; i++) {
343 /* allocate the scatter request */
344 s_req = kzalloc(scat_req_sz, GFP_KERNEL);
345 if (!s_req)
346 return -ENOMEM;
347
cfeab10b
VT		 348 if (virt_scat) {
349 virt_buf = kzalloc(buf_sz, GFP_KERNEL);
350 if (!virt_buf) {
351 kfree(s_req);
352 return -ENOMEM;
353 }
354
355 s_req->virt_dma_buf =
356 (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf);
357 } else {
3df505ad
VT		 358 /* allocate sglist */
359 s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL);
360
361 if (!s_req->sgentries) {
362 kfree(s_req);
363 return -ENOMEM;
364 }
365 }
366
367 /* allocate a bus request for this scatter request */
368 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
369 if (!bus_req) {
370 kfree(s_req->sgentries);
cfeab10b 371 kfree(s_req->virt_dma_buf);
3df505ad
VT		 372 kfree(s_req);
373 return -ENOMEM;
374 }
375
376 /* assign the scatter request to this bus request */
377 bus_req->scat_req = s_req;
378 s_req->busrequest = bus_req;
379
4a005c3e
VT		 380 s_req->virt_scat = virt_scat;
381
3df505ad
VT		 382 /* add it to the scatter pool */
383 hif_scatter_req_add(ar_sdio->ar, s_req);
384 }
385
386 return 0;
387}
388
bdcd8170
KV		 389static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf,
390 u32 len, u32 request)
391{
392 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
393 u8 *tbuf = NULL;
394 int ret;
395 bool bounced = false;
396
397 if (request & HIF_BLOCK_BASIS)
398 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
399
400 if (buf_needs_bounce(buf)) {
401 if (!ar_sdio->dma_buffer)
402 return -ENOMEM;
fdb28589 403 mutex_lock(&ar_sdio->dma_buffer_mutex);
bdcd8170
KV		 404 tbuf = ar_sdio->dma_buffer;
405 memcpy(tbuf, buf, len);
406 bounced = true;
407 } else
408 tbuf = buf;
409
da220695
VT		 410 ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len);
411 if ((request & HIF_READ) && bounced)
412 memcpy(buf, tbuf, len);
bdcd8170 413
fdb28589
RM		 414 if (bounced)
415 mutex_unlock(&ar_sdio->dma_buffer_mutex);
416
bdcd8170
KV		 417 return ret;
418}
419
420static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio,
421 struct bus_request *req)
422{
423 if (req->scat_req)
424 ath6kl_sdio_scat_rw(ar_sdio, req);
425 else {
426 void *context;
427 int status;
428
429 status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address,
430 req->buffer, req->length,
431 req->request);
432 context = req->packet;
433 ath6kl_sdio_free_bus_req(ar_sdio, req);
8e8ddb2b 434 ath6kl_hif_rw_comp_handler(context, status);
bdcd8170
KV		 435 }
436}
437
438static void ath6kl_sdio_write_async_work(struct work_struct *work)
439{
440 struct ath6kl_sdio *ar_sdio;
bdcd8170
KV		 441 struct bus_request *req, *tmp_req;
442
443 ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work);
bdcd8170 444
151bd30b 445 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 446 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
447 list_del(&req->list);
151bd30b 448 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170 449 __ath6kl_sdio_write_async(ar_sdio, req);
151bd30b 450 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170 451 }
151bd30b 452 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 453}
454
455static void ath6kl_sdio_irq_handler(struct sdio_func *func)
456{
457 int status;
458 struct ath6kl_sdio *ar_sdio;
459
f7325b85
KV		 460 ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n");
461
bdcd8170
KV		 462 ar_sdio = sdio_get_drvdata(func);
463 atomic_set(&ar_sdio->irq_handling, 1);
464
465 /*
466 * Release the host during interrups so we can pick it back up when
467 * we process commands.
468 */
469 sdio_release_host(ar_sdio->func);
470
8e8ddb2b 471 status = ath6kl_hif_intr_bh_handler(ar_sdio->ar);
bdcd8170
KV		 472 sdio_claim_host(ar_sdio->func);
473 atomic_set(&ar_sdio->irq_handling, 0);
474 WARN_ON(status && status != -ECANCELED);
475}
476
b2e75698 477static int ath6kl_sdio_power_on(struct ath6kl *ar)
bdcd8170 478{
b2e75698 479 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170
KV		 480 struct sdio_func *func = ar_sdio->func;
481 int ret = 0;
482
483 if (!ar_sdio->is_disabled)
484 return 0;
485
3ef987be
KV		 486 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n");
487
bdcd8170
KV		 488 sdio_claim_host(func);
489
490 ret = sdio_enable_func(func);
491 if (ret) {
492 ath6kl_err("Unable to enable sdio func: %d)\n", ret);
493 sdio_release_host(func);
494 return ret;
495 }
496
497 sdio_release_host(func);
498
499 /*
500 * Wait for hardware to initialise. It should take a lot less than
501 * 10 ms but let's be conservative here.
502 */
503 msleep(10);
504
505 ar_sdio->is_disabled = false;
506
507 return ret;
508}
509
b2e75698 510static int ath6kl_sdio_power_off(struct ath6kl *ar)
bdcd8170 511{
b2e75698 512 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170
KV		 513 int ret;
514
515 if (ar_sdio->is_disabled)
516 return 0;
517
3ef987be
KV		 518 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n");
519
bdcd8170
KV		 520 /* Disable the card */
521 sdio_claim_host(ar_sdio->func);
522 ret = sdio_disable_func(ar_sdio->func);
523 sdio_release_host(ar_sdio->func);
524
525 if (ret)
526 return ret;
527
528 ar_sdio->is_disabled = true;
529
530 return ret;
531}
532
533static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer,
534 u32 length, u32 request,
535 struct htc_packet *packet)
536{
537 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
538 struct bus_request *bus_req;
bdcd8170
KV		 539
540 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
541
542 if (!bus_req)
543 return -ENOMEM;
544
545 bus_req->address = address;
546 bus_req->buffer = buffer;
547 bus_req->length = length;
548 bus_req->request = request;
549 bus_req->packet = packet;
550
151bd30b 551 spin_lock_bh(&ar_sdio->wr_async_lock);
bdcd8170 552 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
151bd30b 553 spin_unlock_bh(&ar_sdio->wr_async_lock);
bdcd8170
KV		 554 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
555
556 return 0;
557}
558
559static void ath6kl_sdio_irq_enable(struct ath6kl *ar)
560{
561 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
562 int ret;
563
564 sdio_claim_host(ar_sdio->func);
565
566 /* Register the isr */
567 ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler);
568 if (ret)
569 ath6kl_err("Failed to claim sdio irq: %d\n", ret);
570
571 sdio_release_host(ar_sdio->func);
572}
573
574static void ath6kl_sdio_irq_disable(struct ath6kl *ar)
575{
576 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
577 int ret;
578
579 sdio_claim_host(ar_sdio->func);
580
581 /* Mask our function IRQ */
582 while (atomic_read(&ar_sdio->irq_handling)) {
583 sdio_release_host(ar_sdio->func);
584 schedule_timeout(HZ / 10);
585 sdio_claim_host(ar_sdio->func);
586 }
587
588 ret = sdio_release_irq(ar_sdio->func);
589 if (ret)
590 ath6kl_err("Failed to release sdio irq: %d\n", ret);
591
592 sdio_release_host(ar_sdio->func);
593}
594
595static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar)
596{
597 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
598 struct hif_scatter_req *node = NULL;
bdcd8170 599
151bd30b 600 spin_lock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 601
602 if (!list_empty(&ar_sdio->scat_req)) {
603 node = list_first_entry(&ar_sdio->scat_req,
604 struct hif_scatter_req, list);
605 list_del(&node->list);
606 }
607
151bd30b 608 spin_unlock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 609
610 return node;
611}
612
613static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar,
614 struct hif_scatter_req *s_req)
615{
616 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
bdcd8170 617
151bd30b 618 spin_lock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 619
620 list_add_tail(&s_req->list, &ar_sdio->scat_req);
621
151bd30b 622 spin_unlock_bh(&ar_sdio->scat_lock);
bdcd8170
KV		 623
624}
625
c630d18a
VT		 626/* scatter gather read write request */
627static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar,
628 struct hif_scatter_req *scat_req)
629{
630 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
c630d18a
VT		 631 u32 request = scat_req->req;
632 int status = 0;
c630d18a
VT		 633
634 if (!scat_req->len)
635 return -EINVAL;
636
637 ath6kl_dbg(ATH6KL_DBG_SCATTER,
638 "hif-scatter: total len: %d scatter entries: %d\n",
639 scat_req->len, scat_req->scat_entries);
640
861dd058 641 if (request & HIF_SYNCHRONOUS)
d4df7890 642 status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest);
861dd058 643 else {
151bd30b 644 spin_lock_bh(&ar_sdio->wr_async_lock);
d4df7890 645 list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq);
151bd30b 646 spin_unlock_bh(&ar_sdio->wr_async_lock);
c630d18a
VT		 647 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
648 }
649
650 return status;
651}
652
18a0f93e
VT		 653/* clean up scatter support */
654static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar)
655{
656 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
657 struct hif_scatter_req *s_req, *tmp_req;
18a0f93e
VT		 658
659 /* empty the free list */
151bd30b 660 spin_lock_bh(&ar_sdio->scat_lock);
18a0f93e
VT		 661 list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) {
662 list_del(&s_req->list);
151bd30b 663 spin_unlock_bh(&ar_sdio->scat_lock);
18a0f93e 664
32a07e44
KV		 665 /*
666 * FIXME: should we also call completion handler with
667 * ath6kl_hif_rw_comp_handler() with status -ECANCELED so
668 * that the packet is properly freed?
669 */
18a0f93e
VT		 670 if (s_req->busrequest)
671 ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest);
672 kfree(s_req->virt_dma_buf);
673 kfree(s_req->sgentries);
674 kfree(s_req);
675
151bd30b 676 spin_lock_bh(&ar_sdio->scat_lock);
18a0f93e 677 }
151bd30b 678 spin_unlock_bh(&ar_sdio->scat_lock);
18a0f93e
VT		 679}
680
681/* setup of HIF scatter resources */
50745af7 682static int ath6kl_sdio_enable_scatter(struct ath6kl *ar)
18a0f93e
VT		 683{
684 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
50745af7 685 struct htc_target *target = ar->htc_target;
cfeab10b
VT		 686 int ret;
687 bool virt_scat = false;
18a0f93e 688
32a07e44
KV		 689 if (ar_sdio->scatter_enabled)
690 return 0;
691
692 ar_sdio->scatter_enabled = true;
693
18a0f93e
VT		 694 /* check if host supports scatter and it meets our requirements */
695 if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
cfeab10b 696 ath6kl_err("host only supports scatter of :%d entries, need: %d\n",
18a0f93e
VT		 697 ar_sdio->func->card->host->max_segs,
698 MAX_SCATTER_ENTRIES_PER_REQ);
cfeab10b 699 virt_scat = true;
18a0f93e
VT		 700 }
701
cfeab10b
VT		 702 if (!virt_scat) {
703 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
704 MAX_SCATTER_ENTRIES_PER_REQ,
705 MAX_SCATTER_REQUESTS, virt_scat);
706
707 if (!ret) {
3ef987be
KV		 708 ath6kl_dbg(ATH6KL_DBG_BOOT,
709 "hif-scatter enabled requests %d entries %d\n",
cfeab10b
VT		 710 MAX_SCATTER_REQUESTS,
711 MAX_SCATTER_ENTRIES_PER_REQ);
712
50745af7
VT		 713 target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ;
714 target->max_xfer_szper_scatreq =
cfeab10b
VT		 715 MAX_SCATTER_REQ_TRANSFER_SIZE;
716 } else {
717 ath6kl_sdio_cleanup_scatter(ar);
718 ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n");
719 }
720 }
18a0f93e 721
cfeab10b
VT		 722 if (virt_scat || ret) {
723 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
724 ATH6KL_SCATTER_ENTRIES_PER_REQ,
725 ATH6KL_SCATTER_REQS, virt_scat);
726
727 if (ret) {
728 ath6kl_err("failed to alloc virtual scatter resources !\n");
729 ath6kl_sdio_cleanup_scatter(ar);
730 return ret;
731 }
732
3ef987be
KV		 733 ath6kl_dbg(ATH6KL_DBG_BOOT,
734 "virtual scatter enabled requests %d entries %d\n",
cfeab10b
VT		 735 ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ);
736
50745af7
VT		 737 target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ;
738 target->max_xfer_szper_scatreq =
cfeab10b 739 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
18a0f93e
VT		 740 }
741
18a0f93e
VT		 742 return 0;
743}
744
e28e8104
KV		 745static int ath6kl_sdio_config(struct ath6kl *ar)
746{
747 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
748 struct sdio_func *func = ar_sdio->func;
749 int ret;
750
751 sdio_claim_host(func);
752
753 if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >=
754 MANUFACTURER_ID_AR6003_BASE) {
755 /* enable 4-bit ASYNC interrupt on AR6003 or later */
756 ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card,
757 CCCR_SDIO_IRQ_MODE_REG,
758 SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
759 if (ret) {
760 ath6kl_err("Failed to enable 4-bit async irq mode %d\n",
761 ret);
762 goto out;
763 }
764
765 ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n");
766 }
767
768 /* give us some time to enable, in ms */
769 func->enable_timeout = 100;
770
771 ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
772 if (ret) {
773 ath6kl_err("Set sdio block size %d failed: %d)\n",
774 HIF_MBOX_BLOCK_SIZE, ret);
775 sdio_release_host(func);
776 goto out;
777 }
778
779out:
780 sdio_release_host(func);
781
782 return ret;
783}
784
0f60e9f4 785static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow)
abcb344b
KV		 786{
787 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
788 struct sdio_func *func = ar_sdio->func;
789 mmc_pm_flag_t flags;
790 int ret;
791
792 flags = sdio_get_host_pm_caps(func);
793
b4b2a0b1
KV		 794 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags);
795
8277de15
KV		 796 if (!(flags & MMC_PM_KEEP_POWER) ||
797 (ar->conf_flags & ATH6KL_CONF_SUSPEND_CUTPOWER)) {
b4b2a0b1 798 /* as host doesn't support keep power we need to cut power */
0f60e9f4
RM		 799 return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER,
800 NULL);
17380859 801 }
abcb344b
KV		 802
803 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
804 if (ret) {
805 printk(KERN_ERR "ath6kl: set sdio pm flags failed: %d\n",
806 ret);
807 return ret;
808 }
809
10509f90
KV		 810 if (!(flags & MMC_PM_WAKE_SDIO_IRQ))
811 goto deepsleep;
812
813 /* sdio irq wakes up host */
814
815 if (ar->state == ATH6KL_STATE_SCHED_SCAN) {
816 ret = ath6kl_cfg80211_suspend(ar,
817 ATH6KL_CFG_SUSPEND_SCHED_SCAN,
818 NULL);
819 if (ret) {
820 ath6kl_warn("Schedule scan suspend failed: %d", ret);
821 return ret;
822 }
823
824 ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ);
825 if (ret)
826 ath6kl_warn("set sdio wake irq flag failed: %d\n", ret);
827
828 return ret;
829 }
830
831 if (wow) {
d7c44e0b
RM		 832 /*
833 * The host sdio controller is capable of keep power and
834 * sdio irq wake up at this point. It's fine to continue
835 * wow suspend operation.
836 */
837 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow);
838 if (ret)
839 return ret;
840
841 ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ);
842 if (ret)
843 ath6kl_err("set sdio wake irq flag failed: %d\n", ret);
844
845 return ret;
846 }
847
10509f90 848deepsleep:
0f60e9f4 849 return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP, NULL);
abcb344b
KV		 850}
851
aa6cffc1
CN		 852static int ath6kl_sdio_resume(struct ath6kl *ar)
853{
b4b2a0b1
KV		 854 switch (ar->state) {
855 case ATH6KL_STATE_OFF:
856 case ATH6KL_STATE_CUTPOWER:
857 ath6kl_dbg(ATH6KL_DBG_SUSPEND,
858 "sdio resume configuring sdio\n");
859
860 /* need to set sdio settings after power is cut from sdio */
861 ath6kl_sdio_config(ar);
862 break;
863
864 case ATH6KL_STATE_ON:
b4b2a0b1
KV		 865 break;
866
867 case ATH6KL_STATE_DEEPSLEEP:
868 break;
d7c44e0b
RM		 869
870 case ATH6KL_STATE_WOW:
871 break;
10509f90
KV		 872 case ATH6KL_STATE_SCHED_SCAN:
873 break;
b4b2a0b1
KV		 874 }
875
52d81a68 876 ath6kl_cfg80211_resume(ar);
aa6cffc1
CN		 877
878 return 0;
879}
880
c7111495
KV		 881/* set the window address register (using 4-byte register access ). */
882static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
883{
884 int status;
885 u8 addr_val[4];
886 s32 i;
887
888 /*
889 * Write bytes 1,2,3 of the register to set the upper address bytes,
890 * the LSB is written last to initiate the access cycle
891 */
892
893 for (i = 1; i <= 3; i++) {
894 /*
895 * Fill the buffer with the address byte value we want to
896 * hit 4 times.
897 */
898 memset(addr_val, ((u8 *)&addr)[i], 4);
899
900 /*
901 * Hit each byte of the register address with a 4-byte
902 * write operation to the same address, this is a harmless
903 * operation.
904 */
905 status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val,
906 4, HIF_WR_SYNC_BYTE_FIX);
907 if (status)
908 break;
909 }
910
911 if (status) {
912 ath6kl_err("%s: failed to write initial bytes of 0x%x "
913 "to window reg: 0x%X\n", __func__,
914 addr, reg_addr);
915 return status;
916 }
917
918 /*
919 * Write the address register again, this time write the whole
920 * 4-byte value. The effect here is that the LSB write causes the
921 * cycle to start, the extra 3 byte write to bytes 1,2,3 has no
922 * effect since we are writing the same values again
923 */
924 status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr),
925 4, HIF_WR_SYNC_BYTE_INC);
926
927 if (status) {
928 ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n",
929 __func__, addr, reg_addr);
930 return status;
931 }
932
933 return 0;
934}
935
936static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data)
937{
938 int status;
939
940 /* set window register to start read cycle */
941 status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS,
942 address);
943
944 if (status)
945 return status;
946
947 /* read the data */
948 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
949 (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC);
950 if (status) {
951 ath6kl_err("%s: failed to read from window data addr\n",
952 __func__);
953 return status;
954 }
955
956 return status;
957}
958
959static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address,
960 __le32 data)
961{
962 int status;
963 u32 val = (__force u32) data;
964
965 /* set write data */
966 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
967 (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC);
968 if (status) {
969 ath6kl_err("%s: failed to write 0x%x to window data addr\n",
970 __func__, data);
971 return status;
972 }
973
974 /* set window register, which starts the write cycle */
975 return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS,
976 address);
977}
978
66b693c3
KV		 979static int ath6kl_sdio_bmi_credits(struct ath6kl *ar)
980{
981 u32 addr;
982 unsigned long timeout;
983 int ret;
984
985 ar->bmi.cmd_credits = 0;
986
987 /* Read the counter register to get the command credits */
988 addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
989
990 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
991 while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) {
992
993 /*
994 * Hit the credit counter with a 4-byte access, the first byte
995 * read will hit the counter and cause a decrement, while the
996 * remaining 3 bytes has no effect. The rationale behind this
997 * is to make all HIF accesses 4-byte aligned.
998 */
999 ret = ath6kl_sdio_read_write_sync(ar, addr,
1000 (u8 *)&ar->bmi.cmd_credits, 4,
1001 HIF_RD_SYNC_BYTE_INC);
1002 if (ret) {
1003 ath6kl_err("Unable to decrement the command credit "
1004 "count register: %d\n", ret);
1005 return ret;
1006 }
1007
1008 /* The counter is only 8 bits.
1009 * Ignore anything in the upper 3 bytes
1010 */
1011 ar->bmi.cmd_credits &= 0xFF;
1012 }
1013
1014 if (!ar->bmi.cmd_credits) {
1015 ath6kl_err("bmi communication timeout\n");
1016 return -ETIMEDOUT;
1017 }
1018
1019 return 0;
1020}
1021
1022static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar)
1023{
1024 unsigned long timeout;
1025 u32 rx_word = 0;
1026 int ret = 0;
1027
1028 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
1029 while ((time_before(jiffies, timeout)) && !rx_word) {
1030 ret = ath6kl_sdio_read_write_sync(ar,
1031 RX_LOOKAHEAD_VALID_ADDRESS,
1032 (u8 *)&rx_word, sizeof(rx_word),
1033 HIF_RD_SYNC_BYTE_INC);
1034 if (ret) {
1035 ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n");
1036 return ret;
1037 }
1038
1039 /* all we really want is one bit */
1040 rx_word &= (1 << ENDPOINT1);
1041 }
1042
1043 if (!rx_word) {
1044 ath6kl_err("bmi_recv_buf FIFO empty\n");
1045 return -EINVAL;
1046 }
1047
1048 return ret;
1049}
1050
1051static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len)
1052{
1053 int ret;
1054 u32 addr;
1055
1056 ret = ath6kl_sdio_bmi_credits(ar);
1057 if (ret)
1058 return ret;
1059
1060 addr = ar->mbox_info.htc_addr;
1061
1062 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1063 HIF_WR_SYNC_BYTE_INC);
1064 if (ret)
1065 ath6kl_err("unable to send the bmi data to the device\n");
1066
1067 return ret;
1068}
1069
1070static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len)
1071{
1072 int ret;
1073 u32 addr;
1074
1075 /*
1076 * During normal bootup, small reads may be required.
1077 * Rather than issue an HIF Read and then wait as the Target
1078 * adds successive bytes to the FIFO, we wait here until
1079 * we know that response data is available.
1080 *
1081 * This allows us to cleanly timeout on an unexpected
1082 * Target failure rather than risk problems at the HIF level.
1083 * In particular, this avoids SDIO timeouts and possibly garbage
1084 * data on some host controllers. And on an interconnect
1085 * such as Compact Flash (as well as some SDIO masters) which
1086 * does not provide any indication on data timeout, it avoids
1087 * a potential hang or garbage response.
1088 *
1089 * Synchronization is more difficult for reads larger than the
1090 * size of the MBOX FIFO (128B), because the Target is unable
1091 * to push the 129th byte of data until AFTER the Host posts an
1092 * HIF Read and removes some FIFO data. So for large reads the
1093 * Host proceeds to post an HIF Read BEFORE all the data is
1094 * actually available to read. Fortunately, large BMI reads do
1095 * not occur in practice -- they're supported for debug/development.
1096 *
1097 * So Host/Target BMI synchronization is divided into these cases:
1098 * CASE 1: length < 4
1099 * Should not happen
1100 *
1101 * CASE 2: 4 <= length <= 128
1102 * Wait for first 4 bytes to be in FIFO
1103 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1104 * a BMI command credit, which indicates that the ENTIRE
1105 * response is available in the the FIFO
1106 *
1107 * CASE 3: length > 128
1108 * Wait for the first 4 bytes to be in FIFO
1109 *
1110 * For most uses, a small timeout should be sufficient and we will
1111 * usually see a response quickly; but there may be some unusual
1112 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1113 * For now, we use an unbounded busy loop while waiting for
1114 * BMI_EXECUTE.
1115 *
1116 * If BMI_EXECUTE ever needs to support longer-latency execution,
1117 * especially in production, this code needs to be enhanced to sleep
1118 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1119 * a function of Host processor speed.
1120 */
1121 if (len >= 4) { /* NB: Currently, always true */
1122 ret = ath6kl_bmi_get_rx_lkahd(ar);
1123 if (ret)
1124 return ret;
1125 }
1126
1127 addr = ar->mbox_info.htc_addr;
1128 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1129 HIF_RD_SYNC_BYTE_INC);
1130 if (ret) {
1131 ath6kl_err("Unable to read the bmi data from the device: %d\n",
1132 ret);
1133 return ret;
1134 }
1135
1136 return 0;
1137}
1138
32a07e44
KV		 1139static void ath6kl_sdio_stop(struct ath6kl *ar)
1140{
1141 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
1142 struct bus_request *req, *tmp_req;
1143 void *context;
1144
1145 /* FIXME: make sure that wq is not queued again */
1146
1147 cancel_work_sync(&ar_sdio->wr_async_work);
1148
1149 spin_lock_bh(&ar_sdio->wr_async_lock);
1150
1151 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1152 list_del(&req->list);
1153
1154 if (req->scat_req) {
1155 /* this is a scatter gather request */
1156 req->scat_req->status = -ECANCELED;
1157 req->scat_req->complete(ar_sdio->ar->htc_target,
1158 req->scat_req);
1159 } else {
1160 context = req->packet;
1161 ath6kl_sdio_free_bus_req(ar_sdio, req);
1162 ath6kl_hif_rw_comp_handler(context, -ECANCELED);
1163 }
1164 }
1165
1166 spin_unlock_bh(&ar_sdio->wr_async_lock);
1167
1168 WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4);
1169}
1170
bdcd8170
KV		 1171static const struct ath6kl_hif_ops ath6kl_sdio_ops = {
1172 .read_write_sync = ath6kl_sdio_read_write_sync,
1173 .write_async = ath6kl_sdio_write_async,
1174 .irq_enable = ath6kl_sdio_irq_enable,
1175 .irq_disable = ath6kl_sdio_irq_disable,
1176 .scatter_req_get = ath6kl_sdio_scatter_req_get,
1177 .scatter_req_add = ath6kl_sdio_scatter_req_add,
1178 .enable_scatter = ath6kl_sdio_enable_scatter,
f74a7361 1179 .scat_req_rw = ath6kl_sdio_async_rw_scatter,
bdcd8170 1180 .cleanup_scatter = ath6kl_sdio_cleanup_scatter,
abcb344b 1181 .suspend = ath6kl_sdio_suspend,
aa6cffc1 1182 .resume = ath6kl_sdio_resume,
c7111495
KV		 1183 .diag_read32 = ath6kl_sdio_diag_read32,
1184 .diag_write32 = ath6kl_sdio_diag_write32,
66b693c3
KV		 1185 .bmi_read = ath6kl_sdio_bmi_read,
1186 .bmi_write = ath6kl_sdio_bmi_write,
b2e75698
KV		 1187 .power_on = ath6kl_sdio_power_on,
1188 .power_off = ath6kl_sdio_power_off,
32a07e44 1189 .stop = ath6kl_sdio_stop,
bdcd8170
KV		 1190};
1191
b4b2a0b1
KV		 1192#ifdef CONFIG_PM_SLEEP
1193
1194/*
1195 * Empty handlers so that mmc subsystem doesn't remove us entirely during
1196 * suspend. We instead follow cfg80211 suspend/resume handlers.
1197 */
1198static int ath6kl_sdio_pm_suspend(struct device *device)
1199{
1200 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n");
1201
1202 return 0;
1203}
1204
1205static int ath6kl_sdio_pm_resume(struct device *device)
1206{
1207 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n");
1208
1209 return 0;
1210}
1211
1212static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend,
1213 ath6kl_sdio_pm_resume);
1214
1215#define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops)
1216
1217#else
1218
1219#define ATH6KL_SDIO_PM_OPS NULL
1220
1221#endif /* CONFIG_PM_SLEEP */
1222
bdcd8170
KV		 1223static int ath6kl_sdio_probe(struct sdio_func *func,
1224 const struct sdio_device_id *id)
1225{
1226 int ret;
1227 struct ath6kl_sdio *ar_sdio;
1228 struct ath6kl *ar;
1229 int count;
1230
3ef987be
KV		 1231 ath6kl_dbg(ATH6KL_DBG_BOOT,
1232 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
f7325b85
KV		 1233 func->num, func->vendor, func->device,
1234 func->max_blksize, func->cur_blksize);
bdcd8170
KV		 1235
1236 ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL);
1237 if (!ar_sdio)
1238 return -ENOMEM;
1239
1240 ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
1241 if (!ar_sdio->dma_buffer) {
1242 ret = -ENOMEM;
1243 goto err_hif;
1244 }
1245
1246 ar_sdio->func = func;
1247 sdio_set_drvdata(func, ar_sdio);
1248
1249 ar_sdio->id = id;
1250 ar_sdio->is_disabled = true;
1251
1252 spin_lock_init(&ar_sdio->lock);
1253 spin_lock_init(&ar_sdio->scat_lock);
1254 spin_lock_init(&ar_sdio->wr_async_lock);
fdb28589 1255 mutex_init(&ar_sdio->dma_buffer_mutex);
bdcd8170
KV		 1256
1257 INIT_LIST_HEAD(&ar_sdio->scat_req);
1258 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
1259 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
1260
1261 INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work);
1262
1263 for (count = 0; count < BUS_REQUEST_MAX_NUM; count++)
1264 ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]);
1265
1266 ar = ath6kl_core_alloc(&ar_sdio->func->dev);
1267 if (!ar) {
1268 ath6kl_err("Failed to alloc ath6kl core\n");
1269 ret = -ENOMEM;
1270 goto err_dma;
1271 }
1272
1273 ar_sdio->ar = ar;
77eab1e9 1274 ar->hif_type = ATH6KL_HIF_TYPE_SDIO;
bdcd8170
KV		 1275 ar->hif_priv = ar_sdio;
1276 ar->hif_ops = &ath6kl_sdio_ops;
1f4c894d 1277 ar->bmi.max_data_size = 256;
bdcd8170
KV		 1278
1279 ath6kl_sdio_set_mbox_info(ar);
1280
e28e8104 1281 ret = ath6kl_sdio_config(ar);
bdcd8170 1282 if (ret) {
e28e8104
KV		 1283 ath6kl_err("Failed to config sdio: %d\n", ret);
1284 goto err_core_alloc;
bdcd8170
KV		 1285 }
1286
bdcd8170
KV		 1287 ret = ath6kl_core_init(ar);
1288 if (ret) {
1289 ath6kl_err("Failed to init ath6kl core\n");
e28e8104 1290 goto err_core_alloc;
bdcd8170
KV		 1291 }
1292
1293 return ret;
1294
8dafb70e
VT		 1295err_core_alloc:
1296 ath6kl_core_free(ar_sdio->ar);
bdcd8170
KV		 1297err_dma:
1298 kfree(ar_sdio->dma_buffer);
1299err_hif:
1300 kfree(ar_sdio);
1301
1302 return ret;
1303}
1304
1305static void ath6kl_sdio_remove(struct sdio_func *func)
1306{
1307 struct ath6kl_sdio *ar_sdio;
1308
3ef987be
KV		 1309 ath6kl_dbg(ATH6KL_DBG_BOOT,
1310 "sdio removed func %d vendor 0x%x device 0x%x\n",
f7325b85
KV		 1311 func->num, func->vendor, func->device);
1312
bdcd8170
KV		 1313 ar_sdio = sdio_get_drvdata(func);
1314
1315 ath6kl_stop_txrx(ar_sdio->ar);
1316 cancel_work_sync(&ar_sdio->wr_async_work);
1317
6db8fa53 1318 ath6kl_core_cleanup(ar_sdio->ar);
bdcd8170 1319
bdcd8170
KV		 1320 kfree(ar_sdio->dma_buffer);
1321 kfree(ar_sdio);
1322}
1323
1324static const struct sdio_device_id ath6kl_sdio_devices[] = {
1325 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))},
1326 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))},
d93e2c2f
NG		 1327 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))},
1328 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))},
bdcd8170
KV		 1329 {},
1330};
1331
1332MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices);
1333
1334static struct sdio_driver ath6kl_sdio_driver = {
fde57764 1335 .name = "ath6kl_sdio",
bdcd8170
KV		 1336 .id_table = ath6kl_sdio_devices,
1337 .probe = ath6kl_sdio_probe,
1338 .remove = ath6kl_sdio_remove,
b4b2a0b1 1339 .drv.pm = ATH6KL_SDIO_PM_OPS,
bdcd8170
KV		 1340};
1341
1342static int __init ath6kl_sdio_init(void)
1343{
1344 int ret;
1345
1346 ret = sdio_register_driver(&ath6kl_sdio_driver);
1347 if (ret)
1348 ath6kl_err("sdio driver registration failed: %d\n", ret);
1349
1350 return ret;
1351}
1352
1353static void __exit ath6kl_sdio_exit(void)
1354{
1355 sdio_unregister_driver(&ath6kl_sdio_driver);
1356}
1357
1358module_init(ath6kl_sdio_init);
1359module_exit(ath6kl_sdio_exit);
1360
1361MODULE_AUTHOR("Atheros Communications, Inc.");
1362MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices");
1363MODULE_LICENSE("Dual BSD/GPL");
1364
0d0192ba
KV		 1365MODULE_FIRMWARE(AR6003_HW_2_0_OTP_FILE);
1366MODULE_FIRMWARE(AR6003_HW_2_0_FIRMWARE_FILE);
1367MODULE_FIRMWARE(AR6003_HW_2_0_PATCH_FILE);
1368MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE);
1369MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE);
1370MODULE_FIRMWARE(AR6003_HW_2_1_1_OTP_FILE);
1371MODULE_FIRMWARE(AR6003_HW_2_1_1_FIRMWARE_FILE);
1372MODULE_FIRMWARE(AR6003_HW_2_1_1_PATCH_FILE);
1373MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE);
1374MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE);
f0ea5d58
KV		 1375MODULE_FIRMWARE(AR6004_HW_1_0_FIRMWARE_FILE);
1376MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE);
1377MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE);
1378MODULE_FIRMWARE(AR6004_HW_1_1_FIRMWARE_FILE);
1379MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE);
1380MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE);
Linux kernel - Deliverables
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