[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ani.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/kernel.h>
#include <linux/export.h>
#include "hw.h"
#include "hw-ops.h"

struct ani_ofdm_level_entry {
	int spur_immunity_level;
	int fir_step_level;
	int ofdm_weak_signal_on;
};

/* values here are relative to the INI */

/*
 * Legend:
 *
 * SI: Spur immunity
 * FS: FIR Step
 * WS: OFDM / CCK Weak Signal detection
 * MRC-CCK: Maximal Ratio Combining for CCK
 */

static const struct ani_ofdm_level_entry ofdm_level_table[] = {
	/* SI  FS  WS */
	{  0,  0,  1  }, /* lvl 0 */
	{  1,  1,  1  }, /* lvl 1 */
	{  2,  2,  1  }, /* lvl 2 */
	{  3,  2,  1  }, /* lvl 3  (default) */
	{  4,  3,  1  }, /* lvl 4 */
	{  5,  4,  1  }, /* lvl 5 */
	{  6,  5,  1  }, /* lvl 6 */
	{  7,  6,  1  }, /* lvl 7 */
	{  7,  7,  1  }, /* lvl 8 */
	{  7,  8,  0  }  /* lvl 9 */
};
#define ATH9K_ANI_OFDM_NUM_LEVEL \
	ARRAY_SIZE(ofdm_level_table)
#define ATH9K_ANI_OFDM_MAX_LEVEL \
	(ATH9K_ANI_OFDM_NUM_LEVEL-1)
#define ATH9K_ANI_OFDM_DEF_LEVEL \
	3 /* default level - matches the INI settings */

/*
 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
 * With OFDM for single stream you just add up all antenna inputs, you're
 * only interested in what you get after FFT. Signal aligment is also not
 * required for OFDM because any phase difference adds up in the frequency
 * domain.
 *
 * MRC requires extra work for use with CCK. You need to align the antenna
 * signals from the different antenna before you can add the signals together.
 * You need aligment of signals as CCK is in time domain, so addition can cancel
 * your signal completely if phase is 180 degrees (think of adding sine waves).
 * You also need to remove noise before the addition and this is where ANI
 * MRC CCK comes into play. One of the antenna inputs may be stronger but
 * lower SNR, so just adding after alignment can be dangerous.
 *
 * Regardless of alignment in time, the antenna signals add constructively after
 * FFT and improve your reception. For more information:
 *
 * http://en.wikipedia.org/wiki/Maximal-ratio_combining
 */

struct ani_cck_level_entry {
	int fir_step_level;
	int mrc_cck_on;
};

static const struct ani_cck_level_entry cck_level_table[] = {
	/* FS  MRC-CCK  */
	{  0,  1  }, /* lvl 0 */
	{  1,  1  }, /* lvl 1 */
	{  2,  1  }, /* lvl 2  (default) */
	{  3,  1  }, /* lvl 3 */
	{  4,  0  }, /* lvl 4 */
	{  5,  0  }, /* lvl 5 */
	{  6,  0  }, /* lvl 6 */
	{  7,  0  }, /* lvl 7 (only for high rssi) */
	{  8,  0  }  /* lvl 8 (only for high rssi) */
};

#define ATH9K_ANI_CCK_NUM_LEVEL \
	ARRAY_SIZE(cck_level_table)
#define ATH9K_ANI_CCK_MAX_LEVEL \
	(ATH9K_ANI_CCK_NUM_LEVEL-1)
#define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
	(ATH9K_ANI_CCK_NUM_LEVEL-3)
#define ATH9K_ANI_CCK_DEF_LEVEL \
	2 /* default level - matches the INI settings */

static void ath9k_hw_update_mibstats(struct ath_hw *ah,
				     struct ath9k_mib_stats *stats)
{
	u32 addr[5] = {AR_RTS_OK, AR_RTS_FAIL, AR_ACK_FAIL,
		       AR_FCS_FAIL, AR_BEACON_CNT};
	u32 data[5];

	REG_READ_MULTI(ah, &addr[0], &data[0], 5);
	/* AR_RTS_OK */
	stats->rts_good += data[0];
	/* AR_RTS_FAIL */
	stats->rts_bad += data[1];
	/* AR_ACK_FAIL */
	stats->ackrcv_bad += data[2];
	/* AR_FCS_FAIL */
	stats->fcs_bad += data[3];
	/* AR_BEACON_CNT */
	stats->beacons += data[4];
}

static void ath9k_ani_restart(struct ath_hw *ah)
{
	struct ar5416AniState *aniState;

	if (!ah->curchan)
		return;

	aniState = &ah->ani;
	aniState->listenTime = 0;

	ENABLE_REGWRITE_BUFFER(ah);

	REG_WRITE(ah, AR_PHY_ERR_1, 0);
	REG_WRITE(ah, AR_PHY_ERR_2, 0);
	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);

	REGWRITE_BUFFER_FLUSH(ah);

	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);

	aniState->ofdmPhyErrCount = 0;
	aniState->cckPhyErrCount = 0;
}

/* Adjust the OFDM Noise Immunity Level */
static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel,
				  bool scan)
{
	struct ar5416AniState *aniState = &ah->ani;
	struct ath_common *common = ath9k_hw_common(ah);
	const struct ani_ofdm_level_entry *entry_ofdm;
	const struct ani_cck_level_entry *entry_cck;
	bool weak_sig;

	ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
		aniState->ofdmNoiseImmunityLevel,
		immunityLevel, BEACON_RSSI(ah),
		ATH9K_ANI_RSSI_THR_LOW,
		ATH9K_ANI_RSSI_THR_HIGH);

	if (AR_SREV_9100(ah) && immunityLevel < ATH9K_ANI_OFDM_DEF_LEVEL)
		immunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;

	if (!scan)
		aniState->ofdmNoiseImmunityLevel = immunityLevel;

	entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
	entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];

	if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
		ath9k_hw_ani_control(ah,
				     ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
				     entry_ofdm->spur_immunity_level);

	if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
	    entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
		ath9k_hw_ani_control(ah,
				     ATH9K_ANI_FIRSTEP_LEVEL,
				     entry_ofdm->fir_step_level);

	weak_sig = entry_ofdm->ofdm_weak_signal_on;
	if (ah->opmode == NL80211_IFTYPE_STATION &&
	    BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_HIGH)
		weak_sig = true;
	/*
	 * Newer chipsets are better at dealing with high PHY error counts -
	 * keep weak signal detection enabled when no RSSI threshold is
	 * available to determine if it is needed (mode != STA)
	 */
	else if (AR_SREV_9300_20_OR_LATER(ah) &&
		 ah->opmode != NL80211_IFTYPE_STATION)
		weak_sig = true;

	/* Older chipsets are more sensitive to high PHY error counts */
	else if (!AR_SREV_9300_20_OR_LATER(ah) &&
		 aniState->ofdmNoiseImmunityLevel >= 8)
		weak_sig = false;

	if (aniState->ofdmWeakSigDetect != weak_sig)
		ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
				     weak_sig);

	if (!AR_SREV_9300_20_OR_LATER(ah))
		return;

	if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) {
		ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
		ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI;
	} else {
		ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI;
		ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
	}
}

static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
{
	struct ar5416AniState *aniState;

	if (!ah->curchan)
		return;

	aniState = &ah->ani;

	if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
		ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1, false);
}

/*
 * Set the ANI settings to match an CCK level.
 */
static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel,
				 bool scan)
{
	struct ar5416AniState *aniState = &ah->ani;
	struct ath_common *common = ath9k_hw_common(ah);
	const struct ani_ofdm_level_entry *entry_ofdm;
	const struct ani_cck_level_entry *entry_cck;

	ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
		aniState->cckNoiseImmunityLevel, immunityLevel,
		BEACON_RSSI(ah), ATH9K_ANI_RSSI_THR_LOW,
		ATH9K_ANI_RSSI_THR_HIGH);

	if (AR_SREV_9100(ah) && immunityLevel < ATH9K_ANI_CCK_DEF_LEVEL)
		immunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;

	if (ah->opmode == NL80211_IFTYPE_STATION &&
	    BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_LOW &&
	    immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
		immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;

	if (!scan)
		aniState->cckNoiseImmunityLevel = immunityLevel;

	entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
	entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];

	if (aniState->firstepLevel != entry_cck->fir_step_level &&
	    entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
		ath9k_hw_ani_control(ah,
				     ATH9K_ANI_FIRSTEP_LEVEL,
				     entry_cck->fir_step_level);

	/* Skip MRC CCK for pre AR9003 families */
	if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) ||
	    AR_SREV_9565(ah) || AR_SREV_9561(ah))
		return;

	if (aniState->mrcCCK != entry_cck->mrc_cck_on)
		ath9k_hw_ani_control(ah,
				     ATH9K_ANI_MRC_CCK,
				     entry_cck->mrc_cck_on);
}

static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
{
	struct ar5416AniState *aniState;

	if (!ah->curchan)
		return;

	aniState = &ah->ani;

	if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
		ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1,
				     false);
}

/*
 * only lower either OFDM or CCK errors per turn
 * we lower the other one next time
 */
static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
{
	struct ar5416AniState *aniState;

	aniState = &ah->ani;

	/* lower OFDM noise immunity */
	if (aniState->ofdmNoiseImmunityLevel > 0 &&
	    (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
		ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1,
				      false);
		return;
	}

	/* lower CCK noise immunity */
	if (aniState->cckNoiseImmunityLevel > 0)
		ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1,
				     false);
}

/*
 * Restore the ANI parameters in the HAL and reset the statistics.
 * This routine should be called for every hardware reset and for
 * every channel change.
 */
void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
{
	struct ar5416AniState *aniState = &ah->ani;
	struct ath9k_channel *chan = ah->curchan;
	struct ath_common *common = ath9k_hw_common(ah);
	int ofdm_nil, cck_nil;

	if (!ah->curchan)
		return;

	BUG_ON(aniState == NULL);
	ah->stats.ast_ani_reset++;

	ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL,
			 aniState->ofdmNoiseImmunityLevel);
	cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL,
			 aniState->cckNoiseImmunityLevel);

	if (is_scanning ||
	    (ah->opmode != NL80211_IFTYPE_STATION &&
	     ah->opmode != NL80211_IFTYPE_ADHOC)) {
		/*
		 * If we're scanning or in AP mode, the defaults (ini)
		 * should be in place. For an AP we assume the historical
		 * levels for this channel are probably outdated so start
		 * from defaults instead.
		 */
		if (aniState->ofdmNoiseImmunityLevel !=
		    ATH9K_ANI_OFDM_DEF_LEVEL ||
		    aniState->cckNoiseImmunityLevel !=
		    ATH9K_ANI_CCK_DEF_LEVEL) {
			ath_dbg(common, ANI,
				"Restore defaults: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n",
				ah->opmode,
				chan->channel,
				is_scanning,
				aniState->ofdmNoiseImmunityLevel,
				aniState->cckNoiseImmunityLevel);

			ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL;
			cck_nil = ATH9K_ANI_CCK_DEF_LEVEL;
		}
	} else {
		/*
		 * restore historical levels for this channel
		 */
		ath_dbg(common, ANI,
			"Restore history: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n",
			ah->opmode,
			chan->channel,
			is_scanning,
			aniState->ofdmNoiseImmunityLevel,
			aniState->cckNoiseImmunityLevel);
	}
	ath9k_hw_set_ofdm_nil(ah, ofdm_nil, is_scanning);
	ath9k_hw_set_cck_nil(ah, cck_nil, is_scanning);

	ath9k_ani_restart(ah);
}

static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ar5416AniState *aniState = &ah->ani;
	u32 phyCnt1, phyCnt2;
	int32_t listenTime;

	ath_hw_cycle_counters_update(common);
	listenTime = ath_hw_get_listen_time(common);

	if (listenTime <= 0) {
		ah->stats.ast_ani_lneg_or_lzero++;
		ath9k_ani_restart(ah);
		return false;
	}

	aniState->listenTime += listenTime;

	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);

	phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
	phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);

	ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount;
	aniState->ofdmPhyErrCount = phyCnt1;

	ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount;
	aniState->cckPhyErrCount = phyCnt2;

	return true;
}

void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
{
	struct ar5416AniState *aniState;
	struct ath_common *common = ath9k_hw_common(ah);
	u32 ofdmPhyErrRate, cckPhyErrRate;

	if (!ah->curchan)
		return;

	aniState = &ah->ani;
	if (!ath9k_hw_ani_read_counters(ah))
		return;

	ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
			 aniState->listenTime;
	cckPhyErrRate =  aniState->cckPhyErrCount * 1000 /
			 aniState->listenTime;

	ath_dbg(common, ANI,
		"listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
		aniState->listenTime,
		aniState->ofdmNoiseImmunityLevel,
		ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
		cckPhyErrRate, aniState->ofdmsTurn);

	if (aniState->listenTime > ah->aniperiod) {
		if (cckPhyErrRate < ah->config.cck_trig_low &&
		    ofdmPhyErrRate < ah->config.ofdm_trig_low) {
			ath9k_hw_ani_lower_immunity(ah);
			aniState->ofdmsTurn = !aniState->ofdmsTurn;
		} else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) {
			ath9k_hw_ani_ofdm_err_trigger(ah);
			aniState->ofdmsTurn = false;
		} else if (cckPhyErrRate > ah->config.cck_trig_high) {
			ath9k_hw_ani_cck_err_trigger(ah);
			aniState->ofdmsTurn = true;
		}
		ath9k_ani_restart(ah);
	}
}
EXPORT_SYMBOL(ath9k_hw_ani_monitor);

void ath9k_enable_mib_counters(struct ath_hw *ah)
{
	struct ath_common *common = ath9k_hw_common(ah);

	ath_dbg(common, ANI, "Enable MIB counters\n");

	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);

	ENABLE_REGWRITE_BUFFER(ah);

	REG_WRITE(ah, AR_FILT_OFDM, 0);
	REG_WRITE(ah, AR_FILT_CCK, 0);
	REG_WRITE(ah, AR_MIBC,
		  ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
		  & 0x0f);
	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);

	REGWRITE_BUFFER_FLUSH(ah);
}

/* Freeze the MIB counters, get the stats and then clear them */
void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
{
	struct ath_common *common = ath9k_hw_common(ah);

	ath_dbg(common, ANI, "Disable MIB counters\n");

	REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
	REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
	REG_WRITE(ah, AR_FILT_OFDM, 0);
	REG_WRITE(ah, AR_FILT_CCK, 0);
}
EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);

void ath9k_hw_ani_init(struct ath_hw *ah)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ar5416AniState *ani = &ah->ani;

	ath_dbg(common, ANI, "Initialize ANI\n");

	if (AR_SREV_9300_20_OR_LATER(ah)) {
		ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
		ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
		ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH;
		ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW;
	} else {
		ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
		ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
		ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
		ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
	}

	ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
	ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
	ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false;
	ani->ofdmsTurn = true;
	ani->ofdmWeakSigDetect = true;
	ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
	ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;

	/*
	 * since we expect some ongoing maintenance on the tables, let's sanity
	 * check here default level should not modify INI setting.
	 */
	ah->aniperiod = ATH9K_ANI_PERIOD;
	ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL;

	ath9k_ani_restart(ah);
	ath9k_enable_mib_counters(ah);
}
Commit	Line	Data
f1dc5600	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
f1dc5600 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
bbce80e1	17	#include <linux/kernel.h>
ee40fa06	18	#include <linux/export.h>
cfe8cba9	19	#include "hw.h"
c16fcb49	20	#include "hw-ops.h"
f1dc5600	21
e36b27af LR	22	struct ani_ofdm_level_entry {
	23	int spur_immunity_level;
	24	int fir_step_level;
	25	int ofdm_weak_signal_on;
	26	};
	27
	28	/* values here are relative to the INI */
	29
	30	/*
	31	* Legend:
	32	*
	33	* SI: Spur immunity
	34	* FS: FIR Step
	35	* WS: OFDM / CCK Weak Signal detection
	36	* MRC-CCK: Maximal Ratio Combining for CCK
	37	*/
	38
	39	static const struct ani_ofdm_level_entry ofdm_level_table[] = {
	40	/* SI FS WS */
	41	{ 0, 0, 1 }, /* lvl 0 */
	42	{ 1, 1, 1 }, /* lvl 1 */
	43	{ 2, 2, 1 }, /* lvl 2 */
	44	{ 3, 2, 1 }, /* lvl 3 (default) */
	45	{ 4, 3, 1 }, /* lvl 4 */
	46	{ 5, 4, 1 }, /* lvl 5 */
	47	{ 6, 5, 1 }, /* lvl 6 */
	48	{ 7, 6, 1 }, /* lvl 7 */
b99553fb SM	49	{ 7, 7, 1 }, /* lvl 8 */
b99553fb SM	50	{ 7, 8, 0 } /* lvl 9 */
e36b27af LR	51	};
e36b27af LR	52	#define ATH9K_ANI_OFDM_NUM_LEVEL \
bbce80e1	53	ARRAY_SIZE(ofdm_level_table)
e36b27af LR	54	#define ATH9K_ANI_OFDM_MAX_LEVEL \
	55	(ATH9K_ANI_OFDM_NUM_LEVEL-1)
	56	#define ATH9K_ANI_OFDM_DEF_LEVEL \
	57	3 /* default level - matches the INI settings */
	58
	59	/*
	60	* MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
	61	* With OFDM for single stream you just add up all antenna inputs, you're
	62	* only interested in what you get after FFT. Signal aligment is also not
	63	* required for OFDM because any phase difference adds up in the frequency
	64	* domain.
	65	*
	66	* MRC requires extra work for use with CCK. You need to align the antenna
	67	* signals from the different antenna before you can add the signals together.
	68	* You need aligment of signals as CCK is in time domain, so addition can cancel
	69	* your signal completely if phase is 180 degrees (think of adding sine waves).
	70	* You also need to remove noise before the addition and this is where ANI
	71	* MRC CCK comes into play. One of the antenna inputs may be stronger but
	72	* lower SNR, so just adding after alignment can be dangerous.
	73	*
	74	* Regardless of alignment in time, the antenna signals add constructively after
	75	* FFT and improve your reception. For more information:
	76	*
	77	* http://en.wikipedia.org/wiki/Maximal-ratio_combining
	78	*/
	79
	80	struct ani_cck_level_entry {
	81	int fir_step_level;
	82	int mrc_cck_on;
	83	};
	84
	85	static const struct ani_cck_level_entry cck_level_table[] = {
	86	/* FS MRC-CCK */
	87	{ 0, 1 }, /* lvl 0 */
	88	{ 1, 1 }, /* lvl 1 */
	89	{ 2, 1 }, /* lvl 2 (default) */
	90	{ 3, 1 }, /* lvl 3 */
	91	{ 4, 0 }, /* lvl 4 */
	92	{ 5, 0 }, /* lvl 5 */
	93	{ 6, 0 }, /* lvl 6 */
b99553fb SM	94	{ 7, 0 }, /* lvl 7 (only for high rssi) */
b99553fb SM	95	{ 8, 0 } /* lvl 8 (only for high rssi) */
e36b27af LR	96	};
	97
	98	#define ATH9K_ANI_CCK_NUM_LEVEL \
bbce80e1	99	ARRAY_SIZE(cck_level_table)
e36b27af LR	100	#define ATH9K_ANI_CCK_MAX_LEVEL \
	101	(ATH9K_ANI_CCK_NUM_LEVEL-1)
	102	#define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
	103	(ATH9K_ANI_CCK_NUM_LEVEL-3)
	104	#define ATH9K_ANI_CCK_DEF_LEVEL \
	105	2 /* default level - matches the INI settings */
	106
cbe61d8a	107	static void ath9k_hw_update_mibstats(struct ath_hw *ah,
f1dc5600 S	108	struct ath9k_mib_stats *stats)
f1dc5600 S	109	{
9c05babd OR	110	u32 addr[5] = {AR_RTS_OK, AR_RTS_FAIL, AR_ACK_FAIL,
	111	AR_FCS_FAIL, AR_BEACON_CNT};
	112	u32 data[5];
	113
	114	REG_READ_MULTI(ah, &addr[0], &data[0], 5);
	115	/* AR_RTS_OK */
	116	stats->rts_good += data[0];
	117	/* AR_RTS_FAIL */
	118	stats->rts_bad += data[1];
	119	/* AR_ACK_FAIL */
	120	stats->ackrcv_bad += data[2];
	121	/* AR_FCS_FAIL */
	122	stats->fcs_bad += data[3];
	123	/* AR_BEACON_CNT */
	124	stats->beacons += data[4];
f1dc5600 S	125	}
f1dc5600 S	126
093115b7	127	static void ath9k_ani_restart(struct ath_hw *ah)
f1dc5600	128	{
f1dc5600 S	129	struct ar5416AniState *aniState;
f1dc5600 S	130
e323300d	131	if (!ah->curchan)
f1dc5600 S	132	return;
f1dc5600 S	133
c24bd362	134	aniState = &ah->ani;
f1dc5600	135	aniState->listenTime = 0;
1aa8e847	136
e36b27af LR	137	ENABLE_REGWRITE_BUFFER(ah);
e36b27af LR	138
465dce62 FF	139	REG_WRITE(ah, AR_PHY_ERR_1, 0);
465dce62 FF	140	REG_WRITE(ah, AR_PHY_ERR_2, 0);
e36b27af LR	141	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
	142	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
	143
	144	REGWRITE_BUFFER_FLUSH(ah);
e36b27af LR	145
	146	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
	147
	148	aniState->ofdmPhyErrCount = 0;
	149	aniState->cckPhyErrCount = 0;
	150	}
	151
e36b27af	152	/* Adjust the OFDM Noise Immunity Level */
73dc3eb8 FF	153	static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel,
73dc3eb8 FF	154	bool scan)
e36b27af	155	{
c24bd362	156	struct ar5416AniState *aniState = &ah->ani;
e36b27af LR	157	struct ath_common *common = ath9k_hw_common(ah);
	158	const struct ani_ofdm_level_entry *entry_ofdm;
	159	const struct ani_cck_level_entry *entry_cck;
0b81cc39	160	bool weak_sig;
e36b27af	161
d2182b69	162	ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
226afe68	163	aniState->ofdmNoiseImmunityLevel,
35e808b7	164	immunityLevel, BEACON_RSSI(ah),
9dbac67d FF	165	ATH9K_ANI_RSSI_THR_LOW,
9dbac67d FF	166	ATH9K_ANI_RSSI_THR_HIGH);
e36b27af	167
ae9c25a1 FF	168	if (AR_SREV_9100(ah) && immunityLevel < ATH9K_ANI_OFDM_DEF_LEVEL)
	169	immunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
	170
73dc3eb8	171	if (!scan)
1e8f0a31	172	aniState->ofdmNoiseImmunityLevel = immunityLevel;
e36b27af LR	173
	174	entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
	175	entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
	176
	177	if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
	178	ath9k_hw_ani_control(ah,
	179	ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
	180	entry_ofdm->spur_immunity_level);
	181
	182	if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
	183	entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
	184	ath9k_hw_ani_control(ah,
	185	ATH9K_ANI_FIRSTEP_LEVEL,
	186	entry_ofdm->fir_step_level);
	187
0b81cc39 FF	188	weak_sig = entry_ofdm->ofdm_weak_signal_on;
0b81cc39 FF	189	if (ah->opmode == NL80211_IFTYPE_STATION &&
9dbac67d	190	BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_HIGH)
0b81cc39	191	weak_sig = true;
80b4205b	192	/*
6241226f FF	193	* Newer chipsets are better at dealing with high PHY error counts -
	194	* keep weak signal detection enabled when no RSSI threshold is
	195	* available to determine if it is needed (mode != STA)
80b4205b	196	*/
6241226f FF	197	else if (AR_SREV_9300_20_OR_LATER(ah) &&
	198	ah->opmode != NL80211_IFTYPE_STATION)
	199	weak_sig = true;
	200
f5547245 FF	201	/* Older chipsets are more sensitive to high PHY error counts */
	202	else if (!AR_SREV_9300_20_OR_LATER(ah) &&
	203	aniState->ofdmNoiseImmunityLevel >= 8)
	204	weak_sig = false;
	205
6241226f FF	206	if (aniState->ofdmWeakSigDetect != weak_sig)
	207	ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
	208	weak_sig);
55fee98a	209
f5547245 FF	210	if (!AR_SREV_9300_20_OR_LATER(ah))
	211	return;
	212
55fee98a SM	213	if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) {
	214	ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
	215	ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI;
	216	} else {
	217	ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI;
	218	ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
	219	}
e36b27af LR	220	}
e36b27af LR	221
8eb4980c	222	static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
e36b27af LR	223	{
	224	struct ar5416AniState *aniState;
	225
e323300d	226	if (!ah->curchan)
e36b27af LR	227	return;
e36b27af LR	228
c24bd362	229	aniState = &ah->ani;
e36b27af LR	230
e36b27af LR	231	if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
73dc3eb8	232	ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1, false);
e36b27af LR	233	}
	234
	235	/*
	236	* Set the ANI settings to match an CCK level.
	237	*/
73dc3eb8 FF	238	static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel,
73dc3eb8 FF	239	bool scan)
e36b27af	240	{
c24bd362	241	struct ar5416AniState *aniState = &ah->ani;
e36b27af LR	242	struct ath_common *common = ath9k_hw_common(ah);
	243	const struct ani_ofdm_level_entry *entry_ofdm;
	244	const struct ani_cck_level_entry *entry_cck;
	245
d2182b69	246	ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
226afe68	247	aniState->cckNoiseImmunityLevel, immunityLevel,
9dbac67d FF	248	BEACON_RSSI(ah), ATH9K_ANI_RSSI_THR_LOW,
9dbac67d FF	249	ATH9K_ANI_RSSI_THR_HIGH);
e36b27af	250
ae9c25a1 FF	251	if (AR_SREV_9100(ah) && immunityLevel < ATH9K_ANI_CCK_DEF_LEVEL)
	252	immunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
	253
5330df7b	254	if (ah->opmode == NL80211_IFTYPE_STATION &&
9dbac67d	255	BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_LOW &&
e36b27af LR	256	immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
	257	immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
	258
73dc3eb8	259	if (!scan)
1e8f0a31	260	aniState->cckNoiseImmunityLevel = immunityLevel;
e36b27af LR	261
	262	entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
	263	entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
	264
	265	if (aniState->firstepLevel != entry_cck->fir_step_level &&
	266	entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
	267	ath9k_hw_ani_control(ah,
	268	ATH9K_ANI_FIRSTEP_LEVEL,
	269	entry_cck->fir_step_level);
	270
	271	/* Skip MRC CCK for pre AR9003 families */
ede6a5e7 MP	272	if (!AR_SREV_9300_20_OR_LATER(ah) \|\| AR_SREV_9485(ah) \|\|
ede6a5e7 MP	273	AR_SREV_9565(ah) \|\| AR_SREV_9561(ah))
e36b27af LR	274	return;
e36b27af LR	275
81b67fd6	276	if (aniState->mrcCCK != entry_cck->mrc_cck_on)
e36b27af LR	277	ath9k_hw_ani_control(ah,
	278	ATH9K_ANI_MRC_CCK,
	279	entry_cck->mrc_cck_on);
	280	}
	281
8eb4980c	282	static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
e36b27af LR	283	{
	284	struct ar5416AniState *aniState;
	285
e323300d	286	if (!ah->curchan)
e36b27af LR	287	return;
e36b27af LR	288
c24bd362	289	aniState = &ah->ani;
e36b27af LR	290
e36b27af LR	291	if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
73dc3eb8 FF	292	ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1,
73dc3eb8 FF	293	false);
e36b27af LR	294	}
e36b27af LR	295
e36b27af LR	296	/*
	297	* only lower either OFDM or CCK errors per turn
	298	* we lower the other one next time
	299	*/
8eb4980c	300	static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
e36b27af LR	301	{
	302	struct ar5416AniState *aniState;
	303
c24bd362	304	aniState = &ah->ani;
e36b27af LR	305
	306	/* lower OFDM noise immunity */
	307	if (aniState->ofdmNoiseImmunityLevel > 0 &&
	308	(aniState->ofdmsTurn \|\| aniState->cckNoiseImmunityLevel == 0)) {
73dc3eb8 FF	309	ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1,
73dc3eb8 FF	310	false);
e36b27af LR	311	return;
	312	}
	313
	314	/* lower CCK noise immunity */
	315	if (aniState->cckNoiseImmunityLevel > 0)
73dc3eb8 FF	316	ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1,
73dc3eb8 FF	317	false);
e36b27af LR	318	}
e36b27af LR	319
e36b27af LR	320	/*
	321	* Restore the ANI parameters in the HAL and reset the statistics.
	322	* This routine should be called for every hardware reset and for
	323	* every channel change.
	324	*/
8eb4980c	325	void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
e36b27af	326	{
c24bd362	327	struct ar5416AniState *aniState = &ah->ani;
e36b27af LR	328	struct ath9k_channel *chan = ah->curchan;
e36b27af LR	329	struct ath_common *common = ath9k_hw_common(ah);
1e8f0a31	330	int ofdm_nil, cck_nil;
e36b27af	331
e323300d	332	if (!ah->curchan)
e36b27af LR	333	return;
	334
	335	BUG_ON(aniState == NULL);
	336	ah->stats.ast_ani_reset++;
	337
1e8f0a31 FF	338	ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL,
	339	aniState->ofdmNoiseImmunityLevel);
	340	cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL,
	341	aniState->cckNoiseImmunityLevel);
	342
e36b27af LR	343	if (is_scanning \|\|
	344	(ah->opmode != NL80211_IFTYPE_STATION &&
	345	ah->opmode != NL80211_IFTYPE_ADHOC)) {
	346	/*
	347	* If we're scanning or in AP mode, the defaults (ini)
	348	* should be in place. For an AP we assume the historical
	349	* levels for this channel are probably outdated so start
	350	* from defaults instead.
	351	*/
	352	if (aniState->ofdmNoiseImmunityLevel !=
	353	ATH9K_ANI_OFDM_DEF_LEVEL \|\|
	354	aniState->cckNoiseImmunityLevel !=
	355	ATH9K_ANI_CCK_DEF_LEVEL) {
d2182b69	356	ath_dbg(common, ANI,
8896934c	357	"Restore defaults: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n",
226afe68 JP	358	ah->opmode,
226afe68 JP	359	chan->channel,
226afe68 JP	360	is_scanning,
	361	aniState->ofdmNoiseImmunityLevel,
	362	aniState->cckNoiseImmunityLevel);
e36b27af	363
1e8f0a31 FF	364	ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL;
1e8f0a31 FF	365	cck_nil = ATH9K_ANI_CCK_DEF_LEVEL;
e36b27af LR	366	}
	367	} else {
	368	/*
	369	* restore historical levels for this channel
	370	*/
d2182b69	371	ath_dbg(common, ANI,
8896934c	372	"Restore history: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n",
226afe68 JP	373	ah->opmode,
226afe68 JP	374	chan->channel,
226afe68 JP	375	is_scanning,
	376	aniState->ofdmNoiseImmunityLevel,
	377	aniState->cckNoiseImmunityLevel);
e36b27af	378	}
73dc3eb8 FF	379	ath9k_hw_set_ofdm_nil(ah, ofdm_nil, is_scanning);
73dc3eb8 FF	380	ath9k_hw_set_cck_nil(ah, cck_nil, is_scanning);
e36b27af	381
093115b7	382	ath9k_ani_restart(ah);
f1dc5600 S	383	}
f1dc5600 S	384
e49f9137	385	static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
f1dc5600	386	{
c46917bb	387	struct ath_common *common = ath9k_hw_common(ah);
c24bd362	388	struct ar5416AniState *aniState = &ah->ani;
bfc472bb FF	389	u32 phyCnt1, phyCnt2;
bfc472bb FF	390	int32_t listenTime;
f1dc5600	391
b5bfc568 FF	392	ath_hw_cycle_counters_update(common);
	393	listenTime = ath_hw_get_listen_time(common);
	394
e49f9137	395	if (listenTime <= 0) {
107021c4	396	ah->stats.ast_ani_lneg_or_lzero++;
093115b7	397	ath9k_ani_restart(ah);
e49f9137	398	return false;
f1dc5600 S	399	}
	400
	401	aniState->listenTime += listenTime;
	402
1aa8e847	403	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
f1dc5600	404
1aa8e847 S	405	phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
	406	phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
	407
465dce62 FF	408	ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount;
	409	aniState->ofdmPhyErrCount = phyCnt1;
	410
	411	ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount;
	412	aniState->cckPhyErrCount = phyCnt2;
f1dc5600	413
e49f9137	414	return true;
bfc472bb FF	415	}
bfc472bb FF	416
95792178	417	void ath9k_hw_ani_monitor(struct ath_hw ah, struct ath9k_channel chan)
e36b27af LR	418	{
	419	struct ar5416AniState *aniState;
	420	struct ath_common *common = ath9k_hw_common(ah);
e36b27af LR	421	u32 ofdmPhyErrRate, cckPhyErrRate;
e36b27af LR	422
e323300d	423	if (!ah->curchan)
e36b27af LR	424	return;
e36b27af LR	425
c24bd362	426	aniState = &ah->ani;
e49f9137 FF	427	if (!ath9k_hw_ani_read_counters(ah))
e49f9137 FF	428	return;
e36b27af LR	429
	430	ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
	431	aniState->listenTime;
	432	cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
	433	aniState->listenTime;
	434
d2182b69	435	ath_dbg(common, ANI,
226afe68 JP	436	"listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
	437	aniState->listenTime,
	438	aniState->ofdmNoiseImmunityLevel,
	439	ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
	440	cckPhyErrRate, aniState->ofdmsTurn);
e36b27af	441
55fee98a SM	442	if (aniState->listenTime > ah->aniperiod) {
	443	if (cckPhyErrRate < ah->config.cck_trig_low &&
	444	ofdmPhyErrRate < ah->config.ofdm_trig_low) {
e36b27af LR	445	ath9k_hw_ani_lower_immunity(ah);
e36b27af LR	446	aniState->ofdmsTurn = !aniState->ofdmsTurn;
55fee98a	447	} else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) {
8eb4980c	448	ath9k_hw_ani_ofdm_err_trigger(ah);
e36b27af	449	aniState->ofdmsTurn = false;
093115b7	450	} else if (cckPhyErrRate > ah->config.cck_trig_high) {
8eb4980c	451	ath9k_hw_ani_cck_err_trigger(ah);
e36b27af	452	aniState->ofdmsTurn = true;
f1dc5600	453	}
54da20d8	454	ath9k_ani_restart(ah);
f1dc5600 S	455	}
f1dc5600 S	456	}
95792178	457	EXPORT_SYMBOL(ath9k_hw_ani_monitor);
f1dc5600	458
cbe61d8a	459	void ath9k_enable_mib_counters(struct ath_hw *ah)
f1dc5600	460	{
c46917bb LR	461	struct ath_common *common = ath9k_hw_common(ah);
c46917bb LR	462
d2182b69	463	ath_dbg(common, ANI, "Enable MIB counters\n");
f1dc5600	464
cbe61d8a	465	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
f1dc5600	466
7d0d0df0 S	467	ENABLE_REGWRITE_BUFFER(ah);
7d0d0df0 S	468
f1dc5600 S	469	REG_WRITE(ah, AR_FILT_OFDM, 0);
	470	REG_WRITE(ah, AR_FILT_CCK, 0);
	471	REG_WRITE(ah, AR_MIBC,
	472	~(AR_MIBC_COW \| AR_MIBC_FMC \| AR_MIBC_CMC \| AR_MIBC_MCS)
	473	& 0x0f);
	474	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
	475	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
7d0d0df0 S	476
7d0d0df0 S	477	REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 S	478	}
f1dc5600 S	479
0fd06c90	480	/* Freeze the MIB counters, get the stats and then clear them */
cbe61d8a	481	void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
f1dc5600	482	{
c46917bb LR	483	struct ath_common *common = ath9k_hw_common(ah);
c46917bb LR	484
d2182b69	485	ath_dbg(common, ANI, "Disable MIB counters\n");
c46917bb	486
0fd06c90	487	REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
cbe61d8a	488	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
0fd06c90	489	REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
f1dc5600 S	490	REG_WRITE(ah, AR_FILT_OFDM, 0);
	491	REG_WRITE(ah, AR_FILT_CCK, 0);
	492	}
21d5130b	493	EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
f1dc5600	494
f637cfd6	495	void ath9k_hw_ani_init(struct ath_hw *ah)
f1dc5600	496	{
c46917bb	497	struct ath_common *common = ath9k_hw_common(ah);
c24bd362	498	struct ar5416AniState *ani = &ah->ani;
f1dc5600	499
d2182b69	500	ath_dbg(common, ANI, "Initialize ANI\n");
2660b81a	501
f5547245 FF	502	if (AR_SREV_9300_20_OR_LATER(ah)) {
	503	ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
	504	ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
	505	ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH;
	506	ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW;
	507	} else {
	508	ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
	509	ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
	510	ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
	511	ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
	512	}
e36b27af	513
c24bd362 SM	514	ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
	515	ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
	516	ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false;
	517	ani->ofdmsTurn = true;
	518	ani->ofdmWeakSigDetect = true;
	519	ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
	520	ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
e36b27af LR	521
	522	/*
	523	* since we expect some ongoing maintenance on the tables, let's sanity
	524	* check here default level should not modify INI setting.
	525	*/
465dce62 FF	526	ah->aniperiod = ATH9K_ANI_PERIOD;
465dce62 FF	527	ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL;
1aa8e847	528
093115b7 FF	529	ath9k_ani_restart(ah);
093115b7 FF	530	ath9k_enable_mib_counters(ah);
f1dc5600	531	}