Commit | Line | Data |
---|---|---|
f1dc5600 | 1 | /* |
e36b27af | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
f1dc5600 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
bbce80e1 | 17 | #include <linux/kernel.h> |
cfe8cba9 | 18 | #include "hw.h" |
c16fcb49 | 19 | #include "hw-ops.h" |
f1dc5600 | 20 | |
e36b27af LR |
21 | struct ani_ofdm_level_entry { |
22 | int spur_immunity_level; | |
23 | int fir_step_level; | |
24 | int ofdm_weak_signal_on; | |
25 | }; | |
26 | ||
27 | /* values here are relative to the INI */ | |
28 | ||
29 | /* | |
30 | * Legend: | |
31 | * | |
32 | * SI: Spur immunity | |
33 | * FS: FIR Step | |
34 | * WS: OFDM / CCK Weak Signal detection | |
35 | * MRC-CCK: Maximal Ratio Combining for CCK | |
36 | */ | |
37 | ||
38 | static const struct ani_ofdm_level_entry ofdm_level_table[] = { | |
39 | /* SI FS WS */ | |
40 | { 0, 0, 1 }, /* lvl 0 */ | |
41 | { 1, 1, 1 }, /* lvl 1 */ | |
42 | { 2, 2, 1 }, /* lvl 2 */ | |
43 | { 3, 2, 1 }, /* lvl 3 (default) */ | |
44 | { 4, 3, 1 }, /* lvl 4 */ | |
45 | { 5, 4, 1 }, /* lvl 5 */ | |
46 | { 6, 5, 1 }, /* lvl 6 */ | |
47 | { 7, 6, 1 }, /* lvl 7 */ | |
48 | { 7, 7, 1 }, /* lvl 8 */ | |
49 | { 7, 8, 0 } /* lvl 9 */ | |
50 | }; | |
51 | #define ATH9K_ANI_OFDM_NUM_LEVEL \ | |
bbce80e1 | 52 | ARRAY_SIZE(ofdm_level_table) |
e36b27af LR |
53 | #define ATH9K_ANI_OFDM_MAX_LEVEL \ |
54 | (ATH9K_ANI_OFDM_NUM_LEVEL-1) | |
55 | #define ATH9K_ANI_OFDM_DEF_LEVEL \ | |
56 | 3 /* default level - matches the INI settings */ | |
57 | ||
58 | /* | |
59 | * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm. | |
60 | * With OFDM for single stream you just add up all antenna inputs, you're | |
61 | * only interested in what you get after FFT. Signal aligment is also not | |
62 | * required for OFDM because any phase difference adds up in the frequency | |
63 | * domain. | |
64 | * | |
65 | * MRC requires extra work for use with CCK. You need to align the antenna | |
66 | * signals from the different antenna before you can add the signals together. | |
67 | * You need aligment of signals as CCK is in time domain, so addition can cancel | |
68 | * your signal completely if phase is 180 degrees (think of adding sine waves). | |
69 | * You also need to remove noise before the addition and this is where ANI | |
70 | * MRC CCK comes into play. One of the antenna inputs may be stronger but | |
71 | * lower SNR, so just adding after alignment can be dangerous. | |
72 | * | |
73 | * Regardless of alignment in time, the antenna signals add constructively after | |
74 | * FFT and improve your reception. For more information: | |
75 | * | |
76 | * http://en.wikipedia.org/wiki/Maximal-ratio_combining | |
77 | */ | |
78 | ||
79 | struct ani_cck_level_entry { | |
80 | int fir_step_level; | |
81 | int mrc_cck_on; | |
82 | }; | |
83 | ||
84 | static const struct ani_cck_level_entry cck_level_table[] = { | |
85 | /* FS MRC-CCK */ | |
86 | { 0, 1 }, /* lvl 0 */ | |
87 | { 1, 1 }, /* lvl 1 */ | |
88 | { 2, 1 }, /* lvl 2 (default) */ | |
89 | { 3, 1 }, /* lvl 3 */ | |
90 | { 4, 0 }, /* lvl 4 */ | |
91 | { 5, 0 }, /* lvl 5 */ | |
92 | { 6, 0 }, /* lvl 6 */ | |
93 | { 7, 0 }, /* lvl 7 (only for high rssi) */ | |
94 | { 8, 0 } /* lvl 8 (only for high rssi) */ | |
95 | }; | |
96 | ||
97 | #define ATH9K_ANI_CCK_NUM_LEVEL \ | |
bbce80e1 | 98 | ARRAY_SIZE(cck_level_table) |
e36b27af LR |
99 | #define ATH9K_ANI_CCK_MAX_LEVEL \ |
100 | (ATH9K_ANI_CCK_NUM_LEVEL-1) | |
101 | #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \ | |
102 | (ATH9K_ANI_CCK_NUM_LEVEL-3) | |
103 | #define ATH9K_ANI_CCK_DEF_LEVEL \ | |
104 | 2 /* default level - matches the INI settings */ | |
105 | ||
71ea4209 FF |
106 | static bool use_new_ani(struct ath_hw *ah) |
107 | { | |
108 | return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani; | |
109 | } | |
110 | ||
cbe61d8a | 111 | static void ath9k_hw_update_mibstats(struct ath_hw *ah, |
f1dc5600 S |
112 | struct ath9k_mib_stats *stats) |
113 | { | |
114 | stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); | |
115 | stats->rts_bad += REG_READ(ah, AR_RTS_FAIL); | |
116 | stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL); | |
117 | stats->rts_good += REG_READ(ah, AR_RTS_OK); | |
118 | stats->beacons += REG_READ(ah, AR_BEACON_CNT); | |
119 | } | |
120 | ||
093115b7 | 121 | static void ath9k_ani_restart(struct ath_hw *ah) |
f1dc5600 | 122 | { |
f1dc5600 | 123 | struct ar5416AniState *aniState; |
c46917bb | 124 | struct ath_common *common = ath9k_hw_common(ah); |
093115b7 | 125 | u32 ofdm_base = 0, cck_base = 0; |
f1dc5600 S |
126 | |
127 | if (!DO_ANI(ah)) | |
128 | return; | |
129 | ||
093115b7 | 130 | aniState = &ah->curchan->ani; |
f1dc5600 | 131 | aniState->listenTime = 0; |
1aa8e847 | 132 | |
093115b7 FF |
133 | if (!use_new_ani(ah)) { |
134 | ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high; | |
135 | cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; | |
1aa8e847 | 136 | } |
e36b27af | 137 | |
226afe68 JP |
138 | ath_dbg(common, ATH_DBG_ANI, |
139 | "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base); | |
e36b27af LR |
140 | |
141 | ENABLE_REGWRITE_BUFFER(ah); | |
142 | ||
093115b7 FF |
143 | REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); |
144 | REG_WRITE(ah, AR_PHY_ERR_2, cck_base); | |
e36b27af LR |
145 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
146 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | |
147 | ||
148 | REGWRITE_BUFFER_FLUSH(ah); | |
e36b27af LR |
149 | |
150 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); | |
151 | ||
152 | aniState->ofdmPhyErrCount = 0; | |
153 | aniState->cckPhyErrCount = 0; | |
154 | } | |
155 | ||
156 | static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah) | |
f1dc5600 | 157 | { |
b002a4a9 | 158 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
f1dc5600 | 159 | struct ar5416AniState *aniState; |
f1dc5600 S |
160 | int32_t rssi; |
161 | ||
093115b7 | 162 | aniState = &ah->curchan->ani; |
f1dc5600 S |
163 | |
164 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { | |
165 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | |
166 | aniState->noiseImmunityLevel + 1)) { | |
167 | return; | |
168 | } | |
169 | } | |
170 | ||
171 | if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) { | |
172 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, | |
173 | aniState->spurImmunityLevel + 1)) { | |
174 | return; | |
175 | } | |
176 | } | |
177 | ||
2660b81a | 178 | if (ah->opmode == NL80211_IFTYPE_AP) { |
f1dc5600 S |
179 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { |
180 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | |
181 | aniState->firstepLevel + 1); | |
182 | } | |
183 | return; | |
184 | } | |
cbe61d8a | 185 | rssi = BEACON_RSSI(ah); |
f1dc5600 S |
186 | if (rssi > aniState->rssiThrHigh) { |
187 | if (!aniState->ofdmWeakSigDetectOff) { | |
188 | if (ath9k_hw_ani_control(ah, | |
189 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | |
190 | false)) { | |
191 | ath9k_hw_ani_control(ah, | |
192 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); | |
193 | return; | |
194 | } | |
195 | } | |
196 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { | |
197 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | |
198 | aniState->firstepLevel + 1); | |
199 | return; | |
200 | } | |
201 | } else if (rssi > aniState->rssiThrLow) { | |
202 | if (aniState->ofdmWeakSigDetectOff) | |
203 | ath9k_hw_ani_control(ah, | |
204 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | |
205 | true); | |
206 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) | |
207 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | |
208 | aniState->firstepLevel + 1); | |
209 | return; | |
210 | } else { | |
d37b7da3 S |
211 | if ((conf->channel->band == IEEE80211_BAND_2GHZ) && |
212 | !conf_is_ht(conf)) { | |
f1dc5600 S |
213 | if (!aniState->ofdmWeakSigDetectOff) |
214 | ath9k_hw_ani_control(ah, | |
215 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | |
216 | false); | |
217 | if (aniState->firstepLevel > 0) | |
218 | ath9k_hw_ani_control(ah, | |
219 | ATH9K_ANI_FIRSTEP_LEVEL, 0); | |
220 | return; | |
221 | } | |
222 | } | |
223 | } | |
224 | ||
e36b27af | 225 | static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah) |
f1dc5600 | 226 | { |
b002a4a9 | 227 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
f1dc5600 | 228 | struct ar5416AniState *aniState; |
f1dc5600 S |
229 | int32_t rssi; |
230 | ||
093115b7 | 231 | aniState = &ah->curchan->ani; |
f1dc5600 S |
232 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { |
233 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | |
234 | aniState->noiseImmunityLevel + 1)) { | |
235 | return; | |
236 | } | |
237 | } | |
2660b81a | 238 | if (ah->opmode == NL80211_IFTYPE_AP) { |
f1dc5600 S |
239 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { |
240 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | |
241 | aniState->firstepLevel + 1); | |
242 | } | |
243 | return; | |
244 | } | |
cbe61d8a | 245 | rssi = BEACON_RSSI(ah); |
f1dc5600 S |
246 | if (rssi > aniState->rssiThrLow) { |
247 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) | |
248 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | |
249 | aniState->firstepLevel + 1); | |
250 | } else { | |
d37b7da3 S |
251 | if ((conf->channel->band == IEEE80211_BAND_2GHZ) && |
252 | !conf_is_ht(conf)) { | |
f1dc5600 S |
253 | if (aniState->firstepLevel > 0) |
254 | ath9k_hw_ani_control(ah, | |
255 | ATH9K_ANI_FIRSTEP_LEVEL, 0); | |
256 | } | |
257 | } | |
258 | } | |
259 | ||
e36b27af LR |
260 | /* Adjust the OFDM Noise Immunity Level */ |
261 | static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel) | |
262 | { | |
093115b7 | 263 | struct ar5416AniState *aniState = &ah->curchan->ani; |
e36b27af LR |
264 | struct ath_common *common = ath9k_hw_common(ah); |
265 | const struct ani_ofdm_level_entry *entry_ofdm; | |
266 | const struct ani_cck_level_entry *entry_cck; | |
267 | ||
268 | aniState->noiseFloor = BEACON_RSSI(ah); | |
269 | ||
226afe68 JP |
270 | ath_dbg(common, ATH_DBG_ANI, |
271 | "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", | |
272 | aniState->ofdmNoiseImmunityLevel, | |
273 | immunityLevel, aniState->noiseFloor, | |
274 | aniState->rssiThrLow, aniState->rssiThrHigh); | |
e36b27af LR |
275 | |
276 | aniState->ofdmNoiseImmunityLevel = immunityLevel; | |
277 | ||
278 | entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; | |
279 | entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; | |
280 | ||
281 | if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level) | |
282 | ath9k_hw_ani_control(ah, | |
283 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL, | |
284 | entry_ofdm->spur_immunity_level); | |
285 | ||
286 | if (aniState->firstepLevel != entry_ofdm->fir_step_level && | |
287 | entry_ofdm->fir_step_level >= entry_cck->fir_step_level) | |
288 | ath9k_hw_ani_control(ah, | |
289 | ATH9K_ANI_FIRSTEP_LEVEL, | |
290 | entry_ofdm->fir_step_level); | |
291 | ||
292 | if ((ah->opmode != NL80211_IFTYPE_STATION && | |
293 | ah->opmode != NL80211_IFTYPE_ADHOC) || | |
294 | aniState->noiseFloor <= aniState->rssiThrHigh) { | |
295 | if (aniState->ofdmWeakSigDetectOff) | |
296 | /* force on ofdm weak sig detect */ | |
297 | ath9k_hw_ani_control(ah, | |
298 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | |
299 | true); | |
300 | else if (aniState->ofdmWeakSigDetectOff == | |
301 | entry_ofdm->ofdm_weak_signal_on) | |
302 | ath9k_hw_ani_control(ah, | |
303 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | |
304 | entry_ofdm->ofdm_weak_signal_on); | |
305 | } | |
306 | } | |
307 | ||
8eb4980c | 308 | static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) |
e36b27af LR |
309 | { |
310 | struct ar5416AniState *aniState; | |
311 | ||
312 | if (!DO_ANI(ah)) | |
313 | return; | |
314 | ||
8eb4980c FF |
315 | if (!use_new_ani(ah)) { |
316 | ath9k_hw_ani_ofdm_err_trigger_old(ah); | |
317 | return; | |
318 | } | |
319 | ||
093115b7 | 320 | aniState = &ah->curchan->ani; |
e36b27af LR |
321 | |
322 | if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL) | |
323 | ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1); | |
324 | } | |
325 | ||
326 | /* | |
327 | * Set the ANI settings to match an CCK level. | |
328 | */ | |
329 | static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) | |
330 | { | |
093115b7 | 331 | struct ar5416AniState *aniState = &ah->curchan->ani; |
e36b27af LR |
332 | struct ath_common *common = ath9k_hw_common(ah); |
333 | const struct ani_ofdm_level_entry *entry_ofdm; | |
334 | const struct ani_cck_level_entry *entry_cck; | |
335 | ||
336 | aniState->noiseFloor = BEACON_RSSI(ah); | |
226afe68 JP |
337 | ath_dbg(common, ATH_DBG_ANI, |
338 | "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", | |
339 | aniState->cckNoiseImmunityLevel, immunityLevel, | |
340 | aniState->noiseFloor, aniState->rssiThrLow, | |
341 | aniState->rssiThrHigh); | |
e36b27af LR |
342 | |
343 | if ((ah->opmode == NL80211_IFTYPE_STATION || | |
344 | ah->opmode == NL80211_IFTYPE_ADHOC) && | |
345 | aniState->noiseFloor <= aniState->rssiThrLow && | |
346 | immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI) | |
347 | immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI; | |
348 | ||
349 | aniState->cckNoiseImmunityLevel = immunityLevel; | |
350 | ||
351 | entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; | |
352 | entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; | |
353 | ||
354 | if (aniState->firstepLevel != entry_cck->fir_step_level && | |
355 | entry_cck->fir_step_level >= entry_ofdm->fir_step_level) | |
356 | ath9k_hw_ani_control(ah, | |
357 | ATH9K_ANI_FIRSTEP_LEVEL, | |
358 | entry_cck->fir_step_level); | |
359 | ||
360 | /* Skip MRC CCK for pre AR9003 families */ | |
361 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
362 | return; | |
363 | ||
364 | if (aniState->mrcCCKOff == entry_cck->mrc_cck_on) | |
365 | ath9k_hw_ani_control(ah, | |
366 | ATH9K_ANI_MRC_CCK, | |
367 | entry_cck->mrc_cck_on); | |
368 | } | |
369 | ||
8eb4980c | 370 | static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) |
e36b27af LR |
371 | { |
372 | struct ar5416AniState *aniState; | |
373 | ||
374 | if (!DO_ANI(ah)) | |
375 | return; | |
376 | ||
8eb4980c FF |
377 | if (!use_new_ani(ah)) { |
378 | ath9k_hw_ani_cck_err_trigger_old(ah); | |
379 | return; | |
380 | } | |
381 | ||
093115b7 | 382 | aniState = &ah->curchan->ani; |
e36b27af LR |
383 | |
384 | if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL) | |
385 | ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1); | |
386 | } | |
387 | ||
ac0bb767 | 388 | static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah) |
f1dc5600 | 389 | { |
f1dc5600 S |
390 | struct ar5416AniState *aniState; |
391 | int32_t rssi; | |
392 | ||
093115b7 | 393 | aniState = &ah->curchan->ani; |
f1dc5600 | 394 | |
2660b81a | 395 | if (ah->opmode == NL80211_IFTYPE_AP) { |
f1dc5600 S |
396 | if (aniState->firstepLevel > 0) { |
397 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | |
398 | aniState->firstepLevel - 1)) | |
399 | return; | |
400 | } | |
401 | } else { | |
cbe61d8a | 402 | rssi = BEACON_RSSI(ah); |
f1dc5600 S |
403 | if (rssi > aniState->rssiThrHigh) { |
404 | /* XXX: Handle me */ | |
405 | } else if (rssi > aniState->rssiThrLow) { | |
406 | if (aniState->ofdmWeakSigDetectOff) { | |
407 | if (ath9k_hw_ani_control(ah, | |
408 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | |
409 | true) == true) | |
410 | return; | |
411 | } | |
412 | if (aniState->firstepLevel > 0) { | |
413 | if (ath9k_hw_ani_control(ah, | |
414 | ATH9K_ANI_FIRSTEP_LEVEL, | |
415 | aniState->firstepLevel - 1) == true) | |
416 | return; | |
417 | } | |
418 | } else { | |
419 | if (aniState->firstepLevel > 0) { | |
420 | if (ath9k_hw_ani_control(ah, | |
421 | ATH9K_ANI_FIRSTEP_LEVEL, | |
422 | aniState->firstepLevel - 1) == true) | |
423 | return; | |
424 | } | |
425 | } | |
426 | } | |
427 | ||
428 | if (aniState->spurImmunityLevel > 0) { | |
429 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, | |
430 | aniState->spurImmunityLevel - 1)) | |
431 | return; | |
432 | } | |
433 | ||
434 | if (aniState->noiseImmunityLevel > 0) { | |
435 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | |
436 | aniState->noiseImmunityLevel - 1); | |
437 | return; | |
438 | } | |
439 | } | |
440 | ||
e36b27af LR |
441 | /* |
442 | * only lower either OFDM or CCK errors per turn | |
443 | * we lower the other one next time | |
444 | */ | |
8eb4980c | 445 | static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) |
e36b27af LR |
446 | { |
447 | struct ar5416AniState *aniState; | |
448 | ||
093115b7 | 449 | aniState = &ah->curchan->ani; |
e36b27af | 450 | |
8eb4980c FF |
451 | if (!use_new_ani(ah)) { |
452 | ath9k_hw_ani_lower_immunity_old(ah); | |
453 | return; | |
454 | } | |
455 | ||
e36b27af LR |
456 | /* lower OFDM noise immunity */ |
457 | if (aniState->ofdmNoiseImmunityLevel > 0 && | |
458 | (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) { | |
459 | ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1); | |
460 | return; | |
461 | } | |
462 | ||
463 | /* lower CCK noise immunity */ | |
464 | if (aniState->cckNoiseImmunityLevel > 0) | |
465 | ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1); | |
466 | } | |
467 | ||
40346b66 | 468 | static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning) |
f1dc5600 | 469 | { |
f1dc5600 | 470 | struct ar5416AniState *aniState; |
2660b81a | 471 | struct ath9k_channel *chan = ah->curchan; |
c46917bb | 472 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 S |
473 | |
474 | if (!DO_ANI(ah)) | |
475 | return; | |
476 | ||
093115b7 | 477 | aniState = &ah->curchan->ani; |
f1dc5600 | 478 | |
093115b7 | 479 | if (ah->opmode != NL80211_IFTYPE_STATION |
2660b81a | 480 | && ah->opmode != NL80211_IFTYPE_ADHOC) { |
226afe68 JP |
481 | ath_dbg(common, ATH_DBG_ANI, |
482 | "Reset ANI state opmode %u\n", ah->opmode); | |
2660b81a | 483 | ah->stats.ast_ani_reset++; |
f1dc5600 | 484 | |
c66284f2 LR |
485 | if (ah->opmode == NL80211_IFTYPE_AP) { |
486 | /* | |
487 | * ath9k_hw_ani_control() will only process items set on | |
488 | * ah->ani_function | |
489 | */ | |
490 | if (IS_CHAN_2GHZ(chan)) | |
491 | ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | | |
492 | ATH9K_ANI_FIRSTEP_LEVEL); | |
493 | else | |
494 | ah->ani_function = 0; | |
495 | } | |
496 | ||
f1dc5600 S |
497 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); |
498 | ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); | |
499 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0); | |
500 | ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | |
501 | !ATH9K_ANI_USE_OFDM_WEAK_SIG); | |
502 | ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, | |
503 | ATH9K_ANI_CCK_WEAK_SIG_THR); | |
504 | ||
505 | ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | | |
506 | ATH9K_RX_FILTER_PHYERR); | |
507 | ||
093115b7 | 508 | ath9k_ani_restart(ah); |
f1dc5600 S |
509 | return; |
510 | } | |
511 | ||
512 | if (aniState->noiseImmunityLevel != 0) | |
513 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, | |
514 | aniState->noiseImmunityLevel); | |
515 | if (aniState->spurImmunityLevel != 0) | |
516 | ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, | |
517 | aniState->spurImmunityLevel); | |
518 | if (aniState->ofdmWeakSigDetectOff) | |
519 | ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, | |
520 | !aniState->ofdmWeakSigDetectOff); | |
521 | if (aniState->cckWeakSigThreshold) | |
522 | ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, | |
523 | aniState->cckWeakSigThreshold); | |
524 | if (aniState->firstepLevel != 0) | |
525 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, | |
526 | aniState->firstepLevel); | |
f1dc5600 | 527 | |
1aa8e847 S |
528 | ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & |
529 | ~ATH9K_RX_FILTER_PHYERR); | |
093115b7 | 530 | ath9k_ani_restart(ah); |
e36b27af LR |
531 | |
532 | ENABLE_REGWRITE_BUFFER(ah); | |
533 | ||
534 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); | |
535 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | |
536 | ||
537 | REGWRITE_BUFFER_FLUSH(ah); | |
e36b27af LR |
538 | } |
539 | ||
540 | /* | |
541 | * Restore the ANI parameters in the HAL and reset the statistics. | |
542 | * This routine should be called for every hardware reset and for | |
543 | * every channel change. | |
544 | */ | |
8eb4980c | 545 | void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) |
e36b27af | 546 | { |
093115b7 | 547 | struct ar5416AniState *aniState = &ah->curchan->ani; |
e36b27af LR |
548 | struct ath9k_channel *chan = ah->curchan; |
549 | struct ath_common *common = ath9k_hw_common(ah); | |
550 | ||
551 | if (!DO_ANI(ah)) | |
552 | return; | |
553 | ||
8eb4980c FF |
554 | if (!use_new_ani(ah)) |
555 | return ath9k_ani_reset_old(ah, is_scanning); | |
556 | ||
e36b27af LR |
557 | BUG_ON(aniState == NULL); |
558 | ah->stats.ast_ani_reset++; | |
559 | ||
560 | /* only allow a subset of functions in AP mode */ | |
561 | if (ah->opmode == NL80211_IFTYPE_AP) { | |
562 | if (IS_CHAN_2GHZ(chan)) { | |
563 | ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | | |
564 | ATH9K_ANI_FIRSTEP_LEVEL); | |
565 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
566 | ah->ani_function |= ATH9K_ANI_MRC_CCK; | |
567 | } else | |
568 | ah->ani_function = 0; | |
569 | } | |
570 | ||
571 | /* always allow mode (on/off) to be controlled */ | |
572 | ah->ani_function |= ATH9K_ANI_MODE; | |
573 | ||
574 | if (is_scanning || | |
575 | (ah->opmode != NL80211_IFTYPE_STATION && | |
576 | ah->opmode != NL80211_IFTYPE_ADHOC)) { | |
577 | /* | |
578 | * If we're scanning or in AP mode, the defaults (ini) | |
579 | * should be in place. For an AP we assume the historical | |
580 | * levels for this channel are probably outdated so start | |
581 | * from defaults instead. | |
582 | */ | |
583 | if (aniState->ofdmNoiseImmunityLevel != | |
584 | ATH9K_ANI_OFDM_DEF_LEVEL || | |
585 | aniState->cckNoiseImmunityLevel != | |
586 | ATH9K_ANI_CCK_DEF_LEVEL) { | |
226afe68 JP |
587 | ath_dbg(common, ATH_DBG_ANI, |
588 | "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", | |
589 | ah->opmode, | |
590 | chan->channel, | |
591 | chan->channelFlags, | |
592 | is_scanning, | |
593 | aniState->ofdmNoiseImmunityLevel, | |
594 | aniState->cckNoiseImmunityLevel); | |
e36b27af LR |
595 | |
596 | ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); | |
597 | ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL); | |
598 | } | |
599 | } else { | |
600 | /* | |
601 | * restore historical levels for this channel | |
602 | */ | |
226afe68 JP |
603 | ath_dbg(common, ATH_DBG_ANI, |
604 | "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", | |
605 | ah->opmode, | |
606 | chan->channel, | |
607 | chan->channelFlags, | |
608 | is_scanning, | |
609 | aniState->ofdmNoiseImmunityLevel, | |
610 | aniState->cckNoiseImmunityLevel); | |
e36b27af LR |
611 | |
612 | ath9k_hw_set_ofdm_nil(ah, | |
613 | aniState->ofdmNoiseImmunityLevel); | |
614 | ath9k_hw_set_cck_nil(ah, | |
615 | aniState->cckNoiseImmunityLevel); | |
616 | } | |
617 | ||
618 | /* | |
619 | * enable phy counters if hw supports or if not, enable phy | |
620 | * interrupts (so we can count each one) | |
621 | */ | |
093115b7 | 622 | ath9k_ani_restart(ah); |
7d0d0df0 S |
623 | |
624 | ENABLE_REGWRITE_BUFFER(ah); | |
625 | ||
1aa8e847 S |
626 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
627 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | |
7d0d0df0 S |
628 | |
629 | REGWRITE_BUFFER_FLUSH(ah); | |
f1dc5600 S |
630 | } |
631 | ||
e49f9137 | 632 | static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) |
f1dc5600 | 633 | { |
c46917bb | 634 | struct ath_common *common = ath9k_hw_common(ah); |
bfc472bb FF |
635 | struct ar5416AniState *aniState = &ah->curchan->ani; |
636 | u32 ofdm_base = 0; | |
637 | u32 cck_base = 0; | |
1aa8e847 | 638 | u32 ofdmPhyErrCnt, cckPhyErrCnt; |
bfc472bb FF |
639 | u32 phyCnt1, phyCnt2; |
640 | int32_t listenTime; | |
f1dc5600 | 641 | |
b5bfc568 FF |
642 | ath_hw_cycle_counters_update(common); |
643 | listenTime = ath_hw_get_listen_time(common); | |
644 | ||
e49f9137 | 645 | if (listenTime <= 0) { |
2660b81a | 646 | ah->stats.ast_ani_lneg++; |
093115b7 | 647 | ath9k_ani_restart(ah); |
e49f9137 | 648 | return false; |
f1dc5600 S |
649 | } |
650 | ||
bfc472bb FF |
651 | if (!use_new_ani(ah)) { |
652 | ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high; | |
653 | cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; | |
654 | } | |
655 | ||
f1dc5600 S |
656 | aniState->listenTime += listenTime; |
657 | ||
1aa8e847 | 658 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
f1dc5600 | 659 | |
1aa8e847 S |
660 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); |
661 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); | |
662 | ||
431c7482 | 663 | if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { |
093115b7 | 664 | if (phyCnt1 < ofdm_base) { |
226afe68 JP |
665 | ath_dbg(common, ATH_DBG_ANI, |
666 | "phyCnt1 0x%x, resetting counter value to 0x%x\n", | |
667 | phyCnt1, ofdm_base); | |
093115b7 | 668 | REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); |
1aa8e847 S |
669 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, |
670 | AR_PHY_ERR_OFDM_TIMING); | |
671 | } | |
093115b7 | 672 | if (phyCnt2 < cck_base) { |
226afe68 JP |
673 | ath_dbg(common, ATH_DBG_ANI, |
674 | "phyCnt2 0x%x, resetting counter value to 0x%x\n", | |
675 | phyCnt2, cck_base); | |
093115b7 | 676 | REG_WRITE(ah, AR_PHY_ERR_2, cck_base); |
1aa8e847 S |
677 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, |
678 | AR_PHY_ERR_CCK_TIMING); | |
f1dc5600 | 679 | } |
e49f9137 | 680 | return false; |
1aa8e847 | 681 | } |
f1dc5600 | 682 | |
093115b7 | 683 | ofdmPhyErrCnt = phyCnt1 - ofdm_base; |
1aa8e847 S |
684 | ah->stats.ast_ani_ofdmerrs += |
685 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; | |
686 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; | |
f1dc5600 | 687 | |
093115b7 | 688 | cckPhyErrCnt = phyCnt2 - cck_base; |
1aa8e847 S |
689 | ah->stats.ast_ani_cckerrs += |
690 | cckPhyErrCnt - aniState->cckPhyErrCount; | |
691 | aniState->cckPhyErrCount = cckPhyErrCnt; | |
e49f9137 | 692 | return true; |
bfc472bb FF |
693 | } |
694 | ||
95792178 | 695 | void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) |
e36b27af LR |
696 | { |
697 | struct ar5416AniState *aniState; | |
698 | struct ath_common *common = ath9k_hw_common(ah); | |
e36b27af LR |
699 | u32 ofdmPhyErrRate, cckPhyErrRate; |
700 | ||
701 | if (!DO_ANI(ah)) | |
702 | return; | |
703 | ||
093115b7 | 704 | aniState = &ah->curchan->ani; |
e36b27af LR |
705 | if (WARN_ON(!aniState)) |
706 | return; | |
707 | ||
e49f9137 FF |
708 | if (!ath9k_hw_ani_read_counters(ah)) |
709 | return; | |
e36b27af LR |
710 | |
711 | ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 / | |
712 | aniState->listenTime; | |
713 | cckPhyErrRate = aniState->cckPhyErrCount * 1000 / | |
714 | aniState->listenTime; | |
715 | ||
226afe68 JP |
716 | ath_dbg(common, ATH_DBG_ANI, |
717 | "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", | |
718 | aniState->listenTime, | |
719 | aniState->ofdmNoiseImmunityLevel, | |
720 | ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, | |
721 | cckPhyErrRate, aniState->ofdmsTurn); | |
e36b27af LR |
722 | |
723 | if (aniState->listenTime > 5 * ah->aniperiod) { | |
093115b7 FF |
724 | if (ofdmPhyErrRate <= ah->config.ofdm_trig_low && |
725 | cckPhyErrRate <= ah->config.cck_trig_low) { | |
e36b27af LR |
726 | ath9k_hw_ani_lower_immunity(ah); |
727 | aniState->ofdmsTurn = !aniState->ofdmsTurn; | |
728 | } | |
093115b7 | 729 | ath9k_ani_restart(ah); |
e36b27af LR |
730 | } else if (aniState->listenTime > ah->aniperiod) { |
731 | /* check to see if need to raise immunity */ | |
093115b7 FF |
732 | if (ofdmPhyErrRate > ah->config.ofdm_trig_high && |
733 | (cckPhyErrRate <= ah->config.cck_trig_high || | |
e36b27af | 734 | aniState->ofdmsTurn)) { |
8eb4980c | 735 | ath9k_hw_ani_ofdm_err_trigger(ah); |
093115b7 | 736 | ath9k_ani_restart(ah); |
e36b27af | 737 | aniState->ofdmsTurn = false; |
093115b7 | 738 | } else if (cckPhyErrRate > ah->config.cck_trig_high) { |
8eb4980c | 739 | ath9k_hw_ani_cck_err_trigger(ah); |
093115b7 | 740 | ath9k_ani_restart(ah); |
e36b27af | 741 | aniState->ofdmsTurn = true; |
f1dc5600 S |
742 | } |
743 | } | |
744 | } | |
95792178 | 745 | EXPORT_SYMBOL(ath9k_hw_ani_monitor); |
f1dc5600 | 746 | |
cbe61d8a | 747 | void ath9k_enable_mib_counters(struct ath_hw *ah) |
f1dc5600 | 748 | { |
c46917bb LR |
749 | struct ath_common *common = ath9k_hw_common(ah); |
750 | ||
226afe68 | 751 | ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n"); |
f1dc5600 | 752 | |
cbe61d8a | 753 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
f1dc5600 | 754 | |
7d0d0df0 S |
755 | ENABLE_REGWRITE_BUFFER(ah); |
756 | ||
f1dc5600 S |
757 | REG_WRITE(ah, AR_FILT_OFDM, 0); |
758 | REG_WRITE(ah, AR_FILT_CCK, 0); | |
759 | REG_WRITE(ah, AR_MIBC, | |
760 | ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) | |
761 | & 0x0f); | |
762 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); | |
763 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); | |
7d0d0df0 S |
764 | |
765 | REGWRITE_BUFFER_FLUSH(ah); | |
f1dc5600 S |
766 | } |
767 | ||
0fd06c90 | 768 | /* Freeze the MIB counters, get the stats and then clear them */ |
cbe61d8a | 769 | void ath9k_hw_disable_mib_counters(struct ath_hw *ah) |
f1dc5600 | 770 | { |
c46917bb LR |
771 | struct ath_common *common = ath9k_hw_common(ah); |
772 | ||
226afe68 | 773 | ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n"); |
c46917bb | 774 | |
0fd06c90 | 775 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); |
cbe61d8a | 776 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
0fd06c90 | 777 | REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); |
f1dc5600 S |
778 | REG_WRITE(ah, AR_FILT_OFDM, 0); |
779 | REG_WRITE(ah, AR_FILT_CCK, 0); | |
780 | } | |
21d5130b | 781 | EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); |
f1dc5600 | 782 | |
f1dc5600 S |
783 | /* |
784 | * Process a MIB interrupt. We may potentially be invoked because | |
785 | * any of the MIB counters overflow/trigger so don't assume we're | |
786 | * here because a PHY error counter triggered. | |
787 | */ | |
bfc472bb | 788 | void ath9k_hw_proc_mib_event(struct ath_hw *ah) |
f1dc5600 | 789 | { |
f1dc5600 S |
790 | u32 phyCnt1, phyCnt2; |
791 | ||
792 | /* Reset these counters regardless */ | |
793 | REG_WRITE(ah, AR_FILT_OFDM, 0); | |
794 | REG_WRITE(ah, AR_FILT_CCK, 0); | |
795 | if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING)) | |
796 | REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); | |
797 | ||
798 | /* Clear the mib counters and save them in the stats */ | |
cbe61d8a | 799 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
f1dc5600 | 800 | |
6e97f0fb LR |
801 | if (!DO_ANI(ah)) { |
802 | /* | |
803 | * We must always clear the interrupt cause by | |
804 | * resetting the phy error regs. | |
805 | */ | |
806 | REG_WRITE(ah, AR_PHY_ERR_1, 0); | |
807 | REG_WRITE(ah, AR_PHY_ERR_2, 0); | |
f1dc5600 | 808 | return; |
6e97f0fb | 809 | } |
f1dc5600 S |
810 | |
811 | /* NB: these are not reset-on-read */ | |
812 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); | |
813 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); | |
814 | if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || | |
815 | ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { | |
f1dc5600 | 816 | |
bfc472bb FF |
817 | if (!use_new_ani(ah)) |
818 | ath9k_hw_ani_read_counters(ah); | |
f1dc5600 | 819 | |
f1dc5600 | 820 | /* NB: always restart to insure the h/w counters are reset */ |
093115b7 | 821 | ath9k_ani_restart(ah); |
f1dc5600 S |
822 | } |
823 | } | |
bfc472bb | 824 | EXPORT_SYMBOL(ath9k_hw_proc_mib_event); |
e36b27af | 825 | |
cbe61d8a | 826 | void ath9k_hw_ani_setup(struct ath_hw *ah) |
f1dc5600 | 827 | { |
f1dc5600 S |
828 | int i; |
829 | ||
07b2fa5a JP |
830 | static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; |
831 | static const int coarseHigh[] = { -14, -14, -14, -14, -12 }; | |
832 | static const int coarseLow[] = { -64, -64, -64, -64, -70 }; | |
833 | static const int firpwr[] = { -78, -78, -78, -78, -80 }; | |
f1dc5600 S |
834 | |
835 | for (i = 0; i < 5; i++) { | |
2660b81a S |
836 | ah->totalSizeDesired[i] = totalSizeDesired[i]; |
837 | ah->coarse_high[i] = coarseHigh[i]; | |
838 | ah->coarse_low[i] = coarseLow[i]; | |
839 | ah->firpwr[i] = firpwr[i]; | |
f1dc5600 S |
840 | } |
841 | } | |
842 | ||
f637cfd6 | 843 | void ath9k_hw_ani_init(struct ath_hw *ah) |
f1dc5600 | 844 | { |
c46917bb | 845 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 S |
846 | int i; |
847 | ||
226afe68 | 848 | ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n"); |
2660b81a | 849 | |
093115b7 FF |
850 | if (use_new_ani(ah)) { |
851 | ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; | |
852 | ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW; | |
e36b27af | 853 | |
093115b7 FF |
854 | ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW; |
855 | ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW; | |
856 | } else { | |
857 | ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD; | |
858 | ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD; | |
e36b27af | 859 | |
093115b7 FF |
860 | ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD; |
861 | ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD; | |
862 | } | |
e36b27af | 863 | |
093115b7 FF |
864 | for (i = 0; i < ARRAY_SIZE(ah->channels); i++) { |
865 | struct ath9k_channel *chan = &ah->channels[i]; | |
866 | struct ar5416AniState *ani = &chan->ani; | |
867 | ||
868 | if (use_new_ani(ah)) { | |
869 | ani->spurImmunityLevel = | |
870 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; | |
e36b27af | 871 | |
093115b7 | 872 | ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; |
e36b27af LR |
873 | |
874 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
093115b7 | 875 | ani->mrcCCKOff = |
e36b27af LR |
876 | !ATH9K_ANI_ENABLE_MRC_CCK; |
877 | else | |
093115b7 | 878 | ani->mrcCCKOff = true; |
e36b27af | 879 | |
093115b7 | 880 | ani->ofdmsTurn = true; |
e36b27af | 881 | } else { |
093115b7 | 882 | ani->spurImmunityLevel = |
e36b27af | 883 | ATH9K_ANI_SPUR_IMMUNE_LVL_OLD; |
093115b7 | 884 | ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD; |
e36b27af | 885 | |
093115b7 | 886 | ani->cckWeakSigThreshold = |
e36b27af LR |
887 | ATH9K_ANI_CCK_WEAK_SIG_THR; |
888 | } | |
889 | ||
093115b7 FF |
890 | ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; |
891 | ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; | |
892 | ani->ofdmWeakSigDetectOff = | |
f1dc5600 | 893 | !ATH9K_ANI_USE_OFDM_WEAK_SIG; |
093115b7 | 894 | ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; |
e36b27af LR |
895 | } |
896 | ||
897 | /* | |
898 | * since we expect some ongoing maintenance on the tables, let's sanity | |
899 | * check here default level should not modify INI setting. | |
900 | */ | |
71ea4209 | 901 | if (use_new_ani(ah)) { |
e36b27af LR |
902 | const struct ani_ofdm_level_entry *entry_ofdm; |
903 | const struct ani_cck_level_entry *entry_cck; | |
904 | ||
905 | entry_ofdm = &ofdm_level_table[ATH9K_ANI_OFDM_DEF_LEVEL]; | |
906 | entry_cck = &cck_level_table[ATH9K_ANI_CCK_DEF_LEVEL]; | |
907 | ||
908 | ah->aniperiod = ATH9K_ANI_PERIOD_NEW; | |
909 | ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW; | |
910 | } else { | |
911 | ah->aniperiod = ATH9K_ANI_PERIOD_OLD; | |
912 | ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD; | |
f1dc5600 | 913 | } |
1aa8e847 | 914 | |
2660b81a S |
915 | if (ah->config.enable_ani) |
916 | ah->proc_phyerr |= HAL_PROCESS_ANI; | |
093115b7 FF |
917 | |
918 | ath9k_ani_restart(ah); | |
919 | ath9k_enable_mib_counters(ah); | |
f1dc5600 | 920 | } |