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ath9k_hw: rename mrcCCKOff to fix smatch warning
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ani.c
CommitLineData
f1dc5600 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f1dc5600
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
bbce80e1 17#include <linux/kernel.h>
ee40fa06 18#include <linux/export.h>
cfe8cba9 19#include "hw.h"
c16fcb49 20#include "hw-ops.h"
f1dc5600 21
e36b27af
LR		 22struct ani_ofdm_level_entry {
23 int spur_immunity_level;
24 int fir_step_level;
25 int ofdm_weak_signal_on;
26};
27
28/* values here are relative to the INI */
29
30/*
31 * Legend:
32 *
33 * SI: Spur immunity
34 * FS: FIR Step
35 * WS: OFDM / CCK Weak Signal detection
36 * MRC-CCK: Maximal Ratio Combining for CCK
37 */
38
39static const struct ani_ofdm_level_entry ofdm_level_table[] = {
40 /* SI FS WS */
41 { 0, 0, 1 }, /* lvl 0 */
42 { 1, 1, 1 }, /* lvl 1 */
43 { 2, 2, 1 }, /* lvl 2 */
44 { 3, 2, 1 }, /* lvl 3 (default) */
45 { 4, 3, 1 }, /* lvl 4 */
46 { 5, 4, 1 }, /* lvl 5 */
47 { 6, 5, 1 }, /* lvl 6 */
48 { 7, 6, 1 }, /* lvl 7 */
54da20d8
RM		 49 { 7, 6, 0 }, /* lvl 8 */
50 { 7, 7, 0 } /* lvl 9 */
e36b27af
LR		 51};
52#define ATH9K_ANI_OFDM_NUM_LEVEL \
bbce80e1 53 ARRAY_SIZE(ofdm_level_table)
e36b27af
LR		 54#define ATH9K_ANI_OFDM_MAX_LEVEL \
55 (ATH9K_ANI_OFDM_NUM_LEVEL-1)
56#define ATH9K_ANI_OFDM_DEF_LEVEL \
57 3 /* default level - matches the INI settings */
58
59/*
60 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
61 * With OFDM for single stream you just add up all antenna inputs, you're
62 * only interested in what you get after FFT. Signal aligment is also not
63 * required for OFDM because any phase difference adds up in the frequency
64 * domain.
65 *
66 * MRC requires extra work for use with CCK. You need to align the antenna
67 * signals from the different antenna before you can add the signals together.
68 * You need aligment of signals as CCK is in time domain, so addition can cancel
69 * your signal completely if phase is 180 degrees (think of adding sine waves).
70 * You also need to remove noise before the addition and this is where ANI
71 * MRC CCK comes into play. One of the antenna inputs may be stronger but
72 * lower SNR, so just adding after alignment can be dangerous.
73 *
74 * Regardless of alignment in time, the antenna signals add constructively after
75 * FFT and improve your reception. For more information:
76 *
77 * http://en.wikipedia.org/wiki/Maximal-ratio_combining
78 */
79
80struct ani_cck_level_entry {
81 int fir_step_level;
82 int mrc_cck_on;
83};
84
85static const struct ani_cck_level_entry cck_level_table[] = {
86 /* FS MRC-CCK */
87 { 0, 1 }, /* lvl 0 */
88 { 1, 1 }, /* lvl 1 */
89 { 2, 1 }, /* lvl 2 (default) */
90 { 3, 1 }, /* lvl 3 */
91 { 4, 0 }, /* lvl 4 */
92 { 5, 0 }, /* lvl 5 */
93 { 6, 0 }, /* lvl 6 */
54da20d8
RM		 94 { 6, 0 }, /* lvl 7 (only for high rssi) */
95 { 7, 0 } /* lvl 8 (only for high rssi) */
e36b27af
LR		 96};
97
98#define ATH9K_ANI_CCK_NUM_LEVEL \
bbce80e1 99 ARRAY_SIZE(cck_level_table)
e36b27af
LR		 100#define ATH9K_ANI_CCK_MAX_LEVEL \
101 (ATH9K_ANI_CCK_NUM_LEVEL-1)
102#define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
103 (ATH9K_ANI_CCK_NUM_LEVEL-3)
104#define ATH9K_ANI_CCK_DEF_LEVEL \
105 2 /* default level - matches the INI settings */
106
cbe61d8a 107static void ath9k_hw_update_mibstats(struct ath_hw *ah,
f1dc5600
S		 108 struct ath9k_mib_stats *stats)
109{
110 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
111 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
112 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
113 stats->rts_good += REG_READ(ah, AR_RTS_OK);
114 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
115}
116
093115b7 117static void ath9k_ani_restart(struct ath_hw *ah)
f1dc5600 118{
f1dc5600
S		 119 struct ar5416AniState *aniState;
120
121 if (!DO_ANI(ah))
122 return;
123
093115b7 124 aniState = &ah->curchan->ani;
f1dc5600 125 aniState->listenTime = 0;
1aa8e847 126
e36b27af
LR		 127 ENABLE_REGWRITE_BUFFER(ah);
128
465dce62
FF		 129 REG_WRITE(ah, AR_PHY_ERR_1, 0);
130 REG_WRITE(ah, AR_PHY_ERR_2, 0);
e36b27af
LR		 131 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
132 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
133
134 REGWRITE_BUFFER_FLUSH(ah);
e36b27af
LR		 135
136 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
137
138 aniState->ofdmPhyErrCount = 0;
139 aniState->cckPhyErrCount = 0;
140}
141
e36b27af
LR		 142/* Adjust the OFDM Noise Immunity Level */
143static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
144{
093115b7 145 struct ar5416AniState *aniState = &ah->curchan->ani;
e36b27af
LR		 146 struct ath_common *common = ath9k_hw_common(ah);
147 const struct ani_ofdm_level_entry *entry_ofdm;
148 const struct ani_cck_level_entry *entry_cck;
0b81cc39 149 bool weak_sig;
e36b27af 150
d2182b69 151 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
226afe68 152 aniState->ofdmNoiseImmunityLevel,
35e808b7 153 immunityLevel, BEACON_RSSI(ah),
226afe68 154 aniState->rssiThrLow, aniState->rssiThrHigh);
e36b27af 155
f36369af 156 if (aniState->update_ani)
1e8f0a31 157 aniState->ofdmNoiseImmunityLevel = immunityLevel;
e36b27af
LR		 158
159 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
160 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
161
162 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
163 ath9k_hw_ani_control(ah,
164 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
165 entry_ofdm->spur_immunity_level);
166
167 if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
168 entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
169 ath9k_hw_ani_control(ah,
170 ATH9K_ANI_FIRSTEP_LEVEL,
171 entry_ofdm->fir_step_level);
172
0b81cc39
FF		 173 weak_sig = entry_ofdm->ofdm_weak_signal_on;
174 if (ah->opmode == NL80211_IFTYPE_STATION &&
175 BEACON_RSSI(ah) <= aniState->rssiThrHigh)
176 weak_sig = true;
177
7067e701 178 if (aniState->ofdmWeakSigDetect != weak_sig)
e36b27af
LR		 179 ath9k_hw_ani_control(ah,
180 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
181 entry_ofdm->ofdm_weak_signal_on);
058a6385
FF		 182
183 if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) {
184 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
185 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI;
186 } else {
187 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI;
188 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
189 }
e36b27af
LR		 190}
191
8eb4980c 192static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
e36b27af
LR		 193{
194 struct ar5416AniState *aniState;
195
196 if (!DO_ANI(ah))
197 return;
198
093115b7 199 aniState = &ah->curchan->ani;
e36b27af
LR		 200
201 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
202 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
203}
204
205/*
206 * Set the ANI settings to match an CCK level.
207 */
208static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
209{
093115b7 210 struct ar5416AniState *aniState = &ah->curchan->ani;
e36b27af
LR		 211 struct ath_common *common = ath9k_hw_common(ah);
212 const struct ani_ofdm_level_entry *entry_ofdm;
213 const struct ani_cck_level_entry *entry_cck;
214
d2182b69 215 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
226afe68 216 aniState->cckNoiseImmunityLevel, immunityLevel,
35e808b7 217 BEACON_RSSI(ah), aniState->rssiThrLow,
226afe68 218 aniState->rssiThrHigh);
e36b27af 219
5330df7b 220 if (ah->opmode == NL80211_IFTYPE_STATION &&
35e808b7 221 BEACON_RSSI(ah) <= aniState->rssiThrLow &&
e36b27af
LR		 222 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
223 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
224
f36369af 225 if (aniState->update_ani)
1e8f0a31 226 aniState->cckNoiseImmunityLevel = immunityLevel;
e36b27af
LR		 227
228 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
229 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
230
231 if (aniState->firstepLevel != entry_cck->fir_step_level &&
232 entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
233 ath9k_hw_ani_control(ah,
234 ATH9K_ANI_FIRSTEP_LEVEL,
235 entry_cck->fir_step_level);
236
237 /* Skip MRC CCK for pre AR9003 families */
a95f1600 238 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
e36b27af
LR		 239 return;
240
81b67fd6 241 if (aniState->mrcCCK != entry_cck->mrc_cck_on)
e36b27af
LR		 242 ath9k_hw_ani_control(ah,
243 ATH9K_ANI_MRC_CCK,
244 entry_cck->mrc_cck_on);
245}
246
8eb4980c 247static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
e36b27af
LR		 248{
249 struct ar5416AniState *aniState;
250
251 if (!DO_ANI(ah))
252 return;
253
093115b7 254 aniState = &ah->curchan->ani;
e36b27af
LR		 255
256 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
257 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
258}
259
e36b27af
LR		 260/*
261 * only lower either OFDM or CCK errors per turn
262 * we lower the other one next time
263 */
8eb4980c 264static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
e36b27af
LR		 265{
266 struct ar5416AniState *aniState;
267
093115b7 268 aniState = &ah->curchan->ani;
e36b27af
LR		 269
270 /* lower OFDM noise immunity */
271 if (aniState->ofdmNoiseImmunityLevel > 0 &&
272 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
273 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1);
274 return;
275 }
276
277 /* lower CCK noise immunity */
278 if (aniState->cckNoiseImmunityLevel > 0)
279 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
280}
281
e36b27af
LR		 282/*
283 * Restore the ANI parameters in the HAL and reset the statistics.
284 * This routine should be called for every hardware reset and for
285 * every channel change.
286 */
8eb4980c 287void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
e36b27af 288{
093115b7 289 struct ar5416AniState *aniState = &ah->curchan->ani;
e36b27af
LR		 290 struct ath9k_channel *chan = ah->curchan;
291 struct ath_common *common = ath9k_hw_common(ah);
1e8f0a31 292 int ofdm_nil, cck_nil;
e36b27af
LR		 293
294 if (!DO_ANI(ah))
295 return;
296
297 BUG_ON(aniState == NULL);
298 ah->stats.ast_ani_reset++;
299
300 /* only allow a subset of functions in AP mode */
301 if (ah->opmode == NL80211_IFTYPE_AP) {
302 if (IS_CHAN_2GHZ(chan)) {
303 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
304 ATH9K_ANI_FIRSTEP_LEVEL);
305 if (AR_SREV_9300_20_OR_LATER(ah))
306 ah->ani_function |= ATH9K_ANI_MRC_CCK;
307 } else
308 ah->ani_function = 0;
309 }
310
311 /* always allow mode (on/off) to be controlled */
312 ah->ani_function |= ATH9K_ANI_MODE;
313
1e8f0a31
FF		 314 ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL,
315 aniState->ofdmNoiseImmunityLevel);
316 cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL,
317 aniState->cckNoiseImmunityLevel);
318
e36b27af
LR		 319 if (is_scanning ||
320 (ah->opmode != NL80211_IFTYPE_STATION &&
321 ah->opmode != NL80211_IFTYPE_ADHOC)) {
322 /*
323 * If we're scanning or in AP mode, the defaults (ini)
324 * should be in place. For an AP we assume the historical
325 * levels for this channel are probably outdated so start
326 * from defaults instead.
327 */
328 if (aniState->ofdmNoiseImmunityLevel !=
329 ATH9K_ANI_OFDM_DEF_LEVEL ||
330 aniState->cckNoiseImmunityLevel !=
331 ATH9K_ANI_CCK_DEF_LEVEL) {
d2182b69 332 ath_dbg(common, ANI,
226afe68
JP		 333 "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
334 ah->opmode,
335 chan->channel,
336 chan->channelFlags,
337 is_scanning,
338 aniState->ofdmNoiseImmunityLevel,
339 aniState->cckNoiseImmunityLevel);
e36b27af 340
f36369af 341 aniState->update_ani = false;
1e8f0a31
FF		 342 ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL;
343 cck_nil = ATH9K_ANI_CCK_DEF_LEVEL;
e36b27af
LR		 344 }
345 } else {
346 /*
347 * restore historical levels for this channel
348 */
d2182b69 349 ath_dbg(common, ANI,
226afe68
JP		 350 "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
351 ah->opmode,
352 chan->channel,
353 chan->channelFlags,
354 is_scanning,
355 aniState->ofdmNoiseImmunityLevel,
356 aniState->cckNoiseImmunityLevel);
e36b27af 357
f36369af 358 aniState->update_ani = true;
e36b27af 359 }
1e8f0a31
FF		 360 ath9k_hw_set_ofdm_nil(ah, ofdm_nil);
361 ath9k_hw_set_cck_nil(ah, cck_nil);
e36b27af
LR		 362
363 /*
364 * enable phy counters if hw supports or if not, enable phy
365 * interrupts (so we can count each one)
366 */
093115b7 367 ath9k_ani_restart(ah);
7d0d0df0
S		 368
369 ENABLE_REGWRITE_BUFFER(ah);
370
1aa8e847
S		 371 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
372 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
7d0d0df0
S		 373
374 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600
S		 375}
376
e49f9137 377static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
f1dc5600 378{
c46917bb 379 struct ath_common *common = ath9k_hw_common(ah);
bfc472bb 380 struct ar5416AniState *aniState = &ah->curchan->ani;
bfc472bb
FF		 381 u32 phyCnt1, phyCnt2;
382 int32_t listenTime;
f1dc5600 383
b5bfc568
FF		 384 ath_hw_cycle_counters_update(common);
385 listenTime = ath_hw_get_listen_time(common);
386
e49f9137 387 if (listenTime <= 0) {
107021c4 388 ah->stats.ast_ani_lneg_or_lzero++;
093115b7 389 ath9k_ani_restart(ah);
e49f9137 390 return false;
f1dc5600
S		 391 }
392
393 aniState->listenTime += listenTime;
394
1aa8e847 395 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
f1dc5600 396
1aa8e847
S		 397 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
398 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
399
465dce62
FF		 400 ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount;
401 aniState->ofdmPhyErrCount = phyCnt1;
402
403 ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount;
404 aniState->cckPhyErrCount = phyCnt2;
f1dc5600 405
e49f9137 406 return true;
bfc472bb
FF		 407}
408
95792178 409void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
e36b27af
LR		 410{
411 struct ar5416AniState *aniState;
412 struct ath_common *common = ath9k_hw_common(ah);
e36b27af
LR		 413 u32 ofdmPhyErrRate, cckPhyErrRate;
414
415 if (!DO_ANI(ah))
416 return;
417
093115b7 418 aniState = &ah->curchan->ani;
e36b27af
LR		 419 if (WARN_ON(!aniState))
420 return;
421
e49f9137
FF		 422 if (!ath9k_hw_ani_read_counters(ah))
423 return;
e36b27af
LR		 424
425 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
426 aniState->listenTime;
427 cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
428 aniState->listenTime;
429
d2182b69 430 ath_dbg(common, ANI,
226afe68
JP		 431 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
432 aniState->listenTime,
433 aniState->ofdmNoiseImmunityLevel,
434 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
435 cckPhyErrRate, aniState->ofdmsTurn);
e36b27af 436
54da20d8
RM		 437 if (aniState->listenTime > ah->aniperiod) {
438 if (cckPhyErrRate < ah->config.cck_trig_low &&
058a6385 439 ofdmPhyErrRate < ah->config.ofdm_trig_low) {
e36b27af
LR		 440 ath9k_hw_ani_lower_immunity(ah);
441 aniState->ofdmsTurn = !aniState->ofdmsTurn;
058a6385 442 } else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) {
8eb4980c 443 ath9k_hw_ani_ofdm_err_trigger(ah);
e36b27af 444 aniState->ofdmsTurn = false;
093115b7 445 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
8eb4980c 446 ath9k_hw_ani_cck_err_trigger(ah);
e36b27af 447 aniState->ofdmsTurn = true;
f1dc5600 448 }
54da20d8 449 ath9k_ani_restart(ah);
f1dc5600
S		 450 }
451}
95792178 452EXPORT_SYMBOL(ath9k_hw_ani_monitor);
f1dc5600 453
cbe61d8a 454void ath9k_enable_mib_counters(struct ath_hw *ah)
f1dc5600 455{
c46917bb
LR		 456 struct ath_common *common = ath9k_hw_common(ah);
457
d2182b69 458 ath_dbg(common, ANI, "Enable MIB counters\n");
f1dc5600 459
cbe61d8a 460 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
f1dc5600 461
7d0d0df0
S		 462 ENABLE_REGWRITE_BUFFER(ah);
463
f1dc5600
S		 464 REG_WRITE(ah, AR_FILT_OFDM, 0);
465 REG_WRITE(ah, AR_FILT_CCK, 0);
466 REG_WRITE(ah, AR_MIBC,
467 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
468 & 0x0f);
469 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
470 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
7d0d0df0
S		 471
472 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600
S		 473}
474
0fd06c90 475/* Freeze the MIB counters, get the stats and then clear them */
cbe61d8a 476void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
f1dc5600 477{
c46917bb
LR		 478 struct ath_common *common = ath9k_hw_common(ah);
479
d2182b69 480 ath_dbg(common, ANI, "Disable MIB counters\n");
c46917bb 481
0fd06c90 482 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
cbe61d8a 483 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
0fd06c90 484 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
f1dc5600
S		 485 REG_WRITE(ah, AR_FILT_OFDM, 0);
486 REG_WRITE(ah, AR_FILT_CCK, 0);
487}
21d5130b 488EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
f1dc5600 489
cbe61d8a 490void ath9k_hw_ani_setup(struct ath_hw *ah)
f1dc5600 491{
f1dc5600
S		 492 int i;
493
07b2fa5a
JP		 494 static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
495 static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
496 static const int coarseLow[] = { -64, -64, -64, -64, -70 };
497 static const int firpwr[] = { -78, -78, -78, -78, -80 };
f1dc5600
S		 498
499 for (i = 0; i < 5; i++) {
2660b81a
S		 500 ah->totalSizeDesired[i] = totalSizeDesired[i];
501 ah->coarse_high[i] = coarseHigh[i];
502 ah->coarse_low[i] = coarseLow[i];
503 ah->firpwr[i] = firpwr[i];
f1dc5600
S		 504 }
505}
506
f637cfd6 507void ath9k_hw_ani_init(struct ath_hw *ah)
f1dc5600 508{
c46917bb 509 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 510 int i;
511
d2182b69 512 ath_dbg(common, ANI, "Initialize ANI\n");
2660b81a 513
465dce62
FF		 514 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
515 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
e36b27af 516
465dce62
FF		 517 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH;
518 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW;
e36b27af 519
093115b7
FF		 520 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
521 struct ath9k_channel *chan = &ah->channels[i];
522 struct ar5416AniState *ani = &chan->ani;
523
465dce62 524 ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
e36b27af 525
465dce62 526 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
e36b27af 527
81b67fd6 528 ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false;
6790ae7a
FF		 529
530 ani->ofdmsTurn = true;
e36b27af 531
093115b7
FF		 532 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
533 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
7067e701 534 ani->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
093115b7 535 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
f36369af
RM		 536 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
537 ani->update_ani = false;
e36b27af
LR		 538 }
539
540 /*
541 * since we expect some ongoing maintenance on the tables, let's sanity
542 * check here default level should not modify INI setting.
543 */
465dce62
FF		 544 ah->aniperiod = ATH9K_ANI_PERIOD;
545 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL;
1aa8e847 546
2660b81a
S		 547 if (ah->config.enable_ani)
548 ah->proc_phyerr |= HAL_PROCESS_ANI;
093115b7
FF		 549
550 ath9k_ani_restart(ah);
551 ath9k_enable_mib_counters(ah);
f1dc5600 552}
Linux kernel - Deliverables
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