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ath9k_hw: remove code duplication in phy error counter handling
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ani.c
CommitLineData
f1dc5600 1/*
e36b27af 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f1dc5600
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
bbce80e1 17#include <linux/kernel.h>
cfe8cba9 18#include "hw.h"
c16fcb49 19#include "hw-ops.h"
f1dc5600 20
e36b27af
LR		 21struct ani_ofdm_level_entry {
22 int spur_immunity_level;
23 int fir_step_level;
24 int ofdm_weak_signal_on;
25};
26
27/* values here are relative to the INI */
28
29/*
30 * Legend:
31 *
32 * SI: Spur immunity
33 * FS: FIR Step
34 * WS: OFDM / CCK Weak Signal detection
35 * MRC-CCK: Maximal Ratio Combining for CCK
36 */
37
38static const struct ani_ofdm_level_entry ofdm_level_table[] = {
39 /* SI FS WS */
40 { 0, 0, 1 }, /* lvl 0 */
41 { 1, 1, 1 }, /* lvl 1 */
42 { 2, 2, 1 }, /* lvl 2 */
43 { 3, 2, 1 }, /* lvl 3 (default) */
44 { 4, 3, 1 }, /* lvl 4 */
45 { 5, 4, 1 }, /* lvl 5 */
46 { 6, 5, 1 }, /* lvl 6 */
47 { 7, 6, 1 }, /* lvl 7 */
48 { 7, 7, 1 }, /* lvl 8 */
49 { 7, 8, 0 } /* lvl 9 */
50};
51#define ATH9K_ANI_OFDM_NUM_LEVEL \
bbce80e1 52 ARRAY_SIZE(ofdm_level_table)
e36b27af
LR		 53#define ATH9K_ANI_OFDM_MAX_LEVEL \
54 (ATH9K_ANI_OFDM_NUM_LEVEL-1)
55#define ATH9K_ANI_OFDM_DEF_LEVEL \
56 3 /* default level - matches the INI settings */
57
58/*
59 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
60 * With OFDM for single stream you just add up all antenna inputs, you're
61 * only interested in what you get after FFT. Signal aligment is also not
62 * required for OFDM because any phase difference adds up in the frequency
63 * domain.
64 *
65 * MRC requires extra work for use with CCK. You need to align the antenna
66 * signals from the different antenna before you can add the signals together.
67 * You need aligment of signals as CCK is in time domain, so addition can cancel
68 * your signal completely if phase is 180 degrees (think of adding sine waves).
69 * You also need to remove noise before the addition and this is where ANI
70 * MRC CCK comes into play. One of the antenna inputs may be stronger but
71 * lower SNR, so just adding after alignment can be dangerous.
72 *
73 * Regardless of alignment in time, the antenna signals add constructively after
74 * FFT and improve your reception. For more information:
75 *
76 * http://en.wikipedia.org/wiki/Maximal-ratio_combining
77 */
78
79struct ani_cck_level_entry {
80 int fir_step_level;
81 int mrc_cck_on;
82};
83
84static const struct ani_cck_level_entry cck_level_table[] = {
85 /* FS MRC-CCK */
86 { 0, 1 }, /* lvl 0 */
87 { 1, 1 }, /* lvl 1 */
88 { 2, 1 }, /* lvl 2 (default) */
89 { 3, 1 }, /* lvl 3 */
90 { 4, 0 }, /* lvl 4 */
91 { 5, 0 }, /* lvl 5 */
92 { 6, 0 }, /* lvl 6 */
93 { 7, 0 }, /* lvl 7 (only for high rssi) */
94 { 8, 0 } /* lvl 8 (only for high rssi) */
95};
96
97#define ATH9K_ANI_CCK_NUM_LEVEL \
bbce80e1 98 ARRAY_SIZE(cck_level_table)
e36b27af
LR		 99#define ATH9K_ANI_CCK_MAX_LEVEL \
100 (ATH9K_ANI_CCK_NUM_LEVEL-1)
101#define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
102 (ATH9K_ANI_CCK_NUM_LEVEL-3)
103#define ATH9K_ANI_CCK_DEF_LEVEL \
104 2 /* default level - matches the INI settings */
105
ac0bb767 106/* Private to ani.c */
e36b27af 107static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
ac0bb767
LR		 108{
109 ath9k_hw_private_ops(ah)->ani_lower_immunity(ah);
110}
111
71ea4209
FF		 112static bool use_new_ani(struct ath_hw *ah)
113{
114 return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
115}
116
cbe61d8a 117static void ath9k_hw_update_mibstats(struct ath_hw *ah,
f1dc5600
S		 118 struct ath9k_mib_stats *stats)
119{
120 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
121 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
122 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
123 stats->rts_good += REG_READ(ah, AR_RTS_OK);
124 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
125}
126
093115b7 127static void ath9k_ani_restart(struct ath_hw *ah)
f1dc5600 128{
f1dc5600 129 struct ar5416AniState *aniState;
c46917bb 130 struct ath_common *common = ath9k_hw_common(ah);
093115b7 131 u32 ofdm_base = 0, cck_base = 0;
f1dc5600
S		 132
133 if (!DO_ANI(ah))
134 return;
135
093115b7 136 aniState = &ah->curchan->ani;
f1dc5600 137 aniState->listenTime = 0;
1aa8e847 138
093115b7
FF		 139 if (!use_new_ani(ah)) {
140 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
141 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
1aa8e847 142 }
e36b27af
LR		 143
144 ath_print(common, ATH_DBG_ANI,
093115b7 145 "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base);
e36b27af
LR		 146
147 ENABLE_REGWRITE_BUFFER(ah);
148
093115b7
FF		 149 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
150 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
e36b27af
LR		 151 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
152 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
153
154 REGWRITE_BUFFER_FLUSH(ah);
e36b27af
LR		 155
156 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
157
158 aniState->ofdmPhyErrCount = 0;
159 aniState->cckPhyErrCount = 0;
160}
161
162static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
f1dc5600 163{
b002a4a9 164 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600 165 struct ar5416AniState *aniState;
f1dc5600
S		 166 int32_t rssi;
167
168 if (!DO_ANI(ah))
169 return;
170
093115b7 171 aniState = &ah->curchan->ani;
f1dc5600
S		 172
173 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
174 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
175 aniState->noiseImmunityLevel + 1)) {
176 return;
177 }
178 }
179
180 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
181 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
182 aniState->spurImmunityLevel + 1)) {
183 return;
184 }
185 }
186
2660b81a 187 if (ah->opmode == NL80211_IFTYPE_AP) {
f1dc5600
S		 188 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
189 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
190 aniState->firstepLevel + 1);
191 }
192 return;
193 }
cbe61d8a 194 rssi = BEACON_RSSI(ah);
f1dc5600
S		 195 if (rssi > aniState->rssiThrHigh) {
196 if (!aniState->ofdmWeakSigDetectOff) {
197 if (ath9k_hw_ani_control(ah,
198 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
199 false)) {
200 ath9k_hw_ani_control(ah,
201 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
202 return;
203 }
204 }
205 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
206 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
207 aniState->firstepLevel + 1);
208 return;
209 }
210 } else if (rssi > aniState->rssiThrLow) {
211 if (aniState->ofdmWeakSigDetectOff)
212 ath9k_hw_ani_control(ah,
213 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
214 true);
215 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
216 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
217 aniState->firstepLevel + 1);
218 return;
219 } else {
d37b7da3
S		 220 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
221 !conf_is_ht(conf)) {
f1dc5600
S		 222 if (!aniState->ofdmWeakSigDetectOff)
223 ath9k_hw_ani_control(ah,
224 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
225 false);
226 if (aniState->firstepLevel > 0)
227 ath9k_hw_ani_control(ah,
228 ATH9K_ANI_FIRSTEP_LEVEL, 0);
229 return;
230 }
231 }
232}
233
e36b27af 234static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
f1dc5600 235{
b002a4a9 236 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600 237 struct ar5416AniState *aniState;
f1dc5600
S		 238 int32_t rssi;
239
240 if (!DO_ANI(ah))
241 return;
242
093115b7 243 aniState = &ah->curchan->ani;
f1dc5600
S		 244 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
245 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
246 aniState->noiseImmunityLevel + 1)) {
247 return;
248 }
249 }
2660b81a 250 if (ah->opmode == NL80211_IFTYPE_AP) {
f1dc5600
S		 251 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
252 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
253 aniState->firstepLevel + 1);
254 }
255 return;
256 }
cbe61d8a 257 rssi = BEACON_RSSI(ah);
f1dc5600
S		 258 if (rssi > aniState->rssiThrLow) {
259 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
260 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
261 aniState->firstepLevel + 1);
262 } else {
d37b7da3
S		 263 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
264 !conf_is_ht(conf)) {
f1dc5600
S		 265 if (aniState->firstepLevel > 0)
266 ath9k_hw_ani_control(ah,
267 ATH9K_ANI_FIRSTEP_LEVEL, 0);
268 }
269 }
270}
271
e36b27af
LR		 272/* Adjust the OFDM Noise Immunity Level */
273static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
274{
093115b7 275 struct ar5416AniState *aniState = &ah->curchan->ani;
e36b27af
LR		 276 struct ath_common *common = ath9k_hw_common(ah);
277 const struct ani_ofdm_level_entry *entry_ofdm;
278 const struct ani_cck_level_entry *entry_cck;
279
280 aniState->noiseFloor = BEACON_RSSI(ah);
281
282 ath_print(common, ATH_DBG_ANI,
283 "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
284 aniState->ofdmNoiseImmunityLevel,
285 immunityLevel, aniState->noiseFloor,
286 aniState->rssiThrLow, aniState->rssiThrHigh);
287
288 aniState->ofdmNoiseImmunityLevel = immunityLevel;
289
290 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
291 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
292
293 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
294 ath9k_hw_ani_control(ah,
295 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
296 entry_ofdm->spur_immunity_level);
297
298 if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
299 entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
300 ath9k_hw_ani_control(ah,
301 ATH9K_ANI_FIRSTEP_LEVEL,
302 entry_ofdm->fir_step_level);
303
304 if ((ah->opmode != NL80211_IFTYPE_STATION &&
305 ah->opmode != NL80211_IFTYPE_ADHOC) ||
306 aniState->noiseFloor <= aniState->rssiThrHigh) {
307 if (aniState->ofdmWeakSigDetectOff)
308 /* force on ofdm weak sig detect */
309 ath9k_hw_ani_control(ah,
310 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
311 true);
312 else if (aniState->ofdmWeakSigDetectOff ==
313 entry_ofdm->ofdm_weak_signal_on)
314 ath9k_hw_ani_control(ah,
315 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
316 entry_ofdm->ofdm_weak_signal_on);
317 }
318}
319
320static void ath9k_hw_ani_ofdm_err_trigger_new(struct ath_hw *ah)
321{
322 struct ar5416AniState *aniState;
323
324 if (!DO_ANI(ah))
325 return;
326
093115b7 327 aniState = &ah->curchan->ani;
e36b27af
LR		 328
329 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
330 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
331}
332
333/*
334 * Set the ANI settings to match an CCK level.
335 */
336static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
337{
093115b7 338 struct ar5416AniState *aniState = &ah->curchan->ani;
e36b27af
LR		 339 struct ath_common *common = ath9k_hw_common(ah);
340 const struct ani_ofdm_level_entry *entry_ofdm;
341 const struct ani_cck_level_entry *entry_cck;
342
343 aniState->noiseFloor = BEACON_RSSI(ah);
344 ath_print(common, ATH_DBG_ANI,
345 "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
346 aniState->cckNoiseImmunityLevel, immunityLevel,
347 aniState->noiseFloor, aniState->rssiThrLow,
348 aniState->rssiThrHigh);
349
350 if ((ah->opmode == NL80211_IFTYPE_STATION ||
351 ah->opmode == NL80211_IFTYPE_ADHOC) &&
352 aniState->noiseFloor <= aniState->rssiThrLow &&
353 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
354 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
355
356 aniState->cckNoiseImmunityLevel = immunityLevel;
357
358 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
359 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
360
361 if (aniState->firstepLevel != entry_cck->fir_step_level &&
362 entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
363 ath9k_hw_ani_control(ah,
364 ATH9K_ANI_FIRSTEP_LEVEL,
365 entry_cck->fir_step_level);
366
367 /* Skip MRC CCK for pre AR9003 families */
368 if (!AR_SREV_9300_20_OR_LATER(ah))
369 return;
370
371 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
372 ath9k_hw_ani_control(ah,
373 ATH9K_ANI_MRC_CCK,
374 entry_cck->mrc_cck_on);
375}
376
377static void ath9k_hw_ani_cck_err_trigger_new(struct ath_hw *ah)
378{
379 struct ar5416AniState *aniState;
380
381 if (!DO_ANI(ah))
382 return;
383
093115b7 384 aniState = &ah->curchan->ani;
e36b27af
LR		 385
386 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
387 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
388}
389
ac0bb767 390static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
f1dc5600 391{
f1dc5600
S		 392 struct ar5416AniState *aniState;
393 int32_t rssi;
394
093115b7 395 aniState = &ah->curchan->ani;
f1dc5600 396
2660b81a 397 if (ah->opmode == NL80211_IFTYPE_AP) {
f1dc5600
S		 398 if (aniState->firstepLevel > 0) {
399 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
400 aniState->firstepLevel - 1))
401 return;
402 }
403 } else {
cbe61d8a 404 rssi = BEACON_RSSI(ah);
f1dc5600
S		 405 if (rssi > aniState->rssiThrHigh) {
406 /* XXX: Handle me */
407 } else if (rssi > aniState->rssiThrLow) {
408 if (aniState->ofdmWeakSigDetectOff) {
409 if (ath9k_hw_ani_control(ah,
410 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
411 true) == true)
412 return;
413 }
414 if (aniState->firstepLevel > 0) {
415 if (ath9k_hw_ani_control(ah,
416 ATH9K_ANI_FIRSTEP_LEVEL,
417 aniState->firstepLevel - 1) == true)
418 return;
419 }
420 } else {
421 if (aniState->firstepLevel > 0) {
422 if (ath9k_hw_ani_control(ah,
423 ATH9K_ANI_FIRSTEP_LEVEL,
424 aniState->firstepLevel - 1) == true)
425 return;
426 }
427 }
428 }
429
430 if (aniState->spurImmunityLevel > 0) {
431 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
432 aniState->spurImmunityLevel - 1))
433 return;
434 }
435
436 if (aniState->noiseImmunityLevel > 0) {
437 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
438 aniState->noiseImmunityLevel - 1);
439 return;
440 }
441}
442
e36b27af
LR		 443/*
444 * only lower either OFDM or CCK errors per turn
445 * we lower the other one next time
446 */
447static void ath9k_hw_ani_lower_immunity_new(struct ath_hw *ah)
448{
449 struct ar5416AniState *aniState;
450
093115b7 451 aniState = &ah->curchan->ani;
e36b27af
LR		 452
453 /* lower OFDM noise immunity */
454 if (aniState->ofdmNoiseImmunityLevel > 0 &&
455 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
456 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1);
457 return;
458 }
459
460 /* lower CCK noise immunity */
461 if (aniState->cckNoiseImmunityLevel > 0)
462 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
463}
464
37e5bf65
LR		 465static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
466{
467 struct ath9k_channel *chan = ah->curchan;
468 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
469 u8 clockrate; /* in MHz */
470
471 if (!ah->curchan) /* should really check for CCK instead */
472 clockrate = ATH9K_CLOCK_RATE_CCK;
473 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
474 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
475 else if (IS_CHAN_A_FAST_CLOCK(ah, chan))
476 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
477 else
478 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
479
480 if (conf_is_ht40(conf))
481 return clockrate * 2;
482
918df629 483 return clockrate;
37e5bf65
LR		 484}
485
cbe61d8a 486static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
f1dc5600 487{
9dbebc7f
FF		 488 int32_t listen_time;
489 int32_t clock_rate;
37e5bf65 490
9dbebc7f
FF		 491 ath9k_hw_update_cycle_counters(ah);
492 clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;
493 listen_time = ah->listen_time / clock_rate;
494 ah->listen_time = 0;
e36b27af 495
9dbebc7f 496 return listen_time;
f1dc5600
S		 497}
498
40346b66 499static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
f1dc5600 500{
f1dc5600 501 struct ar5416AniState *aniState;
2660b81a 502 struct ath9k_channel *chan = ah->curchan;
c46917bb 503 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 504
505 if (!DO_ANI(ah))
506 return;
507
093115b7 508 aniState = &ah->curchan->ani;
f1dc5600 509
093115b7 510 if (ah->opmode != NL80211_IFTYPE_STATION
2660b81a 511 && ah->opmode != NL80211_IFTYPE_ADHOC) {
c46917bb
LR		 512 ath_print(common, ATH_DBG_ANI,
513 "Reset ANI state opmode %u\n", ah->opmode);
2660b81a 514 ah->stats.ast_ani_reset++;
f1dc5600 515
c66284f2
LR		 516 if (ah->opmode == NL80211_IFTYPE_AP) {
517 /*
518 * ath9k_hw_ani_control() will only process items set on
519 * ah->ani_function
520 */
521 if (IS_CHAN_2GHZ(chan))
522 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
523 ATH9K_ANI_FIRSTEP_LEVEL);
524 else
525 ah->ani_function = 0;
526 }
527
f1dc5600
S		 528 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
529 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
530 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
531 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
532 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
533 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
534 ATH9K_ANI_CCK_WEAK_SIG_THR);
535
536 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
537 ATH9K_RX_FILTER_PHYERR);
538
093115b7 539 ath9k_ani_restart(ah);
f1dc5600
S		 540 return;
541 }
542
543 if (aniState->noiseImmunityLevel != 0)
544 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
545 aniState->noiseImmunityLevel);
546 if (aniState->spurImmunityLevel != 0)
547 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
548 aniState->spurImmunityLevel);
549 if (aniState->ofdmWeakSigDetectOff)
550 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
551 !aniState->ofdmWeakSigDetectOff);
552 if (aniState->cckWeakSigThreshold)
553 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
554 aniState->cckWeakSigThreshold);
555 if (aniState->firstepLevel != 0)
556 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
557 aniState->firstepLevel);
f1dc5600 558
1aa8e847
S		 559 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
560 ~ATH9K_RX_FILTER_PHYERR);
093115b7 561 ath9k_ani_restart(ah);
e36b27af
LR		 562
563 ENABLE_REGWRITE_BUFFER(ah);
564
565 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
566 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
567
568 REGWRITE_BUFFER_FLUSH(ah);
e36b27af
LR		 569}
570
571/*
572 * Restore the ANI parameters in the HAL and reset the statistics.
573 * This routine should be called for every hardware reset and for
574 * every channel change.
575 */
576static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
577{
093115b7 578 struct ar5416AniState *aniState = &ah->curchan->ani;
e36b27af
LR		 579 struct ath9k_channel *chan = ah->curchan;
580 struct ath_common *common = ath9k_hw_common(ah);
581
582 if (!DO_ANI(ah))
583 return;
584
585 BUG_ON(aniState == NULL);
586 ah->stats.ast_ani_reset++;
587
588 /* only allow a subset of functions in AP mode */
589 if (ah->opmode == NL80211_IFTYPE_AP) {
590 if (IS_CHAN_2GHZ(chan)) {
591 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
592 ATH9K_ANI_FIRSTEP_LEVEL);
593 if (AR_SREV_9300_20_OR_LATER(ah))
594 ah->ani_function |= ATH9K_ANI_MRC_CCK;
595 } else
596 ah->ani_function = 0;
597 }
598
599 /* always allow mode (on/off) to be controlled */
600 ah->ani_function |= ATH9K_ANI_MODE;
601
602 if (is_scanning ||
603 (ah->opmode != NL80211_IFTYPE_STATION &&
604 ah->opmode != NL80211_IFTYPE_ADHOC)) {
605 /*
606 * If we're scanning or in AP mode, the defaults (ini)
607 * should be in place. For an AP we assume the historical
608 * levels for this channel are probably outdated so start
609 * from defaults instead.
610 */
611 if (aniState->ofdmNoiseImmunityLevel !=
612 ATH9K_ANI_OFDM_DEF_LEVEL ||
613 aniState->cckNoiseImmunityLevel !=
614 ATH9K_ANI_CCK_DEF_LEVEL) {
615 ath_print(common, ATH_DBG_ANI,
616 "Restore defaults: opmode %u "
617 "chan %d Mhz/0x%x is_scanning=%d "
618 "ofdm:%d cck:%d\n",
619 ah->opmode,
620 chan->channel,
621 chan->channelFlags,
622 is_scanning,
623 aniState->ofdmNoiseImmunityLevel,
624 aniState->cckNoiseImmunityLevel);
625
626 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
627 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
628 }
629 } else {
630 /*
631 * restore historical levels for this channel
632 */
633 ath_print(common, ATH_DBG_ANI,
634 "Restore history: opmode %u "
635 "chan %d Mhz/0x%x is_scanning=%d "
636 "ofdm:%d cck:%d\n",
637 ah->opmode,
638 chan->channel,
639 chan->channelFlags,
640 is_scanning,
641 aniState->ofdmNoiseImmunityLevel,
642 aniState->cckNoiseImmunityLevel);
643
644 ath9k_hw_set_ofdm_nil(ah,
645 aniState->ofdmNoiseImmunityLevel);
646 ath9k_hw_set_cck_nil(ah,
647 aniState->cckNoiseImmunityLevel);
648 }
649
650 /*
651 * enable phy counters if hw supports or if not, enable phy
652 * interrupts (so we can count each one)
653 */
093115b7 654 ath9k_ani_restart(ah);
7d0d0df0
S		 655
656 ENABLE_REGWRITE_BUFFER(ah);
657
1aa8e847
S		 658 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
659 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
7d0d0df0
S		 660
661 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600
S		 662}
663
bfc472bb 664static void ath9k_hw_ani_read_counters(struct ath_hw *ah)
f1dc5600 665{
c46917bb 666 struct ath_common *common = ath9k_hw_common(ah);
bfc472bb
FF		 667 struct ar5416AniState *aniState = &ah->curchan->ani;
668 u32 ofdm_base = 0;
669 u32 cck_base = 0;
1aa8e847 670 u32 ofdmPhyErrCnt, cckPhyErrCnt;
bfc472bb
FF		 671 u32 phyCnt1, phyCnt2;
672 int32_t listenTime;
f1dc5600
S		 673
674 listenTime = ath9k_hw_ani_get_listen_time(ah);
675 if (listenTime < 0) {
2660b81a 676 ah->stats.ast_ani_lneg++;
093115b7 677 ath9k_ani_restart(ah);
f1dc5600
S		 678 return;
679 }
680
bfc472bb
FF		 681 if (!use_new_ani(ah)) {
682 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
683 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
684 }
685
f1dc5600
S		 686 aniState->listenTime += listenTime;
687
1aa8e847 688 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
f1dc5600 689
1aa8e847
S		 690 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
691 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
692
bfc472bb 693 if (use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
093115b7 694 if (phyCnt1 < ofdm_base) {
c46917bb
LR		 695 ath_print(common, ATH_DBG_ANI,
696 "phyCnt1 0x%x, resetting "
697 "counter value to 0x%x\n",
093115b7
FF		 698 phyCnt1, ofdm_base);
699 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
1aa8e847
S		 700 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
701 AR_PHY_ERR_OFDM_TIMING);
702 }
093115b7 703 if (phyCnt2 < cck_base) {
c46917bb
LR		 704 ath_print(common, ATH_DBG_ANI,
705 "phyCnt2 0x%x, resetting "
706 "counter value to 0x%x\n",
093115b7
FF		 707 phyCnt2, cck_base);
708 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
1aa8e847
S		 709 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
710 AR_PHY_ERR_CCK_TIMING);
f1dc5600 711 }
1aa8e847
S		 712 return;
713 }
f1dc5600 714
093115b7 715 ofdmPhyErrCnt = phyCnt1 - ofdm_base;
1aa8e847
S		 716 ah->stats.ast_ani_ofdmerrs +=
717 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
718 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
f1dc5600 719
093115b7 720 cckPhyErrCnt = phyCnt2 - cck_base;
1aa8e847
S		 721 ah->stats.ast_ani_cckerrs +=
722 cckPhyErrCnt - aniState->cckPhyErrCount;
723 aniState->cckPhyErrCount = cckPhyErrCnt;
f1dc5600 724
bfc472bb
FF		 725}
726
727static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
728 struct ath9k_channel *chan)
729{
730 struct ar5416AniState *aniState;
731
732 if (!DO_ANI(ah))
733 return;
734
735 aniState = &ah->curchan->ani;
736 ath9k_hw_ani_read_counters(ah);
737
2660b81a 738 if (aniState->listenTime > 5 * ah->aniperiod) {
f1dc5600 739 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
093115b7 740 ah->config.ofdm_trig_low / 1000 &&
f1dc5600 741 aniState->cckPhyErrCount <= aniState->listenTime *
093115b7 742 ah->config.cck_trig_low / 1000)
f1dc5600 743 ath9k_hw_ani_lower_immunity(ah);
093115b7 744 ath9k_ani_restart(ah);
2660b81a 745 } else if (aniState->listenTime > ah->aniperiod) {
f1dc5600 746 if (aniState->ofdmPhyErrCount > aniState->listenTime *
093115b7 747 ah->config.ofdm_trig_high / 1000) {
e36b27af 748 ath9k_hw_ani_ofdm_err_trigger_old(ah);
093115b7 749 ath9k_ani_restart(ah);
f1dc5600 750 } else if (aniState->cckPhyErrCount >
093115b7 751 aniState->listenTime * ah->config.cck_trig_high /
f1dc5600 752 1000) {
e36b27af 753 ath9k_hw_ani_cck_err_trigger_old(ah);
093115b7 754 ath9k_ani_restart(ah);
e36b27af
LR		 755 }
756 }
757}
758
759static void ath9k_hw_ani_monitor_new(struct ath_hw *ah,
760 struct ath9k_channel *chan)
761{
762 struct ar5416AniState *aniState;
763 struct ath_common *common = ath9k_hw_common(ah);
e36b27af
LR		 764 u32 ofdmPhyErrRate, cckPhyErrRate;
765
766 if (!DO_ANI(ah))
767 return;
768
093115b7 769 aniState = &ah->curchan->ani;
e36b27af
LR		 770 if (WARN_ON(!aniState))
771 return;
772
bfc472bb 773 ath9k_hw_ani_read_counters(ah);
e36b27af
LR		 774
775 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
776 aniState->listenTime;
777 cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
778 aniState->listenTime;
779
780 ath_print(common, ATH_DBG_ANI,
781 "listenTime=%d OFDM:%d errs=%d/s CCK:%d "
782 "errs=%d/s ofdm_turn=%d\n",
bfc472bb
FF		 783 aniState->listenTime,
784 aniState->ofdmNoiseImmunityLevel,
e36b27af
LR		 785 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
786 cckPhyErrRate, aniState->ofdmsTurn);
787
788 if (aniState->listenTime > 5 * ah->aniperiod) {
093115b7
FF		 789 if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
790 cckPhyErrRate <= ah->config.cck_trig_low) {
e36b27af
LR		 791 ath_print(common, ATH_DBG_ANI,
792 "1. listenTime=%d OFDM:%d errs=%d/s(<%d) "
793 "CCK:%d errs=%d/s(<%d) -> "
794 "ath9k_hw_ani_lower_immunity()\n",
795 aniState->listenTime,
796 aniState->ofdmNoiseImmunityLevel,
797 ofdmPhyErrRate,
093115b7 798 ah->config.ofdm_trig_low,
e36b27af
LR		 799 aniState->cckNoiseImmunityLevel,
800 cckPhyErrRate,
093115b7 801 ah->config.cck_trig_low);
e36b27af
LR		 802 ath9k_hw_ani_lower_immunity(ah);
803 aniState->ofdmsTurn = !aniState->ofdmsTurn;
804 }
805 ath_print(common, ATH_DBG_ANI,
806 "1 listenTime=%d ofdm=%d/s cck=%d/s - "
093115b7 807 "calling ath9k_ani_restart()\n",
e36b27af 808 aniState->listenTime, ofdmPhyErrRate, cckPhyErrRate);
093115b7 809 ath9k_ani_restart(ah);
e36b27af
LR		 810 } else if (aniState->listenTime > ah->aniperiod) {
811 /* check to see if need to raise immunity */
093115b7
FF		 812 if (ofdmPhyErrRate > ah->config.ofdm_trig_high &&
813 (cckPhyErrRate <= ah->config.cck_trig_high ||
e36b27af
LR		 814 aniState->ofdmsTurn)) {
815 ath_print(common, ATH_DBG_ANI,
816 "2 listenTime=%d OFDM:%d errs=%d/s(>%d) -> "
817 "ath9k_hw_ani_ofdm_err_trigger_new()\n",
818 aniState->listenTime,
819 aniState->ofdmNoiseImmunityLevel,
820 ofdmPhyErrRate,
093115b7 821 ah->config.ofdm_trig_high);
e36b27af 822 ath9k_hw_ani_ofdm_err_trigger_new(ah);
093115b7 823 ath9k_ani_restart(ah);
e36b27af 824 aniState->ofdmsTurn = false;
093115b7 825 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
e36b27af
LR		 826 ath_print(common, ATH_DBG_ANI,
827 "3 listenTime=%d CCK:%d errs=%d/s(>%d) -> "
828 "ath9k_hw_ani_cck_err_trigger_new()\n",
829 aniState->listenTime,
830 aniState->cckNoiseImmunityLevel,
831 cckPhyErrRate,
093115b7 832 ah->config.cck_trig_high);
e36b27af 833 ath9k_hw_ani_cck_err_trigger_new(ah);
093115b7 834 ath9k_ani_restart(ah);
e36b27af 835 aniState->ofdmsTurn = true;
f1dc5600
S		 836 }
837 }
838}
839
cbe61d8a 840void ath9k_enable_mib_counters(struct ath_hw *ah)
f1dc5600 841{
c46917bb
LR		 842 struct ath_common *common = ath9k_hw_common(ah);
843
844 ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
f1dc5600 845
cbe61d8a 846 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
f1dc5600 847
7d0d0df0
S		 848 ENABLE_REGWRITE_BUFFER(ah);
849
f1dc5600
S		 850 REG_WRITE(ah, AR_FILT_OFDM, 0);
851 REG_WRITE(ah, AR_FILT_CCK, 0);
852 REG_WRITE(ah, AR_MIBC,
853 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
854 & 0x0f);
855 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
856 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
7d0d0df0
S		 857
858 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600
S		 859}
860
0fd06c90 861/* Freeze the MIB counters, get the stats and then clear them */
cbe61d8a 862void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
f1dc5600 863{
c46917bb
LR		 864 struct ath_common *common = ath9k_hw_common(ah);
865
866 ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
867
0fd06c90 868 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
cbe61d8a 869 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
0fd06c90 870 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
f1dc5600
S		 871 REG_WRITE(ah, AR_FILT_OFDM, 0);
872 REG_WRITE(ah, AR_FILT_CCK, 0);
873}
21d5130b 874EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
f1dc5600 875
9dbebc7f 876void ath9k_hw_update_cycle_counters(struct ath_hw *ah)
f1dc5600 877{
9dbebc7f
FF		 878 struct ath_cycle_counters cc;
879 bool clear;
f1dc5600 880
9dbebc7f 881 memcpy(&cc, &ah->cc, sizeof(cc));
f1dc5600 882
9dbebc7f
FF		 883 /* freeze counters */
884 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
885
886 ah->cc.cycles = REG_READ(ah, AR_CCCNT);
887 if (ah->cc.cycles < cc.cycles) {
888 clear = true;
889 goto skip;
f1dc5600
S		 890 }
891
9dbebc7f
FF		 892 ah->cc.rx_clear = REG_READ(ah, AR_RCCNT);
893 ah->cc.rx_frame = REG_READ(ah, AR_RFCNT);
894 ah->cc.tx_frame = REG_READ(ah, AR_TFCNT);
895
896 /* prevent wraparound */
897 if (ah->cc.cycles & BIT(31))
898 clear = true;
899
900#define CC_DELTA(_field, _reg) ah->cc_delta._field += ah->cc._field - cc._field
901 CC_DELTA(cycles, AR_CCCNT);
902 CC_DELTA(rx_frame, AR_RFCNT);
903 CC_DELTA(rx_clear, AR_RCCNT);
904 CC_DELTA(tx_frame, AR_TFCNT);
905#undef CC_DELTA
906
907 ah->listen_time += (ah->cc.cycles - cc.cycles) -
908 ((ah->cc.rx_frame - cc.rx_frame) +
909 (ah->cc.tx_frame - cc.tx_frame));
910
911skip:
912 if (clear) {
913 REG_WRITE(ah, AR_CCCNT, 0);
914 REG_WRITE(ah, AR_RFCNT, 0);
915 REG_WRITE(ah, AR_RCCNT, 0);
916 REG_WRITE(ah, AR_TFCNT, 0);
917 memset(&ah->cc, 0, sizeof(ah->cc));
918 }
f1dc5600 919
9dbebc7f
FF		 920 /* unfreeze counters */
921 REG_WRITE(ah, AR_MIBC, 0);
f1dc5600
S		 922}
923
924/*
925 * Process a MIB interrupt. We may potentially be invoked because
926 * any of the MIB counters overflow/trigger so don't assume we're
927 * here because a PHY error counter triggered.
928 */
bfc472bb 929void ath9k_hw_proc_mib_event(struct ath_hw *ah)
f1dc5600 930{
f1dc5600
S		 931 u32 phyCnt1, phyCnt2;
932
933 /* Reset these counters regardless */
934 REG_WRITE(ah, AR_FILT_OFDM, 0);
935 REG_WRITE(ah, AR_FILT_CCK, 0);
936 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
937 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
938
939 /* Clear the mib counters and save them in the stats */
cbe61d8a 940 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
f1dc5600 941
6e97f0fb
LR		 942 if (!DO_ANI(ah)) {
943 /*
944 * We must always clear the interrupt cause by
945 * resetting the phy error regs.
946 */
947 REG_WRITE(ah, AR_PHY_ERR_1, 0);
948 REG_WRITE(ah, AR_PHY_ERR_2, 0);
f1dc5600 949 return;
6e97f0fb 950 }
f1dc5600
S		 951
952 /* NB: these are not reset-on-read */
953 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
954 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
955 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
956 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
f1dc5600 957
bfc472bb
FF		 958 if (!use_new_ani(ah))
959 ath9k_hw_ani_read_counters(ah);
f1dc5600 960
f1dc5600 961 /* NB: always restart to insure the h/w counters are reset */
093115b7 962 ath9k_ani_restart(ah);
f1dc5600
S		 963 }
964}
bfc472bb 965EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
e36b27af 966
cbe61d8a 967void ath9k_hw_ani_setup(struct ath_hw *ah)
f1dc5600 968{
f1dc5600
S		 969 int i;
970
971 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
972 const int coarseHigh[] = { -14, -14, -14, -14, -12 };
973 const int coarseLow[] = { -64, -64, -64, -64, -70 };
974 const int firpwr[] = { -78, -78, -78, -78, -80 };
975
976 for (i = 0; i < 5; i++) {
2660b81a
S		 977 ah->totalSizeDesired[i] = totalSizeDesired[i];
978 ah->coarse_high[i] = coarseHigh[i];
979 ah->coarse_low[i] = coarseLow[i];
980 ah->firpwr[i] = firpwr[i];
f1dc5600
S		 981 }
982}
983
f637cfd6 984void ath9k_hw_ani_init(struct ath_hw *ah)
f1dc5600 985{
c46917bb 986 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 987 int i;
988
c46917bb 989 ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
2660b81a 990
093115b7
FF		 991 if (use_new_ani(ah)) {
992 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
993 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
e36b27af 994
093115b7
FF		 995 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
996 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW;
997 } else {
998 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
999 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
e36b27af 1000
093115b7
FF		 1001 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
1002 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
1003 }
e36b27af 1004
093115b7
FF		 1005 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
1006 struct ath9k_channel *chan = &ah->channels[i];
1007 struct ar5416AniState *ani = &chan->ani;
1008
1009 if (use_new_ani(ah)) {
1010 ani->spurImmunityLevel =
1011 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
e36b27af 1012
093115b7 1013 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
e36b27af
LR		 1014
1015 if (AR_SREV_9300_20_OR_LATER(ah))
093115b7 1016 ani->mrcCCKOff =
e36b27af
LR		 1017 !ATH9K_ANI_ENABLE_MRC_CCK;
1018 else
093115b7 1019 ani->mrcCCKOff = true;
e36b27af 1020
093115b7 1021 ani->ofdmsTurn = true;
e36b27af 1022 } else {
093115b7 1023 ani->spurImmunityLevel =
e36b27af 1024 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
093115b7 1025 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
e36b27af 1026
093115b7 1027 ani->cckWeakSigThreshold =
e36b27af
LR		 1028 ATH9K_ANI_CCK_WEAK_SIG_THR;
1029 }
1030
093115b7
FF		 1031 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
1032 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
1033 ani->ofdmWeakSigDetectOff =
f1dc5600 1034 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
093115b7 1035 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
e36b27af
LR		 1036 }
1037
1038 /*
1039 * since we expect some ongoing maintenance on the tables, let's sanity
1040 * check here default level should not modify INI setting.
1041 */
71ea4209 1042 if (use_new_ani(ah)) {
e36b27af
LR		 1043 const struct ani_ofdm_level_entry *entry_ofdm;
1044 const struct ani_cck_level_entry *entry_cck;
1045
1046 entry_ofdm = &ofdm_level_table[ATH9K_ANI_OFDM_DEF_LEVEL];
1047 entry_cck = &cck_level_table[ATH9K_ANI_CCK_DEF_LEVEL];
1048
1049 ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
1050 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
1051 } else {
1052 ah->aniperiod = ATH9K_ANI_PERIOD_OLD;
1053 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
f1dc5600 1054 }
1aa8e847 1055
2660b81a
S		 1056 if (ah->config.enable_ani)
1057 ah->proc_phyerr |= HAL_PROCESS_ANI;
093115b7
FF		 1058
1059 ath9k_ani_restart(ah);
1060 ath9k_enable_mib_counters(ah);
f1dc5600 1061}
ac0bb767
LR		 1062
1063void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah)
1064{
1065 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1066 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1067
1068 priv_ops->ani_reset = ath9k_ani_reset_old;
1069 priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_old;
1070
ac0bb767 1071 ops->ani_monitor = ath9k_hw_ani_monitor_old;
e36b27af
LR		 1072
1073 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v1\n");
1074}
1075
1076void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah)
1077{
1078 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1079 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1080
1081 priv_ops->ani_reset = ath9k_ani_reset_new;
1082 priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_new;
1083
e36b27af
LR		 1084 ops->ani_monitor = ath9k_hw_ani_monitor_new;
1085
1086 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v2\n");
ac0bb767 1087}
Linux kernel - Deliverables
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