[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ani.h

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef ANI_H
#define ANI_H

#define HAL_PROCESS_ANI           0x00000001

#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI) && ah->curchan)

#define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)

/* units are errors per second */
#define ATH9K_ANI_OFDM_TRIG_HIGH_OLD      500
#define ATH9K_ANI_OFDM_TRIG_HIGH_NEW      3500
#define ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI 1000

/* units are errors per second */
#define ATH9K_ANI_OFDM_TRIG_LOW_OLD       200
#define ATH9K_ANI_OFDM_TRIG_LOW_NEW       400
#define ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI 900

/* units are errors per second */
#define ATH9K_ANI_CCK_TRIG_HIGH_OLD       200
#define ATH9K_ANI_CCK_TRIG_HIGH_NEW       600

/* units are errors per second */
#define ATH9K_ANI_CCK_TRIG_LOW_OLD        100
#define ATH9K_ANI_CCK_TRIG_LOW_NEW        300

#define ATH9K_ANI_NOISE_IMMUNE_LVL        4
#define ATH9K_ANI_USE_OFDM_WEAK_SIG       true
#define ATH9K_ANI_CCK_WEAK_SIG_THR        false

#define ATH9K_ANI_SPUR_IMMUNE_LVL_OLD     7
#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW     3

#define ATH9K_ANI_FIRSTEP_LVL_OLD         0
#define ATH9K_ANI_FIRSTEP_LVL_NEW         2

#define ATH9K_ANI_RSSI_THR_HIGH           40
#define ATH9K_ANI_RSSI_THR_LOW            7

#define ATH9K_ANI_PERIOD_OLD              100
#define ATH9K_ANI_PERIOD_NEW              300

/* in ms */
#define ATH9K_ANI_POLLINTERVAL_OLD        100
#define ATH9K_ANI_POLLINTERVAL_NEW        1000

#define HAL_NOISE_IMMUNE_MAX              4
#define HAL_SPUR_IMMUNE_MAX               7
#define HAL_FIRST_STEP_MAX                2

#define ATH9K_SIG_FIRSTEP_SETTING_MIN     0
#define ATH9K_SIG_FIRSTEP_SETTING_MAX     20
#define ATH9K_SIG_SPUR_IMM_SETTING_MIN    0
#define ATH9K_SIG_SPUR_IMM_SETTING_MAX    22

#define ATH9K_ANI_ENABLE_MRC_CCK          true

/* values here are relative to the INI */

enum ath9k_ani_cmd {
	ATH9K_ANI_PRESENT = 0x1,
	ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
	ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
	ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
	ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
	ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
	ATH9K_ANI_MODE = 0x40,
	ATH9K_ANI_PHYERR_RESET = 0x80,
	ATH9K_ANI_MRC_CCK = 0x100,
	ATH9K_ANI_ALL = 0xfff
};

struct ath9k_mib_stats {
	u32 ackrcv_bad;
	u32 rts_bad;
	u32 rts_good;
	u32 fcs_bad;
	u32 beacons;
};

/* INI default values for ANI registers */
struct ath9k_ani_default {
	u16 m1ThreshLow;
	u16 m2ThreshLow;
	u16 m1Thresh;
	u16 m2Thresh;
	u16 m2CountThr;
	u16 m2CountThrLow;
	u16 m1ThreshLowExt;
	u16 m2ThreshLowExt;
	u16 m1ThreshExt;
	u16 m2ThreshExt;
	u16 firstep;
	u16 firstepLow;
	u16 cycpwrThr1;
	u16 cycpwrThr1Ext;
};

struct ar5416AniState {
	struct ath9k_channel *c;
	u8 noiseImmunityLevel;
	u8 ofdmNoiseImmunityLevel;
	u8 cckNoiseImmunityLevel;
	bool ofdmsTurn;
	u8 mrcCCKOff;
	u8 spurImmunityLevel;
	u8 firstepLevel;
	u8 ofdmWeakSigDetectOff;
	u8 cckWeakSigThreshold;
	bool update_ani;
	u32 listenTime;
	int32_t rssiThrLow;
	int32_t rssiThrHigh;
	u32 ofdmPhyErrCount;
	u32 cckPhyErrCount;
	int16_t pktRssi[2];
	int16_t ofdmErrRssi[2];
	int16_t cckErrRssi[2];
	struct ath9k_ani_default iniDef;
};

struct ar5416Stats {
	u32 ast_ani_niup;
	u32 ast_ani_nidown;
	u32 ast_ani_spurup;
	u32 ast_ani_spurdown;
	u32 ast_ani_ofdmon;
	u32 ast_ani_ofdmoff;
	u32 ast_ani_cckhigh;
	u32 ast_ani_ccklow;
	u32 ast_ani_stepup;
	u32 ast_ani_stepdown;
	u32 ast_ani_ofdmerrs;
	u32 ast_ani_cckerrs;
	u32 ast_ani_reset;
	u32 ast_ani_lneg_or_lzero;
	u32 avgbrssi;
	struct ath9k_mib_stats ast_mibstats;
};
#define ah_mibStats stats.ast_mibstats

void ath9k_enable_mib_counters(struct ath_hw *ah);
void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
void ath9k_hw_ani_setup(struct ath_hw *ah);
void ath9k_hw_ani_init(struct ath_hw *ah);

#endif /* ANI_H */
Commit	Line	Data
394cf0a1	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
394cf0a1 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef ANI_H
	18	#define ANI_H
	19
	20	#define HAL_PROCESS_ANI 0x00000001
394cf0a1	21
093115b7	22	#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI) && ah->curchan)
394cf0a1	23
22e66a4c	24	#define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)
394cf0a1	25
e36b27af LR	26	/* units are errors per second */
e36b27af LR	27	#define ATH9K_ANI_OFDM_TRIG_HIGH_OLD 500
54da20d8 RM	28	#define ATH9K_ANI_OFDM_TRIG_HIGH_NEW 3500
54da20d8 RM	29	#define ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI 1000
e36b27af LR	30
	31	/* units are errors per second */
	32	#define ATH9K_ANI_OFDM_TRIG_LOW_OLD 200
	33	#define ATH9K_ANI_OFDM_TRIG_LOW_NEW 400
54da20d8	34	#define ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI 900
e36b27af LR	35
	36	/* units are errors per second */
	37	#define ATH9K_ANI_CCK_TRIG_HIGH_OLD 200
	38	#define ATH9K_ANI_CCK_TRIG_HIGH_NEW 600
	39
	40	/* units are errors per second */
	41	#define ATH9K_ANI_CCK_TRIG_LOW_OLD 100
	42	#define ATH9K_ANI_CCK_TRIG_LOW_NEW 300
	43
394cf0a1 S	44	#define ATH9K_ANI_NOISE_IMMUNE_LVL 4
	45	#define ATH9K_ANI_USE_OFDM_WEAK_SIG true
	46	#define ATH9K_ANI_CCK_WEAK_SIG_THR false
e36b27af LR	47
	48	#define ATH9K_ANI_SPUR_IMMUNE_LVL_OLD 7
	49	#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW 3
	50
	51	#define ATH9K_ANI_FIRSTEP_LVL_OLD 0
	52	#define ATH9K_ANI_FIRSTEP_LVL_NEW 2
	53
394cf0a1 S	54	#define ATH9K_ANI_RSSI_THR_HIGH 40
394cf0a1 S	55	#define ATH9K_ANI_RSSI_THR_LOW 7
e36b27af LR	56
e36b27af LR	57	#define ATH9K_ANI_PERIOD_OLD 100
54da20d8	58	#define ATH9K_ANI_PERIOD_NEW 300
e36b27af LR	59
	60	/* in ms */
	61	#define ATH9K_ANI_POLLINTERVAL_OLD 100
	62	#define ATH9K_ANI_POLLINTERVAL_NEW 1000
394cf0a1 S	63
	64	#define HAL_NOISE_IMMUNE_MAX 4
	65	#define HAL_SPUR_IMMUNE_MAX 7
	66	#define HAL_FIRST_STEP_MAX 2
	67
e36b27af LR	68	#define ATH9K_SIG_FIRSTEP_SETTING_MIN 0
	69	#define ATH9K_SIG_FIRSTEP_SETTING_MAX 20
	70	#define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0
	71	#define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22
	72
	73	#define ATH9K_ANI_ENABLE_MRC_CCK true
	74
	75	/* values here are relative to the INI */
	76
394cf0a1 S	77	enum ath9k_ani_cmd {
	78	ATH9K_ANI_PRESENT = 0x1,
	79	ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
	80	ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
	81	ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
	82	ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
	83	ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
	84	ATH9K_ANI_MODE = 0x40,
	85	ATH9K_ANI_PHYERR_RESET = 0x80,
e36b27af LR	86	ATH9K_ANI_MRC_CCK = 0x100,
e36b27af LR	87	ATH9K_ANI_ALL = 0xfff
394cf0a1 S	88	};
	89
	90	struct ath9k_mib_stats {
	91	u32 ackrcv_bad;
	92	u32 rts_bad;
	93	u32 rts_good;
	94	u32 fcs_bad;
	95	u32 beacons;
	96	};
	97
e36b27af LR	98	/* INI default values for ANI registers */
	99	struct ath9k_ani_default {
	100	u16 m1ThreshLow;
	101	u16 m2ThreshLow;
	102	u16 m1Thresh;
	103	u16 m2Thresh;
	104	u16 m2CountThr;
	105	u16 m2CountThrLow;
	106	u16 m1ThreshLowExt;
	107	u16 m2ThreshLowExt;
	108	u16 m1ThreshExt;
	109	u16 m2ThreshExt;
	110	u16 firstep;
	111	u16 firstepLow;
	112	u16 cycpwrThr1;
	113	u16 cycpwrThr1Ext;
	114	};
	115
ee6e8d1c S	116	struct ar5416AniState {
	117	struct ath9k_channel *c;
	118	u8 noiseImmunityLevel;
e36b27af LR	119	u8 ofdmNoiseImmunityLevel;
	120	u8 cckNoiseImmunityLevel;
	121	bool ofdmsTurn;
	122	u8 mrcCCKOff;
ee6e8d1c S	123	u8 spurImmunityLevel;
	124	u8 firstepLevel;
	125	u8 ofdmWeakSigDetectOff;
	126	u8 cckWeakSigThreshold;
f36369af	127	bool update_ani;
ee6e8d1c	128	u32 listenTime;
ee6e8d1c S	129	int32_t rssiThrLow;
ee6e8d1c S	130	int32_t rssiThrHigh;
ee6e8d1c S	131	u32 ofdmPhyErrCount;
ee6e8d1c S	132	u32 cckPhyErrCount;
ee6e8d1c S	133	int16_t pktRssi[2];
	134	int16_t ofdmErrRssi[2];
	135	int16_t cckErrRssi[2];
e36b27af	136	struct ath9k_ani_default iniDef;
ee6e8d1c S	137	};
ee6e8d1c S	138
394cf0a1 S	139	struct ar5416Stats {
	140	u32 ast_ani_niup;
	141	u32 ast_ani_nidown;
	142	u32 ast_ani_spurup;
	143	u32 ast_ani_spurdown;
	144	u32 ast_ani_ofdmon;
	145	u32 ast_ani_ofdmoff;
	146	u32 ast_ani_cckhigh;
	147	u32 ast_ani_ccklow;
	148	u32 ast_ani_stepup;
	149	u32 ast_ani_stepdown;
	150	u32 ast_ani_ofdmerrs;
	151	u32 ast_ani_cckerrs;
	152	u32 ast_ani_reset;
107021c4	153	u32 ast_ani_lneg_or_lzero;
22e66a4c	154	u32 avgbrssi;
394cf0a1	155	struct ath9k_mib_stats ast_mibstats;
394cf0a1	156	};
2660b81a	157	#define ah_mibStats stats.ast_mibstats
394cf0a1	158
cbe61d8a S	159	void ath9k_enable_mib_counters(struct ath_hw *ah);
cbe61d8a S	160	void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
cbe61d8a	161	void ath9k_hw_ani_setup(struct ath_hw *ah);
f637cfd6	162	void ath9k_hw_ani_init(struct ath_hw *ah);
394cf0a1 S	163
394cf0a1 S	164	#endif /* ANI_H */