Commit | Line | Data |
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394cf0a1 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
394cf0a1 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ANI_H | |
18 | #define ANI_H | |
19 | ||
20 | #define HAL_PROCESS_ANI 0x00000001 | |
394cf0a1 | 21 | |
093115b7 | 22 | #define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI) && ah->curchan) |
394cf0a1 | 23 | |
22e66a4c | 24 | #define BEACON_RSSI(ahp) (ahp->stats.avgbrssi) |
394cf0a1 | 25 | |
e36b27af LR |
26 | /* units are errors per second */ |
27 | #define ATH9K_ANI_OFDM_TRIG_HIGH_OLD 500 | |
28 | #define ATH9K_ANI_OFDM_TRIG_HIGH_NEW 1000 | |
29 | ||
30 | /* units are errors per second */ | |
31 | #define ATH9K_ANI_OFDM_TRIG_LOW_OLD 200 | |
32 | #define ATH9K_ANI_OFDM_TRIG_LOW_NEW 400 | |
33 | ||
34 | /* units are errors per second */ | |
35 | #define ATH9K_ANI_CCK_TRIG_HIGH_OLD 200 | |
36 | #define ATH9K_ANI_CCK_TRIG_HIGH_NEW 600 | |
37 | ||
38 | /* units are errors per second */ | |
39 | #define ATH9K_ANI_CCK_TRIG_LOW_OLD 100 | |
40 | #define ATH9K_ANI_CCK_TRIG_LOW_NEW 300 | |
41 | ||
394cf0a1 S |
42 | #define ATH9K_ANI_NOISE_IMMUNE_LVL 4 |
43 | #define ATH9K_ANI_USE_OFDM_WEAK_SIG true | |
44 | #define ATH9K_ANI_CCK_WEAK_SIG_THR false | |
e36b27af LR |
45 | |
46 | #define ATH9K_ANI_SPUR_IMMUNE_LVL_OLD 7 | |
47 | #define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW 3 | |
48 | ||
49 | #define ATH9K_ANI_FIRSTEP_LVL_OLD 0 | |
50 | #define ATH9K_ANI_FIRSTEP_LVL_NEW 2 | |
51 | ||
394cf0a1 S |
52 | #define ATH9K_ANI_RSSI_THR_HIGH 40 |
53 | #define ATH9K_ANI_RSSI_THR_LOW 7 | |
e36b27af LR |
54 | |
55 | #define ATH9K_ANI_PERIOD_OLD 100 | |
56 | #define ATH9K_ANI_PERIOD_NEW 1000 | |
57 | ||
58 | /* in ms */ | |
59 | #define ATH9K_ANI_POLLINTERVAL_OLD 100 | |
60 | #define ATH9K_ANI_POLLINTERVAL_NEW 1000 | |
394cf0a1 S |
61 | |
62 | #define HAL_NOISE_IMMUNE_MAX 4 | |
63 | #define HAL_SPUR_IMMUNE_MAX 7 | |
64 | #define HAL_FIRST_STEP_MAX 2 | |
65 | ||
e36b27af LR |
66 | #define ATH9K_SIG_FIRSTEP_SETTING_MIN 0 |
67 | #define ATH9K_SIG_FIRSTEP_SETTING_MAX 20 | |
68 | #define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0 | |
69 | #define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22 | |
70 | ||
71 | #define ATH9K_ANI_ENABLE_MRC_CCK true | |
72 | ||
73 | /* values here are relative to the INI */ | |
74 | ||
394cf0a1 S |
75 | enum ath9k_ani_cmd { |
76 | ATH9K_ANI_PRESENT = 0x1, | |
77 | ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, | |
78 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, | |
79 | ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, | |
80 | ATH9K_ANI_FIRSTEP_LEVEL = 0x10, | |
81 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, | |
82 | ATH9K_ANI_MODE = 0x40, | |
83 | ATH9K_ANI_PHYERR_RESET = 0x80, | |
e36b27af LR |
84 | ATH9K_ANI_MRC_CCK = 0x100, |
85 | ATH9K_ANI_ALL = 0xfff | |
394cf0a1 S |
86 | }; |
87 | ||
88 | struct ath9k_mib_stats { | |
89 | u32 ackrcv_bad; | |
90 | u32 rts_bad; | |
91 | u32 rts_good; | |
92 | u32 fcs_bad; | |
93 | u32 beacons; | |
94 | }; | |
95 | ||
e36b27af LR |
96 | /* INI default values for ANI registers */ |
97 | struct ath9k_ani_default { | |
98 | u16 m1ThreshLow; | |
99 | u16 m2ThreshLow; | |
100 | u16 m1Thresh; | |
101 | u16 m2Thresh; | |
102 | u16 m2CountThr; | |
103 | u16 m2CountThrLow; | |
104 | u16 m1ThreshLowExt; | |
105 | u16 m2ThreshLowExt; | |
106 | u16 m1ThreshExt; | |
107 | u16 m2ThreshExt; | |
108 | u16 firstep; | |
109 | u16 firstepLow; | |
110 | u16 cycpwrThr1; | |
111 | u16 cycpwrThr1Ext; | |
112 | }; | |
113 | ||
ee6e8d1c S |
114 | struct ar5416AniState { |
115 | struct ath9k_channel *c; | |
116 | u8 noiseImmunityLevel; | |
e36b27af LR |
117 | u8 ofdmNoiseImmunityLevel; |
118 | u8 cckNoiseImmunityLevel; | |
119 | bool ofdmsTurn; | |
120 | u8 mrcCCKOff; | |
ee6e8d1c S |
121 | u8 spurImmunityLevel; |
122 | u8 firstepLevel; | |
123 | u8 ofdmWeakSigDetectOff; | |
124 | u8 cckWeakSigThreshold; | |
f36369af | 125 | bool update_ani; |
ee6e8d1c | 126 | u32 listenTime; |
ee6e8d1c S |
127 | int32_t rssiThrLow; |
128 | int32_t rssiThrHigh; | |
129 | u32 noiseFloor; | |
ee6e8d1c S |
130 | u32 ofdmPhyErrCount; |
131 | u32 cckPhyErrCount; | |
ee6e8d1c S |
132 | int16_t pktRssi[2]; |
133 | int16_t ofdmErrRssi[2]; | |
134 | int16_t cckErrRssi[2]; | |
e36b27af | 135 | struct ath9k_ani_default iniDef; |
ee6e8d1c S |
136 | }; |
137 | ||
394cf0a1 S |
138 | struct ar5416Stats { |
139 | u32 ast_ani_niup; | |
140 | u32 ast_ani_nidown; | |
141 | u32 ast_ani_spurup; | |
142 | u32 ast_ani_spurdown; | |
143 | u32 ast_ani_ofdmon; | |
144 | u32 ast_ani_ofdmoff; | |
145 | u32 ast_ani_cckhigh; | |
146 | u32 ast_ani_ccklow; | |
147 | u32 ast_ani_stepup; | |
148 | u32 ast_ani_stepdown; | |
149 | u32 ast_ani_ofdmerrs; | |
150 | u32 ast_ani_cckerrs; | |
151 | u32 ast_ani_reset; | |
107021c4 | 152 | u32 ast_ani_lneg_or_lzero; |
22e66a4c | 153 | u32 avgbrssi; |
394cf0a1 | 154 | struct ath9k_mib_stats ast_mibstats; |
394cf0a1 | 155 | }; |
2660b81a | 156 | #define ah_mibStats stats.ast_mibstats |
394cf0a1 | 157 | |
cbe61d8a S |
158 | void ath9k_enable_mib_counters(struct ath_hw *ah); |
159 | void ath9k_hw_disable_mib_counters(struct ath_hw *ah); | |
cbe61d8a | 160 | void ath9k_hw_ani_setup(struct ath_hw *ah); |
f637cfd6 | 161 | void ath9k_hw_ani_init(struct ath_hw *ah); |
394cf0a1 S |
162 | |
163 | #endif /* ANI_H */ |