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[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar5008_phy.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
cfe8cba9 17#include "hw.h"
8fe65368
LR		 18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
a043dfb9 21#include "ar5008_initvals.h"
e16393bb 22
e36b27af
LR		 23/* All code below is for AR5008, AR9001, AR9002 */
24
c08267dc
LB		 25#define AR5008_OFDM_RATES 8
26#define AR5008_HT_SS_RATES 8
27#define AR5008_HT_DS_RATES 8
28
29#define AR5008_HT20_SHIFT 16
30#define AR5008_HT40_SHIFT 24
31
32#define AR5008_11NA_OFDM_SHIFT 0
33#define AR5008_11NA_HT_SS_SHIFT 8
34#define AR5008_11NA_HT_DS_SHIFT 16
35
36#define AR5008_11NG_OFDM_SHIFT 4
37#define AR5008_11NG_HT_SS_SHIFT 12
38#define AR5008_11NG_HT_DS_SHIFT 20
39
e36b27af
LR		 40static const int firstep_table[] =
41/* level: 0 1 2 3 4 5 6 7 8 */
42 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
43
e36b27af
LR		 44/*
45 * register values to turn OFDM weak signal detection OFF
46 */
47static const int m1ThreshLow_off = 127;
48static const int m2ThreshLow_off = 127;
49static const int m1Thresh_off = 127;
50static const int m2Thresh_off = 127;
51static const int m2CountThr_off = 31;
52static const int m2CountThrLow_off = 63;
53static const int m1ThreshLowExt_off = 127;
54static const int m2ThreshLowExt_off = 127;
55static const int m1ThreshExt_off = 127;
56static const int m2ThreshExt_off = 127;
57
a043dfb9
FF		 58static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0);
59static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1);
60static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2);
61static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3);
62static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7);
e16393bb 63
a043dfb9 64static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt)
a9b6b256 65{
a043dfb9
FF		 66 struct ar5416IniArray *array = &ah->iniBank6;
67 u32 *data = ah->analogBank6Data;
a9b6b256
FF		 68 int r;
69
70 ENABLE_REGWRITE_BUFFER(ah);
71
72 for (r = 0; r < array->ia_rows; r++) {
73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
74 DO_DELAY(*writecnt);
75 }
76
77 REGWRITE_BUFFER_FLUSH(ah);
78}
79
ddcd4c08 80/**
8fe65368 81 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
ddcd4c08
LR		 82 * @rfbuf:
83 * @reg32:
84 * @numBits:
85 * @firstBit:
86 * @column:
87 *
88 * Performs analog "swizzling" of parameters into their location.
89 * Used on external AR2133/AR5133 radios.
90 */
8fe65368
LR		 91static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
92 u32 numBits, u32 firstBit,
93 u32 column)
ddcd4c08
LR		 94{
95 u32 tmp32, mask, arrayEntry, lastBit;
96 int32_t bitPosition, bitsLeft;
97
98 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
99 arrayEntry = (firstBit - 1) / 8;
100 bitPosition = (firstBit - 1) % 8;
101 bitsLeft = numBits;
102 while (bitsLeft > 0) {
103 lastBit = (bitPosition + bitsLeft > 8) ?
104 8 : bitPosition + bitsLeft;
105 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
106 (column * 8);
107 rfBuf[arrayEntry] &= ~mask;
108 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
109 (column * 8)) & mask;
110 bitsLeft -= 8 - bitPosition;
111 tmp32 = tmp32 >> (8 - bitPosition);
112 bitPosition = 0;
113 arrayEntry++;
114 }
115}
116
a7765828
LR		 117/*
118 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
119 * rf_pwd_icsyndiv.
120 *
121 * Theoretical Rules:
122 * if 2 GHz band
123 * if forceBiasAuto
124 * if synth_freq < 2412
125 * bias = 0
126 * else if 2412 <= synth_freq <= 2422
127 * bias = 1
128 * else // synth_freq > 2422
129 * bias = 2
130 * else if forceBias > 0
131 * bias = forceBias & 7
132 * else
133 * no change, use value from ini file
134 * else
135 * no change, invalid band
136 *
137 * 1st Mod:
138 * 2422 also uses value of 2
139 * <approved>
140 *
141 * 2nd Mod:
142 * Less than 2412 uses value of 0, 2412 and above uses value of 2
143 */
8fe65368 144static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
a7765828
LR		 145{
146 struct ath_common *common = ath9k_hw_common(ah);
147 u32 tmp_reg;
148 int reg_writes = 0;
149 u32 new_bias = 0;
150
8fe65368 151 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
a7765828 152 return;
a7765828 153
7a37081e 154 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
a7765828
LR		 155
156 if (synth_freq < 2412)
157 new_bias = 0;
158 else if (synth_freq < 2422)
159 new_bias = 1;
160 else
161 new_bias = 2;
162
163 /* pre-reverse this field */
164 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
165
d2182b69 166 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
226afe68 167 new_bias, synth_freq);
a7765828
LR		 168
169 /* swizzle rf_pwd_icsyndiv */
8fe65368 170 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
a7765828
LR		 171
172 /* write Bank 6 with new params */
a043dfb9 173 ar5008_write_bank6(ah, &reg_writes);
a7765828
LR		 174}
175
e16393bb 176/**
8fe65368 177 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
25985edc 178 * @ah: atheros hardware structure
e16393bb
LR		 179 * @chan:
180 *
181 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
182 * the channel value. Assumes writes enabled to analog bus and bank6 register
183 * cache in ah->analogBank6Data.
184 */
8fe65368 185static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
e16393bb
LR		 186{
187 struct ath_common *common = ath9k_hw_common(ah);
188 u32 channelSel = 0;
189 u32 bModeSynth = 0;
190 u32 aModeRefSel = 0;
191 u32 reg32 = 0;
192 u16 freq;
193 struct chan_centers centers;
194
195 ath9k_hw_get_channel_centers(ah, chan, &centers);
196 freq = centers.synth_center;
197
198 if (freq < 4800) {
199 u32 txctl;
200
201 if (((freq - 2192) % 5) == 0) {
202 channelSel = ((freq - 672) * 2 - 3040) / 10;
203 bModeSynth = 0;
204 } else if (((freq - 2224) % 5) == 0) {
205 channelSel = ((freq - 704) * 2 - 3040) / 10;
206 bModeSynth = 1;
207 } else {
3800276a 208 ath_err(common, "Invalid channel %u MHz\n", freq);
e16393bb
LR		 209 return -EINVAL;
210 }
211
212 channelSel = (channelSel << 2) & 0xff;
213 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
214
215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
216 if (freq == 2484) {
217
218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
219 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
220 } else {
221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
222 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
223 }
224
225 } else if ((freq % 20) == 0 && freq >= 5120) {
226 channelSel =
227 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
228 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
229 } else if ((freq % 10) == 0) {
230 channelSel =
231 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
232 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
233 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
234 else
235 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
236 } else if ((freq % 5) == 0) {
237 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
238 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
239 } else {
3800276a 240 ath_err(common, "Invalid channel %u MHz\n", freq);
e16393bb
LR		 241 return -EINVAL;
242 }
243
8fe65368 244 ar5008_hw_force_bias(ah, freq);
a7765828 245
e16393bb
LR		 246 reg32 =
247 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
248 (1 << 5) | 0x1;
249
250 REG_WRITE(ah, AR_PHY(0x37), reg32);
251
252 ah->curchan = chan;
e16393bb
LR		 253
254 return 0;
255}
256
257/**
8fe65368 258 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
e16393bb
LR		 259 * @ah: atheros hardware structure
260 * @chan:
261 *
262 * For non single-chip solutions. Converts to baseband spur frequency given the
263 * input channel frequency and compute register settings below.
264 */
8fe65368
LR		 265static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
266 struct ath9k_channel *chan)
e16393bb
LR		 267{
268 int bb_spur = AR_NO_SPUR;
269 int bin, cur_bin;
270 int spur_freq_sd;
271 int spur_delta_phase;
272 int denominator;
273 int upper, lower, cur_vit_mask;
274 int tmp, new;
275 int i;
07b2fa5a
JP		 276 static int pilot_mask_reg[4] = {
277 AR_PHY_TIMING7, AR_PHY_TIMING8,
278 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
e16393bb 279 };
07b2fa5a
JP		 280 static int chan_mask_reg[4] = {
281 AR_PHY_TIMING9, AR_PHY_TIMING10,
282 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
e16393bb 283 };
07b2fa5a 284 static int inc[4] = { 0, 100, 0, 0 };
e16393bb
LR		 285
286 int8_t mask_m[123];
287 int8_t mask_p[123];
288 int8_t mask_amt;
289 int tmp_mask;
290 int cur_bb_spur;
291 bool is2GHz = IS_CHAN_2GHZ(chan);
292
293 memset(&mask_m, 0, sizeof(int8_t) * 123);
294 memset(&mask_p, 0, sizeof(int8_t) * 123);
295
296 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
297 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
298 if (AR_NO_SPUR == cur_bb_spur)
299 break;
300 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
301 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
302 bb_spur = cur_bb_spur;
303 break;
304 }
305 }
306
307 if (AR_NO_SPUR == bb_spur)
308 return;
309
310 bin = bb_spur * 32;
311
312 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
313 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
314 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
315 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
316 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
317
318 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
319
320 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
321 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
322 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
323 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
324 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
325 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
326
327 spur_delta_phase = ((bb_spur * 524288) / 100) &
328 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
329
330 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
331 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
332
333 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
334 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
335 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
336 REG_WRITE(ah, AR_PHY_TIMING11, new);
337
338 cur_bin = -6000;
339 upper = bin + 100;
340 lower = bin - 100;
341
342 for (i = 0; i < 4; i++) {
343 int pilot_mask = 0;
344 int chan_mask = 0;
345 int bp = 0;
346 for (bp = 0; bp < 30; bp++) {
347 if ((cur_bin > lower) && (cur_bin < upper)) {
348 pilot_mask = pilot_mask | 0x1 << bp;
349 chan_mask = chan_mask | 0x1 << bp;
350 }
351 cur_bin += 100;
352 }
353 cur_bin += inc[i];
354 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
355 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
356 }
357
358 cur_vit_mask = 6100;
359 upper = bin + 120;
360 lower = bin - 120;
361
362 for (i = 0; i < 123; i++) {
363 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
364
365 /* workaround for gcc bug #37014 */
366 volatile int tmp_v = abs(cur_vit_mask - bin);
367
368 if (tmp_v < 75)
369 mask_amt = 1;
370 else
371 mask_amt = 0;
372 if (cur_vit_mask < 0)
373 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
374 else
375 mask_p[cur_vit_mask / 100] = mask_amt;
376 }
377 cur_vit_mask -= 100;
378 }
379
380 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
381 | (mask_m[48] << 26) | (mask_m[49] << 24)
382 | (mask_m[50] << 22) | (mask_m[51] << 20)
383 | (mask_m[52] << 18) | (mask_m[53] << 16)
384 | (mask_m[54] << 14) | (mask_m[55] << 12)
385 | (mask_m[56] << 10) | (mask_m[57] << 8)
386 | (mask_m[58] << 6) | (mask_m[59] << 4)
387 | (mask_m[60] << 2) | (mask_m[61] << 0);
388 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
389 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
390
391 tmp_mask = (mask_m[31] << 28)
392 | (mask_m[32] << 26) | (mask_m[33] << 24)
393 | (mask_m[34] << 22) | (mask_m[35] << 20)
394 | (mask_m[36] << 18) | (mask_m[37] << 16)
395 | (mask_m[48] << 14) | (mask_m[39] << 12)
396 | (mask_m[40] << 10) | (mask_m[41] << 8)
397 | (mask_m[42] << 6) | (mask_m[43] << 4)
398 | (mask_m[44] << 2) | (mask_m[45] << 0);
399 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
400 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
401
402 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
403 | (mask_m[18] << 26) | (mask_m[18] << 24)
404 | (mask_m[20] << 22) | (mask_m[20] << 20)
405 | (mask_m[22] << 18) | (mask_m[22] << 16)
406 | (mask_m[24] << 14) | (mask_m[24] << 12)
407 | (mask_m[25] << 10) | (mask_m[26] << 8)
408 | (mask_m[27] << 6) | (mask_m[28] << 4)
409 | (mask_m[29] << 2) | (mask_m[30] << 0);
410 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
411 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
412
413 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
414 | (mask_m[2] << 26) | (mask_m[3] << 24)
415 | (mask_m[4] << 22) | (mask_m[5] << 20)
416 | (mask_m[6] << 18) | (mask_m[7] << 16)
417 | (mask_m[8] << 14) | (mask_m[9] << 12)
418 | (mask_m[10] << 10) | (mask_m[11] << 8)
419 | (mask_m[12] << 6) | (mask_m[13] << 4)
420 | (mask_m[14] << 2) | (mask_m[15] << 0);
421 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
422 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
423
424 tmp_mask = (mask_p[15] << 28)
425 | (mask_p[14] << 26) | (mask_p[13] << 24)
426 | (mask_p[12] << 22) | (mask_p[11] << 20)
427 | (mask_p[10] << 18) | (mask_p[9] << 16)
428 | (mask_p[8] << 14) | (mask_p[7] << 12)
429 | (mask_p[6] << 10) | (mask_p[5] << 8)
430 | (mask_p[4] << 6) | (mask_p[3] << 4)
431 | (mask_p[2] << 2) | (mask_p[1] << 0);
432 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
433 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
434
435 tmp_mask = (mask_p[30] << 28)
436 | (mask_p[29] << 26) | (mask_p[28] << 24)
437 | (mask_p[27] << 22) | (mask_p[26] << 20)
438 | (mask_p[25] << 18) | (mask_p[24] << 16)
439 | (mask_p[23] << 14) | (mask_p[22] << 12)
440 | (mask_p[21] << 10) | (mask_p[20] << 8)
441 | (mask_p[19] << 6) | (mask_p[18] << 4)
442 | (mask_p[17] << 2) | (mask_p[16] << 0);
443 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
444 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
445
446 tmp_mask = (mask_p[45] << 28)
447 | (mask_p[44] << 26) | (mask_p[43] << 24)
448 | (mask_p[42] << 22) | (mask_p[41] << 20)
449 | (mask_p[40] << 18) | (mask_p[39] << 16)
450 | (mask_p[38] << 14) | (mask_p[37] << 12)
451 | (mask_p[36] << 10) | (mask_p[35] << 8)
452 | (mask_p[34] << 6) | (mask_p[33] << 4)
453 | (mask_p[32] << 2) | (mask_p[31] << 0);
454 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
455 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
456
457 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
458 | (mask_p[59] << 26) | (mask_p[58] << 24)
459 | (mask_p[57] << 22) | (mask_p[56] << 20)
460 | (mask_p[55] << 18) | (mask_p[54] << 16)
461 | (mask_p[53] << 14) | (mask_p[52] << 12)
462 | (mask_p[51] << 10) | (mask_p[50] << 8)
463 | (mask_p[49] << 6) | (mask_p[48] << 4)
464 | (mask_p[47] << 2) | (mask_p[46] << 0);
465 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
466 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
467}
468
469/**
8fe65368 470 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
e16393bb
LR		 471 * @ah: atheros hardware structure
472 *
473 * Only required for older devices with external AR2133/AR5133 radios.
474 */
8fe65368 475static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
e16393bb 476{
a043dfb9 477 int size = ah->iniBank6.ia_rows * sizeof(u32);
e16393bb 478
c1b976d2
FF		 479 if (AR_SREV_9280_20_OR_LATER(ah))
480 return 0;
e16393bb 481
a043dfb9
FF		 482 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
483 if (!ah->analogBank6Data)
484 return -ENOMEM;
e16393bb
LR		 485
486 return 0;
e16393bb
LR		 487}
488
489
131d1d03 490/* *
8fe65368 491 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
131d1d03
LR		 492 * @ah: atheros hardware structure
493 * @chan:
494 * @modesIndex:
495 *
496 * Used for the external AR2133/AR5133 radios.
497 *
498 * Reads the EEPROM header info from the device structure and programs
499 * all rf registers. This routine requires access to the analog
500 * rf device. This is not required for single-chip devices.
501 */
8fe65368
LR		 502static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
503 struct ath9k_channel *chan,
504 u16 modesIndex)
f078f209 505{
f078f209
LR		 506 u32 eepMinorRev;
507 u32 ob5GHz = 0, db5GHz = 0;
508 u32 ob2GHz = 0, db2GHz = 0;
509 int regWrites = 0;
37c62fec 510 int i;
f078f209 511
131d1d03
LR		 512 /*
513 * Software does not need to program bank data
514 * for single chip devices, that is AR9280 or anything
515 * after that.
516 */
7a37081e 517 if (AR_SREV_9280_20_OR_LATER(ah))
f078f209
LR		 518 return true;
519
131d1d03 520 /* Setup rf parameters */
f74df6fb 521 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
f078f209 522
37c62fec
FF		 523 for (i = 0; i < ah->iniBank6.ia_rows; i++)
524 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
f078f209 525
131d1d03 526 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
f078f209
LR		 527 if (eepMinorRev >= 2) {
528 if (IS_CHAN_2GHZ(chan)) {
f74df6fb
S		 529 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
530 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
8fe65368
LR		 531 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
532 ob2GHz, 3, 197, 0);
533 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
534 db2GHz, 3, 194, 0);
f078f209 535 } else {
f74df6fb
S		 536 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
537 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
8fe65368
LR		 538 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
539 ob5GHz, 3, 203, 0);
540 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
541 db5GHz, 3, 200, 0);
f078f209
LR		 542 }
543 }
544
131d1d03 545 /* Write Analog registers */
a043dfb9
FF		 546 REG_WRITE_ARRAY(&bank0, 1, regWrites);
547 REG_WRITE_ARRAY(&bank1, 1, regWrites);
548 REG_WRITE_ARRAY(&bank2, 1, regWrites);
549 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites);
550 ar5008_write_bank6(ah, &regWrites);
551 REG_WRITE_ARRAY(&bank7, 1, regWrites);
f078f209
LR		 552
553 return true;
554}
8fe65368
LR		 555
556static void ar5008_hw_init_bb(struct ath_hw *ah,
557 struct ath9k_channel *chan)
558{
559 u32 synthDelay;
560
561 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
7d865c70 562
8fe65368
LR		 563 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
564
7c5adc8d 565 ath9k_hw_synth_delay(ah, chan, synthDelay);
8fe65368
LR		 566}
567
568static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
569{
570 int rx_chainmask, tx_chainmask;
571
572 rx_chainmask = ah->rxchainmask;
573 tx_chainmask = ah->txchainmask;
574
7d0d0df0 575
8fe65368
LR		 576 switch (rx_chainmask) {
577 case 0x5:
578 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
579 AR_PHY_SWAP_ALT_CHAIN);
580 case 0x3:
581 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
582 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
583 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
584 break;
585 }
586 case 0x1:
587 case 0x2:
588 case 0x7:
435c1610 589 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 590 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
591 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
592 break;
593 default:
435c1610 594 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 595 break;
596 }
597
598 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
7d0d0df0
S		 599
600 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 601
8fe65368
LR		 602 if (tx_chainmask == 0x5) {
603 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
604 AR_PHY_SWAP_ALT_CHAIN);
605 }
606 if (AR_SREV_9100(ah))
607 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
608 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
609}
610
611static void ar5008_hw_override_ini(struct ath_hw *ah,
612 struct ath9k_channel *chan)
613{
614 u32 val;
615
616 /*
617 * Set the RX_ABORT and RX_DIS and clear if off only after
618 * RXE is set for MAC. This prevents frames with corrupted
619 * descriptor status.
620 */
621 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
622
7a37081e 623 if (AR_SREV_9280_20_OR_LATER(ah)) {
64b6f46f
SM		 624 /*
625 * For AR9280 and above, there is a new feature that allows
626 * Multicast search based on both MAC Address and Key ID.
627 * By default, this feature is enabled. But since the driver
628 * is not using this feature, we switch it off; otherwise
629 * multicast search based on MAC addr only will fail.
630 */
631 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
632 (~AR_ADHOC_MCAST_KEYID_ENABLE);
8fe65368
LR		 633
634 if (!AR_SREV_9271(ah))
635 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
636
a42acef0 637 if (AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 638 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
639
9ef48932
SM		 640 val |= AR_PCU_MISC_MODE2_CFP_IGNORE;
641
8fe65368
LR		 642 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
643 }
644
1b8714f7 645 if (AR_SREV_9280_20_OR_LATER(ah))
8fe65368
LR		 646 return;
647 /*
648 * Disable BB clock gating
649 * Necessary to avoid issues on AR5416 2.0
650 */
651 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
652
653 /*
654 * Disable RIFS search on some chips to avoid baseband
655 * hang issues.
656 */
657 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
658 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
659 val &= ~AR_PHY_RIFS_INIT_DELAY;
660 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
661 }
662}
663
664static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
665 struct ath9k_channel *chan)
666{
667 u32 phymode;
668 u32 enableDacFifo = 0;
669
e17f83ea 670 if (AR_SREV_9285_12_OR_LATER(ah))
8fe65368
LR		 671 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
672 AR_PHY_FC_ENABLE_DAC_FIFO);
673
674 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
675 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
676
677 if (IS_CHAN_HT40(chan)) {
678 phymode |= AR_PHY_FC_DYN2040_EN;
679
8896934c 680 if (IS_CHAN_HT40PLUS(chan))
8fe65368
LR		 681 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
682
683 }
3df5dd90 684 ENABLE_REGWRITE_BUFFER(ah);
8fe65368
LR		 685 REG_WRITE(ah, AR_PHY_TURBO, phymode);
686
3df5dd90
OR		 687 /* This function do only REG_WRITE, so
688 * we can include it to REGWRITE_BUFFER. */
e4744ec7 689 ath9k_hw_set11nmac2040(ah, chan);
8fe65368
LR		 690
691 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
692 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
7d0d0df0
S		 693
694 REGWRITE_BUFFER_FLUSH(ah);
8fe65368
LR		 695}
696
697
698static int ar5008_hw_process_ini(struct ath_hw *ah,
699 struct ath9k_channel *chan)
700{
e7fc6338 701 struct ath_common *common = ath9k_hw_common(ah);
8fe65368 702 int i, regWrites = 0;
8fe65368
LR		 703 u32 modesIndex, freqIndex;
704
8896934c 705 if (IS_CHAN_5GHZ(chan)) {
8fe65368 706 freqIndex = 1;
8896934c
FF		 707 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
708 } else {
8fe65368 709 freqIndex = 2;
8896934c 710 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
8fe65368
LR		 711 }
712
8fe65368
LR		 713 /*
714 * Set correct baseband to analog shift setting to
715 * access analog chips.
716 */
717 REG_WRITE(ah, AR_PHY(0), 0x00000007);
718
719 /* Write ADDAC shifts */
720 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
d7084da0
FF		 721 if (ah->eep_ops->set_addac)
722 ah->eep_ops->set_addac(ah, chan);
8fe65368 723
9bbb8168 724 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
8fe65368
LR		 725 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
726
7d0d0df0
S		 727 ENABLE_REGWRITE_BUFFER(ah);
728
8fe65368
LR		 729 for (i = 0; i < ah->iniModes.ia_rows; i++) {
730 u32 reg = INI_RA(&ah->iniModes, i, 0);
731 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
732
733 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
734 val &= ~AR_AN_TOP2_PWDCLKIND;
735
736 REG_WRITE(ah, reg, val);
737
738 if (reg >= 0x7800 && reg < 0x78a0
e7fc6338
RM		 739 && ah->config.analog_shiftreg
740 && (common->bus_ops->ath_bus_type != ATH_USB)) {
8fe65368
LR		 741 udelay(100);
742 }
743
744 DO_DELAY(regWrites);
745 }
746
7d0d0df0 747 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 748
a42acef0 749 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 750 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
751
752 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
a42acef0 753 AR_SREV_9287_11_OR_LATER(ah))
8fe65368
LR		 754 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
755
c7effd35
FF		 756 if (AR_SREV_9271_10(ah)) {
757 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA);
758 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa);
759 }
8fe65368 760
7d0d0df0
S		 761 ENABLE_REGWRITE_BUFFER(ah);
762
8fe65368
LR		 763 /* Write common array parameters */
764 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
765 u32 reg = INI_RA(&ah->iniCommon, i, 0);
766 u32 val = INI_RA(&ah->iniCommon, i, 1);
767
768 REG_WRITE(ah, reg, val);
769
770 if (reg >= 0x7800 && reg < 0x78a0
e7fc6338
RM		 771 && ah->config.analog_shiftreg
772 && (common->bus_ops->ath_bus_type != ATH_USB)) {
8fe65368
LR		 773 udelay(100);
774 }
775
776 DO_DELAY(regWrites);
777 }
778
7d0d0df0 779 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 780
8fe65368
LR		 781 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
782
c7d36f9f
FF		 783 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
784 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,
8fe65368 785 regWrites);
8fe65368
LR		 786
787 ar5008_hw_override_ini(ah, chan);
788 ar5008_hw_set_channel_regs(ah, chan);
789 ar5008_hw_init_chain_masks(ah);
790 ath9k_olc_init(ah);
64ea57d0 791 ath9k_hw_apply_txpower(ah, chan, false);
8fe65368
LR		 792
793 /* Write analog registers */
794 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
3800276a 795 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
8fe65368
LR		 796 return -EIO;
797 }
798
799 return 0;
800}
801
802static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
803{
804 u32 rfMode = 0;
805
806 if (chan == NULL)
807 return;
808
1a5e6326
FF		 809 if (IS_CHAN_2GHZ(chan))
810 rfMode |= AR_PHY_MODE_DYNAMIC;
811 else
812 rfMode |= AR_PHY_MODE_OFDM;
8fe65368 813
7a37081e 814 if (!AR_SREV_9280_20_OR_LATER(ah))
8fe65368
LR		 815 rfMode |= (IS_CHAN_5GHZ(chan)) ?
816 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
817
6b42e8d0 818 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
8fe65368
LR		 819 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
820
821 REG_WRITE(ah, AR_PHY_MODE, rfMode);
822}
823
824static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
825{
826 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
827}
828
829static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
830 struct ath9k_channel *chan)
831{
832 u32 coef_scaled, ds_coef_exp, ds_coef_man;
833 u32 clockMhzScaled = 0x64000000;
834 struct chan_centers centers;
835
836 if (IS_CHAN_HALF_RATE(chan))
837 clockMhzScaled = clockMhzScaled >> 1;
838 else if (IS_CHAN_QUARTER_RATE(chan))
839 clockMhzScaled = clockMhzScaled >> 2;
840
841 ath9k_hw_get_channel_centers(ah, chan, &centers);
842 coef_scaled = clockMhzScaled / centers.synth_center;
843
844 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
845 &ds_coef_exp);
846
847 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
848 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
849 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
850 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
851
852 coef_scaled = (9 * coef_scaled) / 10;
853
854 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
855 &ds_coef_exp);
856
857 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
858 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
859 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
860 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
861}
862
863static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
864{
865 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
866 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
867 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
868}
869
870static void ar5008_hw_rfbus_done(struct ath_hw *ah)
871{
872 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
8fe65368 873
7c5adc8d 874 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
8fe65368
LR		 875
876 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
877}
878
8fe65368
LR		 879static void ar5008_restore_chainmask(struct ath_hw *ah)
880{
881 int rx_chainmask = ah->rxchainmask;
882
883 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
884 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
885 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
886 }
887}
888
64773964
LR		 889static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
890 struct ath9k_channel *chan)
891{
892 u32 pll;
893
894 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
895
896 if (chan && IS_CHAN_HALF_RATE(chan))
897 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
898 else if (chan && IS_CHAN_QUARTER_RATE(chan))
899 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
900
901 if (chan && IS_CHAN_5GHZ(chan))
902 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
903 else
904 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
905
906 return pll;
907}
908
909static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
910 struct ath9k_channel *chan)
911{
912 u32 pll;
913
914 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
915
916 if (chan && IS_CHAN_HALF_RATE(chan))
917 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
918 else if (chan && IS_CHAN_QUARTER_RATE(chan))
919 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
920
921 if (chan && IS_CHAN_5GHZ(chan))
922 pll |= SM(0xa, AR_RTC_PLL_DIV);
923 else
924 pll |= SM(0xb, AR_RTC_PLL_DIV);
925
926 return pll;
927}
928
e36b27af
LR		 929static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
930 enum ath9k_ani_cmd cmd,
931 int param)
932{
e36b27af
LR		 933 struct ath_common *common = ath9k_hw_common(ah);
934 struct ath9k_channel *chan = ah->curchan;
c24bd362 935 struct ar5416AniState *aniState = &ah->ani;
9301ca90 936 s32 value;
e36b27af
LR		 937
938 switch (cmd & ah->ani_function) {
939 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
940 /*
941 * on == 1 means ofdm weak signal detection is ON
942 * on == 1 is the default, for less noise immunity
943 *
944 * on == 0 means ofdm weak signal detection is OFF
945 * on == 0 means more noise imm
946 */
947 u32 on = param ? 1 : 0;
948 /*
949 * make register setting for default
950 * (weak sig detect ON) come from INI file
951 */
952 int m1ThreshLow = on ?
953 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
954 int m2ThreshLow = on ?
955 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
956 int m1Thresh = on ?
957 aniState->iniDef.m1Thresh : m1Thresh_off;
958 int m2Thresh = on ?
959 aniState->iniDef.m2Thresh : m2Thresh_off;
960 int m2CountThr = on ?
961 aniState->iniDef.m2CountThr : m2CountThr_off;
962 int m2CountThrLow = on ?
963 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
964 int m1ThreshLowExt = on ?
965 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
966 int m2ThreshLowExt = on ?
967 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
968 int m1ThreshExt = on ?
969 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
970 int m2ThreshExt = on ?
971 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
972
973 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
974 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
975 m1ThreshLow);
976 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
977 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
978 m2ThreshLow);
979 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
980 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
981 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
982 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
983 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
984 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
985 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
986 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
987 m2CountThrLow);
988
989 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
990 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
991 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
992 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
993 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
994 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
995 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
996 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
997
998 if (on)
999 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1000 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1001 else
1002 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1003 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1004
7067e701 1005 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 1006 ath_dbg(common, ANI,
226afe68
JP		 1007 "** ch %d: ofdm weak signal: %s=>%s\n",
1008 chan->channel,
7067e701 1009 aniState->ofdmWeakSigDetect ?
226afe68
JP		 1010 "on" : "off",
1011 on ? "on" : "off");
e36b27af
LR		 1012 if (on)
1013 ah->stats.ast_ani_ofdmon++;
1014 else
1015 ah->stats.ast_ani_ofdmoff++;
7067e701 1016 aniState->ofdmWeakSigDetect = on;
e36b27af
LR		 1017 }
1018 break;
1019 }
1020 case ATH9K_ANI_FIRSTEP_LEVEL:{
1021 u32 level = param;
1022
171cdab8 1023 value = level * 2;
e36b27af 1024 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
9301ca90 1025 AR_PHY_FIND_SIG_FIRSTEP, value);
171cdab8
FF		 1026 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1027 AR_PHY_FIND_SIG_FIRSTEP_LOW, value);
e36b27af
LR		 1028
1029 if (level != aniState->firstepLevel) {
d2182b69 1030 ath_dbg(common, ANI,
226afe68
JP		 1031 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1032 chan->channel,
1033 aniState->firstepLevel,
1034 level,
465dce62 1035 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1036 value,
1037 aniState->iniDef.firstep);
d2182b69 1038 ath_dbg(common, ANI,
226afe68
JP		 1039 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1040 chan->channel,
1041 aniState->firstepLevel,
1042 level,
465dce62 1043 ATH9K_ANI_FIRSTEP_LVL,
9301ca90 1044 value,
226afe68 1045 aniState->iniDef.firstepLow);
e36b27af
LR		 1046 if (level > aniState->firstepLevel)
1047 ah->stats.ast_ani_stepup++;
1048 else if (level < aniState->firstepLevel)
1049 ah->stats.ast_ani_stepdown++;
1050 aniState->firstepLevel = level;
1051 }
1052 break;
1053 }
1054 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1055 u32 level = param;
1056
28327fd0 1057 value = (level + 1) * 2;
e36b27af 1058 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
28327fd0 1059 AR_PHY_TIMING5_CYCPWR_THR1, value);
e36b27af 1060
b874ec8d
FF		 1061 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1062 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1);
e36b27af
LR		 1063
1064 if (level != aniState->spurImmunityLevel) {
d2182b69 1065 ath_dbg(common, ANI,
226afe68
JP		 1066 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1067 chan->channel,
1068 aniState->spurImmunityLevel,
1069 level,
465dce62 1070 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1071 value,
1072 aniState->iniDef.cycpwrThr1);
d2182b69 1073 ath_dbg(common, ANI,
226afe68
JP		 1074 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1075 chan->channel,
1076 aniState->spurImmunityLevel,
1077 level,
465dce62 1078 ATH9K_ANI_SPUR_IMMUNE_LVL,
28327fd0 1079 value,
226afe68 1080 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1081 if (level > aniState->spurImmunityLevel)
1082 ah->stats.ast_ani_spurup++;
1083 else if (level < aniState->spurImmunityLevel)
1084 ah->stats.ast_ani_spurdown++;
1085 aniState->spurImmunityLevel = level;
1086 }
1087 break;
1088 }
1089 case ATH9K_ANI_MRC_CCK:
1090 /*
1091 * You should not see this as AR5008, AR9001, AR9002
1092 * does not have hardware support for MRC CCK.
1093 */
1094 WARN_ON(1);
1095 break;
e36b27af 1096 default:
d2182b69 1097 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
e36b27af
LR		 1098 return false;
1099 }
1100
d2182b69 1101 ath_dbg(common, ANI,
226afe68
JP		 1102 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1103 aniState->spurImmunityLevel,
7067e701 1104 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1105 aniState->firstepLevel,
81b67fd6 1106 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1107 aniState->listenTime,
1108 aniState->ofdmPhyErrCount,
1109 aniState->cckPhyErrCount);
e36b27af
LR		 1110 return true;
1111}
1112
641d9921
FF		 1113static void ar5008_hw_do_getnf(struct ath_hw *ah,
1114 int16_t nfarray[NUM_NF_READINGS])
1115{
641d9921
FF		 1116 int16_t nf;
1117
1118 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
7919a57b 1119 nfarray[0] = sign_extend32(nf, 8);
641d9921
FF		 1120
1121 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
7919a57b 1122 nfarray[1] = sign_extend32(nf, 8);
641d9921
FF		 1123
1124 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
7919a57b 1125 nfarray[2] = sign_extend32(nf, 8);
641d9921 1126
866b7780
FF		 1127 if (!IS_CHAN_HT40(ah->curchan))
1128 return;
1129
641d9921 1130 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
7919a57b 1131 nfarray[3] = sign_extend32(nf, 8);
641d9921
FF		 1132
1133 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
7919a57b 1134 nfarray[4] = sign_extend32(nf, 8);
641d9921
FF		 1135
1136 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
7919a57b 1137 nfarray[5] = sign_extend32(nf, 8);
641d9921
FF		 1138}
1139
e36b27af
LR		 1140/*
1141 * Initialize the ANI register values with default (ini) values.
1142 * This routine is called during a (full) hardware reset after
1143 * all the registers are initialised from the INI.
1144 */
1145static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1146{
e36b27af
LR		 1147 struct ath_common *common = ath9k_hw_common(ah);
1148 struct ath9k_channel *chan = ah->curchan;
c24bd362 1149 struct ar5416AniState *aniState = &ah->ani;
e36b27af 1150 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1151 u32 val;
1152
e36b27af
LR		 1153 iniDef = &aniState->iniDef;
1154
8896934c 1155 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
226afe68
JP		 1156 ah->hw_version.macVersion,
1157 ah->hw_version.macRev,
1158 ah->opmode,
8896934c 1159 chan->channel);
e36b27af
LR		 1160
1161 val = REG_READ(ah, AR_PHY_SFCORR);
1162 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1163 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1164 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1165
1166 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1167 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1168 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1169 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1170
1171 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1172 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1173 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1174 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1175 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1176 iniDef->firstep = REG_READ_FIELD(ah,
1177 AR_PHY_FIND_SIG,
1178 AR_PHY_FIND_SIG_FIRSTEP);
1179 iniDef->firstepLow = REG_READ_FIELD(ah,
1180 AR_PHY_FIND_SIG_LOW,
1181 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1182 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1183 AR_PHY_TIMING5,
1184 AR_PHY_TIMING5_CYCPWR_THR1);
1185 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1186 AR_PHY_EXT_CCA,
1187 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1188
1189 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1190 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1191 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
4f4395c6 1192 aniState->ofdmWeakSigDetect = true;
81b67fd6 1193 aniState->mrcCCK = false; /* not available on pre AR9003 */
e36b27af
LR		 1194}
1195
f2552e28
FF		 1196static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1197{
1198 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1199 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1200 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1201 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1202 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1203 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1204}
e36b27af 1205
4e8c14e9
FF		 1206static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1207 struct ath_hw_radar_conf *conf)
1208{
992a36a6 1209 u32 radar_0 = 0, radar_1;
4e8c14e9
FF		 1210
1211 if (!conf) {
1212 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1213 return;
1214 }
1215
1216 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1217 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1218 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1219 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1220 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1221 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1222
992a36a6
LB		 1223 radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1224 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1225 AR_PHY_RADAR_1_RELPWR_THRESH);
4e8c14e9
FF		 1226 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1227 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1228 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1229 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1230 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1231
1232 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1233 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1234 if (conf->ext_channel)
1235 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1236 else
1237 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1238}
1239
c5d0855a
FF		 1240static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1241{
1242 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1243
1244 conf->fir_power = -33;
1245 conf->radar_rssi = 20;
1246 conf->pulse_height = 10;
edad1873 1247 conf->pulse_rssi = 15;
c5d0855a
FF		 1248 conf->pulse_inband = 15;
1249 conf->pulse_maxlen = 255;
1250 conf->pulse_inband_step = 12;
1251 conf->radar_inband = 8;
1252}
1253
c08267dc
LB		 1254static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array)
1255{
1256#define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x))
1257 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]);
1258 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l],
1259 rate_array[rate2s]));
1260 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l],
1261 rate_array[rate5_5s]));
1262 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l],
1263 rate_array[rate11s]));
1264#undef CCK_DELTA
1265}
1266
1267static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array,
1268 int offset)
1269{
1270 int i, idx = 0;
1271
1272 for (i = offset; i < offset + AR5008_OFDM_RATES; i++) {
1273 ah->tx_power[i] = rate_array[idx];
1274 idx++;
1275 }
1276}
1277
1278static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array,
1279 int ss_offset, int ds_offset,
1280 bool is_40, int ht40_delta)
1281{
1282 int i, mcs_idx = (is_40) ? AR5008_HT40_SHIFT : AR5008_HT20_SHIFT;
1283
1284 for (i = ss_offset; i < ss_offset + AR5008_HT_SS_RATES; i++) {
1285 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta;
1286 mcs_idx++;
1287 }
1288 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset],
1289 AR5008_HT_SS_RATES);
1290}
1291
1292void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1293 struct ath9k_channel *chan, int ht40_delta)
1294{
1295 if (IS_CHAN_5GHZ(chan)) {
1296 ar5008_hw_init_txpower_ofdm(ah, rate_array,
1297 AR5008_11NA_OFDM_SHIFT);
1298 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1299 ar5008_hw_init_txpower_ht(ah, rate_array,
1300 AR5008_11NA_HT_SS_SHIFT,
1301 AR5008_11NA_HT_DS_SHIFT,
1302 IS_CHAN_HT40(chan),
1303 ht40_delta);
1304 }
1305 } else {
1306 ar5008_hw_init_txpower_cck(ah, rate_array);
1307 ar5008_hw_init_txpower_ofdm(ah, rate_array,
1308 AR5008_11NG_OFDM_SHIFT);
1309 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1310 ar5008_hw_init_txpower_ht(ah, rate_array,
1311 AR5008_11NG_HT_SS_SHIFT,
1312 AR5008_11NG_HT_DS_SHIFT,
1313 IS_CHAN_HT40(chan),
1314 ht40_delta);
1315 }
1316 }
1317}
1318
c1b976d2 1319int ar5008_hw_attach_phy_ops(struct ath_hw *ah)
8fe65368
LR		 1320{
1321 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
07b2fa5a 1322 static const u32 ar5416_cca_regs[6] = {
bbacee13
FF		 1323 AR_PHY_CCA,
1324 AR_PHY_CH1_CCA,
1325 AR_PHY_CH2_CCA,
1326 AR_PHY_EXT_CCA,
1327 AR_PHY_CH1_EXT_CCA,
1328 AR_PHY_CH2_EXT_CCA
1329 };
c1b976d2
FF		 1330 int ret;
1331
1332 ret = ar5008_hw_rf_alloc_ext_banks(ah);
1333 if (ret)
1334 return ret;
8fe65368
LR		 1335
1336 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1337 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1338
8fe65368
LR		 1339 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1340 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1341 priv_ops->init_bb = ar5008_hw_init_bb;
1342 priv_ops->process_ini = ar5008_hw_process_ini;
1343 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1344 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1345 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1346 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1347 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
8fe65368 1348 priv_ops->restore_chainmask = ar5008_restore_chainmask;
641d9921 1349 priv_ops->do_getnf = ar5008_hw_do_getnf;
4e8c14e9 1350 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
64773964 1351
6790ae7a
FF		 1352 priv_ops->ani_control = ar5008_hw_ani_control_new;
1353 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
e36b27af 1354
491b209d 1355 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
64773964
LR		 1356 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1357 else
1358 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
f2552e28
FF		 1359
1360 ar5008_hw_set_nf_limits(ah);
c5d0855a 1361 ar5008_hw_set_radar_conf(ah);
bbacee13 1362 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
c1b976d2 1363 return 0;
8fe65368 1364}
Linux kernel - Deliverables
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