[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9002_mac.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"
#include <linux/export.h>

#define AR_BufLen           0x00000fff

static void ar9002_hw_rx_enable(struct ath_hw *ah)
{
	REG_WRITE(ah, AR_CR, AR_CR_RXE);
}

static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
{
	((struct ath_desc*) ds)->ds_link = ds_link;
}

static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked,
			      u32 *sync_cause_p)
{
	u32 isr = 0;
	u32 mask2 = 0;
	struct ath9k_hw_capabilities *pCap = &ah->caps;
	u32 sync_cause = 0;
	bool fatal_int = false;
	struct ath_common *common = ath9k_hw_common(ah);

	if (!AR_SREV_9100(ah)) {
		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
			    == AR_RTC_STATUS_ON) {
				isr = REG_READ(ah, AR_ISR);
			}
		}

		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
			AR_INTR_SYNC_DEFAULT;

		*masked = 0;

		if (!isr && !sync_cause)
			return false;
	} else {
		*masked = 0;
		isr = REG_READ(ah, AR_ISR);
	}

	if (isr) {
		if (isr & AR_ISR_BCNMISC) {
			u32 isr2;
			isr2 = REG_READ(ah, AR_ISR_S2);
			if (isr2 & AR_ISR_S2_TIM)
				mask2 |= ATH9K_INT_TIM;
			if (isr2 & AR_ISR_S2_DTIM)
				mask2 |= ATH9K_INT_DTIM;
			if (isr2 & AR_ISR_S2_DTIMSYNC)
				mask2 |= ATH9K_INT_DTIMSYNC;
			if (isr2 & (AR_ISR_S2_CABEND))
				mask2 |= ATH9K_INT_CABEND;
			if (isr2 & AR_ISR_S2_GTT)
				mask2 |= ATH9K_INT_GTT;
			if (isr2 & AR_ISR_S2_CST)
				mask2 |= ATH9K_INT_CST;
			if (isr2 & AR_ISR_S2_TSFOOR)
				mask2 |= ATH9K_INT_TSFOOR;

			if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
				REG_WRITE(ah, AR_ISR_S2, isr2);
				isr &= ~AR_ISR_BCNMISC;
			}
		}

		if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
			isr = REG_READ(ah, AR_ISR_RAC);

		if (isr == 0xffffffff) {
			*masked = 0;
			return false;
		}

		*masked = isr & ATH9K_INT_COMMON;

		if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
			   AR_ISR_RXOK | AR_ISR_RXERR))
			*masked |= ATH9K_INT_RX;

		if (isr &
		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
		     AR_ISR_TXEOL)) {
			u32 s0_s, s1_s;

			*masked |= ATH9K_INT_TX;

			if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
				s0_s = REG_READ(ah, AR_ISR_S0_S);
				s1_s = REG_READ(ah, AR_ISR_S1_S);
			} else {
				s0_s = REG_READ(ah, AR_ISR_S0);
				REG_WRITE(ah, AR_ISR_S0, s0_s);
				s1_s = REG_READ(ah, AR_ISR_S1);
				REG_WRITE(ah, AR_ISR_S1, s1_s);

				isr &= ~(AR_ISR_TXOK |
					 AR_ISR_TXDESC |
					 AR_ISR_TXERR |
					 AR_ISR_TXEOL);
			}

			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
		}

		if (isr & AR_ISR_RXORN) {
			ath_dbg(common, INTERRUPT,
				"receive FIFO overrun interrupt\n");
		}

		*masked |= mask2;
	}

	if (!AR_SREV_9100(ah) && (isr & AR_ISR_GENTMR)) {
		u32 s5_s;

		if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
			s5_s = REG_READ(ah, AR_ISR_S5_S);
		} else {
			s5_s = REG_READ(ah, AR_ISR_S5);
		}

		ah->intr_gen_timer_trigger =
				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);

		ah->intr_gen_timer_thresh =
			MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);

		if (ah->intr_gen_timer_trigger)
			*masked |= ATH9K_INT_GENTIMER;

		if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
		    !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
			*masked |= ATH9K_INT_TIM_TIMER;

		if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
			REG_WRITE(ah, AR_ISR_S5, s5_s);
			isr &= ~AR_ISR_GENTMR;
		}
	}

	if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
		REG_WRITE(ah, AR_ISR, isr);
		REG_READ(ah, AR_ISR);
	}

	if (AR_SREV_9100(ah))
		return true;

	if (sync_cause) {
		if (sync_cause_p)
			*sync_cause_p = sync_cause;
		fatal_int =
			(sync_cause &
			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
			? true : false;

		if (fatal_int) {
			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
				ath_dbg(common, ANY,
					"received PCI FATAL interrupt\n");
			}
			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
				ath_dbg(common, ANY,
					"received PCI PERR interrupt\n");
			}
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
			ath_dbg(common, INTERRUPT,
				"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
			REG_WRITE(ah, AR_RC, 0);
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
			ath_dbg(common, INTERRUPT,
				"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
		}

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	}

	return true;
}

static void
ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	u32 ctl1, ctl6;

	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
	ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;

	ACCESS_ONCE(ads->ds_link) = i->link;
	ACCESS_ONCE(ads->ds_data) = i->buf_addr[0];

	ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore);
	ctl6 = SM(i->keytype, AR_EncrType);

	if (AR_SREV_9285(ah)) {
		ads->ds_ctl8 = 0;
		ads->ds_ctl9 = 0;
		ads->ds_ctl10 = 0;
		ads->ds_ctl11 = 0;
	}

	if ((i->is_first || i->is_last) &&
	    i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
		ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0)
			| set11nTries(i->rates, 1)
			| set11nTries(i->rates, 2)
			| set11nTries(i->rates, 3)
			| (i->dur_update ? AR_DurUpdateEna : 0)
			| SM(0, AR_BurstDur);

		ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0)
			| set11nRate(i->rates, 1)
			| set11nRate(i->rates, 2)
			| set11nRate(i->rates, 3);
	} else {
		ACCESS_ONCE(ads->ds_ctl2) = 0;
		ACCESS_ONCE(ads->ds_ctl3) = 0;
	}

	if (!i->is_first) {
		ACCESS_ONCE(ads->ds_ctl0) = 0;
		ACCESS_ONCE(ads->ds_ctl1) = ctl1;
		ACCESS_ONCE(ads->ds_ctl6) = ctl6;
		return;
	}

	ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
		| SM(i->type, AR_FrameType)
		| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
		| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
		| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);

	switch (i->aggr) {
	case AGGR_BUF_FIRST:
		ctl6 |= SM(i->aggr_len, AR_AggrLen);
		/* fall through */
	case AGGR_BUF_MIDDLE:
		ctl1 |= AR_IsAggr | AR_MoreAggr;
		ctl6 |= SM(i->ndelim, AR_PadDelim);
		break;
	case AGGR_BUF_LAST:
		ctl1 |= AR_IsAggr;
		break;
	case AGGR_BUF_NONE:
		break;
	}

	ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen)
		| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
		| SM(i->txpower[0], AR_XmitPower0)
		| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
		| (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
		| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
		| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
		| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
		   (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));

	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
	ACCESS_ONCE(ads->ds_ctl6) = ctl6;

	if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST)
		return;

	ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0)
		| set11nPktDurRTSCTS(i->rates, 1);

	ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2)
		| set11nPktDurRTSCTS(i->rates, 3);

	ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0)
		| set11nRateFlags(i->rates, 1)
		| set11nRateFlags(i->rates, 2)
		| set11nRateFlags(i->rates, 3)
		| SM(i->rtscts_rate, AR_RTSCTSRate);

	ACCESS_ONCE(ads->ds_ctl9) = SM(i->txpower[1], AR_XmitPower1);
	ACCESS_ONCE(ads->ds_ctl10) = SM(i->txpower[2], AR_XmitPower2);
	ACCESS_ONCE(ads->ds_ctl11) = SM(i->txpower[3], AR_XmitPower3);
}

static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
				 struct ath_tx_status *ts)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	u32 status;

	status = ACCESS_ONCE(ads->ds_txstatus9);
	if ((status & AR_TxDone) == 0)
		return -EINPROGRESS;

	ts->ts_tstamp = ads->AR_SendTimestamp;
	ts->ts_status = 0;
	ts->ts_flags = 0;

	if (status & AR_TxOpExceeded)
		ts->ts_status |= ATH9K_TXERR_XTXOP;
	ts->tid = MS(status, AR_TxTid);
	ts->ts_rateindex = MS(status, AR_FinalTxIdx);
	ts->ts_seqnum = MS(status, AR_SeqNum);

	status = ACCESS_ONCE(ads->ds_txstatus0);
	ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
	ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
	ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
	if (status & AR_TxBaStatus) {
		ts->ts_flags |= ATH9K_TX_BA;
		ts->ba_low = ads->AR_BaBitmapLow;
		ts->ba_high = ads->AR_BaBitmapHigh;
	}

	status = ACCESS_ONCE(ads->ds_txstatus1);
	if (status & AR_FrmXmitOK)
		ts->ts_status |= ATH9K_TX_ACKED;
	else {
		if (status & AR_ExcessiveRetries)
			ts->ts_status |= ATH9K_TXERR_XRETRY;
		if (status & AR_Filtered)
			ts->ts_status |= ATH9K_TXERR_FILT;
		if (status & AR_FIFOUnderrun) {
			ts->ts_status |= ATH9K_TXERR_FIFO;
			ath9k_hw_updatetxtriglevel(ah, true);
		}
	}
	if (status & AR_TxTimerExpired)
		ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
	if (status & AR_DescCfgErr)
		ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
	if (status & AR_TxDataUnderrun) {
		ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	if (status & AR_TxDelimUnderrun) {
		ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	ts->ts_shortretry = MS(status, AR_RTSFailCnt);
	ts->ts_longretry = MS(status, AR_DataFailCnt);
	ts->ts_virtcol = MS(status, AR_VirtRetryCnt);

	status = ACCESS_ONCE(ads->ds_txstatus5);
	ts->ts_rssi = MS(status, AR_TxRSSICombined);
	ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
	ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
	ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);

	ts->evm0 = ads->AR_TxEVM0;
	ts->evm1 = ads->AR_TxEVM1;
	ts->evm2 = ads->AR_TxEVM2;

	return 0;
}

static int ar9002_hw_get_duration(struct ath_hw *ah, const void *ds, int index)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	switch (index) {
	case 0:
		return MS(ACCESS_ONCE(ads->ds_ctl4), AR_PacketDur0);
	case 1:
		return MS(ACCESS_ONCE(ads->ds_ctl4), AR_PacketDur1);
	case 2:
		return MS(ACCESS_ONCE(ads->ds_ctl5), AR_PacketDur2);
	case 3:
		return MS(ACCESS_ONCE(ads->ds_ctl5), AR_PacketDur3);
	default:
		return -1;
	}
}

void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
			  u32 size, u32 flags)
{
	struct ar5416_desc *ads = AR5416DESC(ds);

	ads->ds_ctl1 = size & AR_BufLen;
	if (flags & ATH9K_RXDESC_INTREQ)
		ads->ds_ctl1 |= AR_RxIntrReq;

	memset(&ads->u.rx, 0, sizeof(ads->u.rx));
}
EXPORT_SYMBOL(ath9k_hw_setuprxdesc);

void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
{
	struct ath_hw_ops *ops = ath9k_hw_ops(ah);

	ops->rx_enable = ar9002_hw_rx_enable;
	ops->set_desc_link = ar9002_hw_set_desc_link;
	ops->get_isr = ar9002_hw_get_isr;
	ops->set_txdesc = ar9002_set_txdesc;
	ops->proc_txdesc = ar9002_hw_proc_txdesc;
	ops->get_duration = ar9002_hw_get_duration;
}
Commit	Line	Data
b622a720	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
b622a720 LR	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include "hw.h"
ee40fa06	18	#include <linux/export.h>
b622a720 LR	19
	20	#define AR_BufLen 0x00000fff
	21
	22	static void ar9002_hw_rx_enable(struct ath_hw *ah)
	23	{
	24	REG_WRITE(ah, AR_CR, AR_CR_RXE);
	25	}
	26
	27	static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
	28	{
	29	((struct ath_desc*) ds)->ds_link = ds_link;
	30	}
	31
6a4d05dc FF	32	static bool ar9002_hw_get_isr(struct ath_hw ah, enum ath9k_int masked,
6a4d05dc FF	33	u32 *sync_cause_p)
b622a720 LR	34	{
	35	u32 isr = 0;
	36	u32 mask2 = 0;
	37	struct ath9k_hw_capabilities *pCap = &ah->caps;
	38	u32 sync_cause = 0;
	39	bool fatal_int = false;
	40	struct ath_common *common = ath9k_hw_common(ah);
	41
	42	if (!AR_SREV_9100(ah)) {
	43	if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
	44	if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
	45	== AR_RTC_STATUS_ON) {
	46	isr = REG_READ(ah, AR_ISR);
	47	}
	48	}
	49
	50	sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
	51	AR_INTR_SYNC_DEFAULT;
	52
	53	*masked = 0;
	54
	55	if (!isr && !sync_cause)
	56	return false;
	57	} else {
	58	*masked = 0;
	59	isr = REG_READ(ah, AR_ISR);
	60	}
	61
	62	if (isr) {
	63	if (isr & AR_ISR_BCNMISC) {
	64	u32 isr2;
	65	isr2 = REG_READ(ah, AR_ISR_S2);
	66	if (isr2 & AR_ISR_S2_TIM)
	67	mask2 \|= ATH9K_INT_TIM;
	68	if (isr2 & AR_ISR_S2_DTIM)
	69	mask2 \|= ATH9K_INT_DTIM;
	70	if (isr2 & AR_ISR_S2_DTIMSYNC)
	71	mask2 \|= ATH9K_INT_DTIMSYNC;
	72	if (isr2 & (AR_ISR_S2_CABEND))
	73	mask2 \|= ATH9K_INT_CABEND;
	74	if (isr2 & AR_ISR_S2_GTT)
	75	mask2 \|= ATH9K_INT_GTT;
	76	if (isr2 & AR_ISR_S2_CST)
	77	mask2 \|= ATH9K_INT_CST;
	78	if (isr2 & AR_ISR_S2_TSFOOR)
	79	mask2 \|= ATH9K_INT_TSFOOR;
73f0b56a SM	80
	81	if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
	82	REG_WRITE(ah, AR_ISR_S2, isr2);
	83	isr &= ~AR_ISR_BCNMISC;
	84	}
b622a720 LR	85	}
b622a720 LR	86
73f0b56a SM	87	if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
	88	isr = REG_READ(ah, AR_ISR_RAC);
	89
b622a720 LR	90	if (isr == 0xffffffff) {
	91	*masked = 0;
	92	return false;
	93	}
	94
	95	*masked = isr & ATH9K_INT_COMMON;
	96
45684c75 FF	97	if (isr & (AR_ISR_RXMINTR \| AR_ISR_RXINTM \|
45684c75 FF	98	AR_ISR_RXOK \| AR_ISR_RXERR))
b622a720	99	*masked \|= ATH9K_INT_RX;
45684c75	100
b622a720 LR	101	if (isr &
	102	(AR_ISR_TXOK \| AR_ISR_TXDESC \| AR_ISR_TXERR \|
	103	AR_ISR_TXEOL)) {
	104	u32 s0_s, s1_s;
	105
	106	*masked \|= ATH9K_INT_TX;
	107
73f0b56a SM	108	if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
	109	s0_s = REG_READ(ah, AR_ISR_S0_S);
	110	s1_s = REG_READ(ah, AR_ISR_S1_S);
	111	} else {
	112	s0_s = REG_READ(ah, AR_ISR_S0);
	113	REG_WRITE(ah, AR_ISR_S0, s0_s);
	114	s1_s = REG_READ(ah, AR_ISR_S1);
	115	REG_WRITE(ah, AR_ISR_S1, s1_s);
	116
	117	isr &= ~(AR_ISR_TXOK \|
	118	AR_ISR_TXDESC \|
	119	AR_ISR_TXERR \|
	120	AR_ISR_TXEOL);
	121	}
	122
b622a720 LR	123	ah->intr_txqs \|= MS(s0_s, AR_ISR_S0_QCU_TXOK);
b622a720 LR	124	ah->intr_txqs \|= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
b622a720 LR	125	ah->intr_txqs \|= MS(s1_s, AR_ISR_S1_QCU_TXERR);
	126	ah->intr_txqs \|= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
	127	}
	128
	129	if (isr & AR_ISR_RXORN) {
d2182b69	130	ath_dbg(common, INTERRUPT,
226afe68	131	"receive FIFO overrun interrupt\n");
b622a720 LR	132	}
b622a720 LR	133
b622a720 LR	134	*masked \|= mask2;
	135	}
	136
73f0b56a	137	if (!AR_SREV_9100(ah) && (isr & AR_ISR_GENTMR)) {
b622a720 LR	138	u32 s5_s;
b622a720 LR	139
73f0b56a SM	140	if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
	141	s5_s = REG_READ(ah, AR_ISR_S5_S);
	142	} else {
	143	s5_s = REG_READ(ah, AR_ISR_S5);
	144	}
	145
45684c75	146	ah->intr_gen_timer_trigger =
b622a720 LR	147	MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
b622a720 LR	148
45684c75 FF	149	ah->intr_gen_timer_thresh =
45684c75 FF	150	MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
b622a720	151
45684c75 FF	152	if (ah->intr_gen_timer_trigger)
45684c75 FF	153	*masked \|= ATH9K_INT_GENTIMER;
b622a720	154
45684c75 FF	155	if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
	156	!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
	157	*masked \|= ATH9K_INT_TIM_TIMER;
73f0b56a SM	158
	159	if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
	160	REG_WRITE(ah, AR_ISR_S5, s5_s);
	161	isr &= ~AR_ISR_GENTMR;
	162	}
b622a720 LR	163	}
b622a720 LR	164
73f0b56a SM	165	if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
	166	REG_WRITE(ah, AR_ISR, isr);
	167	REG_READ(ah, AR_ISR);
	168	}
	169
	170	if (AR_SREV_9100(ah))
	171	return true;
	172
b622a720	173	if (sync_cause) {
6a4d05dc FF	174	if (sync_cause_p)
6a4d05dc FF	175	*sync_cause_p = sync_cause;
b622a720 LR	176	fatal_int =
	177	(sync_cause &
	178	(AR_INTR_SYNC_HOST1_FATAL \| AR_INTR_SYNC_HOST1_PERR))
	179	? true : false;
	180
	181	if (fatal_int) {
	182	if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
d2182b69	183	ath_dbg(common, ANY,
226afe68	184	"received PCI FATAL interrupt\n");
b622a720 LR	185	}
b622a720 LR	186	if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
d2182b69	187	ath_dbg(common, ANY,
226afe68	188	"received PCI PERR interrupt\n");
b622a720 LR	189	}
	190	*masked \|= ATH9K_INT_FATAL;
	191	}
	192	if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
d2182b69	193	ath_dbg(common, INTERRUPT,
226afe68	194	"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
b622a720 LR	195	REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
	196	REG_WRITE(ah, AR_RC, 0);
	197	*masked \|= ATH9K_INT_FATAL;
	198	}
	199	if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
d2182b69	200	ath_dbg(common, INTERRUPT,
226afe68	201	"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
b622a720 LR	202	}
	203
	204	REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
	205	(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	206	}
	207
	208	return true;
	209	}
	210
2b63a41d FF	211	static void
	212	ar9002_set_txdesc(struct ath_hw ah, void ds, struct ath_tx_info *i)
	213	{
	214	struct ar5416_desc *ads = AR5416DESC(ds);
	215	u32 ctl1, ctl6;
	216
	217	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
	218	ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
	219	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
	220	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
	221	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
	222
	223	ACCESS_ONCE(ads->ds_link) = i->link;
	224	ACCESS_ONCE(ads->ds_data) = i->buf_addr[0];
	225
	226	ctl1 = i->buf_len[0] \| (i->is_last ? 0 : AR_TxMore);
	227	ctl6 = SM(i->keytype, AR_EncrType);
	228
	229	if (AR_SREV_9285(ah)) {
	230	ads->ds_ctl8 = 0;
	231	ads->ds_ctl9 = 0;
	232	ads->ds_ctl10 = 0;
	233	ads->ds_ctl11 = 0;
	234	}
	235
	236	if ((i->is_first \|\| i->is_last) &&
	237	i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
	238	ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0)
	239	\| set11nTries(i->rates, 1)
	240	\| set11nTries(i->rates, 2)
	241	\| set11nTries(i->rates, 3)
	242	\| (i->dur_update ? AR_DurUpdateEna : 0)
	243	\| SM(0, AR_BurstDur);
	244
	245	ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0)
	246	\| set11nRate(i->rates, 1)
	247	\| set11nRate(i->rates, 2)
	248	\| set11nRate(i->rates, 3);
	249	} else {
	250	ACCESS_ONCE(ads->ds_ctl2) = 0;
	251	ACCESS_ONCE(ads->ds_ctl3) = 0;
	252	}
	253
	254	if (!i->is_first) {
	255	ACCESS_ONCE(ads->ds_ctl0) = 0;
	256	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
	257	ACCESS_ONCE(ads->ds_ctl6) = ctl6;
	258	return;
	259	}
	260
	261	ctl1 \|= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
	262	\| SM(i->type, AR_FrameType)
	263	\| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
	264	\| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
	265	\| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
	266
	267	switch (i->aggr) {
	268	case AGGR_BUF_FIRST:
	269	ctl6 \|= SM(i->aggr_len, AR_AggrLen);
	270	/* fall through */
	271	case AGGR_BUF_MIDDLE:
	272	ctl1 \|= AR_IsAggr \| AR_MoreAggr;
	273	ctl6 \|= SM(i->ndelim, AR_PadDelim);
	274	break;
275	case AGGR_BUF_LAST:
276	ctl1 \|= AR_IsAggr;
277	break;
278	case AGGR_BUF_NONE:
279	break;
280	}
281
282	ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen)
283	\| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
8b537686	284	\| SM(i->txpower[0], AR_XmitPower0)
2b63a41d FF	285	\| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
	286	\| (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
	287	\| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
	288	\| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
	289	\| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
	290	(i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
	291
	292	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
	293	ACCESS_ONCE(ads->ds_ctl6) = ctl6;
	294
	295	if (i->aggr == AGGR_BUF_MIDDLE \|\| i->aggr == AGGR_BUF_LAST)
	296	return;
	297
	298	ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0)
	299	\| set11nPktDurRTSCTS(i->rates, 1);
	300
	301	ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2)
	302	\| set11nPktDurRTSCTS(i->rates, 3);
	303
	304	ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0)
	305	\| set11nRateFlags(i->rates, 1)
	306	\| set11nRateFlags(i->rates, 2)
	307	\| set11nRateFlags(i->rates, 3)
	308	\| SM(i->rtscts_rate, AR_RTSCTSRate);
3ae351ab	309
8b537686 LB	310	ACCESS_ONCE(ads->ds_ctl9) = SM(i->txpower[1], AR_XmitPower1);
	311	ACCESS_ONCE(ads->ds_ctl10) = SM(i->txpower[2], AR_XmitPower2);
	312	ACCESS_ONCE(ads->ds_ctl11) = SM(i->txpower[3], AR_XmitPower3);
2b63a41d FF	313	}
2b63a41d FF	314
b622a720 LR	315	static int ar9002_hw_proc_txdesc(struct ath_hw ah, void ds,
	316	struct ath_tx_status *ts)
	317	{
	318	struct ar5416_desc *ads = AR5416DESC(ds);
e0e9bc82	319	u32 status;
b622a720	320
e0e9bc82 FF	321	status = ACCESS_ONCE(ads->ds_txstatus9);
e0e9bc82 FF	322	if ((status & AR_TxDone) == 0)
b622a720 LR	323	return -EINPROGRESS;
b622a720 LR	324
b622a720 LR	325	ts->ts_tstamp = ads->AR_SendTimestamp;
	326	ts->ts_status = 0;
	327	ts->ts_flags = 0;
	328
e0e9bc82 FF	329	if (status & AR_TxOpExceeded)
	330	ts->ts_status \|= ATH9K_TXERR_XTXOP;
	331	ts->tid = MS(status, AR_TxTid);
	332	ts->ts_rateindex = MS(status, AR_FinalTxIdx);
	333	ts->ts_seqnum = MS(status, AR_SeqNum);
	334
	335	status = ACCESS_ONCE(ads->ds_txstatus0);
	336	ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
	337	ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
	338	ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
	339	if (status & AR_TxBaStatus) {
	340	ts->ts_flags \|= ATH9K_TX_BA;
	341	ts->ba_low = ads->AR_BaBitmapLow;
	342	ts->ba_high = ads->AR_BaBitmapHigh;
	343	}
	344
	345	status = ACCESS_ONCE(ads->ds_txstatus1);
	346	if (status & AR_FrmXmitOK)
b622a720	347	ts->ts_status \|= ATH9K_TX_ACKED;
ff32d9cd FF	348	else {
	349	if (status & AR_ExcessiveRetries)
	350	ts->ts_status \|= ATH9K_TXERR_XRETRY;
	351	if (status & AR_Filtered)
	352	ts->ts_status \|= ATH9K_TXERR_FILT;
	353	if (status & AR_FIFOUnderrun) {
	354	ts->ts_status \|= ATH9K_TXERR_FIFO;
	355	ath9k_hw_updatetxtriglevel(ah, true);
	356	}
b622a720	357	}
e0e9bc82	358	if (status & AR_TxTimerExpired)
b622a720	359	ts->ts_status \|= ATH9K_TXERR_TIMER_EXPIRED;
e0e9bc82	360	if (status & AR_DescCfgErr)
b622a720	361	ts->ts_flags \|= ATH9K_TX_DESC_CFG_ERR;
e0e9bc82	362	if (status & AR_TxDataUnderrun) {
b622a720 LR	363	ts->ts_flags \|= ATH9K_TX_DATA_UNDERRUN;
	364	ath9k_hw_updatetxtriglevel(ah, true);
	365	}
e0e9bc82	366	if (status & AR_TxDelimUnderrun) {
b622a720 LR	367	ts->ts_flags \|= ATH9K_TX_DELIM_UNDERRUN;
	368	ath9k_hw_updatetxtriglevel(ah, true);
	369	}
e0e9bc82 FF	370	ts->ts_shortretry = MS(status, AR_RTSFailCnt);
	371	ts->ts_longretry = MS(status, AR_DataFailCnt);
	372	ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
b622a720	373
e0e9bc82 FF	374	status = ACCESS_ONCE(ads->ds_txstatus5);
	375	ts->ts_rssi = MS(status, AR_TxRSSICombined);
	376	ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
	377	ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
	378	ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
b622a720	379
b622a720 LR	380	ts->evm0 = ads->AR_TxEVM0;
	381	ts->evm1 = ads->AR_TxEVM1;
	382	ts->evm2 = ads->AR_TxEVM2;
b622a720 LR	383
	384	return 0;
	385	}
	386
315dd114 FF	387	static int ar9002_hw_get_duration(struct ath_hw ah, const void ds, int index)
	388	{
	389	struct ar5416_desc *ads = AR5416DESC(ds);
	390
	391	switch (index) {
	392	case 0:
	393	return MS(ACCESS_ONCE(ads->ds_ctl4), AR_PacketDur0);
	394	case 1:
	395	return MS(ACCESS_ONCE(ads->ds_ctl4), AR_PacketDur1);
	396	case 2:
	397	return MS(ACCESS_ONCE(ads->ds_ctl5), AR_PacketDur2);
	398	case 3:
	399	return MS(ACCESS_ONCE(ads->ds_ctl5), AR_PacketDur3);
	400	default:
	401	return -1;
	402	}
	403	}
	404
b622a720 LR	405	void ath9k_hw_setuprxdesc(struct ath_hw ah, struct ath_desc ds,
	406	u32 size, u32 flags)
	407	{
	408	struct ar5416_desc *ads = AR5416DESC(ds);
b622a720 LR	409
	410	ads->ds_ctl1 = size & AR_BufLen;
	411	if (flags & ATH9K_RXDESC_INTREQ)
	412	ads->ds_ctl1 \|= AR_RxIntrReq;
	413
aebc0a88	414	memset(&ads->u.rx, 0, sizeof(ads->u.rx));
b622a720 LR	415	}
	416	EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
	417
	418	void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
	419	{
	420	struct ath_hw_ops *ops = ath9k_hw_ops(ah);
	421
	422	ops->rx_enable = ar9002_hw_rx_enable;
	423	ops->set_desc_link = ar9002_hw_set_desc_link;
b622a720	424	ops->get_isr = ar9002_hw_get_isr;
2b63a41d	425	ops->set_txdesc = ar9002_set_txdesc;
b622a720	426	ops->proc_txdesc = ar9002_hw_proc_txdesc;
315dd114	427	ops->get_duration = ar9002_hw_get_duration;
b622a720	428	}