[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9002_phy.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/**
 * DOC: Programming Atheros 802.11n analog front end radios
 *
 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
 * devices have either an external AR2133 analog front end radio for single
 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
 * band 2.4 GHz / 5 GHz communication.
 *
 * All devices after the AR5416 and AR5418 family starting with the AR9280
 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
 * into a single-chip and require less programming.
 *
 * The following single-chips exist with a respective embedded radio:
 *
 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
 * AR9281 - 11n single-band 1x2 MIMO for PCIe
 * AR9285 - 11n single-band 1x1 for PCIe
 * AR9287 - 11n single-band 2x2 MIMO for PCIe
 *
 * AR9220 - 11n dual-band 2x2 MIMO for PCI
 * AR9223 - 11n single-band 2x2 MIMO for PCI
 *
 * AR9287 - 11n single-band 1x1 MIMO for USB
 */

#include "hw.h"
#include "ar9002_phy.h"

/**
 * ar9002_hw_set_channel - set channel on single-chip device
 * @ah: atheros hardware structure
 * @chan:
 *
 * This is the function to change channel on single-chip devices, that is
 * all devices after ar9280.
 *
 * This function takes the channel value in MHz and sets
 * hardware channel value. Assumes writes have been enabled to analog bus.
 *
 * Actual Expression,
 *
 * For 2GHz channel,
 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
 * (freq_ref = 40MHz)
 *
 * For 5GHz channel,
 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
 * (freq_ref = 40MHz/(24>>amodeRefSel))
 */
static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
{
	u16 bMode, fracMode, aModeRefSel = 0;
	u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
	struct chan_centers centers;
	u32 refDivA = 24;

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	freq = centers.synth_center;

	reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
	reg32 &= 0xc0000000;

	if (freq < 4800) { /* 2 GHz, fractional mode */
		u32 txctl;
		int regWrites = 0;

		bMode = 1;
		fracMode = 1;
		aModeRefSel = 0;
		channelSel = CHANSEL_2G(freq);

		if (AR_SREV_9287_11_OR_LATER(ah)) {
			if (freq == 2484) {
				/* Enable channel spreading for channel 14 */
				REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
						1, regWrites);
			} else {
				REG_WRITE_ARRAY(&ah->iniCckfirNormal,
						1, regWrites);
			}
		} else {
			txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
			if (freq == 2484) {
				/* Enable channel spreading for channel 14 */
				REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
					  txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
			} else {
				REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
					  txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
			}
		}
	} else {
		bMode = 0;
		fracMode = 0;

		switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
		case 0:
			if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
				aModeRefSel = 0;
			else if ((freq % 20) == 0)
				aModeRefSel = 3;
			else if ((freq % 10) == 0)
				aModeRefSel = 2;
			if (aModeRefSel)
				break;
		case 1:
		default:
			aModeRefSel = 0;
			/*
			 * Enable 2G (fractional) mode for channels
			 * which are 5MHz spaced.
			 */
			fracMode = 1;
			refDivA = 1;
			channelSel = CHANSEL_5G(freq);

			/* RefDivA setting */
			REG_RMW_FIELD(ah, AR_AN_SYNTH9,
				      AR_AN_SYNTH9_REFDIVA, refDivA);

		}

		if (!fracMode) {
			ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
			channelSel = ndiv & 0x1ff;
			channelFrac = (ndiv & 0xfffffe00) * 2;
			channelSel = (channelSel << 17) | channelFrac;
		}
	}

	reg32 = reg32 |
	    (bMode << 29) |
	    (fracMode << 28) | (aModeRefSel << 26) | (channelSel);

	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);

	ah->curchan = chan;
	ah->curchan_rad_index = -1;

	return 0;
}

/**
 * ar9002_hw_spur_mitigate - convert baseband spur frequency
 * @ah: atheros hardware structure
 * @chan:
 *
 * For single-chip solutions. Converts to baseband spur frequency given the
 * input channel frequency and compute register settings below.
 */
static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
				    struct ath9k_channel *chan)
{
	int bb_spur = AR_NO_SPUR;
	int freq;
	int bin, cur_bin;
	int bb_spur_off, spur_subchannel_sd;
	int spur_freq_sd;
	int spur_delta_phase;
	int denominator;
	int upper, lower, cur_vit_mask;
	int tmp, newVal;
	int i;
	static const int pilot_mask_reg[4] = {
		AR_PHY_TIMING7, AR_PHY_TIMING8,
		AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
	};
	static const int chan_mask_reg[4] = {
		AR_PHY_TIMING9, AR_PHY_TIMING10,
		AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
	};
	static const int inc[4] = { 0, 100, 0, 0 };
	struct chan_centers centers;

	int8_t mask_m[123];
	int8_t mask_p[123];
	int8_t mask_amt;
	int tmp_mask;
	int cur_bb_spur;
	bool is2GHz = IS_CHAN_2GHZ(chan);

	memset(&mask_m, 0, sizeof(int8_t) * 123);
	memset(&mask_p, 0, sizeof(int8_t) * 123);

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	freq = centers.synth_center;

	ah->config.spurmode = SPUR_ENABLE_EEPROM;
	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);

		if (AR_NO_SPUR == cur_bb_spur)
			break;

		if (is2GHz)
			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
		else
			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;

		cur_bb_spur = cur_bb_spur - freq;

		if (IS_CHAN_HT40(chan)) {
			if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
			    (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
				bb_spur = cur_bb_spur;
				break;
			}
		} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
			   (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
			bb_spur = cur_bb_spur;
			break;
		}
	}

	if (AR_NO_SPUR == bb_spur) {
		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
		return;
	} else {
		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
	}

	bin = bb_spur * 320;

	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

	ENABLE_REGWRITE_BUFFER(ah);

	newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
			AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
			AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
			AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);

	newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
		  AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
		  AR_PHY_SPUR_REG_MASK_RATE_SELECT |
		  AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
		  SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);

	if (IS_CHAN_HT40(chan)) {
		if (bb_spur < 0) {
			spur_subchannel_sd = 1;
			bb_spur_off = bb_spur + 10;
		} else {
			spur_subchannel_sd = 0;
			bb_spur_off = bb_spur - 10;
		}
	} else {
		spur_subchannel_sd = 0;
		bb_spur_off = bb_spur;
	}

	if (IS_CHAN_HT40(chan))
		spur_delta_phase =
			((bb_spur * 262144) /
			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
	else
		spur_delta_phase =
			((bb_spur * 524288) /
			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;

	denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
	spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;

	newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
		  SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
		  SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
	REG_WRITE(ah, AR_PHY_TIMING11, newVal);

	newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);

	cur_bin = -6000;
	upper = bin + 100;
	lower = bin - 100;

	for (i = 0; i < 4; i++) {
		int pilot_mask = 0;
		int chan_mask = 0;
		int bp = 0;
		for (bp = 0; bp < 30; bp++) {
			if ((cur_bin > lower) && (cur_bin < upper)) {
				pilot_mask = pilot_mask | 0x1 << bp;
				chan_mask = chan_mask | 0x1 << bp;
			}
			cur_bin += 100;
		}
		cur_bin += inc[i];
		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
		REG_WRITE(ah, chan_mask_reg[i], chan_mask);
	}

	cur_vit_mask = 6100;
	upper = bin + 120;
	lower = bin - 120;

	for (i = 0; i < 123; i++) {
		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {

			/* workaround for gcc bug #37014 */
			volatile int tmp_v = abs(cur_vit_mask - bin);

			if (tmp_v < 75)
				mask_amt = 1;
			else
				mask_amt = 0;
			if (cur_vit_mask < 0)
				mask_m[abs(cur_vit_mask / 100)] = mask_amt;
			else
				mask_p[cur_vit_mask / 100] = mask_amt;
		}
		cur_vit_mask -= 100;
	}

	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
		| (mask_m[48] << 26) | (mask_m[49] << 24)
		| (mask_m[50] << 22) | (mask_m[51] << 20)
		| (mask_m[52] << 18) | (mask_m[53] << 16)
		| (mask_m[54] << 14) | (mask_m[55] << 12)
		| (mask_m[56] << 10) | (mask_m[57] << 8)
		| (mask_m[58] << 6) | (mask_m[59] << 4)
		| (mask_m[60] << 2) | (mask_m[61] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);

	tmp_mask = (mask_m[31] << 28)
		| (mask_m[32] << 26) | (mask_m[33] << 24)
		| (mask_m[34] << 22) | (mask_m[35] << 20)
		| (mask_m[36] << 18) | (mask_m[37] << 16)
		| (mask_m[48] << 14) | (mask_m[39] << 12)
		| (mask_m[40] << 10) | (mask_m[41] << 8)
		| (mask_m[42] << 6) | (mask_m[43] << 4)
		| (mask_m[44] << 2) | (mask_m[45] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);

	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
		| (mask_m[18] << 26) | (mask_m[18] << 24)
		| (mask_m[20] << 22) | (mask_m[20] << 20)
		| (mask_m[22] << 18) | (mask_m[22] << 16)
		| (mask_m[24] << 14) | (mask_m[24] << 12)
		| (mask_m[25] << 10) | (mask_m[26] << 8)
		| (mask_m[27] << 6) | (mask_m[28] << 4)
		| (mask_m[29] << 2) | (mask_m[30] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);

	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
		| (mask_m[2] << 26) | (mask_m[3] << 24)
		| (mask_m[4] << 22) | (mask_m[5] << 20)
		| (mask_m[6] << 18) | (mask_m[7] << 16)
		| (mask_m[8] << 14) | (mask_m[9] << 12)
		| (mask_m[10] << 10) | (mask_m[11] << 8)
		| (mask_m[12] << 6) | (mask_m[13] << 4)
		| (mask_m[14] << 2) | (mask_m[15] << 0);
	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);

	tmp_mask = (mask_p[15] << 28)
		| (mask_p[14] << 26) | (mask_p[13] << 24)
		| (mask_p[12] << 22) | (mask_p[11] << 20)
		| (mask_p[10] << 18) | (mask_p[9] << 16)
		| (mask_p[8] << 14) | (mask_p[7] << 12)
		| (mask_p[6] << 10) | (mask_p[5] << 8)
		| (mask_p[4] << 6) | (mask_p[3] << 4)
		| (mask_p[2] << 2) | (mask_p[1] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);

	tmp_mask = (mask_p[30] << 28)
		| (mask_p[29] << 26) | (mask_p[28] << 24)
		| (mask_p[27] << 22) | (mask_p[26] << 20)
		| (mask_p[25] << 18) | (mask_p[24] << 16)
		| (mask_p[23] << 14) | (mask_p[22] << 12)
		| (mask_p[21] << 10) | (mask_p[20] << 8)
		| (mask_p[19] << 6) | (mask_p[18] << 4)
		| (mask_p[17] << 2) | (mask_p[16] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);

	tmp_mask = (mask_p[45] << 28)
		| (mask_p[44] << 26) | (mask_p[43] << 24)
		| (mask_p[42] << 22) | (mask_p[41] << 20)
		| (mask_p[40] << 18) | (mask_p[39] << 16)
		| (mask_p[38] << 14) | (mask_p[37] << 12)
		| (mask_p[36] << 10) | (mask_p[35] << 8)
		| (mask_p[34] << 6) | (mask_p[33] << 4)
		| (mask_p[32] << 2) | (mask_p[31] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);

	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
		| (mask_p[59] << 26) | (mask_p[58] << 24)
		| (mask_p[57] << 22) | (mask_p[56] << 20)
		| (mask_p[55] << 18) | (mask_p[54] << 16)
		| (mask_p[53] << 14) | (mask_p[52] << 12)
		| (mask_p[51] << 10) | (mask_p[50] << 8)
		| (mask_p[49] << 6) | (mask_p[48] << 4)
		| (mask_p[47] << 2) | (mask_p[46] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);

	REGWRITE_BUFFER_FLUSH(ah);
}

static void ar9002_olc_init(struct ath_hw *ah)
{
	u32 i;

	if (!OLC_FOR_AR9280_20_LATER)
		return;

	if (OLC_FOR_AR9287_10_LATER) {
		REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
				AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
		ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
				AR9287_AN_TXPC0_TXPCMODE,
				AR9287_AN_TXPC0_TXPCMODE_S,
				AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
		udelay(100);
	} else {
		for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
			ah->originalGain[i] =
				MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
						AR_PHY_TX_GAIN);
		ah->PDADCdelta = 0;
	}
}

static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
					 struct ath9k_channel *chan)
{
	int ref_div = 5;
	int pll_div = 0x2c;
	u32 pll;

	if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
		if (AR_SREV_9280_20(ah)) {
			ref_div = 10;
			pll_div = 0x50;
		} else {
			pll_div = 0x28;
		}
	}

	pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
	pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);

	if (chan && IS_CHAN_HALF_RATE(chan))
		pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
	else if (chan && IS_CHAN_QUARTER_RATE(chan))
		pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);

	return pll;
}

static void ar9002_hw_do_getnf(struct ath_hw *ah,
			      int16_t nfarray[NUM_NF_READINGS])
{
	int16_t nf;

	nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
	nfarray[0] = sign_extend32(nf, 8);

	nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
	if (IS_CHAN_HT40(ah->curchan))
		nfarray[3] = sign_extend32(nf, 8);

	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		return;

	nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
	nfarray[1] = sign_extend32(nf, 8);

	nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
	if (IS_CHAN_HT40(ah->curchan))
		nfarray[4] = sign_extend32(nf, 8);
}

static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
{
	if (AR_SREV_9285(ah)) {
		ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
	} else if (AR_SREV_9287(ah)) {
		ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
	} else if (AR_SREV_9271(ah)) {
		ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
	} else {
		ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
		ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
		ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
		ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
	}
}

static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
				   struct ath_hw_antcomb_conf *antconf)
{
	u32 regval;

	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
	antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
				  AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
	antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
				 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
	antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
				  AR_PHY_9285_FAST_DIV_BIAS_S;
	antconf->lna1_lna2_delta = -3;
	antconf->div_group = 0;
}

static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
				   struct ath_hw_antcomb_conf *antconf)
{
	u32 regval;

	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
	regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
		    AR_PHY_9285_ANT_DIV_ALT_LNACONF |
		    AR_PHY_9285_FAST_DIV_BIAS);
	regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
		   & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
	regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
		   & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
	regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
		   & AR_PHY_9285_FAST_DIV_BIAS);

	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
}

void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
{
	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
	struct ath_hw_ops *ops = ath9k_hw_ops(ah);

	priv_ops->set_rf_regs = NULL;
	priv_ops->rf_alloc_ext_banks = NULL;
	priv_ops->rf_free_ext_banks = NULL;
	priv_ops->rf_set_freq = ar9002_hw_set_channel;
	priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
	priv_ops->olc_init = ar9002_olc_init;
	priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
	priv_ops->do_getnf = ar9002_hw_do_getnf;

	ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get;
	ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set;

	ar9002_hw_set_nf_limits(ah);
}
Commit	Line	Data
8fe65368	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
8fe65368 LR	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	/**
	18	* DOC: Programming Atheros 802.11n analog front end radios
	19	*
	20	* AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
	21	* devices have either an external AR2133 analog front end radio for single
	22	* band 2.4 GHz communication or an AR5133 analog front end radio for dual
	23	* band 2.4 GHz / 5 GHz communication.
	24	*
	25	* All devices after the AR5416 and AR5418 family starting with the AR9280
	26	* have their analog front radios, MAC/BB and host PCIe/USB interface embedded
	27	* into a single-chip and require less programming.
	28	*
	29	* The following single-chips exist with a respective embedded radio:
	30	*
	31	* AR9280 - 11n dual-band 2x2 MIMO for PCIe
	32	* AR9281 - 11n single-band 1x2 MIMO for PCIe
	33	* AR9285 - 11n single-band 1x1 for PCIe
	34	* AR9287 - 11n single-band 2x2 MIMO for PCIe
	35	*
	36	* AR9220 - 11n dual-band 2x2 MIMO for PCI
	37	* AR9223 - 11n single-band 2x2 MIMO for PCI
	38	*
	39	* AR9287 - 11n single-band 1x1 MIMO for USB
	40	*/
	41
	42	#include "hw.h"
	43	#include "ar9002_phy.h"
	44
	45	/**
	46	* ar9002_hw_set_channel - set channel on single-chip device
	47	* @ah: atheros hardware structure
	48	* @chan:
	49	*
	50	* This is the function to change channel on single-chip devices, that is
	51	* all devices after ar9280.
	52	*
	53	* This function takes the channel value in MHz and sets
	54	* hardware channel value. Assumes writes have been enabled to analog bus.
	55	*
	56	* Actual Expression,
	57	*
	58	* For 2GHz channel,
	59	* Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
	60	* (freq_ref = 40MHz)
	61	*
	62	* For 5GHz channel,
	63	* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
	64	* (freq_ref = 40MHz/(24>>amodeRefSel))
	65	*/
	66	static int ar9002_hw_set_channel(struct ath_hw ah, struct ath9k_channel chan)
67	{
68	u16 bMode, fracMode, aModeRefSel = 0;
69	u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
70	struct chan_centers centers;
71	u32 refDivA = 24;
72
73	ath9k_hw_get_channel_centers(ah, chan, &centers);
74	freq = centers.synth_center;
75
76	reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
77	reg32 &= 0xc0000000;
78
79	if (freq < 4800) { /* 2 GHz, fractional mode */
80	u32 txctl;
81	int regWrites = 0;
82
83	bMode = 1;
84	fracMode = 1;
85	aModeRefSel = 0;
7152451a	86	channelSel = CHANSEL_2G(freq);
8fe65368 LR	87
	88	if (AR_SREV_9287_11_OR_LATER(ah)) {
	89	if (freq == 2484) {
	90	/* Enable channel spreading for channel 14 */
	91	REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
	92	1, regWrites);
	93	} else {
	94	REG_WRITE_ARRAY(&ah->iniCckfirNormal,
	95	1, regWrites);
	96	}
	97	} else {
	98	txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
	99	if (freq == 2484) {
	100	/* Enable channel spreading for channel 14 */
	101	REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
	102	txctl \| AR_PHY_CCK_TX_CTRL_JAPAN);
	103	} else {
	104	REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
	105	txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
	106	}
	107	}
	108	} else {
	109	bMode = 0;
	110	fracMode = 0;
	111
	112	switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
	113	case 0:
0407cf1c FF	114	if (IS_CHAN_HALF_RATE(chan) \|\| IS_CHAN_QUARTER_RATE(chan))
	115	aModeRefSel = 0;
	116	else if ((freq % 20) == 0)
8fe65368 LR	117	aModeRefSel = 3;
	118	else if ((freq % 10) == 0)
	119	aModeRefSel = 2;
	120	if (aModeRefSel)
	121	break;
	122	case 1:
	123	default:
	124	aModeRefSel = 0;
	125	/*
	126	* Enable 2G (fractional) mode for channels
	127	* which are 5MHz spaced.
	128	*/
	129	fracMode = 1;
	130	refDivA = 1;
7152451a	131	channelSel = CHANSEL_5G(freq);
8fe65368 LR	132
	133	/* RefDivA setting */
	134	REG_RMW_FIELD(ah, AR_AN_SYNTH9,
	135	AR_AN_SYNTH9_REFDIVA, refDivA);
	136
	137	}
	138
	139	if (!fracMode) {
	140	ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
	141	channelSel = ndiv & 0x1ff;
	142	channelFrac = (ndiv & 0xfffffe00) * 2;
	143	channelSel = (channelSel << 17) \| channelFrac;
	144	}
	145	}
	146
	147	reg32 = reg32 \|
	148	(bMode << 29) \|
	149	(fracMode << 28) \| (aModeRefSel << 26) \| (channelSel);
	150
	151	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
	152
	153	ah->curchan = chan;
	154	ah->curchan_rad_index = -1;
	155
	156	return 0;
	157	}
	158
	159	/**
	160	* ar9002_hw_spur_mitigate - convert baseband spur frequency
	161	* @ah: atheros hardware structure
	162	* @chan:
	163	*
	164	* For single-chip solutions. Converts to baseband spur frequency given the
	165	* input channel frequency and compute register settings below.
	166	*/
	167	static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
	168	struct ath9k_channel *chan)
	169	{
	170	int bb_spur = AR_NO_SPUR;
	171	int freq;
	172	int bin, cur_bin;
	173	int bb_spur_off, spur_subchannel_sd;
	174	int spur_freq_sd;
	175	int spur_delta_phase;
	176	int denominator;
	177	int upper, lower, cur_vit_mask;
	178	int tmp, newVal;
	179	int i;
07b2fa5a JP	180	static const int pilot_mask_reg[4] = {
	181	AR_PHY_TIMING7, AR_PHY_TIMING8,
	182	AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
8fe65368	183	};
07b2fa5a JP	184	static const int chan_mask_reg[4] = {
	185	AR_PHY_TIMING9, AR_PHY_TIMING10,
	186	AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
8fe65368	187	};
07b2fa5a	188	static const int inc[4] = { 0, 100, 0, 0 };
8fe65368 LR	189	struct chan_centers centers;
	190
	191	int8_t mask_m[123];
	192	int8_t mask_p[123];
	193	int8_t mask_amt;
	194	int tmp_mask;
	195	int cur_bb_spur;
	196	bool is2GHz = IS_CHAN_2GHZ(chan);
	197
	198	memset(&mask_m, 0, sizeof(int8_t) * 123);
	199	memset(&mask_p, 0, sizeof(int8_t) * 123);
	200
	201	ath9k_hw_get_channel_centers(ah, chan, &centers);
	202	freq = centers.synth_center;
	203
	204	ah->config.spurmode = SPUR_ENABLE_EEPROM;
	205	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
	206	cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
	207
44cefead BP	208	if (AR_NO_SPUR == cur_bb_spur)
	209	break;
	210
8fe65368 LR	211	if (is2GHz)
	212	cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
	213	else
	214	cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
	215
8fe65368 LR	216	cur_bb_spur = cur_bb_spur - freq;
	217
	218	if (IS_CHAN_HT40(chan)) {
	219	if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
	220	(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
	221	bb_spur = cur_bb_spur;
	222	break;
	223	}
	224	} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
	225	(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
	226	bb_spur = cur_bb_spur;
	227	break;
	228	}
	229	}
	230
	231	if (AR_NO_SPUR == bb_spur) {
	232	REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
	233	AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
	234	return;
	235	} else {
	236	REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
	237	AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
	238	}
	239
	240	bin = bb_spur * 320;
	241
	242	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
	243
7d0d0df0 S	244	ENABLE_REGWRITE_BUFFER(ah);
7d0d0df0 S	245
8fe65368 LR	246	newVal = tmp \| (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI \|
	247	AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER \|
	248	AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK \|
	249	AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
	250	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
	251
	252	newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL \|
	253	AR_PHY_SPUR_REG_ENABLE_MASK_PPM \|
	254	AR_PHY_SPUR_REG_MASK_RATE_SELECT \|
	255	AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI \|
	256	SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
	257	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
	258
	259	if (IS_CHAN_HT40(chan)) {
	260	if (bb_spur < 0) {
	261	spur_subchannel_sd = 1;
	262	bb_spur_off = bb_spur + 10;
	263	} else {
	264	spur_subchannel_sd = 0;
	265	bb_spur_off = bb_spur - 10;
	266	}
	267	} else {
	268	spur_subchannel_sd = 0;
	269	bb_spur_off = bb_spur;
	270	}
	271
	272	if (IS_CHAN_HT40(chan))
	273	spur_delta_phase =
	274	((bb_spur * 262144) /
	275	10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
	276	else
	277	spur_delta_phase =
	278	((bb_spur * 524288) /
	279	10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
	280
	281	denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
	282	spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
	283
	284	newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC \|
	285	SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) \|
	286	SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
	287	REG_WRITE(ah, AR_PHY_TIMING11, newVal);
	288
	289	newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
	290	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
	291
	292	cur_bin = -6000;
	293	upper = bin + 100;
	294	lower = bin - 100;
	295
	296	for (i = 0; i < 4; i++) {
	297	int pilot_mask = 0;
	298	int chan_mask = 0;
	299	int bp = 0;
	300	for (bp = 0; bp < 30; bp++) {
	301	if ((cur_bin > lower) && (cur_bin < upper)) {
	302	pilot_mask = pilot_mask \| 0x1 << bp;
	303	chan_mask = chan_mask \| 0x1 << bp;
	304	}
	305	cur_bin += 100;
	306	}
	307	cur_bin += inc[i];
	308	REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
	309	REG_WRITE(ah, chan_mask_reg[i], chan_mask);
310	}
311
312	cur_vit_mask = 6100;
313	upper = bin + 120;
314	lower = bin - 120;
315
316	for (i = 0; i < 123; i++) {
317	if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
318
319	/* workaround for gcc bug #37014 */
320	volatile int tmp_v = abs(cur_vit_mask - bin);
321
322	if (tmp_v < 75)
323	mask_amt = 1;
324	else
325	mask_amt = 0;
326	if (cur_vit_mask < 0)
327	mask_m[abs(cur_vit_mask / 100)] = mask_amt;
328	else
329	mask_p[cur_vit_mask / 100] = mask_amt;
330	}
331	cur_vit_mask -= 100;
332	}
333
334	tmp_mask = (mask_m[46] << 30) \| (mask_m[47] << 28)
335	\| (mask_m[48] << 26) \| (mask_m[49] << 24)
336	\| (mask_m[50] << 22) \| (mask_m[51] << 20)
337	\| (mask_m[52] << 18) \| (mask_m[53] << 16)
338	\| (mask_m[54] << 14) \| (mask_m[55] << 12)
339	\| (mask_m[56] << 10) \| (mask_m[57] << 8)
340	\| (mask_m[58] << 6) \| (mask_m[59] << 4)
341	\| (mask_m[60] << 2) \| (mask_m[61] << 0);
342	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
343	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
344
345	tmp_mask = (mask_m[31] << 28)
346	\| (mask_m[32] << 26) \| (mask_m[33] << 24)
347	\| (mask_m[34] << 22) \| (mask_m[35] << 20)
348	\| (mask_m[36] << 18) \| (mask_m[37] << 16)
349	\| (mask_m[48] << 14) \| (mask_m[39] << 12)
350	\| (mask_m[40] << 10) \| (mask_m[41] << 8)
351	\| (mask_m[42] << 6) \| (mask_m[43] << 4)
352	\| (mask_m[44] << 2) \| (mask_m[45] << 0);
353	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
354	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
355
356	tmp_mask = (mask_m[16] << 30) \| (mask_m[16] << 28)
357	\| (mask_m[18] << 26) \| (mask_m[18] << 24)
358	\| (mask_m[20] << 22) \| (mask_m[20] << 20)
359	\| (mask_m[22] << 18) \| (mask_m[22] << 16)
360	\| (mask_m[24] << 14) \| (mask_m[24] << 12)
361	\| (mask_m[25] << 10) \| (mask_m[26] << 8)
362	\| (mask_m[27] << 6) \| (mask_m[28] << 4)
363	\| (mask_m[29] << 2) \| (mask_m[30] << 0);
364	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
365	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
366
367	tmp_mask = (mask_m[0] << 30) \| (mask_m[1] << 28)
368	\| (mask_m[2] << 26) \| (mask_m[3] << 24)
369	\| (mask_m[4] << 22) \| (mask_m[5] << 20)
370	\| (mask_m[6] << 18) \| (mask_m[7] << 16)
371	\| (mask_m[8] << 14) \| (mask_m[9] << 12)
372	\| (mask_m[10] << 10) \| (mask_m[11] << 8)
373	\| (mask_m[12] << 6) \| (mask_m[13] << 4)
374	\| (mask_m[14] << 2) \| (mask_m[15] << 0);
375	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
376	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
377
378	tmp_mask = (mask_p[15] << 28)
379	\| (mask_p[14] << 26) \| (mask_p[13] << 24)
380	\| (mask_p[12] << 22) \| (mask_p[11] << 20)
381	\| (mask_p[10] << 18) \| (mask_p[9] << 16)
382	\| (mask_p[8] << 14) \| (mask_p[7] << 12)
383	\| (mask_p[6] << 10) \| (mask_p[5] << 8)
384	\| (mask_p[4] << 6) \| (mask_p[3] << 4)
385	\| (mask_p[2] << 2) \| (mask_p[1] << 0);
386	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
387	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
388
389	tmp_mask = (mask_p[30] << 28)
390	\| (mask_p[29] << 26) \| (mask_p[28] << 24)
391	\| (mask_p[27] << 22) \| (mask_p[26] << 20)
392	\| (mask_p[25] << 18) \| (mask_p[24] << 16)
393	\| (mask_p[23] << 14) \| (mask_p[22] << 12)
394	\| (mask_p[21] << 10) \| (mask_p[20] << 8)
395	\| (mask_p[19] << 6) \| (mask_p[18] << 4)
396	\| (mask_p[17] << 2) \| (mask_p[16] << 0);
397	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
398	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
399
400	tmp_mask = (mask_p[45] << 28)
401	\| (mask_p[44] << 26) \| (mask_p[43] << 24)
402	\| (mask_p[42] << 22) \| (mask_p[41] << 20)
403	\| (mask_p[40] << 18) \| (mask_p[39] << 16)
404	\| (mask_p[38] << 14) \| (mask_p[37] << 12)
405	\| (mask_p[36] << 10) \| (mask_p[35] << 8)
406	\| (mask_p[34] << 6) \| (mask_p[33] << 4)
407	\| (mask_p[32] << 2) \| (mask_p[31] << 0);
408	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
409	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
410
411	tmp_mask = (mask_p[61] << 30) \| (mask_p[60] << 28)
412	\| (mask_p[59] << 26) \| (mask_p[58] << 24)
413	\| (mask_p[57] << 22) \| (mask_p[56] << 20)
414	\| (mask_p[55] << 18) \| (mask_p[54] << 16)
415	\| (mask_p[53] << 14) \| (mask_p[52] << 12)
416	\| (mask_p[51] << 10) \| (mask_p[50] << 8)
417	\| (mask_p[49] << 6) \| (mask_p[48] << 4)
418	\| (mask_p[47] << 2) \| (mask_p[46] << 0);
419	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
420	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
7d0d0df0 S	421
7d0d0df0 S	422	REGWRITE_BUFFER_FLUSH(ah);
8fe65368 LR	423	}
	424
	425	static void ar9002_olc_init(struct ath_hw *ah)
	426	{
	427	u32 i;
	428
	429	if (!OLC_FOR_AR9280_20_LATER)
	430	return;
	431
	432	if (OLC_FOR_AR9287_10_LATER) {
	433	REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
	434	AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
	435	ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
	436	AR9287_AN_TXPC0_TXPCMODE,
	437	AR9287_AN_TXPC0_TXPCMODE_S,
	438	AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
	439	udelay(100);
	440	} else {
	441	for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
	442	ah->originalGain[i] =
	443	MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
	444	AR_PHY_TX_GAIN);
	445	ah->PDADCdelta = 0;
	446	}
	447	}
	448
64773964 LR	449	static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
	450	struct ath9k_channel *chan)
	451	{
804f6acb FF	452	int ref_div = 5;
804f6acb FF	453	int pll_div = 0x2c;
64773964 LR	454	u32 pll;
64773964 LR	455
804f6acb FF	456	if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
	457	if (AR_SREV_9280_20(ah)) {
	458	ref_div = 10;
	459	pll_div = 0x50;
	460	} else {
	461	pll_div = 0x28;
	462	}
	463	}
	464
	465	pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
	466	pll \|= SM(pll_div, AR_RTC_9160_PLL_DIV);
64773964 LR	467
	468	if (chan && IS_CHAN_HALF_RATE(chan))
	469	pll \|= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
	470	else if (chan && IS_CHAN_QUARTER_RATE(chan))
	471	pll \|= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
	472
64773964 LR	473	return pll;
	474	}
	475
641d9921 FF	476	static void ar9002_hw_do_getnf(struct ath_hw *ah,
	477	int16_t nfarray[NUM_NF_READINGS])
	478	{
641d9921 FF	479	int16_t nf;
	480
	481	nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
7919a57b	482	nfarray[0] = sign_extend32(nf, 8);
641d9921	483
54bd5006	484	nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
866b7780	485	if (IS_CHAN_HT40(ah->curchan))
7919a57b	486	nfarray[3] = sign_extend32(nf, 8);
641d9921	487
54bd5006 FF	488	if (AR_SREV_9285(ah) \|\| AR_SREV_9271(ah))
54bd5006 FF	489	return;
641d9921	490
54bd5006	491	nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
7919a57b	492	nfarray[1] = sign_extend32(nf, 8);
641d9921	493
54bd5006	494	nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
866b7780	495	if (IS_CHAN_HT40(ah->curchan))
7919a57b	496	nfarray[4] = sign_extend32(nf, 8);
641d9921 FF	497	}
641d9921 FF	498
f2552e28 FF	499	static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
	500	{
	501	if (AR_SREV_9285(ah)) {
	502	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
	503	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
	504	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
	505	} else if (AR_SREV_9287(ah)) {
	506	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
	507	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
	508	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
	509	} else if (AR_SREV_9271(ah)) {
	510	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
	511	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
	512	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
	513	} else {
	514	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
	515	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
	516	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
	517	ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
	518	ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
	519	ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
	520	}
	521	}
	522
69de3721	523	static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
21cc630f VT	524	struct ath_hw_antcomb_conf *antconf)
	525	{
	526	u32 regval;
	527
	528	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
	529	antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
	530	AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
	531	antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
	532	AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
	533	antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
	534	AR_PHY_9285_FAST_DIV_BIAS_S;
8afbcc8b MSS	535	antconf->lna1_lna2_delta = -3;
8afbcc8b MSS	536	antconf->div_group = 0;
21cc630f	537	}
21cc630f	538
69de3721	539	static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
21cc630f VT	540	struct ath_hw_antcomb_conf *antconf)
	541	{
	542	u32 regval;
	543
	544	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
	545	regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF \|
	546	AR_PHY_9285_ANT_DIV_ALT_LNACONF \|
	547	AR_PHY_9285_FAST_DIV_BIAS);
	548	regval \|= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
	549	& AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
	550	regval \|= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
	551	& AR_PHY_9285_ANT_DIV_ALT_LNACONF);
	552	regval \|= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
	553	& AR_PHY_9285_FAST_DIV_BIAS);
	554
	555	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
	556	}
69de3721 MSS	557
	558	void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
	559	{
	560	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
	561	struct ath_hw_ops *ops = ath9k_hw_ops(ah);
	562
	563	priv_ops->set_rf_regs = NULL;
	564	priv_ops->rf_alloc_ext_banks = NULL;
	565	priv_ops->rf_free_ext_banks = NULL;
	566	priv_ops->rf_set_freq = ar9002_hw_set_channel;
	567	priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
	568	priv_ops->olc_init = ar9002_olc_init;
	569	priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
	570	priv_ops->do_getnf = ar9002_hw_do_getnf;
	571
	572	ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get;
	573	ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set;
	574
	575	ar9002_hw_set_nf_limits(ah);
	576	}