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15c9ee7a | 1 | /* |
5b68138e | 2 | * Copyright (c) 2010-2011 Atheros Communications Inc. |
15c9ee7a SB |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
78fa99ab | 17 | #include <asm/unaligned.h> |
15c9ee7a SB |
18 | #include "hw.h" |
19 | #include "ar9003_phy.h" | |
20 | #include "ar9003_eeprom.h" | |
e82cb03f | 21 | #include "ar9003_mci.h" |
15c9ee7a SB |
22 | |
23 | #define COMP_HDR_LEN 4 | |
24 | #define COMP_CKSUM_LEN 2 | |
25 | ||
ffdc4cbe FF |
26 | #define LE16(x) __constant_cpu_to_le16(x) |
27 | #define LE32(x) __constant_cpu_to_le32(x) | |
28 | ||
824b185a LR |
29 | /* Local defines to distinguish between extension and control CTL's */ |
30 | #define EXT_ADDITIVE (0x8000) | |
31 | #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) | |
32 | #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) | |
33 | #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) | |
824b185a LR |
34 | |
35 | #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ | |
36 | #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ | |
37 | ||
e702ba18 FF |
38 | #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) |
39 | ||
d0ce2d17 VT |
40 | #define EEPROM_DATA_LEN_9485 1088 |
41 | ||
f4475a6e VT |
42 | static int ar9003_hw_power_interpolate(int32_t x, |
43 | int32_t *px, int32_t *py, u_int16_t np); | |
fe6c7915 | 44 | |
15c9ee7a SB |
45 | static const struct ar9300_eeprom ar9300_default = { |
46 | .eepromVersion = 2, | |
47 | .templateVersion = 2, | |
b503c7a2 | 48 | .macAddr = {0, 2, 3, 4, 5, 6}, |
15c9ee7a SB |
49 | .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
50 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | |
51 | .baseEepHeader = { | |
ffdc4cbe | 52 | .regDmn = { LE16(0), LE16(0x1f) }, |
15c9ee7a SB |
53 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
54 | .opCapFlags = { | |
4ddfcd7d | 55 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
15c9ee7a SB |
56 | .eepMisc = 0, |
57 | }, | |
58 | .rfSilent = 0, | |
59 | .blueToothOptions = 0, | |
60 | .deviceCap = 0, | |
61 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
62 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
63 | .params_for_tuning_caps = {0, 0}, | |
64 | .featureEnable = 0x0c, | |
65 | /* | |
66 | * bit0 - enable tx temp comp - disabled | |
67 | * bit1 - enable tx volt comp - disabled | |
68 | * bit2 - enable fastClock - enabled | |
69 | * bit3 - enable doubling - enabled | |
70 | * bit4 - enable internal regulator - disabled | |
4935250a | 71 | * bit5 - enable pa predistortion - disabled |
15c9ee7a SB |
72 | */ |
73 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
74 | .eepromWriteEnableGpio = 3, | |
75 | .wlanDisableGpio = 0, | |
76 | .wlanLedGpio = 8, | |
77 | .rxBandSelectGpio = 0xff, | |
78 | .txrxgain = 0, | |
79 | .swreg = 0, | |
80 | }, | |
81 | .modalHeader2G = { | |
82 | /* ar9300_modal_eep_header 2g */ | |
83 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
ffdc4cbe | 84 | .antCtrlCommon = LE32(0x110), |
15c9ee7a | 85 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ |
ffdc4cbe | 86 | .antCtrlCommon2 = LE32(0x22222), |
15c9ee7a SB |
87 | |
88 | /* | |
89 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, | |
90 | * rx1, rx12, b (2 bits each) | |
91 | */ | |
ffdc4cbe | 92 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, |
15c9ee7a SB |
93 | |
94 | /* | |
95 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db | |
96 | * for ar9280 (0xa20c/b20c 5:0) | |
97 | */ | |
98 | .xatten1DB = {0, 0, 0}, | |
99 | ||
100 | /* | |
101 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
102 | * for ar9280 (0xa20c/b20c 16:12 | |
103 | */ | |
104 | .xatten1Margin = {0, 0, 0}, | |
105 | .tempSlope = 36, | |
106 | .voltSlope = 0, | |
107 | ||
108 | /* | |
109 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur | |
110 | * channels in usual fbin coding format | |
111 | */ | |
112 | .spurChans = {0, 0, 0, 0, 0}, | |
113 | ||
114 | /* | |
115 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check | |
116 | * if the register is per chain | |
117 | */ | |
118 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
119 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
120 | .quick_drop = 0, | |
15c9ee7a SB |
121 | .xpaBiasLvl = 0, |
122 | .txFrameToDataStart = 0x0e, | |
123 | .txFrameToPaOn = 0x0e, | |
124 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
125 | .antennaGain = 0, | |
126 | .switchSettling = 0x2c, | |
127 | .adcDesiredSize = -30, | |
128 | .txEndToXpaOff = 0, | |
129 | .txEndToRxOn = 0x2, | |
130 | .txFrameToXpaOn = 0xe, | |
131 | .thresh62 = 28, | |
3ceb801b SB |
132 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
133 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
3e2ea543 | 134 | .xlna_bias_strength = 0, |
4935250a | 135 | .futureModal = { |
3e2ea543 | 136 | 0, 0, 0, 0, 0, 0, 0, |
15c9ee7a SB |
137 | }, |
138 | }, | |
b3dd6bc1 SB |
139 | .base_ext1 = { |
140 | .ant_div_control = 0, | |
420e2b1b RM |
141 | .future = {0, 0, 0}, |
142 | .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} | |
b3dd6bc1 | 143 | }, |
15c9ee7a SB |
144 | .calFreqPier2G = { |
145 | FREQ2FBIN(2412, 1), | |
146 | FREQ2FBIN(2437, 1), | |
147 | FREQ2FBIN(2472, 1), | |
148 | }, | |
149 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
150 | .calPierData2G = { | |
151 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
152 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
153 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
154 | }, | |
155 | .calTarget_freqbin_Cck = { | |
156 | FREQ2FBIN(2412, 1), | |
157 | FREQ2FBIN(2484, 1), | |
158 | }, | |
159 | .calTarget_freqbin_2G = { | |
160 | FREQ2FBIN(2412, 1), | |
161 | FREQ2FBIN(2437, 1), | |
162 | FREQ2FBIN(2472, 1) | |
163 | }, | |
164 | .calTarget_freqbin_2GHT20 = { | |
165 | FREQ2FBIN(2412, 1), | |
166 | FREQ2FBIN(2437, 1), | |
167 | FREQ2FBIN(2472, 1) | |
168 | }, | |
169 | .calTarget_freqbin_2GHT40 = { | |
170 | FREQ2FBIN(2412, 1), | |
171 | FREQ2FBIN(2437, 1), | |
172 | FREQ2FBIN(2472, 1) | |
173 | }, | |
174 | .calTargetPowerCck = { | |
175 | /* 1L-5L,5S,11L,11S */ | |
176 | { {36, 36, 36, 36} }, | |
177 | { {36, 36, 36, 36} }, | |
178 | }, | |
179 | .calTargetPower2G = { | |
180 | /* 6-24,36,48,54 */ | |
181 | { {32, 32, 28, 24} }, | |
182 | { {32, 32, 28, 24} }, | |
183 | { {32, 32, 28, 24} }, | |
184 | }, | |
185 | .calTargetPower2GHT20 = { | |
186 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
187 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
188 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
189 | }, | |
190 | .calTargetPower2GHT40 = { | |
191 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
192 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
193 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, | |
194 | }, | |
195 | .ctlIndex_2G = { | |
196 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
197 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
198 | }, | |
199 | .ctl_freqbin_2G = { | |
200 | { | |
201 | FREQ2FBIN(2412, 1), | |
202 | FREQ2FBIN(2417, 1), | |
203 | FREQ2FBIN(2457, 1), | |
204 | FREQ2FBIN(2462, 1) | |
205 | }, | |
206 | { | |
207 | FREQ2FBIN(2412, 1), | |
208 | FREQ2FBIN(2417, 1), | |
209 | FREQ2FBIN(2462, 1), | |
210 | 0xFF, | |
211 | }, | |
212 | ||
213 | { | |
214 | FREQ2FBIN(2412, 1), | |
215 | FREQ2FBIN(2417, 1), | |
216 | FREQ2FBIN(2462, 1), | |
217 | 0xFF, | |
218 | }, | |
219 | { | |
220 | FREQ2FBIN(2422, 1), | |
221 | FREQ2FBIN(2427, 1), | |
222 | FREQ2FBIN(2447, 1), | |
223 | FREQ2FBIN(2452, 1) | |
224 | }, | |
225 | ||
226 | { | |
227 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
228 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
229 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
230 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), | |
231 | }, | |
232 | ||
233 | { | |
234 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
235 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
236 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
237 | 0, | |
238 | }, | |
239 | ||
240 | { | |
241 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
242 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
243 | FREQ2FBIN(2472, 1), | |
244 | 0, | |
245 | }, | |
246 | ||
247 | { | |
248 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
249 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
250 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
251 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
252 | }, | |
253 | ||
254 | { | |
255 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
256 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
257 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
258 | }, | |
259 | ||
260 | { | |
261 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
262 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
263 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
264 | 0 | |
265 | }, | |
266 | ||
267 | { | |
268 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
269 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
270 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
271 | 0 | |
272 | }, | |
273 | ||
274 | { | |
275 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
276 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
277 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
b3dd6bc1 | 278 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
15c9ee7a SB |
279 | } |
280 | }, | |
281 | .ctlPowerData_2G = { | |
fe6c7915 DM |
282 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
283 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
284 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
15c9ee7a | 285 | |
15052f81 | 286 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, |
fe6c7915 DM |
287 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
288 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
15c9ee7a | 289 | |
fe6c7915 DM |
290 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
291 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
292 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
15c9ee7a | 293 | |
fe6c7915 DM |
294 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
295 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
296 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
15c9ee7a SB |
297 | }, |
298 | .modalHeader5G = { | |
299 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
ffdc4cbe | 300 | .antCtrlCommon = LE32(0x110), |
15c9ee7a | 301 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ |
ffdc4cbe | 302 | .antCtrlCommon2 = LE32(0x22222), |
15c9ee7a SB |
303 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ |
304 | .antCtrlChain = { | |
ffdc4cbe | 305 | LE16(0x000), LE16(0x000), LE16(0x000), |
15c9ee7a SB |
306 | }, |
307 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ | |
308 | .xatten1DB = {0, 0, 0}, | |
309 | ||
310 | /* | |
311 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
312 | * for merlin (0xa20c/b20c 16:12 | |
313 | */ | |
314 | .xatten1Margin = {0, 0, 0}, | |
315 | .tempSlope = 68, | |
316 | .voltSlope = 0, | |
317 | /* spurChans spur channels in usual fbin coding format */ | |
318 | .spurChans = {0, 0, 0, 0, 0}, | |
319 | /* noiseFloorThreshCh Check if the register is per chain */ | |
320 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
321 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
322 | .quick_drop = 0, | |
15c9ee7a SB |
323 | .xpaBiasLvl = 0, |
324 | .txFrameToDataStart = 0x0e, | |
325 | .txFrameToPaOn = 0x0e, | |
326 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
327 | .antennaGain = 0, | |
328 | .switchSettling = 0x2d, | |
329 | .adcDesiredSize = -30, | |
330 | .txEndToXpaOff = 0, | |
331 | .txEndToRxOn = 0x2, | |
332 | .txFrameToXpaOn = 0xe, | |
333 | .thresh62 = 28, | |
3ceb801b SB |
334 | .papdRateMaskHt20 = LE32(0x0c80c080), |
335 | .papdRateMaskHt40 = LE32(0x0080c080), | |
3e2ea543 | 336 | .xlna_bias_strength = 0, |
15c9ee7a | 337 | .futureModal = { |
3e2ea543 | 338 | 0, 0, 0, 0, 0, 0, 0, |
15c9ee7a SB |
339 | }, |
340 | }, | |
b3dd6bc1 SB |
341 | .base_ext2 = { |
342 | .tempSlopeLow = 0, | |
343 | .tempSlopeHigh = 0, | |
344 | .xatten1DBLow = {0, 0, 0}, | |
345 | .xatten1MarginLow = {0, 0, 0}, | |
346 | .xatten1DBHigh = {0, 0, 0}, | |
347 | .xatten1MarginHigh = {0, 0, 0} | |
348 | }, | |
15c9ee7a SB |
349 | .calFreqPier5G = { |
350 | FREQ2FBIN(5180, 0), | |
351 | FREQ2FBIN(5220, 0), | |
352 | FREQ2FBIN(5320, 0), | |
353 | FREQ2FBIN(5400, 0), | |
354 | FREQ2FBIN(5500, 0), | |
355 | FREQ2FBIN(5600, 0), | |
356 | FREQ2FBIN(5725, 0), | |
357 | FREQ2FBIN(5825, 0) | |
358 | }, | |
359 | .calPierData5G = { | |
360 | { | |
361 | {0, 0, 0, 0, 0}, | |
362 | {0, 0, 0, 0, 0}, | |
363 | {0, 0, 0, 0, 0}, | |
364 | {0, 0, 0, 0, 0}, | |
365 | {0, 0, 0, 0, 0}, | |
366 | {0, 0, 0, 0, 0}, | |
367 | {0, 0, 0, 0, 0}, | |
368 | {0, 0, 0, 0, 0}, | |
369 | }, | |
370 | { | |
371 | {0, 0, 0, 0, 0}, | |
372 | {0, 0, 0, 0, 0}, | |
373 | {0, 0, 0, 0, 0}, | |
374 | {0, 0, 0, 0, 0}, | |
375 | {0, 0, 0, 0, 0}, | |
376 | {0, 0, 0, 0, 0}, | |
377 | {0, 0, 0, 0, 0}, | |
378 | {0, 0, 0, 0, 0}, | |
379 | }, | |
380 | { | |
381 | {0, 0, 0, 0, 0}, | |
382 | {0, 0, 0, 0, 0}, | |
383 | {0, 0, 0, 0, 0}, | |
384 | {0, 0, 0, 0, 0}, | |
385 | {0, 0, 0, 0, 0}, | |
386 | {0, 0, 0, 0, 0}, | |
387 | {0, 0, 0, 0, 0}, | |
388 | {0, 0, 0, 0, 0}, | |
389 | }, | |
390 | ||
391 | }, | |
392 | .calTarget_freqbin_5G = { | |
393 | FREQ2FBIN(5180, 0), | |
394 | FREQ2FBIN(5220, 0), | |
395 | FREQ2FBIN(5320, 0), | |
396 | FREQ2FBIN(5400, 0), | |
397 | FREQ2FBIN(5500, 0), | |
398 | FREQ2FBIN(5600, 0), | |
399 | FREQ2FBIN(5725, 0), | |
400 | FREQ2FBIN(5825, 0) | |
401 | }, | |
402 | .calTarget_freqbin_5GHT20 = { | |
403 | FREQ2FBIN(5180, 0), | |
404 | FREQ2FBIN(5240, 0), | |
405 | FREQ2FBIN(5320, 0), | |
406 | FREQ2FBIN(5500, 0), | |
407 | FREQ2FBIN(5700, 0), | |
408 | FREQ2FBIN(5745, 0), | |
409 | FREQ2FBIN(5725, 0), | |
410 | FREQ2FBIN(5825, 0) | |
411 | }, | |
412 | .calTarget_freqbin_5GHT40 = { | |
413 | FREQ2FBIN(5180, 0), | |
414 | FREQ2FBIN(5240, 0), | |
415 | FREQ2FBIN(5320, 0), | |
416 | FREQ2FBIN(5500, 0), | |
417 | FREQ2FBIN(5700, 0), | |
418 | FREQ2FBIN(5745, 0), | |
419 | FREQ2FBIN(5725, 0), | |
420 | FREQ2FBIN(5825, 0) | |
421 | }, | |
422 | .calTargetPower5G = { | |
423 | /* 6-24,36,48,54 */ | |
424 | { {20, 20, 20, 10} }, | |
425 | { {20, 20, 20, 10} }, | |
426 | { {20, 20, 20, 10} }, | |
427 | { {20, 20, 20, 10} }, | |
428 | { {20, 20, 20, 10} }, | |
429 | { {20, 20, 20, 10} }, | |
430 | { {20, 20, 20, 10} }, | |
431 | { {20, 20, 20, 10} }, | |
432 | }, | |
433 | .calTargetPower5GHT20 = { | |
434 | /* | |
435 | * 0_8_16,1-3_9-11_17-19, | |
436 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
437 | */ | |
438 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
439 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
440 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
441 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
442 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
443 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
444 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
445 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
446 | }, | |
447 | .calTargetPower5GHT40 = { | |
448 | /* | |
449 | * 0_8_16,1-3_9-11_17-19, | |
450 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
451 | */ | |
452 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
453 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
454 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
455 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
456 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
457 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
458 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
459 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, | |
460 | }, | |
461 | .ctlIndex_5G = { | |
462 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
463 | 0x48, 0x30, 0x36, 0x38 | |
464 | }, | |
465 | .ctl_freqbin_5G = { | |
466 | { | |
467 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
468 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
469 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
470 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
471 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), | |
472 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
473 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
474 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
475 | }, | |
476 | { | |
477 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
478 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
479 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
480 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
481 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), | |
482 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
483 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
484 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
485 | }, | |
486 | ||
487 | { | |
488 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
489 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
490 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
491 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), | |
492 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), | |
493 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), | |
494 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), | |
495 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) | |
496 | }, | |
497 | ||
498 | { | |
499 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
500 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
501 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), | |
502 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), | |
503 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
504 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
505 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, | |
506 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, | |
507 | }, | |
508 | ||
509 | { | |
510 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
511 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
512 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), | |
513 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), | |
514 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, | |
515 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, | |
516 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, | |
517 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, | |
518 | }, | |
519 | ||
520 | { | |
521 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
522 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), | |
523 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), | |
524 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
525 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), | |
526 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
527 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, | |
528 | /* Data[5].ctlEdges[7].bChannel */ 0xFF | |
529 | }, | |
530 | ||
531 | { | |
532 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
533 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
534 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), | |
535 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), | |
536 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
537 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), | |
538 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), | |
539 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) | |
540 | }, | |
541 | ||
542 | { | |
543 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
544 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
545 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), | |
546 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
547 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), | |
548 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
549 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
550 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
551 | }, | |
552 | ||
553 | { | |
554 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
555 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
556 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
557 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
558 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), | |
559 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
560 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), | |
561 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) | |
562 | } | |
563 | }, | |
564 | .ctlPowerData_5G = { | |
565 | { | |
566 | { | |
fe6c7915 DM |
567 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
568 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
15c9ee7a SB |
569 | } |
570 | }, | |
571 | { | |
572 | { | |
fe6c7915 DM |
573 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
574 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
15c9ee7a SB |
575 | } |
576 | }, | |
577 | { | |
578 | { | |
fe6c7915 DM |
579 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
580 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
15c9ee7a SB |
581 | } |
582 | }, | |
583 | { | |
584 | { | |
fe6c7915 DM |
585 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
586 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
15c9ee7a SB |
587 | } |
588 | }, | |
589 | { | |
590 | { | |
fe6c7915 DM |
591 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
592 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
15c9ee7a SB |
593 | } |
594 | }, | |
595 | { | |
596 | { | |
fe6c7915 DM |
597 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
598 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
15c9ee7a SB |
599 | } |
600 | }, | |
601 | { | |
602 | { | |
fe6c7915 DM |
603 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
604 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
15c9ee7a SB |
605 | } |
606 | }, | |
607 | { | |
608 | { | |
fe6c7915 DM |
609 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
610 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
15c9ee7a SB |
611 | } |
612 | }, | |
613 | { | |
614 | { | |
fe6c7915 DM |
615 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
616 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
15c9ee7a SB |
617 | } |
618 | }, | |
619 | } | |
620 | }; | |
621 | ||
30923549 SB |
622 | static const struct ar9300_eeprom ar9300_x113 = { |
623 | .eepromVersion = 2, | |
624 | .templateVersion = 6, | |
625 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, | |
626 | .custData = {"x113-023-f0000"}, | |
627 | .baseEepHeader = { | |
628 | .regDmn = { LE16(0), LE16(0x1f) }, | |
629 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | |
630 | .opCapFlags = { | |
9ba7f4f5 | 631 | .opFlags = AR5416_OPFLAGS_11A, |
30923549 SB |
632 | .eepMisc = 0, |
633 | }, | |
634 | .rfSilent = 0, | |
635 | .blueToothOptions = 0, | |
636 | .deviceCap = 0, | |
637 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
638 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
639 | .params_for_tuning_caps = {0, 0}, | |
640 | .featureEnable = 0x0d, | |
641 | /* | |
642 | * bit0 - enable tx temp comp - disabled | |
643 | * bit1 - enable tx volt comp - disabled | |
644 | * bit2 - enable fastClock - enabled | |
645 | * bit3 - enable doubling - enabled | |
646 | * bit4 - enable internal regulator - disabled | |
647 | * bit5 - enable pa predistortion - disabled | |
648 | */ | |
649 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
650 | .eepromWriteEnableGpio = 6, | |
651 | .wlanDisableGpio = 0, | |
652 | .wlanLedGpio = 8, | |
653 | .rxBandSelectGpio = 0xff, | |
654 | .txrxgain = 0x21, | |
655 | .swreg = 0, | |
656 | }, | |
657 | .modalHeader2G = { | |
658 | /* ar9300_modal_eep_header 2g */ | |
659 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
660 | .antCtrlCommon = LE32(0x110), | |
661 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ | |
662 | .antCtrlCommon2 = LE32(0x44444), | |
663 | ||
664 | /* | |
665 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, | |
666 | * rx1, rx12, b (2 bits each) | |
667 | */ | |
668 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, | |
669 | ||
670 | /* | |
671 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db | |
672 | * for ar9280 (0xa20c/b20c 5:0) | |
673 | */ | |
674 | .xatten1DB = {0, 0, 0}, | |
675 | ||
676 | /* | |
677 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
678 | * for ar9280 (0xa20c/b20c 16:12 | |
679 | */ | |
680 | .xatten1Margin = {0, 0, 0}, | |
681 | .tempSlope = 25, | |
682 | .voltSlope = 0, | |
683 | ||
684 | /* | |
685 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur | |
686 | * channels in usual fbin coding format | |
687 | */ | |
688 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, | |
689 | ||
690 | /* | |
691 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check | |
692 | * if the register is per chain | |
693 | */ | |
694 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
695 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
696 | .quick_drop = 0, | |
30923549 SB |
697 | .xpaBiasLvl = 0, |
698 | .txFrameToDataStart = 0x0e, | |
699 | .txFrameToPaOn = 0x0e, | |
700 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
701 | .antennaGain = 0, | |
702 | .switchSettling = 0x2c, | |
703 | .adcDesiredSize = -30, | |
704 | .txEndToXpaOff = 0, | |
705 | .txEndToRxOn = 0x2, | |
706 | .txFrameToXpaOn = 0xe, | |
707 | .thresh62 = 28, | |
708 | .papdRateMaskHt20 = LE32(0x0c80c080), | |
709 | .papdRateMaskHt40 = LE32(0x0080c080), | |
3e2ea543 | 710 | .xlna_bias_strength = 0, |
30923549 | 711 | .futureModal = { |
3e2ea543 | 712 | 0, 0, 0, 0, 0, 0, 0, |
30923549 SB |
713 | }, |
714 | }, | |
715 | .base_ext1 = { | |
716 | .ant_div_control = 0, | |
420e2b1b RM |
717 | .future = {0, 0, 0}, |
718 | .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} | |
30923549 SB |
719 | }, |
720 | .calFreqPier2G = { | |
721 | FREQ2FBIN(2412, 1), | |
722 | FREQ2FBIN(2437, 1), | |
723 | FREQ2FBIN(2472, 1), | |
724 | }, | |
725 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
726 | .calPierData2G = { | |
727 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
728 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
729 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
730 | }, | |
731 | .calTarget_freqbin_Cck = { | |
732 | FREQ2FBIN(2412, 1), | |
733 | FREQ2FBIN(2472, 1), | |
734 | }, | |
735 | .calTarget_freqbin_2G = { | |
736 | FREQ2FBIN(2412, 1), | |
737 | FREQ2FBIN(2437, 1), | |
738 | FREQ2FBIN(2472, 1) | |
739 | }, | |
740 | .calTarget_freqbin_2GHT20 = { | |
741 | FREQ2FBIN(2412, 1), | |
742 | FREQ2FBIN(2437, 1), | |
743 | FREQ2FBIN(2472, 1) | |
744 | }, | |
745 | .calTarget_freqbin_2GHT40 = { | |
746 | FREQ2FBIN(2412, 1), | |
747 | FREQ2FBIN(2437, 1), | |
748 | FREQ2FBIN(2472, 1) | |
749 | }, | |
750 | .calTargetPowerCck = { | |
751 | /* 1L-5L,5S,11L,11S */ | |
752 | { {34, 34, 34, 34} }, | |
753 | { {34, 34, 34, 34} }, | |
754 | }, | |
755 | .calTargetPower2G = { | |
756 | /* 6-24,36,48,54 */ | |
757 | { {34, 34, 32, 32} }, | |
758 | { {34, 34, 32, 32} }, | |
759 | { {34, 34, 32, 32} }, | |
760 | }, | |
761 | .calTargetPower2GHT20 = { | |
762 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
763 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
764 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
765 | }, | |
766 | .calTargetPower2GHT40 = { | |
767 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
768 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
769 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
770 | }, | |
771 | .ctlIndex_2G = { | |
772 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
773 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
774 | }, | |
775 | .ctl_freqbin_2G = { | |
776 | { | |
777 | FREQ2FBIN(2412, 1), | |
778 | FREQ2FBIN(2417, 1), | |
779 | FREQ2FBIN(2457, 1), | |
780 | FREQ2FBIN(2462, 1) | |
781 | }, | |
782 | { | |
783 | FREQ2FBIN(2412, 1), | |
784 | FREQ2FBIN(2417, 1), | |
785 | FREQ2FBIN(2462, 1), | |
786 | 0xFF, | |
787 | }, | |
788 | ||
789 | { | |
790 | FREQ2FBIN(2412, 1), | |
791 | FREQ2FBIN(2417, 1), | |
792 | FREQ2FBIN(2462, 1), | |
793 | 0xFF, | |
794 | }, | |
795 | { | |
796 | FREQ2FBIN(2422, 1), | |
797 | FREQ2FBIN(2427, 1), | |
798 | FREQ2FBIN(2447, 1), | |
799 | FREQ2FBIN(2452, 1) | |
800 | }, | |
801 | ||
802 | { | |
803 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
804 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
805 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
806 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), | |
807 | }, | |
808 | ||
809 | { | |
810 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
811 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
812 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
813 | 0, | |
814 | }, | |
815 | ||
816 | { | |
817 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
818 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
819 | FREQ2FBIN(2472, 1), | |
820 | 0, | |
821 | }, | |
822 | ||
823 | { | |
824 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
825 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
826 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
827 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
828 | }, | |
829 | ||
830 | { | |
831 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
832 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
833 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
834 | }, | |
835 | ||
836 | { | |
837 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
838 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
839 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
840 | 0 | |
841 | }, | |
842 | ||
843 | { | |
844 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
845 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
846 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
847 | 0 | |
848 | }, | |
849 | ||
850 | { | |
851 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
852 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
853 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
854 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
855 | } | |
856 | }, | |
857 | .ctlPowerData_2G = { | |
fe6c7915 DM |
858 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
859 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
860 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
30923549 | 861 | |
15052f81 | 862 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, |
fe6c7915 DM |
863 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
864 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 865 | |
fe6c7915 DM |
866 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
867 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
868 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 869 | |
fe6c7915 DM |
870 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
871 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
872 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
30923549 SB |
873 | }, |
874 | .modalHeader5G = { | |
875 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
876 | .antCtrlCommon = LE32(0x220), | |
877 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ | |
878 | .antCtrlCommon2 = LE32(0x11111), | |
879 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ | |
880 | .antCtrlChain = { | |
881 | LE16(0x150), LE16(0x150), LE16(0x150), | |
882 | }, | |
883 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ | |
884 | .xatten1DB = {0, 0, 0}, | |
885 | ||
886 | /* | |
887 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
888 | * for merlin (0xa20c/b20c 16:12 | |
889 | */ | |
890 | .xatten1Margin = {0, 0, 0}, | |
891 | .tempSlope = 68, | |
892 | .voltSlope = 0, | |
893 | /* spurChans spur channels in usual fbin coding format */ | |
894 | .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0}, | |
895 | /* noiseFloorThreshCh Check if the register is per chain */ | |
896 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
897 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
898 | .quick_drop = 0, | |
be0e6aa5 | 899 | .xpaBiasLvl = 0xf, |
30923549 SB |
900 | .txFrameToDataStart = 0x0e, |
901 | .txFrameToPaOn = 0x0e, | |
902 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
903 | .antennaGain = 0, | |
904 | .switchSettling = 0x2d, | |
905 | .adcDesiredSize = -30, | |
906 | .txEndToXpaOff = 0, | |
907 | .txEndToRxOn = 0x2, | |
908 | .txFrameToXpaOn = 0xe, | |
909 | .thresh62 = 28, | |
910 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | |
911 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
3e2ea543 | 912 | .xlna_bias_strength = 0, |
30923549 | 913 | .futureModal = { |
3e2ea543 | 914 | 0, 0, 0, 0, 0, 0, 0, |
30923549 SB |
915 | }, |
916 | }, | |
917 | .base_ext2 = { | |
918 | .tempSlopeLow = 72, | |
919 | .tempSlopeHigh = 105, | |
920 | .xatten1DBLow = {0, 0, 0}, | |
921 | .xatten1MarginLow = {0, 0, 0}, | |
922 | .xatten1DBHigh = {0, 0, 0}, | |
923 | .xatten1MarginHigh = {0, 0, 0} | |
924 | }, | |
925 | .calFreqPier5G = { | |
926 | FREQ2FBIN(5180, 0), | |
927 | FREQ2FBIN(5240, 0), | |
928 | FREQ2FBIN(5320, 0), | |
929 | FREQ2FBIN(5400, 0), | |
930 | FREQ2FBIN(5500, 0), | |
931 | FREQ2FBIN(5600, 0), | |
932 | FREQ2FBIN(5745, 0), | |
933 | FREQ2FBIN(5785, 0) | |
934 | }, | |
935 | .calPierData5G = { | |
936 | { | |
937 | {0, 0, 0, 0, 0}, | |
938 | {0, 0, 0, 0, 0}, | |
939 | {0, 0, 0, 0, 0}, | |
940 | {0, 0, 0, 0, 0}, | |
941 | {0, 0, 0, 0, 0}, | |
942 | {0, 0, 0, 0, 0}, | |
943 | {0, 0, 0, 0, 0}, | |
944 | {0, 0, 0, 0, 0}, | |
945 | }, | |
946 | { | |
947 | {0, 0, 0, 0, 0}, | |
948 | {0, 0, 0, 0, 0}, | |
949 | {0, 0, 0, 0, 0}, | |
950 | {0, 0, 0, 0, 0}, | |
951 | {0, 0, 0, 0, 0}, | |
952 | {0, 0, 0, 0, 0}, | |
953 | {0, 0, 0, 0, 0}, | |
954 | {0, 0, 0, 0, 0}, | |
955 | }, | |
956 | { | |
957 | {0, 0, 0, 0, 0}, | |
958 | {0, 0, 0, 0, 0}, | |
959 | {0, 0, 0, 0, 0}, | |
960 | {0, 0, 0, 0, 0}, | |
961 | {0, 0, 0, 0, 0}, | |
962 | {0, 0, 0, 0, 0}, | |
963 | {0, 0, 0, 0, 0}, | |
964 | {0, 0, 0, 0, 0}, | |
965 | }, | |
966 | ||
967 | }, | |
968 | .calTarget_freqbin_5G = { | |
969 | FREQ2FBIN(5180, 0), | |
970 | FREQ2FBIN(5220, 0), | |
971 | FREQ2FBIN(5320, 0), | |
972 | FREQ2FBIN(5400, 0), | |
973 | FREQ2FBIN(5500, 0), | |
974 | FREQ2FBIN(5600, 0), | |
975 | FREQ2FBIN(5745, 0), | |
976 | FREQ2FBIN(5785, 0) | |
977 | }, | |
978 | .calTarget_freqbin_5GHT20 = { | |
979 | FREQ2FBIN(5180, 0), | |
980 | FREQ2FBIN(5240, 0), | |
981 | FREQ2FBIN(5320, 0), | |
982 | FREQ2FBIN(5400, 0), | |
983 | FREQ2FBIN(5500, 0), | |
984 | FREQ2FBIN(5700, 0), | |
985 | FREQ2FBIN(5745, 0), | |
986 | FREQ2FBIN(5825, 0) | |
987 | }, | |
988 | .calTarget_freqbin_5GHT40 = { | |
989 | FREQ2FBIN(5190, 0), | |
990 | FREQ2FBIN(5230, 0), | |
991 | FREQ2FBIN(5320, 0), | |
992 | FREQ2FBIN(5410, 0), | |
993 | FREQ2FBIN(5510, 0), | |
994 | FREQ2FBIN(5670, 0), | |
995 | FREQ2FBIN(5755, 0), | |
996 | FREQ2FBIN(5825, 0) | |
997 | }, | |
998 | .calTargetPower5G = { | |
999 | /* 6-24,36,48,54 */ | |
1000 | { {42, 40, 40, 34} }, | |
1001 | { {42, 40, 40, 34} }, | |
1002 | { {42, 40, 40, 34} }, | |
1003 | { {42, 40, 40, 34} }, | |
1004 | { {42, 40, 40, 34} }, | |
1005 | { {42, 40, 40, 34} }, | |
1006 | { {42, 40, 40, 34} }, | |
1007 | { {42, 40, 40, 34} }, | |
1008 | }, | |
1009 | .calTargetPower5GHT20 = { | |
1010 | /* | |
1011 | * 0_8_16,1-3_9-11_17-19, | |
1012 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
1013 | */ | |
1014 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1015 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1016 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1017 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1018 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1019 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, | |
1020 | { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} }, | |
1021 | { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} }, | |
1022 | }, | |
1023 | .calTargetPower5GHT40 = { | |
1024 | /* | |
1025 | * 0_8_16,1-3_9-11_17-19, | |
1026 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
1027 | */ | |
1028 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1029 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1030 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1031 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1032 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1033 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, | |
1034 | { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} }, | |
1035 | { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} }, | |
1036 | }, | |
1037 | .ctlIndex_5G = { | |
1038 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
1039 | 0x48, 0x30, 0x36, 0x38 | |
1040 | }, | |
1041 | .ctl_freqbin_5G = { | |
1042 | { | |
1043 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1044 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1045 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
1046 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1047 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), | |
1048 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1049 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1050 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1051 | }, | |
1052 | { | |
1053 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1054 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1055 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
1056 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1057 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), | |
1058 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1059 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1060 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1061 | }, | |
1062 | ||
1063 | { | |
1064 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1065 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
1066 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
1067 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), | |
1068 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), | |
1069 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), | |
1070 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), | |
1071 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) | |
1072 | }, | |
1073 | ||
1074 | { | |
1075 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1076 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
1077 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), | |
1078 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), | |
1079 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
1080 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1081 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, | |
1082 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, | |
1083 | }, | |
1084 | ||
1085 | { | |
1086 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1087 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1088 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), | |
1089 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), | |
1090 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, | |
1091 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, | |
1092 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, | |
1093 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, | |
1094 | }, | |
1095 | ||
1096 | { | |
1097 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1098 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), | |
1099 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), | |
1100 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
1101 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), | |
1102 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
1103 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, | |
1104 | /* Data[5].ctlEdges[7].bChannel */ 0xFF | |
1105 | }, | |
1106 | ||
1107 | { | |
1108 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1109 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
1110 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), | |
1111 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), | |
1112 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
1113 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), | |
1114 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), | |
1115 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) | |
1116 | }, | |
1117 | ||
1118 | { | |
1119 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1120 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1121 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), | |
1122 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1123 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), | |
1124 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1125 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1126 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1127 | }, | |
1128 | ||
1129 | { | |
1130 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1131 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
1132 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
1133 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
1134 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), | |
1135 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
1136 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), | |
1137 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) | |
1138 | } | |
1139 | }, | |
1140 | .ctlPowerData_5G = { | |
1141 | { | |
1142 | { | |
fe6c7915 DM |
1143 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1144 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1145 | } |
1146 | }, | |
1147 | { | |
1148 | { | |
fe6c7915 DM |
1149 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1150 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1151 | } |
1152 | }, | |
1153 | { | |
1154 | { | |
fe6c7915 DM |
1155 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
1156 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
1157 | } |
1158 | }, | |
1159 | { | |
1160 | { | |
fe6c7915 DM |
1161 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
1162 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1163 | } |
1164 | }, | |
1165 | { | |
1166 | { | |
fe6c7915 DM |
1167 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
1168 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1169 | } |
1170 | }, | |
1171 | { | |
1172 | { | |
fe6c7915 DM |
1173 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1174 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1175 | } |
1176 | }, | |
1177 | { | |
1178 | { | |
fe6c7915 DM |
1179 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1180 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
1181 | } |
1182 | }, | |
1183 | { | |
1184 | { | |
fe6c7915 DM |
1185 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
1186 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1187 | } |
1188 | }, | |
1189 | { | |
1190 | { | |
fe6c7915 DM |
1191 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
1192 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
30923549 SB |
1193 | } |
1194 | }, | |
1195 | } | |
1196 | }; | |
1197 | ||
1198 | ||
1199 | static const struct ar9300_eeprom ar9300_h112 = { | |
1200 | .eepromVersion = 2, | |
1201 | .templateVersion = 3, | |
1202 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, | |
1203 | .custData = {"h112-241-f0000"}, | |
1204 | .baseEepHeader = { | |
1205 | .regDmn = { LE16(0), LE16(0x1f) }, | |
1206 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | |
1207 | .opCapFlags = { | |
4ddfcd7d | 1208 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
30923549 SB |
1209 | .eepMisc = 0, |
1210 | }, | |
1211 | .rfSilent = 0, | |
1212 | .blueToothOptions = 0, | |
1213 | .deviceCap = 0, | |
1214 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
1215 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
1216 | .params_for_tuning_caps = {0, 0}, | |
1217 | .featureEnable = 0x0d, | |
1218 | /* | |
1219 | * bit0 - enable tx temp comp - disabled | |
1220 | * bit1 - enable tx volt comp - disabled | |
1221 | * bit2 - enable fastClock - enabled | |
1222 | * bit3 - enable doubling - enabled | |
1223 | * bit4 - enable internal regulator - disabled | |
1224 | * bit5 - enable pa predistortion - disabled | |
1225 | */ | |
1226 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
1227 | .eepromWriteEnableGpio = 6, | |
1228 | .wlanDisableGpio = 0, | |
1229 | .wlanLedGpio = 8, | |
1230 | .rxBandSelectGpio = 0xff, | |
1231 | .txrxgain = 0x10, | |
1232 | .swreg = 0, | |
1233 | }, | |
1234 | .modalHeader2G = { | |
1235 | /* ar9300_modal_eep_header 2g */ | |
1236 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
1237 | .antCtrlCommon = LE32(0x110), | |
1238 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ | |
1239 | .antCtrlCommon2 = LE32(0x44444), | |
1240 | ||
1241 | /* | |
1242 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, | |
1243 | * rx1, rx12, b (2 bits each) | |
1244 | */ | |
1245 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, | |
1246 | ||
1247 | /* | |
1248 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db | |
1249 | * for ar9280 (0xa20c/b20c 5:0) | |
1250 | */ | |
1251 | .xatten1DB = {0, 0, 0}, | |
1252 | ||
1253 | /* | |
1254 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
1255 | * for ar9280 (0xa20c/b20c 16:12 | |
1256 | */ | |
1257 | .xatten1Margin = {0, 0, 0}, | |
1258 | .tempSlope = 25, | |
1259 | .voltSlope = 0, | |
1260 | ||
1261 | /* | |
1262 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur | |
1263 | * channels in usual fbin coding format | |
1264 | */ | |
1265 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, | |
1266 | ||
1267 | /* | |
1268 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check | |
1269 | * if the register is per chain | |
1270 | */ | |
1271 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
1272 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
1273 | .quick_drop = 0, | |
30923549 SB |
1274 | .xpaBiasLvl = 0, |
1275 | .txFrameToDataStart = 0x0e, | |
1276 | .txFrameToPaOn = 0x0e, | |
1277 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
1278 | .antennaGain = 0, | |
1279 | .switchSettling = 0x2c, | |
1280 | .adcDesiredSize = -30, | |
1281 | .txEndToXpaOff = 0, | |
1282 | .txEndToRxOn = 0x2, | |
1283 | .txFrameToXpaOn = 0xe, | |
1284 | .thresh62 = 28, | |
94e2ad9e RM |
1285 | .papdRateMaskHt20 = LE32(0x0c80c080), |
1286 | .papdRateMaskHt40 = LE32(0x0080c080), | |
3e2ea543 | 1287 | .xlna_bias_strength = 0, |
30923549 | 1288 | .futureModal = { |
3e2ea543 | 1289 | 0, 0, 0, 0, 0, 0, 0, |
30923549 SB |
1290 | }, |
1291 | }, | |
1292 | .base_ext1 = { | |
1293 | .ant_div_control = 0, | |
420e2b1b RM |
1294 | .future = {0, 0, 0}, |
1295 | .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} | |
30923549 SB |
1296 | }, |
1297 | .calFreqPier2G = { | |
1298 | FREQ2FBIN(2412, 1), | |
1299 | FREQ2FBIN(2437, 1), | |
94e2ad9e | 1300 | FREQ2FBIN(2462, 1), |
30923549 SB |
1301 | }, |
1302 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
1303 | .calPierData2G = { | |
1304 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1305 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1306 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1307 | }, | |
1308 | .calTarget_freqbin_Cck = { | |
1309 | FREQ2FBIN(2412, 1), | |
94e2ad9e | 1310 | FREQ2FBIN(2472, 1), |
30923549 SB |
1311 | }, |
1312 | .calTarget_freqbin_2G = { | |
1313 | FREQ2FBIN(2412, 1), | |
1314 | FREQ2FBIN(2437, 1), | |
1315 | FREQ2FBIN(2472, 1) | |
1316 | }, | |
1317 | .calTarget_freqbin_2GHT20 = { | |
1318 | FREQ2FBIN(2412, 1), | |
1319 | FREQ2FBIN(2437, 1), | |
1320 | FREQ2FBIN(2472, 1) | |
1321 | }, | |
1322 | .calTarget_freqbin_2GHT40 = { | |
1323 | FREQ2FBIN(2412, 1), | |
1324 | FREQ2FBIN(2437, 1), | |
1325 | FREQ2FBIN(2472, 1) | |
1326 | }, | |
1327 | .calTargetPowerCck = { | |
1328 | /* 1L-5L,5S,11L,11S */ | |
1329 | { {34, 34, 34, 34} }, | |
1330 | { {34, 34, 34, 34} }, | |
1331 | }, | |
1332 | .calTargetPower2G = { | |
1333 | /* 6-24,36,48,54 */ | |
1334 | { {34, 34, 32, 32} }, | |
1335 | { {34, 34, 32, 32} }, | |
1336 | { {34, 34, 32, 32} }, | |
1337 | }, | |
1338 | .calTargetPower2GHT20 = { | |
1339 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, | |
1340 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, | |
1341 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, | |
1342 | }, | |
1343 | .calTargetPower2GHT40 = { | |
1344 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, | |
1345 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, | |
1346 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, | |
1347 | }, | |
1348 | .ctlIndex_2G = { | |
1349 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
1350 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
1351 | }, | |
1352 | .ctl_freqbin_2G = { | |
1353 | { | |
1354 | FREQ2FBIN(2412, 1), | |
1355 | FREQ2FBIN(2417, 1), | |
1356 | FREQ2FBIN(2457, 1), | |
1357 | FREQ2FBIN(2462, 1) | |
1358 | }, | |
1359 | { | |
1360 | FREQ2FBIN(2412, 1), | |
1361 | FREQ2FBIN(2417, 1), | |
1362 | FREQ2FBIN(2462, 1), | |
1363 | 0xFF, | |
1364 | }, | |
1365 | ||
1366 | { | |
1367 | FREQ2FBIN(2412, 1), | |
1368 | FREQ2FBIN(2417, 1), | |
1369 | FREQ2FBIN(2462, 1), | |
1370 | 0xFF, | |
1371 | }, | |
1372 | { | |
1373 | FREQ2FBIN(2422, 1), | |
1374 | FREQ2FBIN(2427, 1), | |
1375 | FREQ2FBIN(2447, 1), | |
1376 | FREQ2FBIN(2452, 1) | |
1377 | }, | |
1378 | ||
1379 | { | |
1380 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1381 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1382 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1383 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), | |
1384 | }, | |
1385 | ||
1386 | { | |
1387 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1388 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1389 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1390 | 0, | |
1391 | }, | |
1392 | ||
1393 | { | |
1394 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1395 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1396 | FREQ2FBIN(2472, 1), | |
1397 | 0, | |
1398 | }, | |
1399 | ||
1400 | { | |
1401 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
1402 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
1403 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
1404 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
1405 | }, | |
1406 | ||
1407 | { | |
1408 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1409 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1410 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1411 | }, | |
1412 | ||
1413 | { | |
1414 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1415 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1416 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1417 | 0 | |
1418 | }, | |
1419 | ||
1420 | { | |
1421 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
1422 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
1423 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
1424 | 0 | |
1425 | }, | |
1426 | ||
1427 | { | |
1428 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
1429 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
1430 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
1431 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
1432 | } | |
1433 | }, | |
1434 | .ctlPowerData_2G = { | |
fe6c7915 DM |
1435 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
1436 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
1437 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
30923549 | 1438 | |
81dc6760 | 1439 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, |
fe6c7915 DM |
1440 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
1441 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 1442 | |
fe6c7915 DM |
1443 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
1444 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
1445 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 1446 | |
fe6c7915 DM |
1447 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
1448 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
1449 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
30923549 SB |
1450 | }, |
1451 | .modalHeader5G = { | |
1452 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
1453 | .antCtrlCommon = LE32(0x220), | |
1454 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ | |
1455 | .antCtrlCommon2 = LE32(0x44444), | |
1456 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ | |
1457 | .antCtrlChain = { | |
1458 | LE16(0x150), LE16(0x150), LE16(0x150), | |
1459 | }, | |
1460 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ | |
1461 | .xatten1DB = {0, 0, 0}, | |
1462 | ||
1463 | /* | |
1464 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
1465 | * for merlin (0xa20c/b20c 16:12 | |
1466 | */ | |
1467 | .xatten1Margin = {0, 0, 0}, | |
1468 | .tempSlope = 45, | |
1469 | .voltSlope = 0, | |
1470 | /* spurChans spur channels in usual fbin coding format */ | |
1471 | .spurChans = {0, 0, 0, 0, 0}, | |
1472 | /* noiseFloorThreshCh Check if the register is per chain */ | |
1473 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
1474 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
1475 | .quick_drop = 0, | |
30923549 SB |
1476 | .xpaBiasLvl = 0, |
1477 | .txFrameToDataStart = 0x0e, | |
1478 | .txFrameToPaOn = 0x0e, | |
1479 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
1480 | .antennaGain = 0, | |
1481 | .switchSettling = 0x2d, | |
1482 | .adcDesiredSize = -30, | |
1483 | .txEndToXpaOff = 0, | |
1484 | .txEndToRxOn = 0x2, | |
1485 | .txFrameToXpaOn = 0xe, | |
1486 | .thresh62 = 28, | |
1487 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | |
1488 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
3e2ea543 | 1489 | .xlna_bias_strength = 0, |
30923549 | 1490 | .futureModal = { |
3e2ea543 | 1491 | 0, 0, 0, 0, 0, 0, 0, |
30923549 SB |
1492 | }, |
1493 | }, | |
1494 | .base_ext2 = { | |
1495 | .tempSlopeLow = 40, | |
1496 | .tempSlopeHigh = 50, | |
1497 | .xatten1DBLow = {0, 0, 0}, | |
1498 | .xatten1MarginLow = {0, 0, 0}, | |
1499 | .xatten1DBHigh = {0, 0, 0}, | |
1500 | .xatten1MarginHigh = {0, 0, 0} | |
1501 | }, | |
1502 | .calFreqPier5G = { | |
1503 | FREQ2FBIN(5180, 0), | |
1504 | FREQ2FBIN(5220, 0), | |
1505 | FREQ2FBIN(5320, 0), | |
1506 | FREQ2FBIN(5400, 0), | |
1507 | FREQ2FBIN(5500, 0), | |
1508 | FREQ2FBIN(5600, 0), | |
1509 | FREQ2FBIN(5700, 0), | |
94e2ad9e | 1510 | FREQ2FBIN(5785, 0) |
30923549 SB |
1511 | }, |
1512 | .calPierData5G = { | |
1513 | { | |
1514 | {0, 0, 0, 0, 0}, | |
1515 | {0, 0, 0, 0, 0}, | |
1516 | {0, 0, 0, 0, 0}, | |
1517 | {0, 0, 0, 0, 0}, | |
1518 | {0, 0, 0, 0, 0}, | |
1519 | {0, 0, 0, 0, 0}, | |
1520 | {0, 0, 0, 0, 0}, | |
1521 | {0, 0, 0, 0, 0}, | |
1522 | }, | |
1523 | { | |
1524 | {0, 0, 0, 0, 0}, | |
1525 | {0, 0, 0, 0, 0}, | |
1526 | {0, 0, 0, 0, 0}, | |
1527 | {0, 0, 0, 0, 0}, | |
1528 | {0, 0, 0, 0, 0}, | |
1529 | {0, 0, 0, 0, 0}, | |
1530 | {0, 0, 0, 0, 0}, | |
1531 | {0, 0, 0, 0, 0}, | |
1532 | }, | |
1533 | { | |
1534 | {0, 0, 0, 0, 0}, | |
1535 | {0, 0, 0, 0, 0}, | |
1536 | {0, 0, 0, 0, 0}, | |
1537 | {0, 0, 0, 0, 0}, | |
1538 | {0, 0, 0, 0, 0}, | |
1539 | {0, 0, 0, 0, 0}, | |
1540 | {0, 0, 0, 0, 0}, | |
1541 | {0, 0, 0, 0, 0}, | |
1542 | }, | |
1543 | ||
1544 | }, | |
1545 | .calTarget_freqbin_5G = { | |
1546 | FREQ2FBIN(5180, 0), | |
1547 | FREQ2FBIN(5240, 0), | |
1548 | FREQ2FBIN(5320, 0), | |
1549 | FREQ2FBIN(5400, 0), | |
1550 | FREQ2FBIN(5500, 0), | |
1551 | FREQ2FBIN(5600, 0), | |
1552 | FREQ2FBIN(5700, 0), | |
1553 | FREQ2FBIN(5825, 0) | |
1554 | }, | |
1555 | .calTarget_freqbin_5GHT20 = { | |
1556 | FREQ2FBIN(5180, 0), | |
1557 | FREQ2FBIN(5240, 0), | |
1558 | FREQ2FBIN(5320, 0), | |
1559 | FREQ2FBIN(5400, 0), | |
1560 | FREQ2FBIN(5500, 0), | |
1561 | FREQ2FBIN(5700, 0), | |
1562 | FREQ2FBIN(5745, 0), | |
1563 | FREQ2FBIN(5825, 0) | |
1564 | }, | |
1565 | .calTarget_freqbin_5GHT40 = { | |
1566 | FREQ2FBIN(5180, 0), | |
1567 | FREQ2FBIN(5240, 0), | |
1568 | FREQ2FBIN(5320, 0), | |
1569 | FREQ2FBIN(5400, 0), | |
1570 | FREQ2FBIN(5500, 0), | |
1571 | FREQ2FBIN(5700, 0), | |
1572 | FREQ2FBIN(5745, 0), | |
1573 | FREQ2FBIN(5825, 0) | |
1574 | }, | |
1575 | .calTargetPower5G = { | |
1576 | /* 6-24,36,48,54 */ | |
1577 | { {30, 30, 28, 24} }, | |
1578 | { {30, 30, 28, 24} }, | |
1579 | { {30, 30, 28, 24} }, | |
1580 | { {30, 30, 28, 24} }, | |
1581 | { {30, 30, 28, 24} }, | |
1582 | { {30, 30, 28, 24} }, | |
1583 | { {30, 30, 28, 24} }, | |
1584 | { {30, 30, 28, 24} }, | |
1585 | }, | |
1586 | .calTargetPower5GHT20 = { | |
1587 | /* | |
1588 | * 0_8_16,1-3_9-11_17-19, | |
1589 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
1590 | */ | |
1591 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, | |
1592 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, | |
1593 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, | |
1594 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, | |
1595 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, | |
1596 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, | |
1597 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, | |
1598 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, | |
1599 | }, | |
1600 | .calTargetPower5GHT40 = { | |
1601 | /* | |
1602 | * 0_8_16,1-3_9-11_17-19, | |
1603 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
1604 | */ | |
1605 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, | |
1606 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, | |
1607 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, | |
1608 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, | |
1609 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, | |
1610 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, | |
1611 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, | |
1612 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, | |
1613 | }, | |
1614 | .ctlIndex_5G = { | |
1615 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
1616 | 0x48, 0x30, 0x36, 0x38 | |
1617 | }, | |
1618 | .ctl_freqbin_5G = { | |
1619 | { | |
1620 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1621 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1622 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
1623 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1624 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), | |
1625 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1626 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1627 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1628 | }, | |
1629 | { | |
1630 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1631 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1632 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
1633 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1634 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), | |
1635 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1636 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1637 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1638 | }, | |
1639 | ||
1640 | { | |
1641 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1642 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
1643 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
1644 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), | |
1645 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), | |
1646 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), | |
1647 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), | |
1648 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) | |
1649 | }, | |
1650 | ||
1651 | { | |
1652 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1653 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
1654 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), | |
1655 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), | |
1656 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
1657 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1658 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, | |
1659 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, | |
1660 | }, | |
1661 | ||
1662 | { | |
1663 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1664 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1665 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), | |
1666 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), | |
1667 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, | |
1668 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, | |
1669 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, | |
1670 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, | |
1671 | }, | |
1672 | ||
1673 | { | |
1674 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1675 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), | |
1676 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), | |
1677 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
1678 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), | |
1679 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
1680 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, | |
1681 | /* Data[5].ctlEdges[7].bChannel */ 0xFF | |
1682 | }, | |
1683 | ||
1684 | { | |
1685 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1686 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
1687 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), | |
1688 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), | |
1689 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
1690 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), | |
1691 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), | |
1692 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) | |
1693 | }, | |
1694 | ||
1695 | { | |
1696 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
1697 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
1698 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), | |
1699 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
1700 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), | |
1701 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
1702 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
1703 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
1704 | }, | |
1705 | ||
1706 | { | |
1707 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
1708 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
1709 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
1710 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
1711 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), | |
1712 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
1713 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), | |
1714 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) | |
1715 | } | |
1716 | }, | |
1717 | .ctlPowerData_5G = { | |
1718 | { | |
1719 | { | |
fe6c7915 DM |
1720 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1721 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1722 | } |
1723 | }, | |
1724 | { | |
1725 | { | |
fe6c7915 DM |
1726 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1727 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1728 | } |
1729 | }, | |
1730 | { | |
1731 | { | |
fe6c7915 DM |
1732 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
1733 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
1734 | } |
1735 | }, | |
1736 | { | |
1737 | { | |
fe6c7915 DM |
1738 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
1739 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1740 | } |
1741 | }, | |
1742 | { | |
1743 | { | |
fe6c7915 DM |
1744 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
1745 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1746 | } |
1747 | }, | |
1748 | { | |
1749 | { | |
fe6c7915 DM |
1750 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1751 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
1752 | } |
1753 | }, | |
1754 | { | |
1755 | { | |
fe6c7915 DM |
1756 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
1757 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
1758 | } |
1759 | }, | |
1760 | { | |
1761 | { | |
fe6c7915 DM |
1762 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
1763 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
1764 | } |
1765 | }, | |
1766 | { | |
1767 | { | |
fe6c7915 DM |
1768 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
1769 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
30923549 SB |
1770 | } |
1771 | }, | |
1772 | } | |
1773 | }; | |
1774 | ||
1775 | ||
1776 | static const struct ar9300_eeprom ar9300_x112 = { | |
1777 | .eepromVersion = 2, | |
1778 | .templateVersion = 5, | |
1779 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, | |
1780 | .custData = {"x112-041-f0000"}, | |
1781 | .baseEepHeader = { | |
1782 | .regDmn = { LE16(0), LE16(0x1f) }, | |
1783 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | |
1784 | .opCapFlags = { | |
4ddfcd7d | 1785 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
30923549 SB |
1786 | .eepMisc = 0, |
1787 | }, | |
1788 | .rfSilent = 0, | |
1789 | .blueToothOptions = 0, | |
1790 | .deviceCap = 0, | |
1791 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
1792 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
1793 | .params_for_tuning_caps = {0, 0}, | |
1794 | .featureEnable = 0x0d, | |
1795 | /* | |
1796 | * bit0 - enable tx temp comp - disabled | |
1797 | * bit1 - enable tx volt comp - disabled | |
1798 | * bit2 - enable fastclock - enabled | |
1799 | * bit3 - enable doubling - enabled | |
1800 | * bit4 - enable internal regulator - disabled | |
1801 | * bit5 - enable pa predistortion - disabled | |
1802 | */ | |
1803 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
1804 | .eepromWriteEnableGpio = 6, | |
1805 | .wlanDisableGpio = 0, | |
1806 | .wlanLedGpio = 8, | |
1807 | .rxBandSelectGpio = 0xff, | |
1808 | .txrxgain = 0x0, | |
1809 | .swreg = 0, | |
1810 | }, | |
1811 | .modalHeader2G = { | |
1812 | /* ar9300_modal_eep_header 2g */ | |
1813 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
1814 | .antCtrlCommon = LE32(0x110), | |
1815 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ | |
1816 | .antCtrlCommon2 = LE32(0x22222), | |
1817 | ||
1818 | /* | |
1819 | * antCtrlChain[ar9300_max_chains]; 6 idle, t, r, | |
1820 | * rx1, rx12, b (2 bits each) | |
1821 | */ | |
1822 | .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, | |
1823 | ||
1824 | /* | |
1825 | * xatten1DB[AR9300_max_chains]; 3 xatten1_db | |
1826 | * for ar9280 (0xa20c/b20c 5:0) | |
1827 | */ | |
1828 | .xatten1DB = {0x1b, 0x1b, 0x1b}, | |
1829 | ||
1830 | /* | |
1831 | * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin | |
1832 | * for ar9280 (0xa20c/b20c 16:12 | |
1833 | */ | |
1834 | .xatten1Margin = {0x15, 0x15, 0x15}, | |
1835 | .tempSlope = 50, | |
1836 | .voltSlope = 0, | |
1837 | ||
1838 | /* | |
1839 | * spurChans[OSPrey_eeprom_modal_sPURS]; spur | |
1840 | * channels in usual fbin coding format | |
1841 | */ | |
1842 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, | |
1843 | ||
1844 | /* | |
1845 | * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check | |
1846 | * if the register is per chain | |
1847 | */ | |
1848 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
1849 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
1850 | .quick_drop = 0, | |
30923549 SB |
1851 | .xpaBiasLvl = 0, |
1852 | .txFrameToDataStart = 0x0e, | |
1853 | .txFrameToPaOn = 0x0e, | |
1854 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
1855 | .antennaGain = 0, | |
1856 | .switchSettling = 0x2c, | |
1857 | .adcDesiredSize = -30, | |
1858 | .txEndToXpaOff = 0, | |
1859 | .txEndToRxOn = 0x2, | |
1860 | .txFrameToXpaOn = 0xe, | |
1861 | .thresh62 = 28, | |
1862 | .papdRateMaskHt20 = LE32(0x0c80c080), | |
1863 | .papdRateMaskHt40 = LE32(0x0080c080), | |
3e2ea543 | 1864 | .xlna_bias_strength = 0, |
30923549 | 1865 | .futureModal = { |
3e2ea543 | 1866 | 0, 0, 0, 0, 0, 0, 0, |
30923549 SB |
1867 | }, |
1868 | }, | |
1869 | .base_ext1 = { | |
1870 | .ant_div_control = 0, | |
420e2b1b RM |
1871 | .future = {0, 0, 0}, |
1872 | .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} | |
30923549 SB |
1873 | }, |
1874 | .calFreqPier2G = { | |
1875 | FREQ2FBIN(2412, 1), | |
1876 | FREQ2FBIN(2437, 1), | |
1877 | FREQ2FBIN(2472, 1), | |
1878 | }, | |
1879 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
1880 | .calPierData2G = { | |
1881 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1882 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1883 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
1884 | }, | |
1885 | .calTarget_freqbin_Cck = { | |
1886 | FREQ2FBIN(2412, 1), | |
1887 | FREQ2FBIN(2472, 1), | |
1888 | }, | |
1889 | .calTarget_freqbin_2G = { | |
1890 | FREQ2FBIN(2412, 1), | |
1891 | FREQ2FBIN(2437, 1), | |
1892 | FREQ2FBIN(2472, 1) | |
1893 | }, | |
1894 | .calTarget_freqbin_2GHT20 = { | |
1895 | FREQ2FBIN(2412, 1), | |
1896 | FREQ2FBIN(2437, 1), | |
1897 | FREQ2FBIN(2472, 1) | |
1898 | }, | |
1899 | .calTarget_freqbin_2GHT40 = { | |
1900 | FREQ2FBIN(2412, 1), | |
1901 | FREQ2FBIN(2437, 1), | |
1902 | FREQ2FBIN(2472, 1) | |
1903 | }, | |
1904 | .calTargetPowerCck = { | |
1905 | /* 1L-5L,5S,11L,11s */ | |
1906 | { {38, 38, 38, 38} }, | |
1907 | { {38, 38, 38, 38} }, | |
1908 | }, | |
1909 | .calTargetPower2G = { | |
1910 | /* 6-24,36,48,54 */ | |
1911 | { {38, 38, 36, 34} }, | |
1912 | { {38, 38, 36, 34} }, | |
1913 | { {38, 38, 34, 32} }, | |
1914 | }, | |
1915 | .calTargetPower2GHT20 = { | |
1916 | { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, | |
1917 | { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} }, | |
1918 | { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, | |
1919 | }, | |
1920 | .calTargetPower2GHT40 = { | |
1921 | { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, | |
1922 | { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} }, | |
1923 | { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, | |
1924 | }, | |
1925 | .ctlIndex_2G = { | |
1926 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
1927 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
1928 | }, | |
1929 | .ctl_freqbin_2G = { | |
1930 | { | |
1931 | FREQ2FBIN(2412, 1), | |
1932 | FREQ2FBIN(2417, 1), | |
1933 | FREQ2FBIN(2457, 1), | |
1934 | FREQ2FBIN(2462, 1) | |
1935 | }, | |
1936 | { | |
1937 | FREQ2FBIN(2412, 1), | |
1938 | FREQ2FBIN(2417, 1), | |
1939 | FREQ2FBIN(2462, 1), | |
1940 | 0xFF, | |
1941 | }, | |
1942 | ||
1943 | { | |
1944 | FREQ2FBIN(2412, 1), | |
1945 | FREQ2FBIN(2417, 1), | |
1946 | FREQ2FBIN(2462, 1), | |
1947 | 0xFF, | |
1948 | }, | |
1949 | { | |
1950 | FREQ2FBIN(2422, 1), | |
1951 | FREQ2FBIN(2427, 1), | |
1952 | FREQ2FBIN(2447, 1), | |
1953 | FREQ2FBIN(2452, 1) | |
1954 | }, | |
1955 | ||
1956 | { | |
1957 | /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1958 | /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
1959 | /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
1960 | /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1), | |
1961 | }, | |
1962 | ||
1963 | { | |
1964 | /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1965 | /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
1966 | /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
1967 | 0, | |
1968 | }, | |
1969 | ||
1970 | { | |
1971 | /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1972 | /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
1973 | FREQ2FBIN(2472, 1), | |
1974 | 0, | |
1975 | }, | |
1976 | ||
1977 | { | |
1978 | /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), | |
1979 | /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), | |
1980 | /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), | |
1981 | /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), | |
1982 | }, | |
1983 | ||
1984 | { | |
1985 | /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1986 | /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
1987 | /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
1988 | }, | |
1989 | ||
1990 | { | |
1991 | /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1992 | /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
1993 | /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
1994 | 0 | |
1995 | }, | |
1996 | ||
1997 | { | |
1998 | /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), | |
1999 | /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), | |
2000 | /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), | |
2001 | 0 | |
2002 | }, | |
2003 | ||
2004 | { | |
2005 | /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), | |
2006 | /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), | |
2007 | /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), | |
2008 | /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), | |
2009 | } | |
2010 | }, | |
2011 | .ctlPowerData_2G = { | |
fe6c7915 DM |
2012 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2013 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2014 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
30923549 | 2015 | |
15052f81 | 2016 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, |
fe6c7915 DM |
2017 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2018 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 2019 | |
fe6c7915 DM |
2020 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
2021 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2022 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 2023 | |
fe6c7915 DM |
2024 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2025 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
2026 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
30923549 SB |
2027 | }, |
2028 | .modalHeader5G = { | |
2029 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
2030 | .antCtrlCommon = LE32(0x110), | |
2031 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ | |
2032 | .antCtrlCommon2 = LE32(0x22222), | |
2033 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ | |
2034 | .antCtrlChain = { | |
2035 | LE16(0x0), LE16(0x0), LE16(0x0), | |
2036 | }, | |
2037 | /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */ | |
2038 | .xatten1DB = {0x13, 0x19, 0x17}, | |
2039 | ||
2040 | /* | |
2041 | * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin | |
2042 | * for merlin (0xa20c/b20c 16:12 | |
2043 | */ | |
2044 | .xatten1Margin = {0x19, 0x19, 0x19}, | |
2045 | .tempSlope = 70, | |
2046 | .voltSlope = 15, | |
2047 | /* spurChans spur channels in usual fbin coding format */ | |
2048 | .spurChans = {0, 0, 0, 0, 0}, | |
2049 | /* noiseFloorThreshch check if the register is per chain */ | |
2050 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
2051 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
2052 | .quick_drop = 0, | |
30923549 SB |
2053 | .xpaBiasLvl = 0, |
2054 | .txFrameToDataStart = 0x0e, | |
2055 | .txFrameToPaOn = 0x0e, | |
2056 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
2057 | .antennaGain = 0, | |
2058 | .switchSettling = 0x2d, | |
2059 | .adcDesiredSize = -30, | |
2060 | .txEndToXpaOff = 0, | |
2061 | .txEndToRxOn = 0x2, | |
2062 | .txFrameToXpaOn = 0xe, | |
2063 | .thresh62 = 28, | |
2064 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | |
2065 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
3e2ea543 | 2066 | .xlna_bias_strength = 0, |
30923549 | 2067 | .futureModal = { |
3e2ea543 | 2068 | 0, 0, 0, 0, 0, 0, 0, |
30923549 SB |
2069 | }, |
2070 | }, | |
2071 | .base_ext2 = { | |
2072 | .tempSlopeLow = 72, | |
2073 | .tempSlopeHigh = 105, | |
2074 | .xatten1DBLow = {0x10, 0x14, 0x10}, | |
2075 | .xatten1MarginLow = {0x19, 0x19 , 0x19}, | |
2076 | .xatten1DBHigh = {0x1d, 0x20, 0x24}, | |
2077 | .xatten1MarginHigh = {0x10, 0x10, 0x10} | |
2078 | }, | |
2079 | .calFreqPier5G = { | |
2080 | FREQ2FBIN(5180, 0), | |
2081 | FREQ2FBIN(5220, 0), | |
2082 | FREQ2FBIN(5320, 0), | |
2083 | FREQ2FBIN(5400, 0), | |
2084 | FREQ2FBIN(5500, 0), | |
2085 | FREQ2FBIN(5600, 0), | |
2086 | FREQ2FBIN(5700, 0), | |
2087 | FREQ2FBIN(5785, 0) | |
2088 | }, | |
2089 | .calPierData5G = { | |
2090 | { | |
2091 | {0, 0, 0, 0, 0}, | |
2092 | {0, 0, 0, 0, 0}, | |
2093 | {0, 0, 0, 0, 0}, | |
2094 | {0, 0, 0, 0, 0}, | |
2095 | {0, 0, 0, 0, 0}, | |
2096 | {0, 0, 0, 0, 0}, | |
2097 | {0, 0, 0, 0, 0}, | |
2098 | {0, 0, 0, 0, 0}, | |
2099 | }, | |
2100 | { | |
2101 | {0, 0, 0, 0, 0}, | |
2102 | {0, 0, 0, 0, 0}, | |
2103 | {0, 0, 0, 0, 0}, | |
2104 | {0, 0, 0, 0, 0}, | |
2105 | {0, 0, 0, 0, 0}, | |
2106 | {0, 0, 0, 0, 0}, | |
2107 | {0, 0, 0, 0, 0}, | |
2108 | {0, 0, 0, 0, 0}, | |
2109 | }, | |
2110 | { | |
2111 | {0, 0, 0, 0, 0}, | |
2112 | {0, 0, 0, 0, 0}, | |
2113 | {0, 0, 0, 0, 0}, | |
2114 | {0, 0, 0, 0, 0}, | |
2115 | {0, 0, 0, 0, 0}, | |
2116 | {0, 0, 0, 0, 0}, | |
2117 | {0, 0, 0, 0, 0}, | |
2118 | {0, 0, 0, 0, 0}, | |
2119 | }, | |
2120 | ||
2121 | }, | |
2122 | .calTarget_freqbin_5G = { | |
2123 | FREQ2FBIN(5180, 0), | |
2124 | FREQ2FBIN(5220, 0), | |
2125 | FREQ2FBIN(5320, 0), | |
2126 | FREQ2FBIN(5400, 0), | |
2127 | FREQ2FBIN(5500, 0), | |
2128 | FREQ2FBIN(5600, 0), | |
2129 | FREQ2FBIN(5725, 0), | |
2130 | FREQ2FBIN(5825, 0) | |
2131 | }, | |
2132 | .calTarget_freqbin_5GHT20 = { | |
2133 | FREQ2FBIN(5180, 0), | |
2134 | FREQ2FBIN(5220, 0), | |
2135 | FREQ2FBIN(5320, 0), | |
2136 | FREQ2FBIN(5400, 0), | |
2137 | FREQ2FBIN(5500, 0), | |
2138 | FREQ2FBIN(5600, 0), | |
2139 | FREQ2FBIN(5725, 0), | |
2140 | FREQ2FBIN(5825, 0) | |
2141 | }, | |
2142 | .calTarget_freqbin_5GHT40 = { | |
2143 | FREQ2FBIN(5180, 0), | |
2144 | FREQ2FBIN(5220, 0), | |
2145 | FREQ2FBIN(5320, 0), | |
2146 | FREQ2FBIN(5400, 0), | |
2147 | FREQ2FBIN(5500, 0), | |
2148 | FREQ2FBIN(5600, 0), | |
2149 | FREQ2FBIN(5725, 0), | |
2150 | FREQ2FBIN(5825, 0) | |
2151 | }, | |
2152 | .calTargetPower5G = { | |
2153 | /* 6-24,36,48,54 */ | |
2154 | { {32, 32, 28, 26} }, | |
2155 | { {32, 32, 28, 26} }, | |
2156 | { {32, 32, 28, 26} }, | |
2157 | { {32, 32, 26, 24} }, | |
2158 | { {32, 32, 26, 24} }, | |
2159 | { {32, 32, 24, 22} }, | |
2160 | { {30, 30, 24, 22} }, | |
2161 | { {30, 30, 24, 22} }, | |
2162 | }, | |
2163 | .calTargetPower5GHT20 = { | |
2164 | /* | |
2165 | * 0_8_16,1-3_9-11_17-19, | |
2166 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
2167 | */ | |
2168 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, | |
2169 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, | |
2170 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, | |
2171 | { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} }, | |
2172 | { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} }, | |
2173 | { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} }, | |
2174 | { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, | |
2175 | { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, | |
2176 | }, | |
2177 | .calTargetPower5GHT40 = { | |
2178 | /* | |
2179 | * 0_8_16,1-3_9-11_17-19, | |
2180 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
2181 | */ | |
2182 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, | |
2183 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, | |
2184 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, | |
2185 | { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} }, | |
2186 | { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} }, | |
2187 | { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, | |
2188 | { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, | |
2189 | { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, | |
2190 | }, | |
2191 | .ctlIndex_5G = { | |
2192 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
2193 | 0x48, 0x30, 0x36, 0x38 | |
2194 | }, | |
2195 | .ctl_freqbin_5G = { | |
2196 | { | |
2197 | /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2198 | /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), | |
2199 | /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), | |
2200 | /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), | |
2201 | /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0), | |
2202 | /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), | |
2203 | /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), | |
2204 | /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) | |
2205 | }, | |
2206 | { | |
2207 | /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2208 | /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), | |
2209 | /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), | |
2210 | /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), | |
2211 | /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0), | |
2212 | /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), | |
2213 | /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), | |
2214 | /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) | |
2215 | }, | |
2216 | ||
2217 | { | |
2218 | /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), | |
2219 | /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), | |
2220 | /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), | |
2221 | /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0), | |
2222 | /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0), | |
2223 | /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0), | |
2224 | /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0), | |
2225 | /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0) | |
2226 | }, | |
2227 | ||
2228 | { | |
2229 | /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2230 | /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), | |
2231 | /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0), | |
2232 | /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0), | |
2233 | /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), | |
2234 | /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), | |
2235 | /* Data[3].ctledges[6].bchannel */ 0xFF, | |
2236 | /* Data[3].ctledges[7].bchannel */ 0xFF, | |
2237 | }, | |
2238 | ||
2239 | { | |
2240 | /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2241 | /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), | |
2242 | /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0), | |
2243 | /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0), | |
2244 | /* Data[4].ctledges[4].bchannel */ 0xFF, | |
2245 | /* Data[4].ctledges[5].bchannel */ 0xFF, | |
2246 | /* Data[4].ctledges[6].bchannel */ 0xFF, | |
2247 | /* Data[4].ctledges[7].bchannel */ 0xFF, | |
2248 | }, | |
2249 | ||
2250 | { | |
2251 | /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), | |
2252 | /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0), | |
2253 | /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0), | |
2254 | /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), | |
2255 | /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0), | |
2256 | /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), | |
2257 | /* Data[5].ctledges[6].bchannel */ 0xFF, | |
2258 | /* Data[5].ctledges[7].bchannel */ 0xFF | |
2259 | }, | |
2260 | ||
2261 | { | |
2262 | /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2263 | /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), | |
2264 | /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0), | |
2265 | /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0), | |
2266 | /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), | |
2267 | /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0), | |
2268 | /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0), | |
2269 | /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0) | |
2270 | }, | |
2271 | ||
2272 | { | |
2273 | /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), | |
2274 | /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), | |
2275 | /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0), | |
2276 | /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), | |
2277 | /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0), | |
2278 | /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), | |
2279 | /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), | |
2280 | /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) | |
2281 | }, | |
2282 | ||
2283 | { | |
2284 | /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), | |
2285 | /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), | |
2286 | /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), | |
2287 | /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), | |
2288 | /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0), | |
2289 | /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), | |
2290 | /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0), | |
2291 | /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0) | |
2292 | } | |
2293 | }, | |
2294 | .ctlPowerData_5G = { | |
2295 | { | |
2296 | { | |
fe6c7915 DM |
2297 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2298 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2299 | } |
2300 | }, | |
2301 | { | |
2302 | { | |
fe6c7915 DM |
2303 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2304 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2305 | } |
2306 | }, | |
2307 | { | |
2308 | { | |
fe6c7915 DM |
2309 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
2310 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
2311 | } |
2312 | }, | |
2313 | { | |
2314 | { | |
fe6c7915 DM |
2315 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
2316 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2317 | } |
2318 | }, | |
2319 | { | |
2320 | { | |
fe6c7915 DM |
2321 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
2322 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2323 | } |
2324 | }, | |
2325 | { | |
2326 | { | |
fe6c7915 DM |
2327 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2328 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2329 | } |
2330 | }, | |
2331 | { | |
2332 | { | |
fe6c7915 DM |
2333 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2334 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
2335 | } |
2336 | }, | |
2337 | { | |
2338 | { | |
fe6c7915 DM |
2339 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
2340 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2341 | } |
2342 | }, | |
2343 | { | |
2344 | { | |
fe6c7915 DM |
2345 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
2346 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
30923549 SB |
2347 | } |
2348 | }, | |
2349 | } | |
2350 | }; | |
2351 | ||
2352 | static const struct ar9300_eeprom ar9300_h116 = { | |
2353 | .eepromVersion = 2, | |
2354 | .templateVersion = 4, | |
2355 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, | |
2356 | .custData = {"h116-041-f0000"}, | |
2357 | .baseEepHeader = { | |
2358 | .regDmn = { LE16(0), LE16(0x1f) }, | |
2359 | .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */ | |
2360 | .opCapFlags = { | |
4ddfcd7d | 2361 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
30923549 SB |
2362 | .eepMisc = 0, |
2363 | }, | |
2364 | .rfSilent = 0, | |
2365 | .blueToothOptions = 0, | |
2366 | .deviceCap = 0, | |
2367 | .deviceType = 5, /* takes lower byte in eeprom location */ | |
2368 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, | |
2369 | .params_for_tuning_caps = {0, 0}, | |
2370 | .featureEnable = 0x0d, | |
2371 | /* | |
2372 | * bit0 - enable tx temp comp - disabled | |
2373 | * bit1 - enable tx volt comp - disabled | |
2374 | * bit2 - enable fastClock - enabled | |
2375 | * bit3 - enable doubling - enabled | |
2376 | * bit4 - enable internal regulator - disabled | |
2377 | * bit5 - enable pa predistortion - disabled | |
2378 | */ | |
2379 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ | |
2380 | .eepromWriteEnableGpio = 6, | |
2381 | .wlanDisableGpio = 0, | |
2382 | .wlanLedGpio = 8, | |
2383 | .rxBandSelectGpio = 0xff, | |
2384 | .txrxgain = 0x10, | |
2385 | .swreg = 0, | |
2386 | }, | |
2387 | .modalHeader2G = { | |
2388 | /* ar9300_modal_eep_header 2g */ | |
2389 | /* 4 idle,t1,t2,b(4 bits per setting) */ | |
2390 | .antCtrlCommon = LE32(0x110), | |
2391 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ | |
2392 | .antCtrlCommon2 = LE32(0x44444), | |
2393 | ||
2394 | /* | |
2395 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, | |
2396 | * rx1, rx12, b (2 bits each) | |
2397 | */ | |
2398 | .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, | |
2399 | ||
2400 | /* | |
2401 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db | |
2402 | * for ar9280 (0xa20c/b20c 5:0) | |
2403 | */ | |
2404 | .xatten1DB = {0x1f, 0x1f, 0x1f}, | |
2405 | ||
2406 | /* | |
2407 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
2408 | * for ar9280 (0xa20c/b20c 16:12 | |
2409 | */ | |
2410 | .xatten1Margin = {0x12, 0x12, 0x12}, | |
2411 | .tempSlope = 25, | |
2412 | .voltSlope = 0, | |
2413 | ||
2414 | /* | |
2415 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur | |
2416 | * channels in usual fbin coding format | |
2417 | */ | |
2418 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, | |
2419 | ||
2420 | /* | |
2421 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check | |
2422 | * if the register is per chain | |
2423 | */ | |
2424 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
2425 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
2426 | .quick_drop = 0, | |
30923549 SB |
2427 | .xpaBiasLvl = 0, |
2428 | .txFrameToDataStart = 0x0e, | |
2429 | .txFrameToPaOn = 0x0e, | |
2430 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
2431 | .antennaGain = 0, | |
2432 | .switchSettling = 0x2c, | |
2433 | .adcDesiredSize = -30, | |
2434 | .txEndToXpaOff = 0, | |
2435 | .txEndToRxOn = 0x2, | |
2436 | .txFrameToXpaOn = 0xe, | |
2437 | .thresh62 = 28, | |
2438 | .papdRateMaskHt20 = LE32(0x0c80C080), | |
2439 | .papdRateMaskHt40 = LE32(0x0080C080), | |
3e2ea543 | 2440 | .xlna_bias_strength = 0, |
30923549 | 2441 | .futureModal = { |
3e2ea543 | 2442 | 0, 0, 0, 0, 0, 0, 0, |
30923549 SB |
2443 | }, |
2444 | }, | |
2445 | .base_ext1 = { | |
2446 | .ant_div_control = 0, | |
420e2b1b RM |
2447 | .future = {0, 0, 0}, |
2448 | .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} | |
30923549 SB |
2449 | }, |
2450 | .calFreqPier2G = { | |
2451 | FREQ2FBIN(2412, 1), | |
2452 | FREQ2FBIN(2437, 1), | |
94e2ad9e | 2453 | FREQ2FBIN(2462, 1), |
30923549 SB |
2454 | }, |
2455 | /* ar9300_cal_data_per_freq_op_loop 2g */ | |
2456 | .calPierData2G = { | |
2457 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
2458 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
2459 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, | |
2460 | }, | |
2461 | .calTarget_freqbin_Cck = { | |
2462 | FREQ2FBIN(2412, 1), | |
2463 | FREQ2FBIN(2472, 1), | |
2464 | }, | |
2465 | .calTarget_freqbin_2G = { | |
2466 | FREQ2FBIN(2412, 1), | |
2467 | FREQ2FBIN(2437, 1), | |
2468 | FREQ2FBIN(2472, 1) | |
2469 | }, | |
2470 | .calTarget_freqbin_2GHT20 = { | |
2471 | FREQ2FBIN(2412, 1), | |
2472 | FREQ2FBIN(2437, 1), | |
2473 | FREQ2FBIN(2472, 1) | |
2474 | }, | |
2475 | .calTarget_freqbin_2GHT40 = { | |
2476 | FREQ2FBIN(2412, 1), | |
2477 | FREQ2FBIN(2437, 1), | |
2478 | FREQ2FBIN(2472, 1) | |
2479 | }, | |
2480 | .calTargetPowerCck = { | |
2481 | /* 1L-5L,5S,11L,11S */ | |
2482 | { {34, 34, 34, 34} }, | |
2483 | { {34, 34, 34, 34} }, | |
2484 | }, | |
2485 | .calTargetPower2G = { | |
2486 | /* 6-24,36,48,54 */ | |
2487 | { {34, 34, 32, 32} }, | |
2488 | { {34, 34, 32, 32} }, | |
2489 | { {34, 34, 32, 32} }, | |
2490 | }, | |
2491 | .calTargetPower2GHT20 = { | |
2492 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
2493 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
2494 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, | |
2495 | }, | |
2496 | .calTargetPower2GHT40 = { | |
2497 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
2498 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
2499 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, | |
2500 | }, | |
2501 | .ctlIndex_2G = { | |
2502 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, | |
2503 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, | |
2504 | }, | |
2505 | .ctl_freqbin_2G = { | |
2506 | { | |
2507 | FREQ2FBIN(2412, 1), | |
2508 | FREQ2FBIN(2417, 1), | |
2509 | FREQ2FBIN(2457, 1), | |
2510 | FREQ2FBIN(2462, 1) | |
2511 | }, | |
2512 | { | |
2513 | FREQ2FBIN(2412, 1), | |
2514 | FREQ2FBIN(2417, 1), | |
2515 | FREQ2FBIN(2462, 1), | |
2516 | 0xFF, | |
2517 | }, | |
2518 | ||
2519 | { | |
2520 | FREQ2FBIN(2412, 1), | |
2521 | FREQ2FBIN(2417, 1), | |
2522 | FREQ2FBIN(2462, 1), | |
2523 | 0xFF, | |
2524 | }, | |
2525 | { | |
2526 | FREQ2FBIN(2422, 1), | |
2527 | FREQ2FBIN(2427, 1), | |
2528 | FREQ2FBIN(2447, 1), | |
2529 | FREQ2FBIN(2452, 1) | |
2530 | }, | |
2531 | ||
2532 | { | |
2533 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2534 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2535 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2536 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), | |
2537 | }, | |
2538 | ||
2539 | { | |
2540 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2541 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2542 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2543 | 0, | |
2544 | }, | |
2545 | ||
2546 | { | |
2547 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2548 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2549 | FREQ2FBIN(2472, 1), | |
2550 | 0, | |
2551 | }, | |
2552 | ||
2553 | { | |
2554 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
2555 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
2556 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
2557 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
2558 | }, | |
2559 | ||
2560 | { | |
2561 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2562 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2563 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2564 | }, | |
2565 | ||
2566 | { | |
2567 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2568 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2569 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2570 | 0 | |
2571 | }, | |
2572 | ||
2573 | { | |
2574 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), | |
2575 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), | |
2576 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), | |
2577 | 0 | |
2578 | }, | |
2579 | ||
2580 | { | |
2581 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), | |
2582 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), | |
2583 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), | |
2584 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), | |
2585 | } | |
2586 | }, | |
2587 | .ctlPowerData_2G = { | |
e702ba18 FF |
2588 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2589 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2590 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, | |
30923549 | 2591 | |
81dc6760 | 2592 | { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, |
e702ba18 FF |
2593 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2594 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 2595 | |
e702ba18 FF |
2596 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, |
2597 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
2598 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, | |
30923549 | 2599 | |
e702ba18 FF |
2600 | { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, |
2601 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
2602 | { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, | |
30923549 SB |
2603 | }, |
2604 | .modalHeader5G = { | |
2605 | /* 4 idle,t1,t2,b (4 bits per setting) */ | |
2606 | .antCtrlCommon = LE32(0x220), | |
2607 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ | |
2608 | .antCtrlCommon2 = LE32(0x44444), | |
2609 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ | |
2610 | .antCtrlChain = { | |
2611 | LE16(0x150), LE16(0x150), LE16(0x150), | |
2612 | }, | |
2613 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ | |
2614 | .xatten1DB = {0x19, 0x19, 0x19}, | |
2615 | ||
2616 | /* | |
2617 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin | |
2618 | * for merlin (0xa20c/b20c 16:12 | |
2619 | */ | |
2620 | .xatten1Margin = {0x14, 0x14, 0x14}, | |
2621 | .tempSlope = 70, | |
2622 | .voltSlope = 0, | |
2623 | /* spurChans spur channels in usual fbin coding format */ | |
2624 | .spurChans = {0, 0, 0, 0, 0}, | |
2625 | /* noiseFloorThreshCh Check if the register is per chain */ | |
2626 | .noiseFloorThreshCh = {-1, 0, 0}, | |
df222edc RM |
2627 | .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
2628 | .quick_drop = 0, | |
30923549 SB |
2629 | .xpaBiasLvl = 0, |
2630 | .txFrameToDataStart = 0x0e, | |
2631 | .txFrameToPaOn = 0x0e, | |
2632 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ | |
2633 | .antennaGain = 0, | |
2634 | .switchSettling = 0x2d, | |
2635 | .adcDesiredSize = -30, | |
2636 | .txEndToXpaOff = 0, | |
2637 | .txEndToRxOn = 0x2, | |
2638 | .txFrameToXpaOn = 0xe, | |
2639 | .thresh62 = 28, | |
2640 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), | |
2641 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), | |
3e2ea543 | 2642 | .xlna_bias_strength = 0, |
30923549 | 2643 | .futureModal = { |
3e2ea543 | 2644 | 0, 0, 0, 0, 0, 0, 0, |
30923549 SB |
2645 | }, |
2646 | }, | |
2647 | .base_ext2 = { | |
2648 | .tempSlopeLow = 35, | |
2649 | .tempSlopeHigh = 50, | |
2650 | .xatten1DBLow = {0, 0, 0}, | |
2651 | .xatten1MarginLow = {0, 0, 0}, | |
2652 | .xatten1DBHigh = {0, 0, 0}, | |
2653 | .xatten1MarginHigh = {0, 0, 0} | |
2654 | }, | |
2655 | .calFreqPier5G = { | |
94e2ad9e | 2656 | FREQ2FBIN(5160, 0), |
30923549 SB |
2657 | FREQ2FBIN(5220, 0), |
2658 | FREQ2FBIN(5320, 0), | |
2659 | FREQ2FBIN(5400, 0), | |
2660 | FREQ2FBIN(5500, 0), | |
2661 | FREQ2FBIN(5600, 0), | |
2662 | FREQ2FBIN(5700, 0), | |
2663 | FREQ2FBIN(5785, 0) | |
2664 | }, | |
2665 | .calPierData5G = { | |
2666 | { | |
2667 | {0, 0, 0, 0, 0}, | |
2668 | {0, 0, 0, 0, 0}, | |
2669 | {0, 0, 0, 0, 0}, | |
2670 | {0, 0, 0, 0, 0}, | |
2671 | {0, 0, 0, 0, 0}, | |
2672 | {0, 0, 0, 0, 0}, | |
2673 | {0, 0, 0, 0, 0}, | |
2674 | {0, 0, 0, 0, 0}, | |
2675 | }, | |
2676 | { | |
2677 | {0, 0, 0, 0, 0}, | |
2678 | {0, 0, 0, 0, 0}, | |
2679 | {0, 0, 0, 0, 0}, | |
2680 | {0, 0, 0, 0, 0}, | |
2681 | {0, 0, 0, 0, 0}, | |
2682 | {0, 0, 0, 0, 0}, | |
2683 | {0, 0, 0, 0, 0}, | |
2684 | {0, 0, 0, 0, 0}, | |
2685 | }, | |
2686 | { | |
2687 | {0, 0, 0, 0, 0}, | |
2688 | {0, 0, 0, 0, 0}, | |
2689 | {0, 0, 0, 0, 0}, | |
2690 | {0, 0, 0, 0, 0}, | |
2691 | {0, 0, 0, 0, 0}, | |
2692 | {0, 0, 0, 0, 0}, | |
2693 | {0, 0, 0, 0, 0}, | |
2694 | {0, 0, 0, 0, 0}, | |
2695 | }, | |
2696 | ||
2697 | }, | |
2698 | .calTarget_freqbin_5G = { | |
2699 | FREQ2FBIN(5180, 0), | |
2700 | FREQ2FBIN(5240, 0), | |
2701 | FREQ2FBIN(5320, 0), | |
2702 | FREQ2FBIN(5400, 0), | |
2703 | FREQ2FBIN(5500, 0), | |
2704 | FREQ2FBIN(5600, 0), | |
2705 | FREQ2FBIN(5700, 0), | |
2706 | FREQ2FBIN(5825, 0) | |
2707 | }, | |
2708 | .calTarget_freqbin_5GHT20 = { | |
2709 | FREQ2FBIN(5180, 0), | |
2710 | FREQ2FBIN(5240, 0), | |
2711 | FREQ2FBIN(5320, 0), | |
2712 | FREQ2FBIN(5400, 0), | |
2713 | FREQ2FBIN(5500, 0), | |
2714 | FREQ2FBIN(5700, 0), | |
2715 | FREQ2FBIN(5745, 0), | |
2716 | FREQ2FBIN(5825, 0) | |
2717 | }, | |
2718 | .calTarget_freqbin_5GHT40 = { | |
2719 | FREQ2FBIN(5180, 0), | |
2720 | FREQ2FBIN(5240, 0), | |
2721 | FREQ2FBIN(5320, 0), | |
2722 | FREQ2FBIN(5400, 0), | |
2723 | FREQ2FBIN(5500, 0), | |
2724 | FREQ2FBIN(5700, 0), | |
2725 | FREQ2FBIN(5745, 0), | |
2726 | FREQ2FBIN(5825, 0) | |
2727 | }, | |
2728 | .calTargetPower5G = { | |
2729 | /* 6-24,36,48,54 */ | |
2730 | { {30, 30, 28, 24} }, | |
2731 | { {30, 30, 28, 24} }, | |
2732 | { {30, 30, 28, 24} }, | |
2733 | { {30, 30, 28, 24} }, | |
2734 | { {30, 30, 28, 24} }, | |
2735 | { {30, 30, 28, 24} }, | |
2736 | { {30, 30, 28, 24} }, | |
2737 | { {30, 30, 28, 24} }, | |
2738 | }, | |
2739 | .calTargetPower5GHT20 = { | |
2740 | /* | |
2741 | * 0_8_16,1-3_9-11_17-19, | |
2742 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
2743 | */ | |
2744 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, | |
2745 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, | |
2746 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, | |
2747 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, | |
2748 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, | |
2749 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, | |
2750 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, | |
2751 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, | |
2752 | }, | |
2753 | .calTargetPower5GHT40 = { | |
2754 | /* | |
2755 | * 0_8_16,1-3_9-11_17-19, | |
2756 | * 4,5,6,7,12,13,14,15,20,21,22,23 | |
2757 | */ | |
2758 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, | |
2759 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, | |
2760 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, | |
2761 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, | |
2762 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, | |
2763 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, | |
2764 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, | |
2765 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, | |
2766 | }, | |
2767 | .ctlIndex_5G = { | |
2768 | 0x10, 0x16, 0x18, 0x40, 0x46, | |
2769 | 0x48, 0x30, 0x36, 0x38 | |
2770 | }, | |
2771 | .ctl_freqbin_5G = { | |
2772 | { | |
2773 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2774 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
2775 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
2776 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
2777 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), | |
2778 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
2779 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
2780 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
2781 | }, | |
2782 | { | |
2783 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2784 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
2785 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), | |
2786 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
2787 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), | |
2788 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
2789 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
2790 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
2791 | }, | |
2792 | ||
2793 | { | |
2794 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
2795 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
2796 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
2797 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), | |
2798 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), | |
2799 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), | |
2800 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), | |
2801 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) | |
2802 | }, | |
2803 | ||
2804 | { | |
2805 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2806 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
2807 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), | |
2808 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), | |
2809 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
2810 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
2811 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, | |
2812 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, | |
2813 | }, | |
2814 | ||
2815 | { | |
2816 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2817 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
2818 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), | |
2819 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), | |
2820 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, | |
2821 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, | |
2822 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, | |
2823 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, | |
2824 | }, | |
2825 | ||
2826 | { | |
2827 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
2828 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), | |
2829 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), | |
2830 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
2831 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), | |
2832 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
2833 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, | |
2834 | /* Data[5].ctlEdges[7].bChannel */ 0xFF | |
2835 | }, | |
2836 | ||
2837 | { | |
2838 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2839 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), | |
2840 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), | |
2841 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), | |
2842 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), | |
2843 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), | |
2844 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), | |
2845 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) | |
2846 | }, | |
2847 | ||
2848 | { | |
2849 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), | |
2850 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), | |
2851 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), | |
2852 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), | |
2853 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), | |
2854 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), | |
2855 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), | |
2856 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) | |
2857 | }, | |
2858 | ||
2859 | { | |
2860 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), | |
2861 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), | |
2862 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), | |
2863 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), | |
2864 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), | |
2865 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), | |
2866 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), | |
2867 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) | |
2868 | } | |
2869 | }, | |
2870 | .ctlPowerData_5G = { | |
2871 | { | |
2872 | { | |
e702ba18 FF |
2873 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2874 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2875 | } |
2876 | }, | |
2877 | { | |
2878 | { | |
e702ba18 FF |
2879 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2880 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2881 | } |
2882 | }, | |
2883 | { | |
2884 | { | |
e702ba18 FF |
2885 | CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
2886 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
2887 | } |
2888 | }, | |
2889 | { | |
2890 | { | |
e702ba18 FF |
2891 | CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
2892 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2893 | } |
2894 | }, | |
2895 | { | |
2896 | { | |
e702ba18 FF |
2897 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), |
2898 | CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2899 | } |
2900 | }, | |
2901 | { | |
2902 | { | |
e702ba18 FF |
2903 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2904 | CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), | |
30923549 SB |
2905 | } |
2906 | }, | |
2907 | { | |
2908 | { | |
e702ba18 FF |
2909 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), |
2910 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), | |
30923549 SB |
2911 | } |
2912 | }, | |
2913 | { | |
2914 | { | |
e702ba18 FF |
2915 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), |
2916 | CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), | |
30923549 SB |
2917 | } |
2918 | }, | |
2919 | { | |
2920 | { | |
e702ba18 FF |
2921 | CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), |
2922 | CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), | |
30923549 SB |
2923 | } |
2924 | }, | |
2925 | } | |
2926 | }; | |
2927 | ||
2928 | ||
2929 | static const struct ar9300_eeprom *ar9300_eep_templates[] = { | |
2930 | &ar9300_default, | |
2931 | &ar9300_x112, | |
2932 | &ar9300_h116, | |
2933 | &ar9300_h112, | |
2934 | &ar9300_x113, | |
2935 | }; | |
2936 | ||
2937 | static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id) | |
2938 | { | |
2939 | #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0])) | |
2940 | int it; | |
2941 | ||
2942 | for (it = 0; it < N_LOOP; it++) | |
2943 | if (ar9300_eep_templates[it]->templateVersion == id) | |
2944 | return ar9300_eep_templates[it]; | |
2945 | return NULL; | |
2946 | #undef N_LOOP | |
2947 | } | |
2948 | ||
15c9ee7a SB |
2949 | static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah) |
2950 | { | |
2951 | return 0; | |
2952 | } | |
2953 | ||
bc206802 VT |
2954 | static int interpolate(int x, int xa, int xb, int ya, int yb) |
2955 | { | |
2956 | int bf, factor, plus; | |
2957 | ||
2958 | bf = 2 * (yb - ya) * (x - xa) / (xb - xa); | |
2959 | factor = bf / 2; | |
2960 | plus = bf % 2; | |
2961 | return ya + factor + plus; | |
2962 | } | |
2963 | ||
15c9ee7a SB |
2964 | static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, |
2965 | enum eeprom_param param) | |
2966 | { | |
2967 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
2968 | struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; | |
2969 | ||
2970 | switch (param) { | |
2971 | case EEP_MAC_LSW: | |
78fa99ab | 2972 | return get_unaligned_be16(eep->macAddr); |
15c9ee7a | 2973 | case EEP_MAC_MID: |
78fa99ab | 2974 | return get_unaligned_be16(eep->macAddr + 2); |
15c9ee7a | 2975 | case EEP_MAC_MSW: |
78fa99ab | 2976 | return get_unaligned_be16(eep->macAddr + 4); |
15c9ee7a | 2977 | case EEP_REG_0: |
ffdc4cbe | 2978 | return le16_to_cpu(pBase->regDmn[0]); |
15c9ee7a SB |
2979 | case EEP_OP_CAP: |
2980 | return pBase->deviceCap; | |
2981 | case EEP_OP_MODE: | |
2982 | return pBase->opCapFlags.opFlags; | |
2983 | case EEP_RF_SILENT: | |
2984 | return pBase->rfSilent; | |
2985 | case EEP_TX_MASK: | |
2986 | return (pBase->txrxMask >> 4) & 0xf; | |
2987 | case EEP_RX_MASK: | |
2988 | return pBase->txrxMask & 0xf; | |
4935250a FF |
2989 | case EEP_PAPRD: |
2990 | return !!(pBase->featureEnable & BIT(5)); | |
ea066d5a MSS |
2991 | case EEP_CHAIN_MASK_REDUCE: |
2992 | return (pBase->miscConfiguration >> 0x3) & 0x1; | |
47e84dfb | 2993 | case EEP_ANT_DIV_CTL1: |
5479de6e | 2994 | return eep->base_ext1.ant_div_control; |
ca2c68cc FF |
2995 | case EEP_ANTENNA_GAIN_5G: |
2996 | return eep->modalHeader5G.antennaGain; | |
2997 | case EEP_ANTENNA_GAIN_2G: | |
2998 | return eep->modalHeader2G.antennaGain; | |
15c9ee7a SB |
2999 | default: |
3000 | return 0; | |
3001 | } | |
3002 | } | |
3003 | ||
0e4b9f2f | 3004 | static bool ar9300_eeprom_read_byte(struct ath_hw *ah, int address, |
ffdc4cbe | 3005 | u8 *buffer) |
15c9ee7a | 3006 | { |
ffdc4cbe | 3007 | u16 val; |
0cf31079 | 3008 | |
0e4b9f2f | 3009 | if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) |
ffdc4cbe | 3010 | return false; |
15c9ee7a | 3011 | |
ffdc4cbe FF |
3012 | *buffer = (val >> (8 * (address % 2))) & 0xff; |
3013 | return true; | |
3014 | } | |
15c9ee7a | 3015 | |
0e4b9f2f | 3016 | static bool ar9300_eeprom_read_word(struct ath_hw *ah, int address, |
ffdc4cbe FF |
3017 | u8 *buffer) |
3018 | { | |
3019 | u16 val; | |
15c9ee7a | 3020 | |
0e4b9f2f | 3021 | if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) |
ffdc4cbe | 3022 | return false; |
15c9ee7a | 3023 | |
ffdc4cbe FF |
3024 | buffer[0] = val >> 8; |
3025 | buffer[1] = val & 0xff; | |
15c9ee7a | 3026 | |
ffdc4cbe | 3027 | return true; |
15c9ee7a | 3028 | } |
15c9ee7a | 3029 | |
ffdc4cbe FF |
3030 | static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, |
3031 | int count) | |
15c9ee7a | 3032 | { |
15c9ee7a | 3033 | struct ath_common *common = ath9k_hw_common(ah); |
ffdc4cbe | 3034 | int i; |
15c9ee7a | 3035 | |
ffdc4cbe | 3036 | if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { |
d2182b69 | 3037 | ath_dbg(common, EEPROM, "eeprom address not in range\n"); |
15c9ee7a SB |
3038 | return false; |
3039 | } | |
3040 | ||
ffdc4cbe FF |
3041 | /* |
3042 | * Since we're reading the bytes in reverse order from a little-endian | |
3043 | * word stream, an even address means we only use the lower half of | |
3044 | * the 16-bit word at that address | |
3045 | */ | |
3046 | if (address % 2 == 0) { | |
0e4b9f2f | 3047 | if (!ar9300_eeprom_read_byte(ah, address--, buffer++)) |
ffdc4cbe FF |
3048 | goto error; |
3049 | ||
3050 | count--; | |
15c9ee7a SB |
3051 | } |
3052 | ||
ffdc4cbe | 3053 | for (i = 0; i < count / 2; i++) { |
0e4b9f2f | 3054 | if (!ar9300_eeprom_read_word(ah, address, buffer)) |
ffdc4cbe | 3055 | goto error; |
15c9ee7a | 3056 | |
ffdc4cbe FF |
3057 | address -= 2; |
3058 | buffer += 2; | |
3059 | } | |
3060 | ||
3061 | if (count % 2) | |
0e4b9f2f | 3062 | if (!ar9300_eeprom_read_byte(ah, address, buffer)) |
ffdc4cbe | 3063 | goto error; |
15c9ee7a | 3064 | |
15c9ee7a | 3065 | return true; |
ffdc4cbe FF |
3066 | |
3067 | error: | |
d2182b69 JP |
3068 | ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n", |
3069 | address); | |
ffdc4cbe | 3070 | return false; |
15c9ee7a SB |
3071 | } |
3072 | ||
488f6ba7 FF |
3073 | static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data) |
3074 | { | |
3075 | REG_READ(ah, AR9300_OTP_BASE + (4 * addr)); | |
3076 | ||
3077 | if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE, | |
3078 | AR9300_OTP_STATUS_VALID, 1000)) | |
3079 | return false; | |
3080 | ||
3081 | *data = REG_READ(ah, AR9300_OTP_READ_DATA); | |
3082 | return true; | |
3083 | } | |
3084 | ||
3085 | static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, | |
3086 | int count) | |
3087 | { | |
3088 | u32 data; | |
3089 | int i; | |
3090 | ||
3091 | for (i = 0; i < count; i++) { | |
3092 | int offset = 8 * ((address - i) % 4); | |
3093 | if (!ar9300_otp_read_word(ah, (address - i) / 4, &data)) | |
3094 | return false; | |
3095 | ||
3096 | buffer[i] = (data >> offset) & 0xff; | |
3097 | } | |
3098 | ||
3099 | return true; | |
3100 | } | |
3101 | ||
3102 | ||
15c9ee7a SB |
3103 | static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, |
3104 | int *length, int *major, int *minor) | |
3105 | { | |
3106 | unsigned long value[4]; | |
3107 | ||
3108 | value[0] = best[0]; | |
3109 | value[1] = best[1]; | |
3110 | value[2] = best[2]; | |
3111 | value[3] = best[3]; | |
3112 | *code = ((value[0] >> 5) & 0x0007); | |
3113 | *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020); | |
3114 | *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f); | |
3115 | *major = (value[2] & 0x000f); | |
3116 | *minor = (value[3] & 0x00ff); | |
3117 | } | |
3118 | ||
3119 | static u16 ar9300_comp_cksum(u8 *data, int dsize) | |
3120 | { | |
3121 | int it, checksum = 0; | |
3122 | ||
3123 | for (it = 0; it < dsize; it++) { | |
3124 | checksum += data[it]; | |
3125 | checksum &= 0xffff; | |
3126 | } | |
3127 | ||
3128 | return checksum; | |
3129 | } | |
3130 | ||
3131 | static bool ar9300_uncompress_block(struct ath_hw *ah, | |
3132 | u8 *mptr, | |
3133 | int mdataSize, | |
3134 | u8 *block, | |
3135 | int size) | |
3136 | { | |
3137 | int it; | |
3138 | int spot; | |
3139 | int offset; | |
3140 | int length; | |
3141 | struct ath_common *common = ath9k_hw_common(ah); | |
3142 | ||
3143 | spot = 0; | |
3144 | ||
3145 | for (it = 0; it < size; it += (length+2)) { | |
3146 | offset = block[it]; | |
3147 | offset &= 0xff; | |
3148 | spot += offset; | |
3149 | length = block[it+1]; | |
3150 | length &= 0xff; | |
3151 | ||
803288e6 | 3152 | if (length > 0 && spot >= 0 && spot+length <= mdataSize) { |
d2182b69 | 3153 | ath_dbg(common, EEPROM, |
226afe68 JP |
3154 | "Restore at %d: spot=%d offset=%d length=%d\n", |
3155 | it, spot, offset, length); | |
15c9ee7a SB |
3156 | memcpy(&mptr[spot], &block[it+2], length); |
3157 | spot += length; | |
3158 | } else if (length > 0) { | |
d2182b69 | 3159 | ath_dbg(common, EEPROM, |
226afe68 JP |
3160 | "Bad restore at %d: spot=%d offset=%d length=%d\n", |
3161 | it, spot, offset, length); | |
15c9ee7a SB |
3162 | return false; |
3163 | } | |
3164 | } | |
3165 | return true; | |
3166 | } | |
3167 | ||
3168 | static int ar9300_compress_decision(struct ath_hw *ah, | |
3169 | int it, | |
3170 | int code, | |
3171 | int reference, | |
3172 | u8 *mptr, | |
3173 | u8 *word, int length, int mdata_size) | |
3174 | { | |
3175 | struct ath_common *common = ath9k_hw_common(ah); | |
30923549 | 3176 | const struct ar9300_eeprom *eep = NULL; |
15c9ee7a SB |
3177 | |
3178 | switch (code) { | |
3179 | case _CompressNone: | |
3180 | if (length != mdata_size) { | |
d2182b69 | 3181 | ath_dbg(common, EEPROM, |
226afe68 JP |
3182 | "EEPROM structure size mismatch memory=%d eeprom=%d\n", |
3183 | mdata_size, length); | |
15c9ee7a SB |
3184 | return -1; |
3185 | } | |
2c208890 | 3186 | memcpy(mptr, word + COMP_HDR_LEN, length); |
d2182b69 | 3187 | ath_dbg(common, EEPROM, |
226afe68 JP |
3188 | "restored eeprom %d: uncompressed, length %d\n", |
3189 | it, length); | |
15c9ee7a SB |
3190 | break; |
3191 | case _CompressBlock: | |
3192 | if (reference == 0) { | |
15c9ee7a | 3193 | } else { |
30923549 SB |
3194 | eep = ar9003_eeprom_struct_find_by_id(reference); |
3195 | if (eep == NULL) { | |
d2182b69 | 3196 | ath_dbg(common, EEPROM, |
25985edc | 3197 | "can't find reference eeprom struct %d\n", |
226afe68 | 3198 | reference); |
15c9ee7a SB |
3199 | return -1; |
3200 | } | |
30923549 | 3201 | memcpy(mptr, eep, mdata_size); |
15c9ee7a | 3202 | } |
d2182b69 | 3203 | ath_dbg(common, EEPROM, |
226afe68 JP |
3204 | "restore eeprom %d: block, reference %d, length %d\n", |
3205 | it, reference, length); | |
15c9ee7a | 3206 | ar9300_uncompress_block(ah, mptr, mdata_size, |
2c208890 | 3207 | (word + COMP_HDR_LEN), length); |
15c9ee7a SB |
3208 | break; |
3209 | default: | |
d2182b69 | 3210 | ath_dbg(common, EEPROM, "unknown compression code %d\n", code); |
15c9ee7a SB |
3211 | return -1; |
3212 | } | |
3213 | return 0; | |
3214 | } | |
3215 | ||
488f6ba7 FF |
3216 | typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer, |
3217 | int count); | |
3218 | ||
3219 | static bool ar9300_check_header(void *data) | |
3220 | { | |
3221 | u32 *word = data; | |
3222 | return !(*word == 0 || *word == ~0); | |
3223 | } | |
3224 | ||
3225 | static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, | |
3226 | int base_addr) | |
3227 | { | |
3228 | u8 header[4]; | |
3229 | ||
3230 | if (!read(ah, base_addr, header, 4)) | |
3231 | return false; | |
3232 | ||
3233 | return ar9300_check_header(header); | |
3234 | } | |
3235 | ||
aaa13ca2 FF |
3236 | static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, |
3237 | int mdata_size) | |
3238 | { | |
aaa13ca2 FF |
3239 | u16 *data = (u16 *) mptr; |
3240 | int i; | |
3241 | ||
3242 | for (i = 0; i < mdata_size / 2; i++, data++) | |
0e4b9f2f | 3243 | ath9k_hw_nvram_read(ah, i, data); |
aaa13ca2 FF |
3244 | |
3245 | return 0; | |
3246 | } | |
15c9ee7a SB |
3247 | /* |
3248 | * Read the configuration data from the eeprom. | |
3249 | * The data can be put in any specified memory buffer. | |
3250 | * | |
3251 | * Returns -1 on error. | |
3252 | * Returns address of next memory location on success. | |
3253 | */ | |
3254 | static int ar9300_eeprom_restore_internal(struct ath_hw *ah, | |
3255 | u8 *mptr, int mdata_size) | |
3256 | { | |
3257 | #define MDEFAULT 15 | |
3258 | #define MSTATE 100 | |
3259 | int cptr; | |
3260 | u8 *word; | |
3261 | int code; | |
3262 | int reference, length, major, minor; | |
3263 | int osize; | |
3264 | int it; | |
3265 | u16 checksum, mchecksum; | |
3266 | struct ath_common *common = ath9k_hw_common(ah); | |
01967360 | 3267 | struct ar9300_eeprom *eep; |
488f6ba7 | 3268 | eeprom_read_op read; |
15c9ee7a | 3269 | |
01967360 FF |
3270 | if (ath9k_hw_use_flash(ah)) { |
3271 | u8 txrx; | |
3272 | ||
3273 | ar9300_eeprom_restore_flash(ah, mptr, mdata_size); | |
3274 | ||
3275 | /* check if eeprom contains valid data */ | |
3276 | eep = (struct ar9300_eeprom *) mptr; | |
3277 | txrx = eep->baseEepHeader.txrxMask; | |
3278 | if (txrx != 0 && txrx != 0xff) | |
3279 | return 0; | |
3280 | } | |
aaa13ca2 | 3281 | |
15c9ee7a SB |
3282 | word = kzalloc(2048, GFP_KERNEL); |
3283 | if (!word) | |
1ba45b9e | 3284 | return -ENOMEM; |
15c9ee7a SB |
3285 | |
3286 | memcpy(mptr, &ar9300_default, mdata_size); | |
3287 | ||
488f6ba7 | 3288 | read = ar9300_read_eeprom; |
60e0c3a7 VT |
3289 | if (AR_SREV_9485(ah)) |
3290 | cptr = AR9300_BASE_ADDR_4K; | |
5b5c033b GJ |
3291 | else if (AR_SREV_9330(ah)) |
3292 | cptr = AR9300_BASE_ADDR_512; | |
60e0c3a7 VT |
3293 | else |
3294 | cptr = AR9300_BASE_ADDR; | |
d2182b69 JP |
3295 | ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n", |
3296 | cptr); | |
488f6ba7 FF |
3297 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3298 | goto found; | |
3299 | ||
3300 | cptr = AR9300_BASE_ADDR_512; | |
d2182b69 JP |
3301 | ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n", |
3302 | cptr); | |
488f6ba7 FF |
3303 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3304 | goto found; | |
3305 | ||
3306 | read = ar9300_read_otp; | |
3307 | cptr = AR9300_BASE_ADDR; | |
d2182b69 | 3308 | ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr); |
488f6ba7 FF |
3309 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3310 | goto found; | |
3311 | ||
3312 | cptr = AR9300_BASE_ADDR_512; | |
d2182b69 | 3313 | ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr); |
488f6ba7 FF |
3314 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3315 | goto found; | |
3316 | ||
3317 | goto fail; | |
3318 | ||
3319 | found: | |
d2182b69 | 3320 | ath_dbg(common, EEPROM, "Found valid EEPROM data\n"); |
488f6ba7 | 3321 | |
15c9ee7a | 3322 | for (it = 0; it < MSTATE; it++) { |
488f6ba7 | 3323 | if (!read(ah, cptr, word, COMP_HDR_LEN)) |
15c9ee7a SB |
3324 | goto fail; |
3325 | ||
488f6ba7 | 3326 | if (!ar9300_check_header(word)) |
15c9ee7a SB |
3327 | break; |
3328 | ||
3329 | ar9300_comp_hdr_unpack(word, &code, &reference, | |
3330 | &length, &major, &minor); | |
d2182b69 | 3331 | ath_dbg(common, EEPROM, |
226afe68 JP |
3332 | "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n", |
3333 | cptr, code, reference, length, major, minor); | |
60e0c3a7 | 3334 | if ((!AR_SREV_9485(ah) && length >= 1024) || |
d0ce2d17 | 3335 | (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) { |
d2182b69 | 3336 | ath_dbg(common, EEPROM, "Skipping bad header\n"); |
15c9ee7a SB |
3337 | cptr -= COMP_HDR_LEN; |
3338 | continue; | |
3339 | } | |
3340 | ||
3341 | osize = length; | |
488f6ba7 | 3342 | read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); |
15c9ee7a | 3343 | checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); |
78fa99ab | 3344 | mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]); |
d2182b69 JP |
3345 | ath_dbg(common, EEPROM, "checksum %x %x\n", |
3346 | checksum, mchecksum); | |
15c9ee7a SB |
3347 | if (checksum == mchecksum) { |
3348 | ar9300_compress_decision(ah, it, code, reference, mptr, | |
3349 | word, length, mdata_size); | |
3350 | } else { | |
d2182b69 | 3351 | ath_dbg(common, EEPROM, |
226afe68 | 3352 | "skipping block with bad checksum\n"); |
15c9ee7a SB |
3353 | } |
3354 | cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); | |
3355 | } | |
3356 | ||
3357 | kfree(word); | |
3358 | return cptr; | |
3359 | ||
3360 | fail: | |
3361 | kfree(word); | |
3362 | return -1; | |
3363 | } | |
3364 | ||
3365 | /* | |
3366 | * Restore the configuration structure by reading the eeprom. | |
3367 | * This function destroys any existing in-memory structure | |
3368 | * content. | |
3369 | */ | |
3370 | static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) | |
3371 | { | |
ffdc4cbe | 3372 | u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; |
15c9ee7a | 3373 | |
ffdc4cbe FF |
3374 | if (ar9300_eeprom_restore_internal(ah, mptr, |
3375 | sizeof(struct ar9300_eeprom)) < 0) | |
3376 | return false; | |
15c9ee7a | 3377 | |
ffdc4cbe | 3378 | return true; |
15c9ee7a SB |
3379 | } |
3380 | ||
26526202 RM |
3381 | #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS) |
3382 | static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size, | |
3383 | struct ar9300_modal_eep_header *modal_hdr) | |
3384 | { | |
3385 | PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0])); | |
3386 | PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1])); | |
3387 | PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2])); | |
3388 | PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); | |
3389 | PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2)); | |
3390 | PR_EEP("Ant. Gain", modal_hdr->antennaGain); | |
3391 | PR_EEP("Switch Settle", modal_hdr->switchSettling); | |
3392 | PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]); | |
3393 | PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]); | |
3394 | PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]); | |
3395 | PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]); | |
3396 | PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]); | |
3397 | PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]); | |
3398 | PR_EEP("Temp Slope", modal_hdr->tempSlope); | |
3399 | PR_EEP("Volt Slope", modal_hdr->voltSlope); | |
3400 | PR_EEP("spur Channels0", modal_hdr->spurChans[0]); | |
3401 | PR_EEP("spur Channels1", modal_hdr->spurChans[1]); | |
3402 | PR_EEP("spur Channels2", modal_hdr->spurChans[2]); | |
3403 | PR_EEP("spur Channels3", modal_hdr->spurChans[3]); | |
3404 | PR_EEP("spur Channels4", modal_hdr->spurChans[4]); | |
3405 | PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); | |
3406 | PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); | |
3407 | PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]); | |
df222edc | 3408 | PR_EEP("Quick Drop", modal_hdr->quick_drop); |
202bff08 | 3409 | PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); |
26526202 RM |
3410 | PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); |
3411 | PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); | |
3412 | PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); | |
3413 | PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); | |
3414 | PR_EEP("txClip", modal_hdr->txClip); | |
3415 | PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); | |
26526202 RM |
3416 | |
3417 | return len; | |
3418 | } | |
3419 | ||
3420 | static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, | |
3421 | u8 *buf, u32 len, u32 size) | |
3422 | { | |
3423 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3424 | struct ar9300_base_eep_hdr *pBase; | |
3425 | ||
3426 | if (!dump_base_hdr) { | |
3427 | len += snprintf(buf + len, size - len, | |
3428 | "%20s :\n", "2GHz modal Header"); | |
d25360b1 | 3429 | len = ar9003_dump_modal_eeprom(buf, len, size, |
26526202 RM |
3430 | &eep->modalHeader2G); |
3431 | len += snprintf(buf + len, size - len, | |
3432 | "%20s :\n", "5GHz modal Header"); | |
d25360b1 | 3433 | len = ar9003_dump_modal_eeprom(buf, len, size, |
26526202 RM |
3434 | &eep->modalHeader5G); |
3435 | goto out; | |
3436 | } | |
3437 | ||
3438 | pBase = &eep->baseEepHeader; | |
3439 | ||
3440 | PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion); | |
3441 | PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0])); | |
3442 | PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1])); | |
3443 | PR_EEP("TX Mask", (pBase->txrxMask >> 4)); | |
3444 | PR_EEP("RX Mask", (pBase->txrxMask & 0x0f)); | |
3445 | PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags & | |
3446 | AR5416_OPFLAGS_11A)); | |
3447 | PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags & | |
3448 | AR5416_OPFLAGS_11G)); | |
3449 | PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags & | |
3450 | AR5416_OPFLAGS_N_2G_HT20)); | |
3451 | PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags & | |
3452 | AR5416_OPFLAGS_N_2G_HT40)); | |
3453 | PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags & | |
3454 | AR5416_OPFLAGS_N_5G_HT20)); | |
3455 | PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags & | |
3456 | AR5416_OPFLAGS_N_5G_HT40)); | |
3457 | PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01)); | |
3458 | PR_EEP("RF Silent", pBase->rfSilent); | |
3459 | PR_EEP("BT option", pBase->blueToothOptions); | |
3460 | PR_EEP("Device Cap", pBase->deviceCap); | |
3461 | PR_EEP("Device Type", pBase->deviceType); | |
3462 | PR_EEP("Power Table Offset", pBase->pwrTableOffset); | |
3463 | PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]); | |
3464 | PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]); | |
3465 | PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0))); | |
3466 | PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1))); | |
3467 | PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2))); | |
3468 | PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3))); | |
3469 | PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4))); | |
3470 | PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5))); | |
3471 | PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0))); | |
df222edc | 3472 | PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1))); |
26526202 RM |
3473 | PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1); |
3474 | PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio); | |
3475 | PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio); | |
3476 | PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio); | |
3477 | PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio); | |
3478 | PR_EEP("Tx Gain", pBase->txrxgain >> 4); | |
3479 | PR_EEP("Rx Gain", pBase->txrxgain & 0xf); | |
3480 | PR_EEP("SW Reg", le32_to_cpu(pBase->swreg)); | |
3481 | ||
3482 | len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", | |
3483 | ah->eeprom.ar9300_eep.macAddr); | |
3484 | out: | |
3485 | if (len > size) | |
3486 | len = size; | |
3487 | ||
3488 | return len; | |
3489 | } | |
3490 | #else | |
3491 | static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, | |
3492 | u8 *buf, u32 len, u32 size) | |
3493 | { | |
3494 | return 0; | |
3495 | } | |
3496 | #endif | |
3497 | ||
15c9ee7a SB |
3498 | /* XXX: review hardware docs */ |
3499 | static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) | |
3500 | { | |
3501 | return ah->eeprom.ar9300_eep.eepromVersion; | |
3502 | } | |
3503 | ||
3504 | /* XXX: could be read from the eepromVersion, not sure yet */ | |
3505 | static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) | |
3506 | { | |
3507 | return 0; | |
3508 | } | |
3509 | ||
0aefc591 FF |
3510 | static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, |
3511 | bool is2ghz) | |
15c9ee7a SB |
3512 | { |
3513 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3514 | ||
3515 | if (is2ghz) | |
0aefc591 | 3516 | return &eep->modalHeader2G; |
15c9ee7a | 3517 | else |
0aefc591 | 3518 | return &eep->modalHeader5G; |
15c9ee7a SB |
3519 | } |
3520 | ||
3521 | static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) | |
3522 | { | |
0aefc591 | 3523 | int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; |
9936e65f | 3524 | |
dc9aa5fc | 3525 | if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) |
9936e65f | 3526 | REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); |
a4a2954f | 3527 | else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah)) |
2577c6e8 | 3528 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); |
9936e65f VT |
3529 | else { |
3530 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); | |
165af96d RM |
3531 | REG_RMW_FIELD(ah, AR_CH0_THERM, |
3532 | AR_CH0_THERM_XPABIASLVL_MSB, | |
3533 | bias >> 2); | |
3534 | REG_RMW_FIELD(ah, AR_CH0_THERM, | |
3535 | AR_CH0_THERM_XPASHORT2GND, 1); | |
9936e65f | 3536 | } |
15c9ee7a SB |
3537 | } |
3538 | ||
0aefc591 | 3539 | static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) |
2577c6e8 | 3540 | { |
0aefc591 | 3541 | return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); |
2577c6e8 SB |
3542 | } |
3543 | ||
3544 | ||
15c9ee7a SB |
3545 | static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) |
3546 | { | |
0aefc591 | 3547 | return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon); |
15c9ee7a SB |
3548 | } |
3549 | ||
3550 | static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) | |
3551 | { | |
0aefc591 | 3552 | return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); |
15c9ee7a SB |
3553 | } |
3554 | ||
0aefc591 | 3555 | static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, |
15c9ee7a SB |
3556 | bool is2ghz) |
3557 | { | |
0aefc591 | 3558 | __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; |
ffdc4cbe | 3559 | return le16_to_cpu(val); |
15c9ee7a SB |
3560 | } |
3561 | ||
3562 | static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) | |
3563 | { | |
915154b6 | 3564 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
2976bc5e | 3565 | int chain; |
30d5b709 | 3566 | u32 regval, value; |
2976bc5e VT |
3567 | static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = { |
3568 | AR_PHY_SWITCH_CHAIN_0, | |
3569 | AR_PHY_SWITCH_CHAIN_1, | |
3570 | AR_PHY_SWITCH_CHAIN_2, | |
3571 | }; | |
3572 | ||
30d5b709 SM |
3573 | if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) |
3574 | ath9k_hw_cfg_output(ah, AR9300_EXT_LNA_CTL_GPIO_AR9485, | |
3575 | AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED); | |
3576 | ||
3577 | value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); | |
2976bc5e | 3578 | |
a4a2954f | 3579 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
2577c6e8 | 3580 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, |
423e38e8 | 3581 | AR_SWITCH_TABLE_COM_AR9462_ALL, value); |
2d00de48 GJ |
3582 | } else if (AR_SREV_9550(ah)) { |
3583 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, | |
3584 | AR_SWITCH_TABLE_COM_AR9550_ALL, value); | |
2577c6e8 SB |
3585 | } else |
3586 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, | |
3587 | AR_SWITCH_TABLE_COM_ALL, value); | |
3588 | ||
3589 | ||
3590 | /* | |
423e38e8 | 3591 | * AR9462 defines new switch table for BT/WLAN, |
2577c6e8 SB |
3592 | * here's new field name in XXX.ref for both 2G and 5G. |
3593 | * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044) | |
3594 | * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX | |
3595 | * SWITCH_TABLE_COM_SPDT_WLAN_RX | |
3596 | * | |
3597 | * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX | |
3598 | * SWITCH_TABLE_COM_SPDT_WLAN_TX | |
3599 | * | |
3600 | * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE | |
3601 | * SWITCH_TABLE_COM_SPDT_WLAN_IDLE | |
3602 | */ | |
506ed95c | 3603 | if (AR_SREV_9462_20(ah) || AR_SREV_9565(ah)) { |
2577c6e8 SB |
3604 | value = ar9003_switch_com_spdt_get(ah, is2ghz); |
3605 | REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, | |
3606 | AR_SWITCH_TABLE_COM_SPDT_ALL, value); | |
9dc08ece | 3607 | REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE); |
2577c6e8 | 3608 | } |
15c9ee7a SB |
3609 | |
3610 | value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); | |
3611 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); | |
3612 | ||
ef95e58d SM |
3613 | if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { |
3614 | value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz); | |
3615 | REG_RMW_FIELD(ah, switch_chain_reg[0], | |
3616 | AR_SWITCH_TABLE_ALL, value); | |
3617 | } | |
3618 | ||
2976bc5e VT |
3619 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
3620 | if ((ah->rxchainmask & BIT(chain)) || | |
3621 | (ah->txchainmask & BIT(chain))) { | |
3622 | value = ar9003_hw_ant_ctrl_chain_get(ah, chain, | |
3623 | is2ghz); | |
3624 | REG_RMW_FIELD(ah, switch_chain_reg[chain], | |
3625 | AR_SWITCH_TABLE_ALL, value); | |
3626 | } | |
47e84dfb | 3627 | } |
15c9ee7a | 3628 | |
a4a2954f | 3629 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
47e84dfb | 3630 | value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); |
842ca780 MSS |
3631 | /* |
3632 | * main_lnaconf, alt_lnaconf, main_tb, alt_tb | |
3633 | * are the fields present | |
3634 | */ | |
3635 | regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); | |
3636 | regval &= (~AR_ANT_DIV_CTRL_ALL); | |
3637 | regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; | |
3638 | /* enable_lnadiv */ | |
9aa49ea3 SM |
3639 | regval &= (~AR_PHY_ANT_DIV_LNADIV); |
3640 | regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; | |
362cd03f SM |
3641 | |
3642 | if (AR_SREV_9565(ah)) { | |
3643 | if (ah->shared_chain_lnadiv) { | |
3644 | regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S); | |
3645 | } else { | |
3646 | regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S); | |
3647 | regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S); | |
3648 | } | |
3649 | } | |
3650 | ||
842ca780 MSS |
3651 | REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); |
3652 | ||
3653 | /*enable fast_div */ | |
3654 | regval = REG_READ(ah, AR_PHY_CCK_DETECT); | |
3655 | regval &= (~AR_FAST_DIV_ENABLE); | |
9aa49ea3 | 3656 | regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; |
842ca780 | 3657 | REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); |
915154b6 SM |
3658 | |
3659 | if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { | |
842ca780 MSS |
3660 | regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); |
3661 | /* | |
3662 | * clear bits 25-30 main_lnaconf, alt_lnaconf, | |
3663 | * main_tb, alt_tb | |
3664 | */ | |
9aa49ea3 SM |
3665 | regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | |
3666 | AR_PHY_ANT_DIV_ALT_LNACONF | | |
3667 | AR_PHY_ANT_DIV_ALT_GAINTB | | |
3668 | AR_PHY_ANT_DIV_MAIN_GAINTB)); | |
842ca780 | 3669 | /* by default use LNA1 for the main antenna */ |
9aa49ea3 SM |
3670 | regval |= (AR_PHY_ANT_DIV_LNA1 << |
3671 | AR_PHY_ANT_DIV_MAIN_LNACONF_S); | |
3672 | regval |= (AR_PHY_ANT_DIV_LNA2 << | |
3673 | AR_PHY_ANT_DIV_ALT_LNACONF_S); | |
842ca780 MSS |
3674 | REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); |
3675 | } | |
47e84dfb | 3676 | } |
15c9ee7a SB |
3677 | } |
3678 | ||
3679 | static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) | |
3680 | { | |
0aefc591 FF |
3681 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
3682 | struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; | |
15c9ee7a SB |
3683 | int drive_strength; |
3684 | unsigned long reg; | |
3685 | ||
0aefc591 | 3686 | drive_strength = pBase->miscConfiguration & BIT(0); |
15c9ee7a SB |
3687 | if (!drive_strength) |
3688 | return; | |
3689 | ||
3690 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); | |
3691 | reg &= ~0x00ffffc0; | |
3692 | reg |= 0x5 << 21; | |
3693 | reg |= 0x5 << 18; | |
3694 | reg |= 0x5 << 15; | |
3695 | reg |= 0x5 << 12; | |
3696 | reg |= 0x5 << 9; | |
3697 | reg |= 0x5 << 6; | |
3698 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); | |
3699 | ||
3700 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); | |
3701 | reg &= ~0xffffffe0; | |
3702 | reg |= 0x5 << 29; | |
3703 | reg |= 0x5 << 26; | |
3704 | reg |= 0x5 << 23; | |
3705 | reg |= 0x5 << 20; | |
3706 | reg |= 0x5 << 17; | |
3707 | reg |= 0x5 << 14; | |
3708 | reg |= 0x5 << 11; | |
3709 | reg |= 0x5 << 8; | |
3710 | reg |= 0x5 << 5; | |
3711 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); | |
3712 | ||
3713 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); | |
3714 | reg &= ~0xff800000; | |
3715 | reg |= 0x5 << 29; | |
3716 | reg |= 0x5 << 26; | |
3717 | reg |= 0x5 << 23; | |
3718 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); | |
3719 | } | |
3720 | ||
f4475a6e VT |
3721 | static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, |
3722 | struct ath9k_channel *chan) | |
3723 | { | |
3724 | int f[3], t[3]; | |
3725 | u16 value; | |
3726 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3727 | ||
3728 | if (chain >= 0 && chain < 3) { | |
3729 | if (IS_CHAN_2GHZ(chan)) | |
3730 | return eep->modalHeader2G.xatten1DB[chain]; | |
3731 | else if (eep->base_ext2.xatten1DBLow[chain] != 0) { | |
3732 | t[0] = eep->base_ext2.xatten1DBLow[chain]; | |
3733 | f[0] = 5180; | |
3734 | t[1] = eep->modalHeader5G.xatten1DB[chain]; | |
3735 | f[1] = 5500; | |
3736 | t[2] = eep->base_ext2.xatten1DBHigh[chain]; | |
3737 | f[2] = 5785; | |
3738 | value = ar9003_hw_power_interpolate((s32) chan->channel, | |
3739 | f, t, 3); | |
3740 | return value; | |
3741 | } else | |
3742 | return eep->modalHeader5G.xatten1DB[chain]; | |
3743 | } | |
3744 | ||
3745 | return 0; | |
3746 | } | |
3747 | ||
3748 | ||
3749 | static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, | |
3750 | struct ath9k_channel *chan) | |
3751 | { | |
3752 | int f[3], t[3]; | |
3753 | u16 value; | |
3754 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3755 | ||
3756 | if (chain >= 0 && chain < 3) { | |
3757 | if (IS_CHAN_2GHZ(chan)) | |
3758 | return eep->modalHeader2G.xatten1Margin[chain]; | |
3759 | else if (eep->base_ext2.xatten1MarginLow[chain] != 0) { | |
3760 | t[0] = eep->base_ext2.xatten1MarginLow[chain]; | |
3761 | f[0] = 5180; | |
3762 | t[1] = eep->modalHeader5G.xatten1Margin[chain]; | |
3763 | f[1] = 5500; | |
3764 | t[2] = eep->base_ext2.xatten1MarginHigh[chain]; | |
3765 | f[2] = 5785; | |
3766 | value = ar9003_hw_power_interpolate((s32) chan->channel, | |
3767 | f, t, 3); | |
3768 | return value; | |
3769 | } else | |
3770 | return eep->modalHeader5G.xatten1Margin[chain]; | |
3771 | } | |
3772 | ||
3773 | return 0; | |
3774 | } | |
3775 | ||
3776 | static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan) | |
3777 | { | |
3778 | int i; | |
3779 | u16 value; | |
3780 | unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0, | |
3781 | AR_PHY_EXT_ATTEN_CTL_1, | |
3782 | AR_PHY_EXT_ATTEN_CTL_2, | |
3783 | }; | |
3784 | ||
ef95e58d SM |
3785 | if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { |
3786 | value = ar9003_hw_atten_chain_get(ah, 1, chan); | |
3787 | REG_RMW_FIELD(ah, ext_atten_reg[0], | |
3788 | AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); | |
3789 | ||
3790 | value = ar9003_hw_atten_chain_get_margin(ah, 1, chan); | |
3791 | REG_RMW_FIELD(ah, ext_atten_reg[0], | |
3792 | AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, | |
3793 | value); | |
3794 | } | |
3795 | ||
f4475a6e VT |
3796 | /* Test value. if 0 then attenuation is unused. Don't load anything. */ |
3797 | for (i = 0; i < 3; i++) { | |
2976bc5e VT |
3798 | if (ah->txchainmask & BIT(i)) { |
3799 | value = ar9003_hw_atten_chain_get(ah, i, chan); | |
3800 | REG_RMW_FIELD(ah, ext_atten_reg[i], | |
3801 | AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); | |
3802 | ||
3803 | value = ar9003_hw_atten_chain_get_margin(ah, i, chan); | |
3804 | REG_RMW_FIELD(ah, ext_atten_reg[i], | |
3805 | AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, | |
3806 | value); | |
3807 | } | |
f4475a6e VT |
3808 | } |
3809 | } | |
3810 | ||
ab09b5b4 VT |
3811 | static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set) |
3812 | { | |
3813 | int timeout = 100; | |
3814 | ||
3815 | while (pmu_set != REG_READ(ah, pmu_reg)) { | |
3816 | if (timeout-- == 0) | |
3817 | return false; | |
3818 | REG_WRITE(ah, pmu_reg, pmu_set); | |
3819 | udelay(10); | |
3820 | } | |
3821 | ||
3822 | return true; | |
3823 | } | |
3824 | ||
bfc441a4 | 3825 | void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) |
15c9ee7a | 3826 | { |
0aefc591 FF |
3827 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
3828 | struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; | |
2577c6e8 | 3829 | u32 reg_val; |
15c9ee7a | 3830 | |
0aefc591 | 3831 | if (pBase->featureEnable & BIT(4)) { |
4187afa2 | 3832 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { |
ab09b5b4 VT |
3833 | int reg_pmu_set; |
3834 | ||
3835 | reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; | |
3836 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); | |
3837 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) | |
3838 | return; | |
3839 | ||
4187afa2 GJ |
3840 | if (AR_SREV_9330(ah)) { |
3841 | if (ah->is_clk_25mhz) { | |
3842 | reg_pmu_set = (3 << 1) | (8 << 4) | | |
3843 | (3 << 8) | (1 << 14) | | |
3844 | (6 << 17) | (1 << 20) | | |
3845 | (3 << 24); | |
3846 | } else { | |
3847 | reg_pmu_set = (4 << 1) | (7 << 4) | | |
3848 | (3 << 8) | (1 << 14) | | |
3849 | (6 << 17) | (1 << 20) | | |
3850 | (3 << 24); | |
3851 | } | |
3852 | } else { | |
3853 | reg_pmu_set = (5 << 1) | (7 << 4) | | |
1fa707aa | 3854 | (2 << 8) | (2 << 14) | |
4187afa2 GJ |
3855 | (6 << 17) | (1 << 20) | |
3856 | (3 << 24) | (1 << 28); | |
3857 | } | |
ab09b5b4 VT |
3858 | |
3859 | REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set); | |
3860 | if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set)) | |
3861 | return; | |
3862 | ||
3863 | reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000) | |
3864 | | (4 << 26); | |
3865 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); | |
3866 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) | |
3867 | return; | |
3868 | ||
3869 | reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000) | |
3870 | | (1 << 21); | |
3871 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); | |
3872 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) | |
3873 | return; | |
a4a2954f | 3874 | } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
0aefc591 | 3875 | reg_val = le32_to_cpu(pBase->swreg); |
2577c6e8 | 3876 | REG_WRITE(ah, AR_PHY_PMU1, reg_val); |
ab09b5b4 VT |
3877 | } else { |
3878 | /* Internal regulator is ON. Write swreg register. */ | |
0aefc591 | 3879 | reg_val = le32_to_cpu(pBase->swreg); |
ab09b5b4 VT |
3880 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, |
3881 | REG_READ(ah, AR_RTC_REG_CONTROL1) & | |
3882 | (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); | |
2577c6e8 | 3883 | REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val); |
ab09b5b4 VT |
3884 | /* Set REG_CONTROL1.SWREG_PROGRAM */ |
3885 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, | |
3886 | REG_READ(ah, | |
3887 | AR_RTC_REG_CONTROL1) | | |
3888 | AR_RTC_REG_CONTROL1_SWREG_PROGRAM); | |
3889 | } | |
15c9ee7a | 3890 | } else { |
4187afa2 | 3891 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { |
ab09b5b4 VT |
3892 | REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0); |
3893 | while (REG_READ_FIELD(ah, AR_PHY_PMU2, | |
2577c6e8 | 3894 | AR_PHY_PMU2_PGM)) |
ab09b5b4 VT |
3895 | udelay(10); |
3896 | ||
3897 | REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); | |
3898 | while (!REG_READ_FIELD(ah, AR_PHY_PMU1, | |
2577c6e8 | 3899 | AR_PHY_PMU1_PWD)) |
ab09b5b4 VT |
3900 | udelay(10); |
3901 | REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1); | |
3902 | while (!REG_READ_FIELD(ah, AR_PHY_PMU2, | |
2577c6e8 | 3903 | AR_PHY_PMU2_PGM)) |
ab09b5b4 | 3904 | udelay(10); |
a4a2954f | 3905 | } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
2577c6e8 SB |
3906 | REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); |
3907 | else { | |
3908 | reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | | |
3909 | AR_RTC_FORCE_SWREG_PRD; | |
3910 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val); | |
3911 | } | |
15c9ee7a | 3912 | } |
ab09b5b4 | 3913 | |
15c9ee7a SB |
3914 | } |
3915 | ||
dd040f76 VT |
3916 | static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) |
3917 | { | |
3918 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3919 | u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; | |
3920 | ||
08a4a1ab FF |
3921 | if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) |
3922 | return; | |
3923 | ||
dd040f76 VT |
3924 | if (eep->baseEepHeader.featureEnable & 0x40) { |
3925 | tuning_caps_param &= 0x7f; | |
3926 | REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC, | |
3927 | tuning_caps_param); | |
3928 | REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC, | |
3929 | tuning_caps_param); | |
15c9ee7a SB |
3930 | } |
3931 | } | |
3932 | ||
df222edc RM |
3933 | static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq) |
3934 | { | |
3935 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
0aefc591 FF |
3936 | struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; |
3937 | int quick_drop; | |
df222edc RM |
3938 | s32 t[3], f[3] = {5180, 5500, 5785}; |
3939 | ||
0aefc591 | 3940 | if (!(pBase->miscConfiguration & BIT(1))) |
df222edc RM |
3941 | return; |
3942 | ||
3943 | if (freq < 4000) | |
3944 | quick_drop = eep->modalHeader2G.quick_drop; | |
3945 | else { | |
3946 | t[0] = eep->base_ext1.quick_drop_low; | |
3947 | t[1] = eep->modalHeader5G.quick_drop; | |
3948 | t[2] = eep->base_ext1.quick_drop_high; | |
3949 | quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3); | |
3950 | } | |
3951 | REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop); | |
3952 | } | |
3953 | ||
0aefc591 | 3954 | static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz) |
202bff08 | 3955 | { |
202bff08 RM |
3956 | u32 value; |
3957 | ||
0aefc591 | 3958 | value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff; |
202bff08 RM |
3959 | |
3960 | REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, | |
3961 | AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value); | |
3962 | REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, | |
3963 | AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value); | |
3964 | } | |
3965 | ||
0aefc591 | 3966 | static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz) |
89be49e1 FF |
3967 | { |
3968 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3969 | u8 xpa_ctl; | |
3970 | ||
3971 | if (!(eep->baseEepHeader.featureEnable & 0x80)) | |
3972 | return; | |
3973 | ||
3974 | if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah)) | |
3975 | return; | |
3976 | ||
0aefc591 FF |
3977 | xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; |
3978 | if (is2ghz) | |
89be49e1 FF |
3979 | REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, |
3980 | AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl); | |
0aefc591 | 3981 | else |
89be49e1 FF |
3982 | REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, |
3983 | AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl); | |
89be49e1 FF |
3984 | } |
3985 | ||
3e2ea543 FF |
3986 | static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz) |
3987 | { | |
3988 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
3989 | u8 bias; | |
3990 | ||
3991 | if (!(eep->baseEepHeader.featureEnable & 0x40)) | |
3992 | return; | |
3993 | ||
3994 | if (!AR_SREV_9300(ah)) | |
3995 | return; | |
3996 | ||
3997 | bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength; | |
3998 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, | |
3999 | bias & 0x3); | |
4000 | bias >>= 2; | |
4001 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, | |
4002 | bias & 0x3); | |
4003 | bias >>= 2; | |
4004 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, | |
4005 | bias & 0x3); | |
4006 | } | |
4007 | ||
02eba421 RM |
4008 | static int ar9003_hw_get_thermometer(struct ath_hw *ah) |
4009 | { | |
4010 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4011 | struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; | |
4012 | int thermometer = (pBase->miscConfiguration >> 1) & 0x3; | |
4013 | ||
4014 | return --thermometer; | |
4015 | } | |
4016 | ||
4017 | static void ar9003_hw_thermometer_apply(struct ath_hw *ah) | |
4018 | { | |
4019 | int thermometer = ar9003_hw_get_thermometer(ah); | |
4020 | u8 therm_on = (thermometer < 0) ? 0 : 1; | |
4021 | ||
4022 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, | |
4023 | AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on); | |
4024 | if (ah->caps.tx_chainmask & BIT(1)) | |
4025 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, | |
4026 | AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on); | |
4027 | if (ah->caps.tx_chainmask & BIT(2)) | |
4028 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, | |
4029 | AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on); | |
4030 | ||
4031 | therm_on = (thermometer < 0) ? 0 : (thermometer == 0); | |
4032 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, | |
4033 | AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on); | |
4034 | if (ah->caps.tx_chainmask & BIT(1)) { | |
4035 | therm_on = (thermometer < 0) ? 0 : (thermometer == 1); | |
4036 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, | |
4037 | AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on); | |
4038 | } | |
4039 | if (ah->caps.tx_chainmask & BIT(2)) { | |
4040 | therm_on = (thermometer < 0) ? 0 : (thermometer == 2); | |
4041 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, | |
4042 | AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on); | |
4043 | } | |
4044 | } | |
4045 | ||
80fe43f2 RM |
4046 | static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah) |
4047 | { | |
4048 | u32 data, ko, kg; | |
4049 | ||
4050 | if (!AR_SREV_9462_20(ah)) | |
4051 | return; | |
4052 | ar9300_otp_read_word(ah, 1, &data); | |
4053 | ko = data & 0xff; | |
4054 | kg = (data >> 8) & 0xff; | |
4055 | if (ko || kg) { | |
4056 | REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3, | |
4057 | AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET, ko); | |
4058 | REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3, | |
4059 | AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN, | |
4060 | kg + 256); | |
4061 | } | |
4062 | } | |
4063 | ||
15c9ee7a SB |
4064 | static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, |
4065 | struct ath9k_channel *chan) | |
4066 | { | |
0aefc591 FF |
4067 | bool is2ghz = IS_CHAN_2GHZ(chan); |
4068 | ar9003_hw_xpa_timing_control_apply(ah, is2ghz); | |
4069 | ar9003_hw_xpa_bias_level_apply(ah, is2ghz); | |
4070 | ar9003_hw_ant_ctrl_apply(ah, is2ghz); | |
15c9ee7a | 4071 | ar9003_hw_drive_strength_apply(ah); |
3e2ea543 | 4072 | ar9003_hw_xlna_bias_strength_apply(ah, is2ghz); |
f4475a6e | 4073 | ar9003_hw_atten_apply(ah, chan); |
df222edc | 4074 | ar9003_hw_quick_drop_apply(ah, chan->channel); |
2e2c9cc3 | 4075 | if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah)) |
3594beae | 4076 | ar9003_hw_internal_regulator_apply(ah); |
08a4a1ab | 4077 | ar9003_hw_apply_tuning_caps(ah); |
0aefc591 | 4078 | ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz); |
02eba421 | 4079 | ar9003_hw_thermometer_apply(ah); |
80fe43f2 | 4080 | ar9003_hw_thermo_cal_apply(ah); |
15c9ee7a SB |
4081 | } |
4082 | ||
4083 | static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, | |
4084 | struct ath9k_channel *chan) | |
4085 | { | |
4086 | } | |
4087 | ||
4088 | /* | |
4089 | * Returns the interpolated y value corresponding to the specified x value | |
4090 | * from the np ordered pairs of data (px,py). | |
4091 | * The pairs do not have to be in any order. | |
4092 | * If the specified x value is less than any of the px, | |
4093 | * the returned y value is equal to the py for the lowest px. | |
4094 | * If the specified x value is greater than any of the px, | |
4095 | * the returned y value is equal to the py for the highest px. | |
4096 | */ | |
4097 | static int ar9003_hw_power_interpolate(int32_t x, | |
4098 | int32_t *px, int32_t *py, u_int16_t np) | |
4099 | { | |
4100 | int ip = 0; | |
4101 | int lx = 0, ly = 0, lhave = 0; | |
4102 | int hx = 0, hy = 0, hhave = 0; | |
4103 | int dx = 0; | |
4104 | int y = 0; | |
4105 | ||
4106 | lhave = 0; | |
4107 | hhave = 0; | |
4108 | ||
4109 | /* identify best lower and higher x calibration measurement */ | |
4110 | for (ip = 0; ip < np; ip++) { | |
4111 | dx = x - px[ip]; | |
4112 | ||
4113 | /* this measurement is higher than our desired x */ | |
4114 | if (dx <= 0) { | |
4115 | if (!hhave || dx > (x - hx)) { | |
4116 | /* new best higher x measurement */ | |
4117 | hx = px[ip]; | |
4118 | hy = py[ip]; | |
4119 | hhave = 1; | |
4120 | } | |
4121 | } | |
4122 | /* this measurement is lower than our desired x */ | |
4123 | if (dx >= 0) { | |
4124 | if (!lhave || dx < (x - lx)) { | |
4125 | /* new best lower x measurement */ | |
4126 | lx = px[ip]; | |
4127 | ly = py[ip]; | |
4128 | lhave = 1; | |
4129 | } | |
4130 | } | |
4131 | } | |
4132 | ||
4133 | /* the low x is good */ | |
4134 | if (lhave) { | |
4135 | /* so is the high x */ | |
4136 | if (hhave) { | |
4137 | /* they're the same, so just pick one */ | |
4138 | if (hx == lx) | |
4139 | y = ly; | |
4140 | else /* interpolate */ | |
bc206802 | 4141 | y = interpolate(x, lx, hx, ly, hy); |
15c9ee7a SB |
4142 | } else /* only low is good, use it */ |
4143 | y = ly; | |
4144 | } else if (hhave) /* only high is good, use it */ | |
4145 | y = hy; | |
4146 | else /* nothing is good,this should never happen unless np=0, ???? */ | |
4147 | y = -(1 << 30); | |
4148 | return y; | |
4149 | } | |
4150 | ||
4151 | static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, | |
4152 | u16 rateIndex, u16 freq, bool is2GHz) | |
4153 | { | |
4154 | u16 numPiers, i; | |
4155 | s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; | |
4156 | s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; | |
4157 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4158 | struct cal_tgt_pow_legacy *pEepromTargetPwr; | |
4159 | u8 *pFreqBin; | |
4160 | ||
4161 | if (is2GHz) { | |
d10baf99 | 4162 | numPiers = AR9300_NUM_2G_20_TARGET_POWERS; |
15c9ee7a SB |
4163 | pEepromTargetPwr = eep->calTargetPower2G; |
4164 | pFreqBin = eep->calTarget_freqbin_2G; | |
4165 | } else { | |
4166 | numPiers = AR9300_NUM_5G_20_TARGET_POWERS; | |
4167 | pEepromTargetPwr = eep->calTargetPower5G; | |
4168 | pFreqBin = eep->calTarget_freqbin_5G; | |
4169 | } | |
4170 | ||
4171 | /* | |
4172 | * create array of channels and targetpower from | |
4173 | * targetpower piers stored on eeprom | |
4174 | */ | |
4175 | for (i = 0; i < numPiers; i++) { | |
8edb254c | 4176 | freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); |
15c9ee7a SB |
4177 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; |
4178 | } | |
4179 | ||
4180 | /* interpolate to get target power for given frequency */ | |
4181 | return (u8) ar9003_hw_power_interpolate((s32) freq, | |
4182 | freqArray, | |
4183 | targetPowerArray, numPiers); | |
4184 | } | |
4185 | ||
4186 | static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, | |
4187 | u16 rateIndex, | |
4188 | u16 freq, bool is2GHz) | |
4189 | { | |
4190 | u16 numPiers, i; | |
4191 | s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; | |
4192 | s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; | |
4193 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4194 | struct cal_tgt_pow_ht *pEepromTargetPwr; | |
4195 | u8 *pFreqBin; | |
4196 | ||
4197 | if (is2GHz) { | |
d10baf99 | 4198 | numPiers = AR9300_NUM_2G_20_TARGET_POWERS; |
15c9ee7a SB |
4199 | pEepromTargetPwr = eep->calTargetPower2GHT20; |
4200 | pFreqBin = eep->calTarget_freqbin_2GHT20; | |
4201 | } else { | |
4202 | numPiers = AR9300_NUM_5G_20_TARGET_POWERS; | |
4203 | pEepromTargetPwr = eep->calTargetPower5GHT20; | |
4204 | pFreqBin = eep->calTarget_freqbin_5GHT20; | |
4205 | } | |
4206 | ||
4207 | /* | |
4208 | * create array of channels and targetpower | |
4209 | * from targetpower piers stored on eeprom | |
4210 | */ | |
4211 | for (i = 0; i < numPiers; i++) { | |
8edb254c | 4212 | freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); |
15c9ee7a SB |
4213 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; |
4214 | } | |
4215 | ||
4216 | /* interpolate to get target power for given frequency */ | |
4217 | return (u8) ar9003_hw_power_interpolate((s32) freq, | |
4218 | freqArray, | |
4219 | targetPowerArray, numPiers); | |
4220 | } | |
4221 | ||
4222 | static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, | |
4223 | u16 rateIndex, | |
4224 | u16 freq, bool is2GHz) | |
4225 | { | |
4226 | u16 numPiers, i; | |
4227 | s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS]; | |
4228 | s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS]; | |
4229 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4230 | struct cal_tgt_pow_ht *pEepromTargetPwr; | |
4231 | u8 *pFreqBin; | |
4232 | ||
4233 | if (is2GHz) { | |
4234 | numPiers = AR9300_NUM_2G_40_TARGET_POWERS; | |
4235 | pEepromTargetPwr = eep->calTargetPower2GHT40; | |
4236 | pFreqBin = eep->calTarget_freqbin_2GHT40; | |
4237 | } else { | |
4238 | numPiers = AR9300_NUM_5G_40_TARGET_POWERS; | |
4239 | pEepromTargetPwr = eep->calTargetPower5GHT40; | |
4240 | pFreqBin = eep->calTarget_freqbin_5GHT40; | |
4241 | } | |
4242 | ||
4243 | /* | |
4244 | * create array of channels and targetpower from | |
4245 | * targetpower piers stored on eeprom | |
4246 | */ | |
4247 | for (i = 0; i < numPiers; i++) { | |
8edb254c | 4248 | freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); |
15c9ee7a SB |
4249 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; |
4250 | } | |
4251 | ||
4252 | /* interpolate to get target power for given frequency */ | |
4253 | return (u8) ar9003_hw_power_interpolate((s32) freq, | |
4254 | freqArray, | |
4255 | targetPowerArray, numPiers); | |
4256 | } | |
4257 | ||
4258 | static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, | |
4259 | u16 rateIndex, u16 freq) | |
4260 | { | |
4261 | u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i; | |
4262 | s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; | |
4263 | s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; | |
4264 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4265 | struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck; | |
4266 | u8 *pFreqBin = eep->calTarget_freqbin_Cck; | |
4267 | ||
4268 | /* | |
4269 | * create array of channels and targetpower from | |
4270 | * targetpower piers stored on eeprom | |
4271 | */ | |
4272 | for (i = 0; i < numPiers; i++) { | |
8edb254c | 4273 | freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1); |
15c9ee7a SB |
4274 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; |
4275 | } | |
4276 | ||
4277 | /* interpolate to get target power for given frequency */ | |
4278 | return (u8) ar9003_hw_power_interpolate((s32) freq, | |
4279 | freqArray, | |
4280 | targetPowerArray, numPiers); | |
4281 | } | |
4282 | ||
4283 | /* Set tx power registers to array of values passed in */ | |
4284 | static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray) | |
4285 | { | |
4286 | #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) | |
4287 | /* make sure forced gain is not set */ | |
4a4fdf2e | 4288 | REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); |
15c9ee7a SB |
4289 | |
4290 | /* Write the OFDM power per rate set */ | |
4291 | ||
4292 | /* 6 (LSB), 9, 12, 18 (MSB) */ | |
4a4fdf2e | 4293 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0), |
15c9ee7a SB |
4294 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) | |
4295 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) | | |
4296 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) | | |
4297 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); | |
4298 | ||
4299 | /* 24 (LSB), 36, 48, 54 (MSB) */ | |
4a4fdf2e | 4300 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), |
15c9ee7a SB |
4301 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) | |
4302 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) | | |
4303 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) | | |
4304 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); | |
4305 | ||
4306 | /* Write the CCK power per rate set */ | |
4307 | ||
4308 | /* 1L (LSB), reserved, 2L, 2S (MSB) */ | |
4a4fdf2e | 4309 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), |
15c9ee7a SB |
4310 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) | |
4311 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | | |
4312 | /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */ | |
4313 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)); | |
4314 | ||
4315 | /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ | |
4a4fdf2e | 4316 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), |
15c9ee7a SB |
4317 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) | |
4318 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) | | |
4319 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) | | |
4320 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) | |
4321 | ); | |
4322 | ||
cf3a03b9 LR |
4323 | /* Write the power for duplicated frames - HT40 */ |
4324 | ||
4325 | /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */ | |
8d7763b4 | 4326 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8), |
cf3a03b9 LR |
4327 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) | |
4328 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | | |
4329 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) | | |
4330 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) | |
4331 | ); | |
4332 | ||
15c9ee7a SB |
4333 | /* Write the HT20 power per rate set */ |
4334 | ||
4335 | /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ | |
4a4fdf2e | 4336 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), |
15c9ee7a SB |
4337 | POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) | |
4338 | POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) | | |
4339 | POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) | | |
4340 | POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0) | |
4341 | ); | |
4342 | ||
4343 | /* 6 (LSB), 7, 12, 13 (MSB) */ | |
4a4fdf2e | 4344 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), |
15c9ee7a SB |
4345 | POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) | |
4346 | POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) | | |
4347 | POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) | | |
4348 | POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0) | |
4349 | ); | |
4350 | ||
4351 | /* 14 (LSB), 15, 20, 21 */ | |
4a4fdf2e | 4352 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9), |
15c9ee7a SB |
4353 | POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) | |
4354 | POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) | | |
4355 | POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) | | |
4356 | POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0) | |
4357 | ); | |
4358 | ||
4359 | /* Mixed HT20 and HT40 rates */ | |
4360 | ||
4361 | /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ | |
4a4fdf2e | 4362 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), |
15c9ee7a SB |
4363 | POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) | |
4364 | POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) | | |
4365 | POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) | | |
4366 | POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0) | |
4367 | ); | |
4368 | ||
4369 | /* | |
4370 | * Write the HT40 power per rate set | |
4371 | * correct PAR difference between HT40 and HT20/LEGACY | |
4372 | * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) | |
4373 | */ | |
4a4fdf2e | 4374 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), |
15c9ee7a SB |
4375 | POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) | |
4376 | POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) | | |
4377 | POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) | | |
4378 | POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0) | |
4379 | ); | |
4380 | ||
4381 | /* 6 (LSB), 7, 12, 13 (MSB) */ | |
4a4fdf2e | 4382 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), |
15c9ee7a SB |
4383 | POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) | |
4384 | POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) | | |
4385 | POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) | | |
4386 | POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0) | |
4387 | ); | |
4388 | ||
4389 | /* 14 (LSB), 15, 20, 21 */ | |
4a4fdf2e | 4390 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), |
15c9ee7a SB |
4391 | POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) | |
4392 | POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) | | |
4393 | POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) | | |
4394 | POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0) | |
4395 | ); | |
4396 | ||
4397 | return 0; | |
4398 | #undef POW_SM | |
4399 | } | |
4400 | ||
75acd5a8 GJ |
4401 | static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq, |
4402 | u8 *targetPowerValT2, | |
4403 | bool is2GHz) | |
15c9ee7a | 4404 | { |
15c9ee7a SB |
4405 | targetPowerValT2[ALL_TARGET_LEGACY_6_24] = |
4406 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq, | |
4407 | is2GHz); | |
4408 | targetPowerValT2[ALL_TARGET_LEGACY_36] = | |
4409 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq, | |
4410 | is2GHz); | |
4411 | targetPowerValT2[ALL_TARGET_LEGACY_48] = | |
4412 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq, | |
4413 | is2GHz); | |
4414 | targetPowerValT2[ALL_TARGET_LEGACY_54] = | |
4415 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq, | |
4416 | is2GHz); | |
75acd5a8 GJ |
4417 | } |
4418 | ||
4419 | static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq, | |
4420 | u8 *targetPowerValT2) | |
4421 | { | |
15c9ee7a SB |
4422 | targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] = |
4423 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L, | |
4424 | freq); | |
4425 | targetPowerValT2[ALL_TARGET_LEGACY_5S] = | |
4426 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq); | |
4427 | targetPowerValT2[ALL_TARGET_LEGACY_11L] = | |
4428 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq); | |
4429 | targetPowerValT2[ALL_TARGET_LEGACY_11S] = | |
4430 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq); | |
75acd5a8 GJ |
4431 | } |
4432 | ||
4433 | static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq, | |
4434 | u8 *targetPowerValT2, bool is2GHz) | |
4435 | { | |
15c9ee7a SB |
4436 | targetPowerValT2[ALL_TARGET_HT20_0_8_16] = |
4437 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, | |
4438 | is2GHz); | |
4439 | targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] = | |
4440 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, | |
4441 | freq, is2GHz); | |
4442 | targetPowerValT2[ALL_TARGET_HT20_4] = | |
4443 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq, | |
4444 | is2GHz); | |
4445 | targetPowerValT2[ALL_TARGET_HT20_5] = | |
4446 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq, | |
4447 | is2GHz); | |
4448 | targetPowerValT2[ALL_TARGET_HT20_6] = | |
4449 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq, | |
4450 | is2GHz); | |
4451 | targetPowerValT2[ALL_TARGET_HT20_7] = | |
4452 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq, | |
4453 | is2GHz); | |
4454 | targetPowerValT2[ALL_TARGET_HT20_12] = | |
4455 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq, | |
4456 | is2GHz); | |
4457 | targetPowerValT2[ALL_TARGET_HT20_13] = | |
4458 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq, | |
4459 | is2GHz); | |
4460 | targetPowerValT2[ALL_TARGET_HT20_14] = | |
4461 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq, | |
4462 | is2GHz); | |
4463 | targetPowerValT2[ALL_TARGET_HT20_15] = | |
4464 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq, | |
4465 | is2GHz); | |
4466 | targetPowerValT2[ALL_TARGET_HT20_20] = | |
4467 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq, | |
4468 | is2GHz); | |
4469 | targetPowerValT2[ALL_TARGET_HT20_21] = | |
4470 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq, | |
4471 | is2GHz); | |
4472 | targetPowerValT2[ALL_TARGET_HT20_22] = | |
4473 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq, | |
4474 | is2GHz); | |
4475 | targetPowerValT2[ALL_TARGET_HT20_23] = | |
4476 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq, | |
4477 | is2GHz); | |
75acd5a8 GJ |
4478 | } |
4479 | ||
4480 | static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah, | |
4481 | u16 freq, | |
4482 | u8 *targetPowerValT2, | |
4483 | bool is2GHz) | |
4484 | { | |
4485 | /* XXX: hard code for now, need to get from eeprom struct */ | |
4486 | u8 ht40PowerIncForPdadc = 0; | |
4487 | ||
15c9ee7a SB |
4488 | targetPowerValT2[ALL_TARGET_HT40_0_8_16] = |
4489 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, | |
4490 | is2GHz) + ht40PowerIncForPdadc; | |
4491 | targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] = | |
4492 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, | |
4493 | freq, | |
4494 | is2GHz) + ht40PowerIncForPdadc; | |
4495 | targetPowerValT2[ALL_TARGET_HT40_4] = | |
4496 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq, | |
4497 | is2GHz) + ht40PowerIncForPdadc; | |
4498 | targetPowerValT2[ALL_TARGET_HT40_5] = | |
4499 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq, | |
4500 | is2GHz) + ht40PowerIncForPdadc; | |
4501 | targetPowerValT2[ALL_TARGET_HT40_6] = | |
4502 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq, | |
4503 | is2GHz) + ht40PowerIncForPdadc; | |
4504 | targetPowerValT2[ALL_TARGET_HT40_7] = | |
4505 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq, | |
4506 | is2GHz) + ht40PowerIncForPdadc; | |
4507 | targetPowerValT2[ALL_TARGET_HT40_12] = | |
4508 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq, | |
4509 | is2GHz) + ht40PowerIncForPdadc; | |
4510 | targetPowerValT2[ALL_TARGET_HT40_13] = | |
4511 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq, | |
4512 | is2GHz) + ht40PowerIncForPdadc; | |
4513 | targetPowerValT2[ALL_TARGET_HT40_14] = | |
4514 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq, | |
4515 | is2GHz) + ht40PowerIncForPdadc; | |
4516 | targetPowerValT2[ALL_TARGET_HT40_15] = | |
4517 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq, | |
4518 | is2GHz) + ht40PowerIncForPdadc; | |
4519 | targetPowerValT2[ALL_TARGET_HT40_20] = | |
4520 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq, | |
4521 | is2GHz) + ht40PowerIncForPdadc; | |
4522 | targetPowerValT2[ALL_TARGET_HT40_21] = | |
4523 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq, | |
4524 | is2GHz) + ht40PowerIncForPdadc; | |
4525 | targetPowerValT2[ALL_TARGET_HT40_22] = | |
4526 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq, | |
4527 | is2GHz) + ht40PowerIncForPdadc; | |
4528 | targetPowerValT2[ALL_TARGET_HT40_23] = | |
4529 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq, | |
4530 | is2GHz) + ht40PowerIncForPdadc; | |
75acd5a8 GJ |
4531 | } |
4532 | ||
4533 | static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah, | |
4534 | struct ath9k_channel *chan, | |
4535 | u8 *targetPowerValT2) | |
4536 | { | |
4537 | bool is2GHz = IS_CHAN_2GHZ(chan); | |
4538 | unsigned int i = 0; | |
4539 | struct ath_common *common = ath9k_hw_common(ah); | |
4540 | u16 freq = chan->channel; | |
4541 | ||
4542 | if (is2GHz) | |
4543 | ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2); | |
4544 | ||
4545 | ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz); | |
4546 | ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz); | |
4547 | ||
4548 | if (IS_CHAN_HT40(chan)) | |
4549 | ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2, | |
4550 | is2GHz); | |
15c9ee7a | 4551 | |
a1cbc7a8 | 4552 | for (i = 0; i < ar9300RateSize; i++) { |
d2182b69 JP |
4553 | ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n", |
4554 | i, targetPowerValT2[i]); | |
15c9ee7a | 4555 | } |
15c9ee7a SB |
4556 | } |
4557 | ||
4558 | static int ar9003_hw_cal_pier_get(struct ath_hw *ah, | |
4559 | int mode, | |
4560 | int ipier, | |
4561 | int ichain, | |
4562 | int *pfrequency, | |
4563 | int *pcorrection, | |
4564 | int *ptemperature, int *pvoltage) | |
4565 | { | |
4566 | u8 *pCalPier; | |
4567 | struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct; | |
4568 | int is2GHz; | |
4569 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
4570 | struct ath_common *common = ath9k_hw_common(ah); | |
4571 | ||
4572 | if (ichain >= AR9300_MAX_CHAINS) { | |
d2182b69 | 4573 | ath_dbg(common, EEPROM, |
226afe68 JP |
4574 | "Invalid chain index, must be less than %d\n", |
4575 | AR9300_MAX_CHAINS); | |
15c9ee7a SB |
4576 | return -1; |
4577 | } | |
4578 | ||
4579 | if (mode) { /* 5GHz */ | |
4580 | if (ipier >= AR9300_NUM_5G_CAL_PIERS) { | |
d2182b69 | 4581 | ath_dbg(common, EEPROM, |
226afe68 JP |
4582 | "Invalid 5GHz cal pier index, must be less than %d\n", |
4583 | AR9300_NUM_5G_CAL_PIERS); | |
15c9ee7a SB |
4584 | return -1; |
4585 | } | |
4586 | pCalPier = &(eep->calFreqPier5G[ipier]); | |
4587 | pCalPierStruct = &(eep->calPierData5G[ichain][ipier]); | |
4588 | is2GHz = 0; | |
4589 | } else { | |
4590 | if (ipier >= AR9300_NUM_2G_CAL_PIERS) { | |
d2182b69 | 4591 | ath_dbg(common, EEPROM, |
226afe68 JP |
4592 | "Invalid 2GHz cal pier index, must be less than %d\n", |
4593 | AR9300_NUM_2G_CAL_PIERS); | |
15c9ee7a SB |
4594 | return -1; |
4595 | } | |
4596 | ||
4597 | pCalPier = &(eep->calFreqPier2G[ipier]); | |
4598 | pCalPierStruct = &(eep->calPierData2G[ichain][ipier]); | |
4599 | is2GHz = 1; | |
4600 | } | |
4601 | ||
8edb254c | 4602 | *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz); |
15c9ee7a SB |
4603 | *pcorrection = pCalPierStruct->refPower; |
4604 | *ptemperature = pCalPierStruct->tempMeas; | |
4605 | *pvoltage = pCalPierStruct->voltMeas; | |
4606 | ||
4607 | return 0; | |
4608 | } | |
4609 | ||
2d7caefb SM |
4610 | static void ar9003_hw_power_control_override(struct ath_hw *ah, |
4611 | int frequency, | |
4612 | int *correction, | |
4613 | int *voltage, int *temperature) | |
15c9ee7a | 4614 | { |
2d7caefb | 4615 | int temp_slope = 0, temp_slope1 = 0, temp_slope2 = 0; |
15c9ee7a | 4616 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
2d7caefb | 4617 | int f[8], t[8], t1[3], t2[3], i; |
15c9ee7a SB |
4618 | |
4619 | REG_RMW(ah, AR_PHY_TPC_11_B0, | |
4620 | (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), | |
4621 | AR_PHY_TPC_OLPC_GAIN_DELTA); | |
5f139eba VT |
4622 | if (ah->caps.tx_chainmask & BIT(1)) |
4623 | REG_RMW(ah, AR_PHY_TPC_11_B1, | |
4624 | (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), | |
4625 | AR_PHY_TPC_OLPC_GAIN_DELTA); | |
4626 | if (ah->caps.tx_chainmask & BIT(2)) | |
4627 | REG_RMW(ah, AR_PHY_TPC_11_B2, | |
4628 | (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), | |
4629 | AR_PHY_TPC_OLPC_GAIN_DELTA); | |
15c9ee7a SB |
4630 | |
4631 | /* enable open loop power control on chip */ | |
4632 | REG_RMW(ah, AR_PHY_TPC_6_B0, | |
4633 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), | |
4634 | AR_PHY_TPC_6_ERROR_EST_MODE); | |
5f139eba VT |
4635 | if (ah->caps.tx_chainmask & BIT(1)) |
4636 | REG_RMW(ah, AR_PHY_TPC_6_B1, | |
4637 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), | |
4638 | AR_PHY_TPC_6_ERROR_EST_MODE); | |
4639 | if (ah->caps.tx_chainmask & BIT(2)) | |
4640 | REG_RMW(ah, AR_PHY_TPC_6_B2, | |
4641 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), | |
4642 | AR_PHY_TPC_6_ERROR_EST_MODE); | |
15c9ee7a SB |
4643 | |
4644 | /* | |
4645 | * enable temperature compensation | |
4646 | * Need to use register names | |
4647 | */ | |
2d7caefb SM |
4648 | if (frequency < 4000) { |
4649 | temp_slope = eep->modalHeader2G.tempSlope; | |
4650 | } else { | |
4651 | if (AR_SREV_9550(ah)) { | |
4652 | t[0] = eep->base_ext1.tempslopextension[2]; | |
4653 | t1[0] = eep->base_ext1.tempslopextension[3]; | |
4654 | t2[0] = eep->base_ext1.tempslopextension[4]; | |
4655 | f[0] = 5180; | |
4656 | ||
4657 | t[1] = eep->modalHeader5G.tempSlope; | |
4658 | t1[1] = eep->base_ext1.tempslopextension[0]; | |
4659 | t2[1] = eep->base_ext1.tempslopextension[1]; | |
4660 | f[1] = 5500; | |
4661 | ||
4662 | t[2] = eep->base_ext1.tempslopextension[5]; | |
4663 | t1[2] = eep->base_ext1.tempslopextension[6]; | |
4664 | t2[2] = eep->base_ext1.tempslopextension[7]; | |
4665 | f[2] = 5785; | |
4666 | ||
4667 | temp_slope = ar9003_hw_power_interpolate(frequency, | |
4668 | f, t, 3); | |
4669 | temp_slope1 = ar9003_hw_power_interpolate(frequency, | |
4670 | f, t1, 3); | |
4671 | temp_slope2 = ar9003_hw_power_interpolate(frequency, | |
4672 | f, t2, 3); | |
4673 | ||
4674 | goto tempslope; | |
420e2b1b | 4675 | } |
15c9ee7a | 4676 | |
2d7caefb SM |
4677 | if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) { |
4678 | for (i = 0; i < 8; i++) { | |
4679 | t[i] = eep->base_ext1.tempslopextension[i]; | |
4680 | f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0); | |
4681 | } | |
4682 | temp_slope = ar9003_hw_power_interpolate((s32) frequency, | |
4683 | f, t, 8); | |
4684 | } else if (eep->base_ext2.tempSlopeLow != 0) { | |
4685 | t[0] = eep->base_ext2.tempSlopeLow; | |
4686 | f[0] = 5180; | |
4687 | t[1] = eep->modalHeader5G.tempSlope; | |
4688 | f[1] = 5500; | |
4689 | t[2] = eep->base_ext2.tempSlopeHigh; | |
4690 | f[2] = 5785; | |
4691 | temp_slope = ar9003_hw_power_interpolate((s32) frequency, | |
4692 | f, t, 3); | |
4693 | } else { | |
4694 | temp_slope = eep->modalHeader5G.tempSlope; | |
4695 | } | |
4696 | } | |
4697 | ||
4698 | tempslope: | |
4699 | if (AR_SREV_9550(ah)) { | |
4700 | /* | |
4701 | * AR955x has tempSlope register for each chain. | |
4702 | * Check whether temp_compensation feature is enabled or not. | |
4703 | */ | |
4704 | if (eep->baseEepHeader.featureEnable & 0x1) { | |
4705 | if (frequency < 4000) { | |
4706 | REG_RMW_FIELD(ah, AR_PHY_TPC_19, | |
4707 | AR_PHY_TPC_19_ALPHA_THERM, | |
4708 | eep->base_ext2.tempSlopeLow); | |
4709 | REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, | |
4710 | AR_PHY_TPC_19_ALPHA_THERM, | |
4711 | temp_slope); | |
4712 | REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, | |
4713 | AR_PHY_TPC_19_ALPHA_THERM, | |
4714 | eep->base_ext2.tempSlopeHigh); | |
4715 | } else { | |
4716 | REG_RMW_FIELD(ah, AR_PHY_TPC_19, | |
4717 | AR_PHY_TPC_19_ALPHA_THERM, | |
4718 | temp_slope); | |
4719 | REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, | |
4720 | AR_PHY_TPC_19_ALPHA_THERM, | |
4721 | temp_slope1); | |
4722 | REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, | |
4723 | AR_PHY_TPC_19_ALPHA_THERM, | |
4724 | temp_slope2); | |
4725 | } | |
4726 | } else { | |
4727 | /* | |
4728 | * If temp compensation is not enabled, | |
4729 | * set all registers to 0. | |
4730 | */ | |
4731 | REG_RMW_FIELD(ah, AR_PHY_TPC_19, | |
4732 | AR_PHY_TPC_19_ALPHA_THERM, 0); | |
4733 | REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, | |
4734 | AR_PHY_TPC_19_ALPHA_THERM, 0); | |
4735 | REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, | |
4736 | AR_PHY_TPC_19_ALPHA_THERM, 0); | |
4737 | } | |
4738 | } else { | |
4739 | REG_RMW_FIELD(ah, AR_PHY_TPC_19, | |
4740 | AR_PHY_TPC_19_ALPHA_THERM, temp_slope); | |
4741 | } | |
2577c6e8 | 4742 | |
423e38e8 | 4743 | if (AR_SREV_9462_20(ah)) |
2577c6e8 | 4744 | REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, |
2d7caefb | 4745 | AR_PHY_TPC_19_B1_ALPHA_THERM, temp_slope); |
2577c6e8 SB |
4746 | |
4747 | ||
15c9ee7a SB |
4748 | REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, |
4749 | temperature[0]); | |
15c9ee7a SB |
4750 | } |
4751 | ||
4752 | /* Apply the recorded correction values. */ | |
4753 | static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) | |
4754 | { | |
4755 | int ichain, ipier, npier; | |
4756 | int mode; | |
4757 | int lfrequency[AR9300_MAX_CHAINS], | |
4758 | lcorrection[AR9300_MAX_CHAINS], | |
4759 | ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS]; | |
4760 | int hfrequency[AR9300_MAX_CHAINS], | |
4761 | hcorrection[AR9300_MAX_CHAINS], | |
4762 | htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS]; | |
4763 | int fdiff; | |
4764 | int correction[AR9300_MAX_CHAINS], | |
4765 | voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS]; | |
4766 | int pfrequency, pcorrection, ptemperature, pvoltage; | |
4767 | struct ath_common *common = ath9k_hw_common(ah); | |
4768 | ||
4769 | mode = (frequency >= 4000); | |
4770 | if (mode) | |
4771 | npier = AR9300_NUM_5G_CAL_PIERS; | |
4772 | else | |
4773 | npier = AR9300_NUM_2G_CAL_PIERS; | |
4774 | ||
4775 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { | |
4776 | lfrequency[ichain] = 0; | |
4777 | hfrequency[ichain] = 100000; | |
4778 | } | |
4779 | /* identify best lower and higher frequency calibration measurement */ | |
4780 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { | |
4781 | for (ipier = 0; ipier < npier; ipier++) { | |
4782 | if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain, | |
4783 | &pfrequency, &pcorrection, | |
4784 | &ptemperature, &pvoltage)) { | |
4785 | fdiff = frequency - pfrequency; | |
4786 | ||
4787 | /* | |
4788 | * this measurement is higher than | |
4789 | * our desired frequency | |
4790 | */ | |
4791 | if (fdiff <= 0) { | |
4792 | if (hfrequency[ichain] <= 0 || | |
4793 | hfrequency[ichain] >= 100000 || | |
4794 | fdiff > | |
4795 | (frequency - hfrequency[ichain])) { | |
4796 | /* | |
4797 | * new best higher | |
4798 | * frequency measurement | |
4799 | */ | |
4800 | hfrequency[ichain] = pfrequency; | |
4801 | hcorrection[ichain] = | |
4802 | pcorrection; | |
4803 | htemperature[ichain] = | |
4804 | ptemperature; | |
4805 | hvoltage[ichain] = pvoltage; | |
4806 | } | |
4807 | } | |
4808 | if (fdiff >= 0) { | |
4809 | if (lfrequency[ichain] <= 0 | |
4810 | || fdiff < | |
4811 | (frequency - lfrequency[ichain])) { | |
4812 | /* | |
4813 | * new best lower | |
4814 | * frequency measurement | |
4815 | */ | |
4816 | lfrequency[ichain] = pfrequency; | |
4817 | lcorrection[ichain] = | |
4818 | pcorrection; | |
4819 | ltemperature[ichain] = | |
4820 | ptemperature; | |
4821 | lvoltage[ichain] = pvoltage; | |
4822 | } | |
4823 | } | |
4824 | } | |
4825 | } | |
4826 | } | |
4827 | ||
4828 | /* interpolate */ | |
4829 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { | |
d2182b69 | 4830 | ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n", |
226afe68 JP |
4831 | ichain, frequency, lfrequency[ichain], |
4832 | lcorrection[ichain], hfrequency[ichain], | |
4833 | hcorrection[ichain]); | |
15c9ee7a SB |
4834 | /* they're the same, so just pick one */ |
4835 | if (hfrequency[ichain] == lfrequency[ichain]) { | |
4836 | correction[ichain] = lcorrection[ichain]; | |
4837 | voltage[ichain] = lvoltage[ichain]; | |
4838 | temperature[ichain] = ltemperature[ichain]; | |
4839 | } | |
4840 | /* the low frequency is good */ | |
4841 | else if (frequency - lfrequency[ichain] < 1000) { | |
4842 | /* so is the high frequency, interpolate */ | |
4843 | if (hfrequency[ichain] - frequency < 1000) { | |
4844 | ||
bc206802 VT |
4845 | correction[ichain] = interpolate(frequency, |
4846 | lfrequency[ichain], | |
4847 | hfrequency[ichain], | |
4848 | lcorrection[ichain], | |
4849 | hcorrection[ichain]); | |
4850 | ||
4851 | temperature[ichain] = interpolate(frequency, | |
4852 | lfrequency[ichain], | |
4853 | hfrequency[ichain], | |
4854 | ltemperature[ichain], | |
4855 | htemperature[ichain]); | |
4856 | ||
4857 | voltage[ichain] = interpolate(frequency, | |
4858 | lfrequency[ichain], | |
4859 | hfrequency[ichain], | |
4860 | lvoltage[ichain], | |
4861 | hvoltage[ichain]); | |
15c9ee7a SB |
4862 | } |
4863 | /* only low is good, use it */ | |
4864 | else { | |
4865 | correction[ichain] = lcorrection[ichain]; | |
4866 | temperature[ichain] = ltemperature[ichain]; | |
4867 | voltage[ichain] = lvoltage[ichain]; | |
4868 | } | |
4869 | } | |
4870 | /* only high is good, use it */ | |
4871 | else if (hfrequency[ichain] - frequency < 1000) { | |
4872 | correction[ichain] = hcorrection[ichain]; | |
4873 | temperature[ichain] = htemperature[ichain]; | |
4874 | voltage[ichain] = hvoltage[ichain]; | |
4875 | } else { /* nothing is good, presume 0???? */ | |
4876 | correction[ichain] = 0; | |
4877 | temperature[ichain] = 0; | |
4878 | voltage[ichain] = 0; | |
4879 | } | |
4880 | } | |
4881 | ||
4882 | ar9003_hw_power_control_override(ah, frequency, correction, voltage, | |
4883 | temperature); | |
4884 | ||
d2182b69 | 4885 | ath_dbg(common, EEPROM, |
226afe68 JP |
4886 | "for frequency=%d, calibration correction = %d %d %d\n", |
4887 | frequency, correction[0], correction[1], correction[2]); | |
15c9ee7a SB |
4888 | |
4889 | return 0; | |
4890 | } | |
4891 | ||
824b185a LR |
4892 | static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, |
4893 | int idx, | |
4894 | int edge, | |
4895 | bool is2GHz) | |
4896 | { | |
4897 | struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; | |
4898 | struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; | |
4899 | ||
4900 | if (is2GHz) | |
e702ba18 | 4901 | return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]); |
824b185a | 4902 | else |
e702ba18 | 4903 | return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]); |
824b185a LR |
4904 | } |
4905 | ||
4906 | static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, | |
4907 | int idx, | |
4908 | unsigned int edge, | |
4909 | u16 freq, | |
4910 | bool is2GHz) | |
4911 | { | |
4912 | struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; | |
4913 | struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; | |
4914 | ||
4915 | u8 *ctl_freqbin = is2GHz ? | |
4916 | &eep->ctl_freqbin_2G[idx][0] : | |
4917 | &eep->ctl_freqbin_5G[idx][0]; | |
4918 | ||
4919 | if (is2GHz) { | |
4920 | if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && | |
e702ba18 FF |
4921 | CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1])) |
4922 | return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]); | |
824b185a LR |
4923 | } else { |
4924 | if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && | |
e702ba18 FF |
4925 | CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1])) |
4926 | return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); | |
824b185a LR |
4927 | } |
4928 | ||
4ddfcd7d | 4929 | return MAX_RATE_POWER; |
824b185a LR |
4930 | } |
4931 | ||
4932 | /* | |
4933 | * Find the maximum conformance test limit for the given channel and CTL info | |
4934 | */ | |
4935 | static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, | |
4936 | u16 freq, int idx, bool is2GHz) | |
4937 | { | |
4ddfcd7d | 4938 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
824b185a LR |
4939 | u8 *ctl_freqbin = is2GHz ? |
4940 | &eep->ctl_freqbin_2G[idx][0] : | |
4941 | &eep->ctl_freqbin_5G[idx][0]; | |
4942 | u16 num_edges = is2GHz ? | |
4943 | AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G; | |
4944 | unsigned int edge; | |
4945 | ||
4946 | /* Get the edge power */ | |
4947 | for (edge = 0; | |
4ddfcd7d | 4948 | (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED); |
824b185a LR |
4949 | edge++) { |
4950 | /* | |
4951 | * If there's an exact channel match or an inband flag set | |
4952 | * on the lower channel use the given rdEdgePower | |
4953 | */ | |
4954 | if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) { | |
4955 | twiceMaxEdgePower = | |
4956 | ar9003_hw_get_direct_edge_power(eep, idx, | |
4957 | edge, is2GHz); | |
4958 | break; | |
4959 | } else if ((edge > 0) && | |
4960 | (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge], | |
4961 | is2GHz))) { | |
4962 | twiceMaxEdgePower = | |
4963 | ar9003_hw_get_indirect_edge_power(eep, idx, | |
4964 | edge, freq, | |
4965 | is2GHz); | |
4966 | /* | |
4967 | * Leave loop - no more affecting edges possible in | |
4968 | * this monotonic increasing list | |
4969 | */ | |
4970 | break; | |
4971 | } | |
4972 | } | |
4973 | return twiceMaxEdgePower; | |
4974 | } | |
4975 | ||
4976 | static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |
4977 | struct ath9k_channel *chan, | |
4978 | u8 *pPwrArray, u16 cfgCtl, | |
ca2c68cc | 4979 | u8 antenna_reduction, |
824b185a LR |
4980 | u16 powerLimit) |
4981 | { | |
824b185a LR |
4982 | struct ath_common *common = ath9k_hw_common(ah); |
4983 | struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; | |
a261f0e9 | 4984 | u16 twiceMaxEdgePower; |
824b185a | 4985 | int i; |
ca2c68cc | 4986 | u16 scaledPower = 0, minCtlPower; |
07b2fa5a | 4987 | static const u16 ctlModesFor11a[] = { |
824b185a LR |
4988 | CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 |
4989 | }; | |
07b2fa5a | 4990 | static const u16 ctlModesFor11g[] = { |
824b185a LR |
4991 | CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, |
4992 | CTL_11G_EXT, CTL_2GHT40 | |
4993 | }; | |
07b2fa5a JP |
4994 | u16 numCtlModes; |
4995 | const u16 *pCtlMode; | |
4996 | u16 ctlMode, freq; | |
824b185a LR |
4997 | struct chan_centers centers; |
4998 | u8 *ctlIndex; | |
4999 | u8 ctlNum; | |
5000 | u16 twiceMinEdgePower; | |
5001 | bool is2ghz = IS_CHAN_2GHZ(chan); | |
5002 | ||
5003 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
ea6f792b GJ |
5004 | scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit, |
5005 | antenna_reduction); | |
824b185a | 5006 | |
824b185a LR |
5007 | if (is2ghz) { |
5008 | /* Setup for CTL modes */ | |
5009 | /* CTL_11B, CTL_11G, CTL_2GHT20 */ | |
5010 | numCtlModes = | |
5011 | ARRAY_SIZE(ctlModesFor11g) - | |
5012 | SUB_NUM_CTL_MODES_AT_2G_40; | |
5013 | pCtlMode = ctlModesFor11g; | |
5014 | if (IS_CHAN_HT40(chan)) | |
5015 | /* All 2G CTL's */ | |
5016 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
5017 | } else { | |
5018 | /* Setup for CTL modes */ | |
5019 | /* CTL_11A, CTL_5GHT20 */ | |
5020 | numCtlModes = ARRAY_SIZE(ctlModesFor11a) - | |
5021 | SUB_NUM_CTL_MODES_AT_5G_40; | |
5022 | pCtlMode = ctlModesFor11a; | |
5023 | if (IS_CHAN_HT40(chan)) | |
5024 | /* All 5G CTL's */ | |
5025 | numCtlModes = ARRAY_SIZE(ctlModesFor11a); | |
5026 | } | |
5027 | ||
5028 | /* | |
5029 | * For MIMO, need to apply regulatory caps individually across | |
5030 | * dynamically running modes: CCK, OFDM, HT20, HT40 | |
5031 | * | |
5032 | * The outer loop walks through each possible applicable runtime mode. | |
5033 | * The inner loop walks through each ctlIndex entry in EEPROM. | |
5034 | * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. | |
5035 | */ | |
5036 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
5037 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
5038 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
5039 | if (isHt40CtlMode) | |
5040 | freq = centers.synth_center; | |
5041 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
5042 | freq = centers.ext_center; | |
5043 | else | |
5044 | freq = centers.ctl_center; | |
5045 | ||
d2182b69 | 5046 | ath_dbg(common, REGULATORY, |
226afe68 JP |
5047 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", |
5048 | ctlMode, numCtlModes, isHt40CtlMode, | |
5049 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); | |
824b185a LR |
5050 | |
5051 | /* walk through each CTL index stored in EEPROM */ | |
5052 | if (is2ghz) { | |
5053 | ctlIndex = pEepData->ctlIndex_2G; | |
5054 | ctlNum = AR9300_NUM_CTLS_2G; | |
5055 | } else { | |
5056 | ctlIndex = pEepData->ctlIndex_5G; | |
5057 | ctlNum = AR9300_NUM_CTLS_5G; | |
5058 | } | |
5059 | ||
a261f0e9 | 5060 | twiceMaxEdgePower = MAX_RATE_POWER; |
824b185a | 5061 | for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { |
d2182b69 | 5062 | ath_dbg(common, REGULATORY, |
226afe68 JP |
5063 | "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", |
5064 | i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], | |
5065 | chan->channel); | |
824b185a | 5066 | |
2a0b50c7 GJ |
5067 | /* |
5068 | * compare test group from regulatory | |
5069 | * channel list with test mode from pCtlMode | |
5070 | * list | |
5071 | */ | |
5072 | if ((((cfgCtl & ~CTL_MODE_M) | | |
5073 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
5074 | ctlIndex[i]) || | |
5075 | (((cfgCtl & ~CTL_MODE_M) | | |
5076 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
5077 | ((ctlIndex[i] & CTL_MODE_M) | | |
5078 | SD_NO_CTL))) { | |
5079 | twiceMinEdgePower = | |
5080 | ar9003_hw_get_max_edge_power(pEepData, | |
5081 | freq, i, | |
5082 | is2ghz); | |
5083 | ||
5084 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) | |
5085 | /* | |
5086 | * Find the minimum of all CTL | |
5087 | * edge powers that apply to | |
5088 | * this channel | |
5089 | */ | |
5090 | twiceMaxEdgePower = | |
5091 | min(twiceMaxEdgePower, | |
5092 | twiceMinEdgePower); | |
5093 | else { | |
5094 | /* specific */ | |
5095 | twiceMaxEdgePower = twiceMinEdgePower; | |
5096 | break; | |
824b185a LR |
5097 | } |
5098 | } | |
2a0b50c7 | 5099 | } |
824b185a | 5100 | |
2a0b50c7 | 5101 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); |
824b185a | 5102 | |
2a0b50c7 GJ |
5103 | ath_dbg(common, REGULATORY, |
5104 | "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", | |
5105 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, | |
5106 | scaledPower, minCtlPower); | |
5107 | ||
5108 | /* Apply ctl mode to correct target power set */ | |
5109 | switch (pCtlMode[ctlMode]) { | |
5110 | case CTL_11B: | |
5111 | for (i = ALL_TARGET_LEGACY_1L_5L; | |
5112 | i <= ALL_TARGET_LEGACY_11S; i++) | |
5113 | pPwrArray[i] = (u8)min((u16)pPwrArray[i], | |
5114 | minCtlPower); | |
5115 | break; | |
5116 | case CTL_11A: | |
5117 | case CTL_11G: | |
5118 | for (i = ALL_TARGET_LEGACY_6_24; | |
5119 | i <= ALL_TARGET_LEGACY_54; i++) | |
5120 | pPwrArray[i] = (u8)min((u16)pPwrArray[i], | |
5121 | minCtlPower); | |
5122 | break; | |
5123 | case CTL_5GHT20: | |
5124 | case CTL_2GHT20: | |
5125 | for (i = ALL_TARGET_HT20_0_8_16; | |
e82cb03f | 5126 | i <= ALL_TARGET_HT20_23; i++) { |
2a0b50c7 GJ |
5127 | pPwrArray[i] = (u8)min((u16)pPwrArray[i], |
5128 | minCtlPower); | |
e82cb03f RM |
5129 | if (ath9k_hw_mci_is_enabled(ah)) |
5130 | pPwrArray[i] = | |
5131 | (u8)min((u16)pPwrArray[i], | |
5132 | ar9003_mci_get_max_txpower(ah, | |
5133 | pCtlMode[ctlMode])); | |
5134 | } | |
2a0b50c7 GJ |
5135 | break; |
5136 | case CTL_5GHT40: | |
5137 | case CTL_2GHT40: | |
5138 | for (i = ALL_TARGET_HT40_0_8_16; | |
e82cb03f | 5139 | i <= ALL_TARGET_HT40_23; i++) { |
2a0b50c7 GJ |
5140 | pPwrArray[i] = (u8)min((u16)pPwrArray[i], |
5141 | minCtlPower); | |
e82cb03f RM |
5142 | if (ath9k_hw_mci_is_enabled(ah)) |
5143 | pPwrArray[i] = | |
5144 | (u8)min((u16)pPwrArray[i], | |
5145 | ar9003_mci_get_max_txpower(ah, | |
5146 | pCtlMode[ctlMode])); | |
5147 | } | |
2a0b50c7 GJ |
5148 | break; |
5149 | default: | |
5150 | break; | |
5151 | } | |
824b185a LR |
5152 | } /* end ctl mode checking */ |
5153 | } | |
5154 | ||
45ef6a0b VT |
5155 | static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx) |
5156 | { | |
5157 | u8 mod_idx = mcs_idx % 8; | |
5158 | ||
5159 | if (mod_idx <= 3) | |
5160 | return mod_idx ? (base_pwridx + 1) : base_pwridx; | |
5161 | else | |
5162 | return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2; | |
5163 | } | |
5164 | ||
1562580e SM |
5165 | static void ar9003_paprd_set_txpower(struct ath_hw *ah, |
5166 | struct ath9k_channel *chan, | |
5167 | u8 *targetPowerValT2) | |
5168 | { | |
5169 | int i; | |
5170 | ||
5171 | if (!ar9003_is_paprd_enabled(ah)) | |
5172 | return; | |
5173 | ||
5174 | if (IS_CHAN_HT40(chan)) | |
5175 | i = ALL_TARGET_HT40_7; | |
5176 | else | |
5177 | i = ALL_TARGET_HT20_7; | |
5178 | ||
5179 | if (IS_CHAN_2GHZ(chan)) { | |
5180 | if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && | |
5181 | !AR_SREV_9462(ah) && !AR_SREV_9565(ah)) { | |
5182 | if (IS_CHAN_HT40(chan)) | |
5183 | i = ALL_TARGET_HT40_0_8_16; | |
5184 | else | |
5185 | i = ALL_TARGET_HT20_0_8_16; | |
5186 | } | |
5187 | } | |
5188 | ||
5189 | ah->paprd_target_power = targetPowerValT2[i]; | |
5190 | } | |
5191 | ||
15c9ee7a SB |
5192 | static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, |
5193 | struct ath9k_channel *chan, u16 cfgCtl, | |
5194 | u8 twiceAntennaReduction, | |
de40f316 | 5195 | u8 powerLimit, bool test) |
15c9ee7a | 5196 | { |
6b7b6cf5 | 5197 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
824b185a | 5198 | struct ath_common *common = ath9k_hw_common(ah); |
7072bf62 | 5199 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
f1a8abb0 | 5200 | struct ar9300_modal_eep_header *modal_hdr; |
824b185a | 5201 | u8 targetPowerValT2[ar9300RateSize]; |
7072bf62 VT |
5202 | u8 target_power_val_t2_eep[ar9300RateSize]; |
5203 | unsigned int i = 0, paprd_scale_factor = 0; | |
45ef6a0b | 5204 | u8 pwr_idx, min_pwridx = 0; |
824b185a | 5205 | |
75acd5a8 GJ |
5206 | memset(targetPowerValT2, 0 , sizeof(targetPowerValT2)); |
5207 | ||
5208 | /* | |
5209 | * Get target powers from EEPROM - our baseline for TX Power | |
5210 | */ | |
5211 | ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2); | |
7072bf62 | 5212 | |
0f21ee8d | 5213 | if (ar9003_is_paprd_enabled(ah)) { |
7072bf62 | 5214 | if (IS_CHAN_2GHZ(chan)) |
f1a8abb0 | 5215 | modal_hdr = &eep->modalHeader2G; |
7072bf62 | 5216 | else |
f1a8abb0 FF |
5217 | modal_hdr = &eep->modalHeader5G; |
5218 | ||
5219 | ah->paprd_ratemask = | |
5220 | le32_to_cpu(modal_hdr->papdRateMaskHt20) & | |
5221 | AR9300_PAPRD_RATE_MASK; | |
5222 | ||
5223 | ah->paprd_ratemask_ht40 = | |
5224 | le32_to_cpu(modal_hdr->papdRateMaskHt40) & | |
5225 | AR9300_PAPRD_RATE_MASK; | |
7072bf62 | 5226 | |
45ef6a0b VT |
5227 | paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan); |
5228 | min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 : | |
5229 | ALL_TARGET_HT20_0_8_16; | |
5230 | ||
5231 | if (!ah->paprd_table_write_done) { | |
5232 | memcpy(target_power_val_t2_eep, targetPowerValT2, | |
5233 | sizeof(targetPowerValT2)); | |
5234 | for (i = 0; i < 24; i++) { | |
5235 | pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx); | |
5236 | if (ah->paprd_ratemask & (1 << i)) { | |
5237 | if (targetPowerValT2[pwr_idx] && | |
5238 | targetPowerValT2[pwr_idx] == | |
5239 | target_power_val_t2_eep[pwr_idx]) | |
5240 | targetPowerValT2[pwr_idx] -= | |
5241 | paprd_scale_factor; | |
5242 | } | |
5243 | } | |
5244 | } | |
7072bf62 VT |
5245 | memcpy(target_power_val_t2_eep, targetPowerValT2, |
5246 | sizeof(targetPowerValT2)); | |
5247 | } | |
5248 | ||
824b185a LR |
5249 | ar9003_hw_set_power_per_rate_table(ah, chan, |
5250 | targetPowerValT2, cfgCtl, | |
5251 | twiceAntennaReduction, | |
824b185a LR |
5252 | powerLimit); |
5253 | ||
0f21ee8d | 5254 | if (ar9003_is_paprd_enabled(ah)) { |
7072bf62 VT |
5255 | for (i = 0; i < ar9300RateSize; i++) { |
5256 | if ((ah->paprd_ratemask & (1 << i)) && | |
5257 | (abs(targetPowerValT2[i] - | |
5258 | target_power_val_t2_eep[i]) > | |
5259 | paprd_scale_factor)) { | |
5260 | ah->paprd_ratemask &= ~(1 << i); | |
d2182b69 | 5261 | ath_dbg(common, EEPROM, |
7072bf62 VT |
5262 | "paprd disabled for mcs %d\n", i); |
5263 | } | |
5264 | } | |
5265 | } | |
5266 | ||
de40f316 FF |
5267 | regulatory->max_power_level = 0; |
5268 | for (i = 0; i < ar9300RateSize; i++) { | |
5269 | if (targetPowerValT2[i] > regulatory->max_power_level) | |
5270 | regulatory->max_power_level = targetPowerValT2[i]; | |
5271 | } | |
5272 | ||
8915f980 RM |
5273 | ath9k_hw_update_regulatory_maxpower(ah); |
5274 | ||
de40f316 FF |
5275 | if (test) |
5276 | return; | |
5277 | ||
5278 | for (i = 0; i < ar9300RateSize; i++) { | |
d2182b69 JP |
5279 | ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n", |
5280 | i, targetPowerValT2[i]); | |
824b185a LR |
5281 | } |
5282 | ||
de40f316 FF |
5283 | /* Write target power array to registers */ |
5284 | ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); | |
15c9ee7a | 5285 | ar9003_hw_calibration_apply(ah, chan->channel); |
1562580e | 5286 | ar9003_paprd_set_txpower(ah, chan, targetPowerValT2); |
15c9ee7a SB |
5287 | } |
5288 | ||
5289 | static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, | |
5290 | u16 i, bool is2GHz) | |
5291 | { | |
5292 | return AR_NO_SPUR; | |
5293 | } | |
5294 | ||
c14a85da LR |
5295 | s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah) |
5296 | { | |
5297 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
5298 | ||
5299 | return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */ | |
5300 | } | |
5301 | ||
5302 | s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) | |
5303 | { | |
5304 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
5305 | ||
5306 | return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ | |
5307 | } | |
5308 | ||
0aefc591 | 5309 | u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz) |
272ceba8 | 5310 | { |
0aefc591 | 5311 | return ar9003_modal_header(ah, is2ghz)->spurChans; |
272ceba8 VT |
5312 | } |
5313 | ||
8698bca6 VT |
5314 | unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, |
5315 | struct ath9k_channel *chan) | |
5316 | { | |
5317 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
5318 | ||
5319 | if (IS_CHAN_2GHZ(chan)) | |
5320 | return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20), | |
5321 | AR9300_PAPRD_SCALE_1); | |
5322 | else { | |
5323 | if (chan->channel >= 5700) | |
5324 | return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20), | |
5325 | AR9300_PAPRD_SCALE_1); | |
5326 | else if (chan->channel >= 5400) | |
5327 | return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40), | |
5328 | AR9300_PAPRD_SCALE_2); | |
5329 | else | |
5330 | return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40), | |
5331 | AR9300_PAPRD_SCALE_1); | |
5332 | } | |
5333 | } | |
5334 | ||
15c9ee7a SB |
5335 | const struct eeprom_ops eep_ar9300_ops = { |
5336 | .check_eeprom = ath9k_hw_ar9300_check_eeprom, | |
5337 | .get_eeprom = ath9k_hw_ar9300_get_eeprom, | |
5338 | .fill_eeprom = ath9k_hw_ar9300_fill_eeprom, | |
26526202 | 5339 | .dump_eeprom = ath9k_hw_ar9003_dump_eeprom, |
15c9ee7a SB |
5340 | .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver, |
5341 | .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev, | |
15c9ee7a SB |
5342 | .set_board_values = ath9k_hw_ar9300_set_board_values, |
5343 | .set_addac = ath9k_hw_ar9300_set_addac, | |
5344 | .set_txpower = ath9k_hw_ar9300_set_txpower, | |
5345 | .get_spur_channel = ath9k_hw_ar9300_get_spur_channel | |
5346 | }; |