Commit | Line | Data |
---|---|---|
ceb26445 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2010-2011 Atheros Communications Inc. |
ceb26445 VT |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef AR9003_MAC_H | |
18 | #define AR9003_MAC_H | |
19 | ||
ad7b8060 VT |
20 | #define AR_DescId 0xffff0000 |
21 | #define AR_DescId_S 16 | |
22 | #define AR_CtrlStat 0x00004000 | |
994089db | 23 | #define AR_CtrlStat_S 14 |
ad7b8060 | 24 | #define AR_TxRxDesc 0x00008000 |
994089db VT |
25 | #define AR_TxRxDesc_S 15 |
26 | #define AR_TxQcuNum 0x00000f00 | |
27 | #define AR_TxQcuNum_S 8 | |
28 | ||
29 | #define AR_BufLen 0x0fff0000 | |
30 | #define AR_BufLen_S 16 | |
31 | ||
32 | #define AR_TxDescId 0xffff0000 | |
33 | #define AR_TxDescId_S 16 | |
34 | #define AR_TxPtrChkSum 0x0000ffff | |
35 | ||
994089db VT |
36 | #define AR_LowRxChain 0x00004000 |
37 | ||
38 | #define AR_Not_Sounding 0x20000000 | |
ad7b8060 | 39 | |
717f6bed FF |
40 | /* ctl 12 */ |
41 | #define AR_PAPRDChainMask 0x00000e00 | |
42 | #define AR_PAPRDChainMask_S 9 | |
43 | ||
6c84ce08 VT |
44 | #define MAP_ISR_S2_CST 6 |
45 | #define MAP_ISR_S2_GTT 6 | |
46 | #define MAP_ISR_S2_TIM 3 | |
47 | #define MAP_ISR_S2_CABEND 0 | |
48 | #define MAP_ISR_S2_DTIMSYNC 7 | |
49 | #define MAP_ISR_S2_DTIM 7 | |
50 | #define MAP_ISR_S2_TSFOOR 4 | |
aea702b7 | 51 | #define MAP_ISR_S2_BB_WATCHDOG 6 |
6c84ce08 | 52 | |
994089db VT |
53 | #define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds) |
54 | ||
ceb26445 VT |
55 | struct ar9003_rxs { |
56 | u32 ds_info; | |
57 | u32 status1; | |
58 | u32 status2; | |
59 | u32 status3; | |
60 | u32 status4; | |
61 | u32 status5; | |
62 | u32 status6; | |
63 | u32 status7; | |
64 | u32 status8; | |
65 | u32 status9; | |
66 | u32 status10; | |
67 | u32 status11; | |
ada9f1ca | 68 | } __packed __aligned(4); |
ceb26445 | 69 | |
162c3be3 VT |
70 | /* Transmit Control Descriptor */ |
71 | struct ar9003_txc { | |
72 | u32 info; /* descriptor information */ | |
73 | u32 link; /* link pointer */ | |
74 | u32 data0; /* data pointer to 1st buffer */ | |
75 | u32 ctl3; /* DMA control 3 */ | |
76 | u32 data1; /* data pointer to 2nd buffer */ | |
77 | u32 ctl5; /* DMA control 5 */ | |
78 | u32 data2; /* data pointer to 3rd buffer */ | |
79 | u32 ctl7; /* DMA control 7 */ | |
80 | u32 data3; /* data pointer to 4th buffer */ | |
81 | u32 ctl9; /* DMA control 9 */ | |
82 | u32 ctl10; /* DMA control 10 */ | |
83 | u32 ctl11; /* DMA control 11 */ | |
84 | u32 ctl12; /* DMA control 12 */ | |
85 | u32 ctl13; /* DMA control 13 */ | |
86 | u32 ctl14; /* DMA control 14 */ | |
87 | u32 ctl15; /* DMA control 15 */ | |
88 | u32 ctl16; /* DMA control 16 */ | |
89 | u32 ctl17; /* DMA control 17 */ | |
90 | u32 ctl18; /* DMA control 18 */ | |
91 | u32 ctl19; /* DMA control 19 */ | |
92 | u32 ctl20; /* DMA control 20 */ | |
93 | u32 ctl21; /* DMA control 21 */ | |
94 | u32 ctl22; /* DMA control 22 */ | |
9da27232 SM |
95 | u32 ctl23; /* DMA control 23 */ |
96 | u32 pad[8]; /* pad to cache line (128 bytes/32 dwords) */ | |
ada9f1ca | 97 | } __packed __aligned(4); |
162c3be3 | 98 | |
744d4025 VT |
99 | struct ar9003_txs { |
100 | u32 ds_info; | |
101 | u32 status1; | |
102 | u32 status2; | |
103 | u32 status3; | |
104 | u32 status4; | |
105 | u32 status5; | |
106 | u32 status6; | |
107 | u32 status7; | |
108 | u32 status8; | |
ada9f1ca | 109 | } __packed __aligned(4); |
744d4025 | 110 | |
ae3bb6d4 | 111 | void ar9003_hw_attach_mac_ops(struct ath_hw *hw); |
ad7b8060 VT |
112 | void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size); |
113 | void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, | |
114 | enum ath9k_rx_qtype qtype); | |
115 | ||
116 | int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, | |
117 | struct ath_rx_status *rxs, | |
118 | void *buf_addr); | |
744d4025 VT |
119 | void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah); |
120 | void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, | |
121 | u32 ts_paddr_start, | |
016c2177 | 122 | u16 size); |
ceb26445 | 123 | #endif |