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ath9k: Set SWCOM value for CUS198
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
ee40fa06 17#include <linux/export.h>
8525f280 18#include "hw.h"
da6f1d7f 19#include "ar9003_phy.h"
8525f280 20
e36b27af
LR		 21static const int firstep_table[] =
22/* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25static const int cycpwrThr1_table[] =
26/* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29/*
30 * register values to turn OFDM weak signal detection OFF
31 */
32static const int m1ThreshLow_off = 127;
33static const int m2ThreshLow_off = 127;
34static const int m1Thresh_off = 127;
35static const int m2Thresh_off = 127;
36static const int m2CountThr_off = 31;
37static const int m2CountThrLow_off = 63;
38static const int m1ThreshLowExt_off = 127;
39static const int m2ThreshLowExt_off = 127;
40static const int m1ThreshExt_off = 127;
41static const int m2ThreshExt_off = 127;
42
8525f280
LR		 43/**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
e4922f2b 49 * for AR9300 family of chipsets.
8525f280
LR		 50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69{
f7abf0c1 70 u16 bMode, fracMode = 0, aModeRefSel = 0;
1a26cda8 71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
f7abf0c1
FF		 72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93 79 if (AR_SREV_9330(ah)) {
5acb4b93
GJ		 80 if (ah->is_clk_25mhz)
81 div = 75;
82 else
83 div = 120;
84
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
a4a2954f 88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60 89 /*
1a26cda8
SM		 90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
3dfd7f60
VT		 92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
94 */
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
1a26cda8 98 } else if (AR_SREV_9340(ah)) {
17869f4f 99 if (ah->is_clk_25mhz) {
17869f4f
VT		 100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
1a26cda8 103 } else {
17869f4f 104 channelSel = CHANSEL_2G(freq) >> 1;
1a26cda8
SM		 105 }
106 } else if (AR_SREV_9550(ah)) {
107 if (ah->is_clk_25mhz)
108 div = 75;
109 else
110 div = 120;
111
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
115 } else {
85dd0921 116 channelSel = CHANSEL_2G(freq);
1a26cda8 117 }
f7abf0c1
FF		 118 /* Set to 2G mode */
119 bMode = 1;
120 } else {
db4a3de9
GJ		 121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
122 ah->is_clk_25mhz) {
530275e5
FF		 123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
17869f4f
VT		 125 channelSel = (channelSel << 17) | chan_frac;
126 } else {
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
129 channelSel >>= 1;
130 }
f7abf0c1
FF		 131 /* Set to 5G mode */
132 bMode = 0;
133 }
134
135 /* Enable fractional mode for all channels */
136 fracMode = 1;
137 aModeRefSel = 0;
138 loadSynthChannel = 0;
139
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
142
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
146
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
151
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
157
158 ah->curchan = chan;
f7abf0c1 159
8525f280
LR		 160 return 0;
161}
162
163/**
e36b27af 164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 165 * @ah: atheros hardware structure
166 * @chan:
167 *
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
170 *
171 * Spur mitigation for MRC CCK
172 */
1547da37
LR		 173static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
8525f280 175{
07b2fa5a 176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 177 int cur_bb_spur, negative = 0, cck_spur_freq;
178 int i;
d9a2545a 179 int range, max_spur_cnts, synth_freq;
4b5237cc 180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
ca375554
FF		 181
182 /*
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
185 */
186
8528f12e
GJ		 187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
188 AR_SREV_9550(ah)) {
d9a2545a
VT		 189 if (spur_fbin_ptr[0] == 0) /* No spur */
190 return;
191 max_spur_cnts = 5;
192 if (IS_CHAN_HT40(chan)) {
193 range = 19;
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
197 else
198 synth_freq = chan->channel - 10;
199 } else {
200 range = 10;
201 synth_freq = chan->channel;
202 }
203 } else {
38df2f07 204 range = AR_SREV_9462(ah) ? 5 : 10;
d9a2545a
VT		 205 max_spur_cnts = 4;
206 synth_freq = chan->channel;
207 }
208
209 for (i = 0; i < max_spur_cnts; i++) {
38df2f07
RM		 210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
211 continue;
d43d04a9 212
ca375554 213 negative = 0;
8528f12e
GJ		 214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
215 AR_SREV_9550(ah))
8edb254c
GJ		 216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
217 IS_CHAN_2GHZ(chan));
d9a2545a 218 else
8edb254c 219 cur_bb_spur = spur_freq[i];
ca375554 220
8edb254c 221 cur_bb_spur -= synth_freq;
ca375554
FF		 222 if (cur_bb_spur < 0) {
223 negative = 1;
224 cur_bb_spur = -cur_bb_spur;
225 }
d9a2545a 226 if (cur_bb_spur < range) {
ca375554
FF		 227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
228
229 if (negative == 1)
230 cck_spur_freq = -cck_spur_freq;
231
232 cck_spur_freq = cck_spur_freq & 0xfffff;
233
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
240 0x2);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
243 0x1);
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
246 cck_spur_freq);
247
248 return;
249 }
250 }
251
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 258}
259
1547da37
LR		 260/* Clean all spur register fields */
261static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
262{
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
281
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
302}
303
304static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
305 int freq_offset,
306 int spur_freq_sd,
307 int spur_delta_phase,
d43d04a9
SM		 308 int spur_subchannel_sd,
309 int range,
310 int synth_freq)
1547da37
LR		 311{
312 int mask_index = 0;
313
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
d43d04a9
SM		 325
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
329
1547da37
LR		 330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
336
23dd9b2a
FF		 337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
1547da37
LR		 339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
342
343 mask_index = (freq_offset << 4) / 5;
344 if (mask_index < 0)
345 mask_index = mask_index - 1;
346
347 mask_index = mask_index & 0x7f;
348
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
369}
370
d43d04a9
SM		 371static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
372 int freq_offset)
373{
374 int mask_index = 0;
375
376 mask_index = (freq_offset << 4) / 5;
377 if (mask_index < 0)
378 mask_index = mask_index - 1;
379
380 mask_index = mask_index & 0x7f;
381
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
384 mask_index);
385
386 /* A == B */
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
389 mask_index);
390
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
393 mask_index);
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
398
399 /* A == B */
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
402}
403
1547da37
LR		 404static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
d43d04a9
SM		 406 int freq_offset,
407 int range,
408 int synth_freq)
1547da37
LR		 409{
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
413
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
419 else
420 spur_subchannel_sd = 0;
421
9d1ceac5 422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
1547da37
LR		 423
424 } else {
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
428 else
429 spur_subchannel_sd = 1;
430
9d1ceac5 431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
1547da37
LR		 432
433 }
434
435 spur_delta_phase = (freq_offset << 17) / 5;
436
437 } else {
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
441 }
442
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
445
446 ar9003_hw_spur_ofdm(ah,
447 freq_offset,
448 spur_freq_sd,
449 spur_delta_phase,
d43d04a9
SM		 450 spur_subchannel_sd,
451 range, synth_freq);
1547da37
LR		 452}
453
454/* Spur mitigation for OFDM */
455static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
457{
458 int synth_freq;
459 int range = 10;
460 int freq_offset = 0;
461 int mode;
462 u8* spurChansPtr;
463 unsigned int i;
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
465
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
468 mode = 0;
469 }
470 else {
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
472 mode = 1;
473 }
474
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
477
478 if (IS_CHAN_HT40(chan)) {
479 range = 19;
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
483 else
484 synth_freq = chan->channel + 10;
485 } else {
486 range = 10;
487 synth_freq = chan->channel;
488 }
489
490 ar9003_hw_spur_ofdm_clear(ah);
491
0f8e94d2 492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
8edb254c
GJ		 493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
1547da37 495 if (abs(freq_offset) < range) {
d43d04a9
SM		 496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
497 range, synth_freq);
498
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
501 mode);
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
505 }
506
1547da37
LR		 507 break;
508 }
509 }
510}
511
512static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
514{
d43d04a9
SM		 515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
1547da37
LR		 517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
518}
519
8525f280
LR		 520static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
521 struct ath9k_channel *chan)
522{
317d3328
FF		 523 u32 pll;
524
525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
526
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
531
14bc1104 532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 533
534 return pll;
8525f280
LR		 535}
536
537static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539{
cffb5e49
LR		 540 u32 phymode;
541 u32 enableDacFifo = 0;
542
543 enableDacFifo =
544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
545
546 /* Enable 11n HT, 20 MHz */
8ad38d22 547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
cffb5e49
LR		 548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
549
550 /* Configure baseband for dynamic 20/40 operation */
551 if (IS_CHAN_HT40(chan)) {
552 phymode |= AR_PHY_GC_DYN2040_EN;
553 /* Configure control (primary) channel at +-10MHz */
554 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
555 (chan->chanmode == CHANNEL_G_HT40PLUS))
556 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
557
558 }
559
560 /* make sure we preserve INI settings */
561 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
562 /* turn off Green Field detection for STA for now */
563 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
564
565 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
566
567 /* Configure MAC for 20/40 operation */
568 ath9k_hw_set11nmac2040(ah);
569
570 /* global transmit timeout (25 TUs default)*/
571 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
572 /* carrier sense timeout */
573 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 574}
575
576static void ar9003_hw_init_bb(struct ath_hw *ah,
577 struct ath9k_channel *chan)
578{
af914a9f
LR		 579 u32 synthDelay;
580
581 /*
582 * Wait for the frequency synth to settle (synth goes on
583 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
584 * Value is in 100ns increments.
585 */
586 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f
LR		 587
588 /* Activate the PHY (includes baseband activate + synthesizer on) */
589 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7c5adc8d 590 ath9k_hw_synth_delay(ah, chan, synthDelay);
8525f280
LR		 591}
592
4a8f1995 593void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
cffb5e49 594{
24171dd9 595 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
cffb5e49
LR		 596 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
597 AR_PHY_SWAP_ALT_CHAIN);
24171dd9
FF		 598
599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
cffb5e49 601
ea066d5a 602 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
24171dd9 603 tx = 3;
ea066d5a 604
24171dd9 605 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
cffb5e49
LR		 606}
607
608/*
609 * Override INI values with chip specific configuration.
610 */
611static void ar9003_hw_override_ini(struct ath_hw *ah)
612{
613 u32 val;
614
615 /*
616 * Set the RX_ABORT and RX_DIS and clear it only after
617 * RXE is set for MAC. This prevents frames with
618 * corrupted descriptor status.
619 */
620 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
621
622 /*
623 * For AR9280 and above, there is a new feature that allows
624 * Multicast search based on both MAC Address and Key ID. By default,
625 * this feature is enabled. But since the driver is not using this
626 * feature, we switch it off; otherwise multicast search based on
627 * MAC addr only will fail.
628 */
629 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
630 REG_WRITE(ah, AR_PCU_MISC_MODE2,
631 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
bf3f204b
FF		 632
633 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
634 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
4b03f16e
SM		 635
636 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
637 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
638 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
639
640 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
641 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
642 ah->enabled_cals |= TX_IQ_CAL;
643 else
644 ah->enabled_cals &= ~TX_IQ_CAL;
645
646 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
647 ah->enabled_cals |= TX_CL_CAL;
648 else
649 ah->enabled_cals &= ~TX_CL_CAL;
650 }
cffb5e49
LR		 651}
652
653static void ar9003_hw_prog_ini(struct ath_hw *ah,
654 struct ar5416IniArray *iniArr,
655 int column)
656{
657 unsigned int i, regWrites = 0;
658
659 /* New INI format: Array may be undefined (pre, core, post arrays) */
660 if (!iniArr->ia_array)
661 return;
662
663 /*
664 * New INI format: Pre, core, and post arrays for a given subsystem
665 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
666 * the array is non-modal and force the column to 1.
667 */
668 if (column >= iniArr->ia_columns)
669 column = 1;
670
671 for (i = 0; i < iniArr->ia_rows; i++) {
672 u32 reg = INI_RA(iniArr, i, 0);
673 u32 val = INI_RA(iniArr, i, column);
674
7e68b746 675 REG_WRITE(ah, reg, val);
b2ccc507 676
cffb5e49
LR		 677 DO_DELAY(regWrites);
678 }
679}
680
8bc45c6b
GJ		 681static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
682 struct ath9k_channel *chan)
683{
684 int ret;
685
686 switch (chan->chanmode) {
687 case CHANNEL_A:
688 case CHANNEL_A_HT20:
689 if (chan->channel <= 5350)
690 ret = 1;
691 else if ((chan->channel > 5350) && (chan->channel <= 5600))
692 ret = 3;
693 else
694 ret = 5;
695 break;
696
697 case CHANNEL_A_HT40PLUS:
698 case CHANNEL_A_HT40MINUS:
699 if (chan->channel <= 5350)
700 ret = 2;
701 else if ((chan->channel > 5350) && (chan->channel <= 5600))
702 ret = 4;
703 else
704 ret = 6;
705 break;
706
707 case CHANNEL_G:
708 case CHANNEL_G_HT20:
709 case CHANNEL_B:
710 ret = 8;
711 break;
712
713 case CHANNEL_G_HT40PLUS:
714 case CHANNEL_G_HT40MINUS:
715 ret = 7;
716 break;
717
718 default:
719 ret = -EINVAL;
720 }
721
722 return ret;
723}
724
8525f280
LR		 725static int ar9003_hw_process_ini(struct ath_hw *ah,
726 struct ath9k_channel *chan)
727{
cffb5e49 728 unsigned int regWrites = 0, i;
0ff2b5c0 729 u32 modesIndex;
cffb5e49
LR		 730
731 switch (chan->chanmode) {
732 case CHANNEL_A:
733 case CHANNEL_A_HT20:
734 modesIndex = 1;
cffb5e49
LR		 735 break;
736 case CHANNEL_A_HT40PLUS:
737 case CHANNEL_A_HT40MINUS:
738 modesIndex = 2;
cffb5e49
LR		 739 break;
740 case CHANNEL_G:
741 case CHANNEL_G_HT20:
742 case CHANNEL_B:
743 modesIndex = 4;
cffb5e49
LR		 744 break;
745 case CHANNEL_G_HT40PLUS:
746 case CHANNEL_G_HT40MINUS:
747 modesIndex = 3;
cffb5e49
LR		 748 break;
749
750 default:
751 return -EINVAL;
752 }
753
51dbd0a8
SM		 754 /*
755 * SOC, MAC, BB, RADIO initvals.
756 */
cffb5e49
LR		 757 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
758 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
759 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
760 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
761 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
2b5e54e2 762 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
2577c6e8
SB		 763 ar9003_hw_prog_ini(ah,
764 &ah->ini_radio_post_sys2ant,
765 modesIndex);
cffb5e49
LR		 766 }
767
51dbd0a8
SM		 768 /*
769 * RXGAIN initvals.
770 */
cffb5e49 771 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
51dbd0a8 772
2b5e54e2 773 if (AR_SREV_9462_20_OR_LATER(ah)) {
c177fabe
SM		 774 /*
775 * CUS217 mix LNA mode.
776 */
777 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
778 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
779 1, regWrites);
780 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
781 modesIndex, regWrites);
782 }
783
51dbd0a8
SM		 784 /*
785 * 5G-XLNA
786 */
787 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
788 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
789 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
790 modesIndex, regWrites);
791 }
792 }
793
8bc45c6b
GJ		 794 if (AR_SREV_9550(ah))
795 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
796 regWrites);
797
51dbd0a8
SM		 798 /*
799 * TXGAIN initvals.
800 */
8bc45c6b
GJ		 801 if (AR_SREV_9550(ah)) {
802 int modes_txgain_index;
803
804 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
805 if (modes_txgain_index < 0)
806 return -EINVAL;
807
808 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
809 regWrites);
810 } else {
811 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
812 }
cffb5e49
LR		 813
814 /*
815 * For 5GHz channels requiring Fast Clock, apply
816 * different modal values.
817 */
6b42e8d0 818 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 819 REG_WRITE_ARRAY(&ah->iniModesFastClock,
cffb5e49
LR		 820 modesIndex, regWrites);
821
51dbd0a8
SM		 822 /*
823 * Clock frequency initvals.
824 */
c7d36f9f 825 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
d89baac8 826
51dbd0a8
SM		 827 /*
828 * JAPAN regulatory.
829 */
9951c4d0 830 if (chan->channel == 2484)
57527f8d 831 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
9951c4d0 832
5f0c04ea 833 ah->modes_index = modesIndex;
cffb5e49
LR		 834 ar9003_hw_override_ini(ah);
835 ar9003_hw_set_channel_regs(ah, chan);
836 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
64ea57d0 837 ath9k_hw_apply_txpower(ah, chan, false);
cffb5e49
LR		 838
839 return 0;
8525f280
LR		 840}
841
842static void ar9003_hw_set_rfmode(struct ath_hw *ah,
843 struct ath9k_channel *chan)
844{
af914a9f
LR		 845 u32 rfMode = 0;
846
847 if (chan == NULL)
848 return;
849
850 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
851 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
852
6b42e8d0 853 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f 854 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
08685ce3
FF		 855 if (IS_CHAN_QUARTER_RATE(chan))
856 rfMode |= AR_PHY_MODE_QUARTER;
857 if (IS_CHAN_HALF_RATE(chan))
858 rfMode |= AR_PHY_MODE_HALF;
af914a9f 859
3e61d3f9
FF		 860 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
861 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
862 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
863
af914a9f 864 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 865}
866
867static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
868{
af914a9f 869 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 870}
871
872static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
873 struct ath9k_channel *chan)
874{
af914a9f
LR		 875 u32 coef_scaled, ds_coef_exp, ds_coef_man;
876 u32 clockMhzScaled = 0x64000000;
877 struct chan_centers centers;
878
879 /*
880 * half and quarter rate can divide the scaled clock by 2 or 4
881 * scale for selected channel bandwidth
882 */
883 if (IS_CHAN_HALF_RATE(chan))
884 clockMhzScaled = clockMhzScaled >> 1;
885 else if (IS_CHAN_QUARTER_RATE(chan))
886 clockMhzScaled = clockMhzScaled >> 2;
887
888 /*
889 * ALGO -> coef = 1e8/fcarrier*fclock/40;
890 * scaled coef to provide precision for this floating calculation
891 */
892 ath9k_hw_get_channel_centers(ah, chan, &centers);
893 coef_scaled = clockMhzScaled / centers.synth_center;
894
895 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
896 &ds_coef_exp);
897
898 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
899 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
900 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
901 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
902
903 /*
904 * For Short GI,
905 * scaled coeff is 9/10 that of normal coeff
906 */
907 coef_scaled = (9 * coef_scaled) / 10;
908
909 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
910 &ds_coef_exp);
911
912 /* for short gi */
913 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
914 AR_PHY_SGI_DSC_MAN, ds_coef_man);
915 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
916 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 917}
918
919static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
920{
af914a9f
LR		 921 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
922 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
923 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 924}
925
af914a9f
LR		 926/*
927 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
928 * Read the phy active delay register. Value is in 100ns increments.
929 */
8525f280
LR		 930static void ar9003_hw_rfbus_done(struct ath_hw *ah)
931{
af914a9f 932 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f 933
7c5adc8d 934 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
af914a9f
LR		 935
936 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 937}
938
c16fcb49
FF		 939static bool ar9003_hw_ani_control(struct ath_hw *ah,
940 enum ath9k_ani_cmd cmd, int param)
941{
af914a9f 942 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 943 struct ath9k_channel *chan = ah->curchan;
c24bd362 944 struct ar5416AniState *aniState = &ah->ani;
ff23e084
SM		 945 int m1ThreshLow, m2ThreshLow;
946 int m1Thresh, m2Thresh;
947 int m2CountThr, m2CountThrLow;
948 int m1ThreshLowExt, m2ThreshLowExt;
949 int m1ThreshExt, m2ThreshExt;
e36b27af 950 s32 value, value2;
af914a9f
LR		 951
952 switch (cmd & ah->ani_function) {
af914a9f 953 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 954 /*
955 * on == 1 means ofdm weak signal detection is ON
956 * on == 1 is the default, for less noise immunity
957 *
958 * on == 0 means ofdm weak signal detection is OFF
959 * on == 0 means more noise imm
960 */
af914a9f 961 u32 on = param ? 1 : 0;
af914a9f 962
ff23e084
SM		 963 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
964 goto skip_ws_det;
965
966 m1ThreshLow = on ?
967 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
968 m2ThreshLow = on ?
969 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
970 m1Thresh = on ?
971 aniState->iniDef.m1Thresh : m1Thresh_off;
972 m2Thresh = on ?
973 aniState->iniDef.m2Thresh : m2Thresh_off;
974 m2CountThr = on ?
975 aniState->iniDef.m2CountThr : m2CountThr_off;
976 m2CountThrLow = on ?
977 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
978 m1ThreshLowExt = on ?
979 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
980 m2ThreshLowExt = on ?
981 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
982 m1ThreshExt = on ?
983 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
984 m2ThreshExt = on ?
985 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
986
987 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
988 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
989 m1ThreshLow);
990 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
991 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
992 m2ThreshLow);
993 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
994 AR_PHY_SFCORR_M1_THRESH,
995 m1Thresh);
996 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
997 AR_PHY_SFCORR_M2_THRESH,
998 m2Thresh);
999 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1000 AR_PHY_SFCORR_M2COUNT_THR,
1001 m2CountThr);
1002 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1003 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1004 m2CountThrLow);
1005 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1006 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1007 m1ThreshLowExt);
1008 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1009 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1010 m2ThreshLowExt);
1011 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1012 AR_PHY_SFCORR_EXT_M1_THRESH,
1013 m1ThreshExt);
1014 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1015 AR_PHY_SFCORR_EXT_M2_THRESH,
1016 m2ThreshExt);
1017skip_ws_det:
af914a9f
LR		 1018 if (on)
1019 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1020 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1021 else
1022 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1023 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1024
7067e701 1025 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 1026 ath_dbg(common, ANI,
226afe68
JP		 1027 "** ch %d: ofdm weak signal: %s=>%s\n",
1028 chan->channel,
7067e701 1029 aniState->ofdmWeakSigDetect ?
226afe68
JP		 1030 "on" : "off",
1031 on ? "on" : "off");
af914a9f
LR		 1032 if (on)
1033 ah->stats.ast_ani_ofdmon++;
1034 else
1035 ah->stats.ast_ani_ofdmoff++;
7067e701 1036 aniState->ofdmWeakSigDetect = on;
af914a9f
LR		 1037 }
1038 break;
1039 }
af914a9f 1040 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 1041 u32 level = param;
1042
e36b27af 1043 if (level >= ARRAY_SIZE(firstep_table)) {
d2182b69 1044 ath_dbg(common, ANI,
226afe68
JP		 1045 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1046 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 1047 return false;
1048 }
e36b27af
LR		 1049
1050 /*
1051 * make register setting relative to default
1052 * from INI file & cap value
1053 */
1054 value = firstep_table[level] -
465dce62 1055 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 1056 aniState->iniDef.firstep;
1057 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1058 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1059 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1060 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 1061 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1062 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 1063 value);
1064 /*
1065 * we need to set first step low register too
1066 * make register setting relative to default
1067 * from INI file & cap value
1068 */
1069 value2 = firstep_table[level] -
465dce62 1070 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 1071 aniState->iniDef.firstepLow;
1072 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1073 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1074 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1075 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1076
1077 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1078 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1079
1080 if (level != aniState->firstepLevel) {
d2182b69 1081 ath_dbg(common, ANI,
226afe68
JP		 1082 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1083 chan->channel,
1084 aniState->firstepLevel,
1085 level,
465dce62 1086 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1087 value,
1088 aniState->iniDef.firstep);
d2182b69 1089 ath_dbg(common, ANI,
226afe68
JP		 1090 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1091 chan->channel,
1092 aniState->firstepLevel,
1093 level,
465dce62 1094 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1095 value2,
1096 aniState->iniDef.firstepLow);
e36b27af
LR		 1097 if (level > aniState->firstepLevel)
1098 ah->stats.ast_ani_stepup++;
1099 else if (level < aniState->firstepLevel)
1100 ah->stats.ast_ani_stepdown++;
1101 aniState->firstepLevel = level;
1102 }
af914a9f
LR		 1103 break;
1104 }
1105 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 1106 u32 level = param;
1107
e36b27af 1108 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
d2182b69 1109 ath_dbg(common, ANI,
226afe68
JP		 1110 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1111 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 1112 return false;
1113 }
e36b27af
LR		 1114 /*
1115 * make register setting relative to default
1116 * from INI file & cap value
1117 */
1118 value = cycpwrThr1_table[level] -
465dce62 1119 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1120 aniState->iniDef.cycpwrThr1;
1121 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1122 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1123 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1124 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 1125 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1126 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 1127 value);
1128
1129 /*
1130 * set AR_PHY_EXT_CCA for extension channel
1131 * make register setting relative to default
1132 * from INI file & cap value
1133 */
1134 value2 = cycpwrThr1_table[level] -
465dce62 1135 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1136 aniState->iniDef.cycpwrThr1Ext;
1137 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1138 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1139 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1140 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1141 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1142 AR_PHY_EXT_CYCPWR_THR1, value2);
1143
1144 if (level != aniState->spurImmunityLevel) {
d2182b69 1145 ath_dbg(common, ANI,
226afe68
JP		 1146 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1147 chan->channel,
1148 aniState->spurImmunityLevel,
1149 level,
465dce62 1150 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1151 value,
1152 aniState->iniDef.cycpwrThr1);
d2182b69 1153 ath_dbg(common, ANI,
226afe68
JP		 1154 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1155 chan->channel,
1156 aniState->spurImmunityLevel,
1157 level,
465dce62 1158 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1159 value2,
1160 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1161 if (level > aniState->spurImmunityLevel)
1162 ah->stats.ast_ani_spurup++;
1163 else if (level < aniState->spurImmunityLevel)
1164 ah->stats.ast_ani_spurdown++;
1165 aniState->spurImmunityLevel = level;
1166 }
af914a9f
LR		 1167 break;
1168 }
e36b27af
LR		 1169 case ATH9K_ANI_MRC_CCK:{
1170 /*
1171 * is_on == 1 means MRC CCK ON (default, less noise imm)
1172 * is_on == 0 means MRC CCK is OFF (more noise imm)
1173 */
1174 bool is_on = param ? 1 : 0;
1175 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1176 AR_PHY_MRC_CCK_ENABLE, is_on);
1177 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1178 AR_PHY_MRC_CCK_MUX_REG, is_on);
81b67fd6 1179 if (is_on != aniState->mrcCCK) {
d2182b69 1180 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
226afe68 1181 chan->channel,
81b67fd6 1182 aniState->mrcCCK ? "on" : "off",
226afe68 1183 is_on ? "on" : "off");
e36b27af
LR		 1184 if (is_on)
1185 ah->stats.ast_ani_ccklow++;
1186 else
1187 ah->stats.ast_ani_cckhigh++;
81b67fd6 1188 aniState->mrcCCK = is_on;
e36b27af
LR		 1189 }
1190 break;
1191 }
af914a9f
LR		 1192 case ATH9K_ANI_PRESENT:
1193 break;
1194 default:
d2182b69 1195 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1196 return false;
1197 }
1198
d2182b69 1199 ath_dbg(common, ANI,
226afe68
JP		 1200 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1201 aniState->spurImmunityLevel,
7067e701 1202 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1203 aniState->firstepLevel,
81b67fd6 1204 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1205 aniState->listenTime,
1206 aniState->ofdmPhyErrCount,
1207 aniState->cckPhyErrCount);
af914a9f 1208 return true;
c16fcb49
FF		 1209}
1210
641d9921
FF		 1211static void ar9003_hw_do_getnf(struct ath_hw *ah,
1212 int16_t nfarray[NUM_NF_READINGS])
1213{
b06af7a5
VT		 1214#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1215#define AR_PHY_CH_MINCCA_PWR_S 20
1216#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1217#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1218
b06af7a5
VT		 1219 int16_t nf;
1220 int i;
866b7780 1221
b06af7a5
VT		 1222 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1223 if (ah->rxchainmask & BIT(i)) {
1224 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1225 AR_PHY_CH_MINCCA_PWR);
1226 nfarray[i] = sign_extend32(nf, 8);
641d9921 1227
b06af7a5
VT		 1228 if (IS_CHAN_HT40(ah->curchan)) {
1229 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1230
b06af7a5
VT		 1231 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1232 AR_PHY_CH_EXT_MINCCA_PWR);
1233 nfarray[ext_idx] = sign_extend32(nf, 8);
1234 }
1235 }
1236 }
641d9921
FF		 1237}
1238
f2552e28 1239static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1240{
f2552e28
FF		 1241 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1242 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
ae245cde 1243 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1244 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1245 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1246 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
ae245cde
SM		 1247
1248 if (AR_SREV_9330(ah))
1249 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1250
a4a2954f 1251 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
ae245cde
SM		 1252 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1253 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1254 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1255 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1256 }
641d9921
FF		 1257}
1258
e36b27af
LR		 1259/*
1260 * Initialize the ANI register values with default (ini) values.
1261 * This routine is called during a (full) hardware reset after
1262 * all the registers are initialised from the INI.
1263 */
1264static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1265{
1266 struct ar5416AniState *aniState;
1267 struct ath_common *common = ath9k_hw_common(ah);
1268 struct ath9k_channel *chan = ah->curchan;
1269 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1270 u32 val;
1271
c24bd362 1272 aniState = &ah->ani;
e36b27af
LR		 1273 iniDef = &aniState->iniDef;
1274
d2182b69 1275 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
226afe68
JP		 1276 ah->hw_version.macVersion,
1277 ah->hw_version.macRev,
1278 ah->opmode,
1279 chan->channel,
1280 chan->channelFlags);
e36b27af
LR		 1281
1282 val = REG_READ(ah, AR_PHY_SFCORR);
1283 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1284 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1285 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1286
1287 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1288 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1289 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1290 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1291
1292 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1293 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1294 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1295 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1296 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1297 iniDef->firstep = REG_READ_FIELD(ah,
1298 AR_PHY_FIND_SIG,
1299 AR_PHY_FIND_SIG_FIRSTEP);
1300 iniDef->firstepLow = REG_READ_FIELD(ah,
1301 AR_PHY_FIND_SIG_LOW,
1302 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1303 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1304 AR_PHY_TIMING5,
1305 AR_PHY_TIMING5_CYCPWR_THR1);
1306 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1307 AR_PHY_EXT_CCA,
1308 AR_PHY_EXT_CYCPWR_THR1);
1309
1310 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1311 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1312 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
4f4395c6 1313 aniState->ofdmWeakSigDetect = true;
81b67fd6 1314 aniState->mrcCCK = true;
e36b27af
LR		 1315}
1316
4e8c14e9
FF		 1317static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1318 struct ath_hw_radar_conf *conf)
1319{
1320 u32 radar_0 = 0, radar_1 = 0;
1321
1322 if (!conf) {
1323 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1324 return;
1325 }
1326
1327 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1328 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1329 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1330 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1331 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1332 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1333
1334 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1335 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1336 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1337 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1338 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1339
1340 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1341 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1342 if (conf->ext_channel)
1343 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1344 else
1345 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1346}
1347
c5d0855a
FF		 1348static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1349{
1350 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1351
1352 conf->fir_power = -28;
1353 conf->radar_rssi = 0;
1354 conf->pulse_height = 10;
1355 conf->pulse_rssi = 24;
1356 conf->pulse_inband = 8;
1357 conf->pulse_maxlen = 255;
1358 conf->pulse_inband_step = 12;
1359 conf->radar_inband = 8;
1360}
1361
6bcbc062 1362static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
9aa49ea3 1363 struct ath_hw_antcomb_conf *antconf)
6bcbc062
MSS		 1364{
1365 u32 regval;
1366
1367 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1368 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1369 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1370 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1371 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1372 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1373 AR_PHY_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1374
c4cf2c58
GJ		 1375 if (AR_SREV_9330_11(ah)) {
1376 antconf->lna1_lna2_delta = -9;
1377 antconf->div_group = 1;
1378 } else if (AR_SREV_9485(ah)) {
cd0ed1b5
GJ		 1379 antconf->lna1_lna2_delta = -9;
1380 antconf->div_group = 2;
5317c9c3
SM		 1381 } else if (AR_SREV_9565(ah)) {
1382 antconf->lna1_lna2_delta = -3;
1383 antconf->div_group = 3;
cd0ed1b5
GJ		 1384 } else {
1385 antconf->lna1_lna2_delta = -3;
1386 antconf->div_group = 0;
1387 }
6bcbc062
MSS		 1388}
1389
1390static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1391 struct ath_hw_antcomb_conf *antconf)
1392{
1393 u32 regval;
1394
1395 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1396 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1397 AR_PHY_ANT_DIV_ALT_LNACONF |
1398 AR_PHY_ANT_FAST_DIV_BIAS |
1399 AR_PHY_ANT_DIV_MAIN_GAINTB |
1400 AR_PHY_ANT_DIV_ALT_GAINTB);
1401 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1402 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1403 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1404 & AR_PHY_ANT_DIV_ALT_LNACONF);
1405 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1406 & AR_PHY_ANT_FAST_DIV_BIAS);
1407 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1408 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1409 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1410 & AR_PHY_ANT_DIV_ALT_GAINTB);
6bcbc062
MSS		 1411
1412 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1413}
1414
d8d7744b 1415static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
362cd03f
SM		 1416{
1417 u8 ant_div_ctl1;
1418 u32 regval;
1419
1420 if (!AR_SREV_9565(ah))
1421 return;
1422
362cd03f
SM		 1423 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1424
1425 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1426 regval &= (~AR_ANT_DIV_CTRL_ALL);
1427 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1428 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1429 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1430
1431 if (enable)
1432 regval |= AR_ANT_DIV_ENABLE;
1433
1434 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1435
1436 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1437 regval &= ~AR_FAST_DIV_ENABLE;
1438 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1439
1440 if (enable)
1441 regval |= AR_FAST_DIV_ENABLE;
1442
1443 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1444
1445 if (enable) {
1446 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1447 (1 << AR_PHY_ANT_SW_RX_PROT_S));
302a3c3a 1448 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
362cd03f
SM		 1449 REG_SET_BIT(ah, AR_PHY_RESTART,
1450 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1451 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1452 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1453 } else {
1454 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1455 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1456 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1457 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1458 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1459 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1460
1461 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1462 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1463 AR_PHY_ANT_DIV_ALT_LNACONF |
1464 AR_PHY_ANT_DIV_MAIN_GAINTB |
1465 AR_PHY_ANT_DIV_ALT_GAINTB);
c2b8359d
SM		 1466 regval |= (ATH_ANT_DIV_COMB_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1467 regval |= (ATH_ANT_DIV_COMB_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
362cd03f
SM		 1468 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1469 }
1470}
1471
5f0c04ea
RM		 1472static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1473 struct ath9k_channel *chan,
1474 u8 *ini_reloaded)
1475{
1476 unsigned int regWrites = 0;
1477 u32 modesIndex;
1478
1479 switch (chan->chanmode) {
1480 case CHANNEL_A:
1481 case CHANNEL_A_HT20:
1482 modesIndex = 1;
1483 break;
1484 case CHANNEL_A_HT40PLUS:
1485 case CHANNEL_A_HT40MINUS:
1486 modesIndex = 2;
1487 break;
1488 case CHANNEL_G:
1489 case CHANNEL_G_HT20:
1490 case CHANNEL_B:
1491 modesIndex = 4;
1492 break;
1493 case CHANNEL_G_HT40PLUS:
1494 case CHANNEL_G_HT40MINUS:
1495 modesIndex = 3;
1496 break;
1497
1498 default:
1499 return -EINVAL;
1500 }
1501
1502 if (modesIndex == ah->modes_index) {
1503 *ini_reloaded = false;
1504 goto set_rfmode;
1505 }
1506
1507 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1508 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1509 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1510 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
aaa53ee9 1511
2b5e54e2 1512 if (AR_SREV_9462_20_OR_LATER(ah))
aaa53ee9
SM		 1513 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1514 modesIndex);
5f0c04ea
RM		 1515
1516 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1517
07a9bd20
SM		 1518 if (AR_SREV_9462_20_OR_LATER(ah)) {
1519 /*
1520 * CUS217 mix LNA mode.
1521 */
1522 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1523 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1524 1, regWrites);
1525 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1526 modesIndex, regWrites);
1527 }
1528 }
1529
5f0c04ea
RM		 1530 /*
1531 * For 5GHz channels requiring Fast Clock, apply
1532 * different modal values.
1533 */
1534 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 1535 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
5f0c04ea 1536
aaa53ee9
SM		 1537 if (AR_SREV_9565(ah))
1538 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1539
07a9bd20
SM		 1540 /*
1541 * JAPAN regulatory.
1542 */
1543 if (chan->channel == 2484)
1544 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
5f0c04ea
RM		 1545
1546 ah->modes_index = modesIndex;
1547 *ini_reloaded = true;
1548
1549set_rfmode:
1550 ar9003_hw_set_rfmode(ah, chan);
1551 return 0;
1552}
1553
e93d083f
SW		 1554static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1555 struct ath_spec_scan *param)
1556{
1557 u8 count;
1558
1559 if (!param->enabled) {
1560 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1561 AR_PHY_SPECTRAL_SCAN_ENABLE);
1562 return;
1563 }
1564
1565 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1566 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1567
1568 /* on AR93xx and newer, count = 0 will make the the chip send
1569 * spectral samples endlessly. Check if this really was intended,
1570 * and fix otherwise.
1571 */
1572 count = param->count;
1573 if (param->endless)
1574 count = 0;
1575 else if (param->count == 0)
1576 count = 1;
1577
1578 if (param->short_repeat)
1579 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1580 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1581 else
1582 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1583 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1584
1585 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1586 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1587 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1588 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1589 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1590 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1591
1592 return;
1593}
1594
1595static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1596{
1597 /* Activate spectral scan */
1598 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1599 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1600}
1601
1602static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1603{
1604 struct ath_common *common = ath9k_hw_common(ah);
1605
1606 /* Poll for spectral scan complete */
1607 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1608 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1609 0, AH_WAIT_TIMEOUT)) {
1610 ath_err(common, "spectral scan wait failed\n");
1611 return;
1612 }
1613}
1614
8525f280
LR		 1615void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1616{
1617 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 1618 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 1619 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 1620 AR_PHY_CCA_0,
1621 AR_PHY_CCA_1,
1622 AR_PHY_CCA_2,
1623 AR_PHY_EXT_CCA,
1624 AR_PHY_EXT_CCA_1,
1625 AR_PHY_EXT_CCA_2,
1626 };
8525f280
LR		 1627
1628 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1629 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1630 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1631 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1632 priv_ops->init_bb = ar9003_hw_init_bb;
1633 priv_ops->process_ini = ar9003_hw_process_ini;
1634 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1635 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1636 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1637 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1638 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
c16fcb49 1639 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1640 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 1641 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 1642 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
5f0c04ea 1643 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
f2552e28 1644
6bcbc062
MSS		 1645 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1646 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
d8d7744b 1647 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
e93d083f
SW		 1648 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1649 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1650 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
6bcbc062 1651
f2552e28 1652 ar9003_hw_set_nf_limits(ah);
c5d0855a 1653 ar9003_hw_set_radar_conf(ah);
bbacee13 1654 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 1655}
aea702b7
LR		 1656
1657void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1658{
1659 struct ath_common *common = ath9k_hw_common(ah);
1660 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1661 u32 val, idle_count;
1662
1663 if (!idle_tmo_ms) {
1664 /* disable IRQ, disable chip-reset for BB panic */
1665 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1666 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1667 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1668 AR_PHY_WATCHDOG_IRQ_ENABLE));
1669
1670 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1671 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1672 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1673 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1674 AR_PHY_WATCHDOG_IDLE_ENABLE));
1675
d2182b69 1676 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 1677 return;
1678 }
1679
1680 /* enable IRQ, disable chip-reset for BB watchdog */
1681 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1682 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1683 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1684 ~AR_PHY_WATCHDOG_RST_ENABLE);
1685
1686 /* bound limit to 10 secs */
1687 if (idle_tmo_ms > 10000)
1688 idle_tmo_ms = 10000;
1689
1690 /*
1691 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1692 *
1693 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1694 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1695 *
1696 * Given we use fast clock now in 5 GHz, these time units should
1697 * be common for both 2 GHz and 5 GHz.
1698 */
1699 idle_count = (100 * idle_tmo_ms) / 74;
1700 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1701 idle_count = (100 * idle_tmo_ms) / 37;
1702
1703 /*
1704 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1705 * set idle time-out.
1706 */
1707 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1708 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1709 AR_PHY_WATCHDOG_IDLE_MASK |
1710 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1711
d2182b69 1712 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
226afe68 1713 idle_tmo_ms);
aea702b7
LR		 1714}
1715
1716void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1717{
1718 /*
1719 * we want to avoid printing in ISR context so we save the
1720 * watchdog status to be printed later in bottom half context.
1721 */
1722 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1723
1724 /*
1725 * the watchdog timer should reset on status read but to be sure
1726 * sure we write 0 to the watchdog status bit.
1727 */
1728 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1729 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1730}
1731
1732void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1733{
1734 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 1735 u32 status;
aea702b7
LR		 1736
1737 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1738 return;
1739
1740 status = ah->bb_watchdog_last_status;
d2182b69 1741 ath_dbg(common, RESET,
226afe68 1742 "\n==== BB update: BB status=0x%08x ====\n", status);
d2182b69 1743 ath_dbg(common, RESET,
226afe68
JP		 1744 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1745 MS(status, AR_PHY_WATCHDOG_INFO),
1746 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1747 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1748 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1749 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1750 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1751 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1752 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1753 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1754
d2182b69 1755 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
226afe68
JP		 1756 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1757 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
d2182b69 1758 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
226afe68 1759 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 1760
b5bfc568
FF		 1761#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1762 if (common->cc_survey.cycles)
d2182b69 1763 ath_dbg(common, RESET,
226afe68
JP		 1764 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1765 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 1766
d2182b69 1767 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
aea702b7
LR		 1768}
1769EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 1770
1771void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1772{
1773 u32 val;
1774
1775 /* While receiving unsupported rate frame rx state machine
1776 * gets into a state 0xb and if phy_restart happens in that
1777 * state, BB would go hang. If RXSM is in 0xb state after
1778 * first bb panic, ensure to disable the phy_restart.
1779 */
1780 if (!((MS(ah->bb_watchdog_last_status,
1781 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1782 ah->bb_hang_rx_ofdm))
1783 return;
1784
1785 ah->bb_hang_rx_ofdm = true;
1786 val = REG_READ(ah, AR_PHY_RESTART);
1787 val &= ~AR_PHY_RESTART_ENA;
1788
1789 REG_WRITE(ah, AR_PHY_RESTART, val);
1790}
1791EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Linux kernel - Deliverables
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