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ath9k: qinfo never be NULL in setuptxqueue
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
da6f1d7f 18#include "ar9003_phy.h"
8525f280 19
e36b27af
LR		 20static const int firstep_table[] =
21/* level: 0 1 2 3 4 5 6 7 8 */
22 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
23
24static const int cycpwrThr1_table[] =
25/* level: 0 1 2 3 4 5 6 7 8 */
26 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
27
28/*
29 * register values to turn OFDM weak signal detection OFF
30 */
31static const int m1ThreshLow_off = 127;
32static const int m2ThreshLow_off = 127;
33static const int m1Thresh_off = 127;
34static const int m2Thresh_off = 127;
35static const int m2CountThr_off = 31;
36static const int m2CountThrLow_off = 63;
37static const int m1ThreshLowExt_off = 127;
38static const int m2ThreshLowExt_off = 127;
39static const int m1ThreshExt_off = 127;
40static const int m2ThreshExt_off = 127;
41
8525f280
LR		 42/**
43 * ar9003_hw_set_channel - set channel on single-chip device
44 * @ah: atheros hardware structure
45 * @chan:
46 *
47 * This is the function to change channel on single-chip devices, that is
48 * all devices after ar9280.
49 *
50 * This function takes the channel value in MHz and sets
51 * hardware channel value. Assumes writes have been enabled to analog bus.
52 *
53 * Actual Expression,
54 *
55 * For 2GHz channel,
56 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
57 * (freq_ref = 40MHz)
58 *
59 * For 5GHz channel,
60 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
61 * (freq_ref = 40MHz/(24>>amodeRefSel))
62 *
63 * For 5GHz channels which are 5MHz spaced,
64 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65 * (freq_ref = 40MHz)
66 */
67static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68{
f7abf0c1
FF		 69 u16 bMode, fracMode = 0, aModeRefSel = 0;
70 u32 freq, channelSel = 0, reg32 = 0;
71 struct chan_centers centers;
72 int loadSynthChannel;
73
74 ath9k_hw_get_channel_centers(ah, chan, &centers);
75 freq = centers.synth_center;
76
77 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93
GJ		 78 if (AR_SREV_9330(ah)) {
79 u32 chan_frac;
80 u32 div;
81
82 if (ah->is_clk_25mhz)
83 div = 75;
84 else
85 div = 120;
86
87 channelSel = (freq * 4) / div;
88 chan_frac = (((freq * 4) % div) * 0x20000) / div;
89 channelSel = (channelSel << 17) | chan_frac;
90 } else if (AR_SREV_9485(ah)) {
3dfd7f60
VT		 91 u32 chan_frac;
92
93 /*
94 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
95 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
96 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
97 */
98 channelSel = (freq * 4) / 120;
99 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
100 channelSel = (channelSel << 17) | chan_frac;
17869f4f
VT		 101 } else if (AR_SREV_9340(ah)) {
102 if (ah->is_clk_25mhz) {
103 u32 chan_frac;
104
105 channelSel = (freq * 2) / 75;
106 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
107 channelSel = (channelSel << 17) | chan_frac;
108 } else
109 channelSel = CHANSEL_2G(freq) >> 1;
3dfd7f60 110 } else
85dd0921 111 channelSel = CHANSEL_2G(freq);
f7abf0c1
FF		 112 /* Set to 2G mode */
113 bMode = 1;
114 } else {
17869f4f
VT		 115 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
116 u32 chan_frac;
117
118 channelSel = (freq * 2) / 75;
dbb204e3 119 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
17869f4f
VT		 120 channelSel = (channelSel << 17) | chan_frac;
121 } else {
122 channelSel = CHANSEL_5G(freq);
123 /* Doubler is ON, so, divide channelSel by 2. */
124 channelSel >>= 1;
125 }
f7abf0c1
FF		 126 /* Set to 5G mode */
127 bMode = 0;
128 }
129
130 /* Enable fractional mode for all channels */
131 fracMode = 1;
132 aModeRefSel = 0;
133 loadSynthChannel = 0;
134
135 reg32 = (bMode << 29);
136 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
137
138 /* Enable Long shift Select for Synthesizer */
139 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
140 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
141
142 /* Program Synth. setting */
143 reg32 = (channelSel << 2) | (fracMode << 30) |
144 (aModeRefSel << 28) | (loadSynthChannel << 31);
145 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
146
147 /* Toggle Load Synth channel bit */
148 loadSynthChannel = 1;
149 reg32 = (channelSel << 2) | (fracMode << 30) |
150 (aModeRefSel << 28) | (loadSynthChannel << 31);
151 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
152
153 ah->curchan = chan;
154 ah->curchan_rad_index = -1;
155
8525f280
LR		 156 return 0;
157}
158
159/**
e36b27af 160 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 161 * @ah: atheros hardware structure
162 * @chan:
163 *
164 * For single-chip solutions. Converts to baseband spur frequency given the
165 * input channel frequency and compute register settings below.
166 *
167 * Spur mitigation for MRC CCK
168 */
1547da37
LR		 169static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
170 struct ath9k_channel *chan)
8525f280 171{
07b2fa5a 172 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 173 int cur_bb_spur, negative = 0, cck_spur_freq;
174 int i;
d9a2545a
VT		 175 int range, max_spur_cnts, synth_freq;
176 u8 *spur_fbin_ptr = NULL;
ca375554
FF		 177
178 /*
179 * Need to verify range +/- 10 MHz in control channel, otherwise spur
180 * is out-of-band and can be ignored.
181 */
182
c1acfbe8 183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
d9a2545a
VT		 184 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
185 IS_CHAN_2GHZ(chan));
186 if (spur_fbin_ptr[0] == 0) /* No spur */
187 return;
188 max_spur_cnts = 5;
189 if (IS_CHAN_HT40(chan)) {
190 range = 19;
191 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
192 AR_PHY_GC_DYN2040_PRI_CH) == 0)
193 synth_freq = chan->channel + 10;
194 else
195 synth_freq = chan->channel - 10;
196 } else {
197 range = 10;
198 synth_freq = chan->channel;
199 }
200 } else {
201 range = 10;
202 max_spur_cnts = 4;
203 synth_freq = chan->channel;
204 }
205
206 for (i = 0; i < max_spur_cnts; i++) {
ca375554 207 negative = 0;
c1acfbe8 208 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
d9a2545a
VT		 209 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
210 IS_CHAN_2GHZ(chan)) - synth_freq;
211 else
212 cur_bb_spur = spur_freq[i] - synth_freq;
ca375554
FF		 213
214 if (cur_bb_spur < 0) {
215 negative = 1;
216 cur_bb_spur = -cur_bb_spur;
217 }
d9a2545a 218 if (cur_bb_spur < range) {
ca375554
FF		 219 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
220
221 if (negative == 1)
222 cck_spur_freq = -cck_spur_freq;
223
224 cck_spur_freq = cck_spur_freq & 0xfffff;
225
226 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
227 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
228 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
229 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
230 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
231 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
232 0x2);
233 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
234 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
235 0x1);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
238 cck_spur_freq);
239
240 return;
241 }
242 }
243
244 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
245 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
246 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
247 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
248 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
249 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 250}
251
1547da37
LR		 252/* Clean all spur register fields */
253static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
254{
255 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
256 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
257 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
258 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
259 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
260 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
261 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
262 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
263 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
264 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
268 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
270 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
271 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
272 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
273
274 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
275 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
276 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
277 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
278 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
279 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
280 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
281 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
283 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
284 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
285 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
286 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
287 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
288 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
289 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
293 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
294}
295
296static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
297 int freq_offset,
298 int spur_freq_sd,
299 int spur_delta_phase,
300 int spur_subchannel_sd)
301{
302 int mask_index = 0;
303
304 /* OFDM Spur mitigation */
305 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
306 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
307 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
308 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
309 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
310 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
311 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
312 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
313 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
314 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
315 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
316 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
318 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
319 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
320 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
321 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
322 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
323
324 if (REG_READ_FIELD(ah, AR_PHY_MODE,
325 AR_PHY_MODE_DYNAMIC) == 0x1)
326 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
327 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
328
329 mask_index = (freq_offset << 4) / 5;
330 if (mask_index < 0)
331 mask_index = mask_index - 1;
332
333 mask_index = mask_index & 0x7f;
334
335 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
336 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
337 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
338 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
339 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
340 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
341 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
342 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
343 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
344 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
345 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
346 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
347 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
348 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
349 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
350 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
351 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
352 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
353 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
354 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
355}
356
357static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
358 struct ath9k_channel *chan,
359 int freq_offset)
360{
361 int spur_freq_sd = 0;
362 int spur_subchannel_sd = 0;
363 int spur_delta_phase = 0;
364
365 if (IS_CHAN_HT40(chan)) {
366 if (freq_offset < 0) {
367 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
368 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
369 spur_subchannel_sd = 1;
370 else
371 spur_subchannel_sd = 0;
372
a844adfd 373 spur_freq_sd = (freq_offset << 9) / 11;
1547da37
LR		 374
375 } else {
376 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
377 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
378 spur_subchannel_sd = 0;
379 else
380 spur_subchannel_sd = 1;
381
a844adfd 382 spur_freq_sd = (freq_offset << 9) / 11;
1547da37
LR		 383
384 }
385
386 spur_delta_phase = (freq_offset << 17) / 5;
387
388 } else {
389 spur_subchannel_sd = 0;
390 spur_freq_sd = (freq_offset << 9) /11;
391 spur_delta_phase = (freq_offset << 18) / 5;
392 }
393
394 spur_freq_sd = spur_freq_sd & 0x3ff;
395 spur_delta_phase = spur_delta_phase & 0xfffff;
396
397 ar9003_hw_spur_ofdm(ah,
398 freq_offset,
399 spur_freq_sd,
400 spur_delta_phase,
401 spur_subchannel_sd);
402}
403
404/* Spur mitigation for OFDM */
405static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
406 struct ath9k_channel *chan)
407{
408 int synth_freq;
409 int range = 10;
410 int freq_offset = 0;
411 int mode;
412 u8* spurChansPtr;
413 unsigned int i;
414 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
415
416 if (IS_CHAN_5GHZ(chan)) {
417 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
418 mode = 0;
419 }
420 else {
421 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
422 mode = 1;
423 }
424
425 if (spurChansPtr[0] == 0)
426 return; /* No spur in the mode */
427
428 if (IS_CHAN_HT40(chan)) {
429 range = 19;
430 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
431 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
432 synth_freq = chan->channel - 10;
433 else
434 synth_freq = chan->channel + 10;
435 } else {
436 range = 10;
437 synth_freq = chan->channel;
438 }
439
440 ar9003_hw_spur_ofdm_clear(ah);
441
0f8e94d2 442 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
1547da37
LR		 443 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
444 if (abs(freq_offset) < range) {
445 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
446 break;
447 }
448 }
449}
450
451static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
452 struct ath9k_channel *chan)
453{
454 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
455 ar9003_hw_spur_mitigate_ofdm(ah, chan);
456}
457
8525f280
LR		 458static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
459 struct ath9k_channel *chan)
460{
317d3328
FF		 461 u32 pll;
462
463 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
464
465 if (chan && IS_CHAN_HALF_RATE(chan))
466 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
467 else if (chan && IS_CHAN_QUARTER_RATE(chan))
468 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
469
14bc1104 470 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 471
472 return pll;
8525f280
LR		 473}
474
475static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
476 struct ath9k_channel *chan)
477{
cffb5e49
LR		 478 u32 phymode;
479 u32 enableDacFifo = 0;
480
481 enableDacFifo =
482 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
483
484 /* Enable 11n HT, 20 MHz */
485 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
486 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
487
488 /* Configure baseband for dynamic 20/40 operation */
489 if (IS_CHAN_HT40(chan)) {
490 phymode |= AR_PHY_GC_DYN2040_EN;
491 /* Configure control (primary) channel at +-10MHz */
492 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
493 (chan->chanmode == CHANNEL_G_HT40PLUS))
494 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
495
496 }
497
498 /* make sure we preserve INI settings */
499 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
500 /* turn off Green Field detection for STA for now */
501 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
502
503 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
504
505 /* Configure MAC for 20/40 operation */
506 ath9k_hw_set11nmac2040(ah);
507
508 /* global transmit timeout (25 TUs default)*/
509 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
510 /* carrier sense timeout */
511 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 512}
513
514static void ar9003_hw_init_bb(struct ath_hw *ah,
515 struct ath9k_channel *chan)
516{
af914a9f
LR		 517 u32 synthDelay;
518
519 /*
520 * Wait for the frequency synth to settle (synth goes on
521 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
522 * Value is in 100ns increments.
523 */
524 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
525 if (IS_CHAN_B(chan))
526 synthDelay = (4 * synthDelay) / 22;
527 else
528 synthDelay /= 10;
529
530 /* Activate the PHY (includes baseband activate + synthesizer on) */
531 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
532
533 /*
534 * There is an issue if the AP starts the calibration before
535 * the base band timeout completes. This could result in the
536 * rx_clear false triggering. As a workaround we add delay an
537 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
538 * does not happen.
539 */
540 udelay(synthDelay + BASE_ACTIVATE_DELAY);
8525f280
LR		 541}
542
cffb5e49
LR		 543void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
544{
545 switch (rx) {
546 case 0x5:
547 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
548 AR_PHY_SWAP_ALT_CHAIN);
549 case 0x3:
550 case 0x1:
551 case 0x2:
552 case 0x7:
553 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
554 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
555 break;
556 default:
557 break;
558 }
559
ea066d5a
MSS		 560 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
561 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
562 else
563 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
564
cffb5e49
LR		 565 if (tx == 0x5) {
566 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
567 AR_PHY_SWAP_ALT_CHAIN);
568 }
569}
570
571/*
572 * Override INI values with chip specific configuration.
573 */
574static void ar9003_hw_override_ini(struct ath_hw *ah)
575{
576 u32 val;
577
578 /*
579 * Set the RX_ABORT and RX_DIS and clear it only after
580 * RXE is set for MAC. This prevents frames with
581 * corrupted descriptor status.
582 */
583 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
584
585 /*
586 * For AR9280 and above, there is a new feature that allows
587 * Multicast search based on both MAC Address and Key ID. By default,
588 * this feature is enabled. But since the driver is not using this
589 * feature, we switch it off; otherwise multicast search based on
590 * MAC addr only will fail.
591 */
592 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
593 REG_WRITE(ah, AR_PCU_MISC_MODE2,
594 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
595}
596
597static void ar9003_hw_prog_ini(struct ath_hw *ah,
598 struct ar5416IniArray *iniArr,
599 int column)
600{
601 unsigned int i, regWrites = 0;
602
603 /* New INI format: Array may be undefined (pre, core, post arrays) */
604 if (!iniArr->ia_array)
605 return;
606
607 /*
608 * New INI format: Pre, core, and post arrays for a given subsystem
609 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
610 * the array is non-modal and force the column to 1.
611 */
612 if (column >= iniArr->ia_columns)
613 column = 1;
614
615 for (i = 0; i < iniArr->ia_rows; i++) {
616 u32 reg = INI_RA(iniArr, i, 0);
617 u32 val = INI_RA(iniArr, i, column);
618
7e68b746 619 REG_WRITE(ah, reg, val);
b2ccc507 620
cffb5e49
LR		 621 DO_DELAY(regWrites);
622 }
623}
624
8525f280
LR		 625static int ar9003_hw_process_ini(struct ath_hw *ah,
626 struct ath9k_channel *chan)
627{
cffb5e49
LR		 628 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
629 unsigned int regWrites = 0, i;
630 struct ieee80211_channel *channel = chan->chan;
0ff2b5c0 631 u32 modesIndex;
cffb5e49
LR		 632
633 switch (chan->chanmode) {
634 case CHANNEL_A:
635 case CHANNEL_A_HT20:
636 modesIndex = 1;
cffb5e49
LR		 637 break;
638 case CHANNEL_A_HT40PLUS:
639 case CHANNEL_A_HT40MINUS:
640 modesIndex = 2;
cffb5e49
LR		 641 break;
642 case CHANNEL_G:
643 case CHANNEL_G_HT20:
644 case CHANNEL_B:
645 modesIndex = 4;
cffb5e49
LR		 646 break;
647 case CHANNEL_G_HT40PLUS:
648 case CHANNEL_G_HT40MINUS:
649 modesIndex = 3;
cffb5e49
LR		 650 break;
651
652 default:
653 return -EINVAL;
654 }
655
656 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
657 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
658 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
659 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
660 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
661 }
662
663 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
664 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
665
666 /*
667 * For 5GHz channels requiring Fast Clock, apply
668 * different modal values.
669 */
6b42e8d0 670 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
cffb5e49
LR		 671 REG_WRITE_ARRAY(&ah->iniModesAdditional,
672 modesIndex, regWrites);
673
172805ad
GJ		 674 if (AR_SREV_9300(ah))
675 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
676
d89baac8
VT		 677 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
678 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
679
cffb5e49
LR		 680 ar9003_hw_override_ini(ah);
681 ar9003_hw_set_channel_regs(ah, chan);
682 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
683
684 /* Set TX power */
685 ah->eep_ops->set_txpower(ah, chan,
686 ath9k_regd_get_ctl(regulatory, chan),
687 channel->max_antenna_gain * 2,
688 channel->max_power * 2,
689 min((u32) MAX_RATE_POWER,
de40f316 690 (u32) regulatory->power_limit), false);
cffb5e49
LR		 691
692 return 0;
8525f280
LR		 693}
694
695static void ar9003_hw_set_rfmode(struct ath_hw *ah,
696 struct ath9k_channel *chan)
697{
af914a9f
LR		 698 u32 rfMode = 0;
699
700 if (chan == NULL)
701 return;
702
703 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
704 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
705
6b42e8d0 706 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f
LR		 707 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
708
709 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 710}
711
712static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
713{
af914a9f 714 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 715}
716
717static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
718 struct ath9k_channel *chan)
719{
af914a9f
LR		 720 u32 coef_scaled, ds_coef_exp, ds_coef_man;
721 u32 clockMhzScaled = 0x64000000;
722 struct chan_centers centers;
723
724 /*
725 * half and quarter rate can divide the scaled clock by 2 or 4
726 * scale for selected channel bandwidth
727 */
728 if (IS_CHAN_HALF_RATE(chan))
729 clockMhzScaled = clockMhzScaled >> 1;
730 else if (IS_CHAN_QUARTER_RATE(chan))
731 clockMhzScaled = clockMhzScaled >> 2;
732
733 /*
734 * ALGO -> coef = 1e8/fcarrier*fclock/40;
735 * scaled coef to provide precision for this floating calculation
736 */
737 ath9k_hw_get_channel_centers(ah, chan, &centers);
738 coef_scaled = clockMhzScaled / centers.synth_center;
739
740 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
741 &ds_coef_exp);
742
743 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
744 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
745 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
746 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
747
748 /*
749 * For Short GI,
750 * scaled coeff is 9/10 that of normal coeff
751 */
752 coef_scaled = (9 * coef_scaled) / 10;
753
754 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
755 &ds_coef_exp);
756
757 /* for short gi */
758 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
759 AR_PHY_SGI_DSC_MAN, ds_coef_man);
760 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
761 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 762}
763
764static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
765{
af914a9f
LR		 766 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
767 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
768 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 769}
770
af914a9f
LR		 771/*
772 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
773 * Read the phy active delay register. Value is in 100ns increments.
774 */
8525f280
LR		 775static void ar9003_hw_rfbus_done(struct ath_hw *ah)
776{
af914a9f
LR		 777 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
778 if (IS_CHAN_B(ah->curchan))
779 synthDelay = (4 * synthDelay) / 22;
780 else
781 synthDelay /= 10;
782
783 udelay(synthDelay + BASE_ACTIVATE_DELAY);
784
785 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 786}
787
8525f280
LR		 788static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
789{
af914a9f
LR		 790 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
791 if (value)
792 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
793 else
794 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
795 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
8525f280
LR		 796}
797
c16fcb49
FF		 798static bool ar9003_hw_ani_control(struct ath_hw *ah,
799 enum ath9k_ani_cmd cmd, int param)
800{
af914a9f 801 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 802 struct ath9k_channel *chan = ah->curchan;
093115b7 803 struct ar5416AniState *aniState = &chan->ani;
e36b27af 804 s32 value, value2;
af914a9f
LR		 805
806 switch (cmd & ah->ani_function) {
af914a9f 807 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 808 /*
809 * on == 1 means ofdm weak signal detection is ON
810 * on == 1 is the default, for less noise immunity
811 *
812 * on == 0 means ofdm weak signal detection is OFF
813 * on == 0 means more noise imm
814 */
af914a9f 815 u32 on = param ? 1 : 0;
e36b27af
LR		 816 /*
817 * make register setting for default
818 * (weak sig detect ON) come from INI file
819 */
820 int m1ThreshLow = on ?
821 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
822 int m2ThreshLow = on ?
823 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
824 int m1Thresh = on ?
825 aniState->iniDef.m1Thresh : m1Thresh_off;
826 int m2Thresh = on ?
827 aniState->iniDef.m2Thresh : m2Thresh_off;
828 int m2CountThr = on ?
829 aniState->iniDef.m2CountThr : m2CountThr_off;
830 int m2CountThrLow = on ?
831 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
832 int m1ThreshLowExt = on ?
833 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
834 int m2ThreshLowExt = on ?
835 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
836 int m1ThreshExt = on ?
837 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
838 int m2ThreshExt = on ?
839 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
af914a9f
LR		 840
841 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
842 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
e36b27af 843 m1ThreshLow);
af914a9f
LR		 844 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
845 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
e36b27af 846 m2ThreshLow);
af914a9f 847 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 848 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
af914a9f 849 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 850 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
af914a9f 851 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 852 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
af914a9f
LR		 853 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
854 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
e36b27af 855 m2CountThrLow);
af914a9f
LR		 856
857 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 858 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
af914a9f 859 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 860 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
af914a9f 861 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 862 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
af914a9f 863 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 864 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
af914a9f
LR		 865
866 if (on)
867 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
868 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
869 else
870 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
871 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
872
873 if (!on != aniState->ofdmWeakSigDetectOff) {
226afe68
JP		 874 ath_dbg(common, ATH_DBG_ANI,
875 "** ch %d: ofdm weak signal: %s=>%s\n",
876 chan->channel,
877 !aniState->ofdmWeakSigDetectOff ?
878 "on" : "off",
879 on ? "on" : "off");
af914a9f
LR		 880 if (on)
881 ah->stats.ast_ani_ofdmon++;
882 else
883 ah->stats.ast_ani_ofdmoff++;
884 aniState->ofdmWeakSigDetectOff = !on;
885 }
886 break;
887 }
af914a9f 888 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 889 u32 level = param;
890
e36b27af 891 if (level >= ARRAY_SIZE(firstep_table)) {
226afe68
JP		 892 ath_dbg(common, ATH_DBG_ANI,
893 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
894 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 895 return false;
896 }
e36b27af
LR		 897
898 /*
899 * make register setting relative to default
900 * from INI file & cap value
901 */
902 value = firstep_table[level] -
903 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
904 aniState->iniDef.firstep;
905 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
906 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
907 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
908 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 909 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
910 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 911 value);
912 /*
913 * we need to set first step low register too
914 * make register setting relative to default
915 * from INI file & cap value
916 */
917 value2 = firstep_table[level] -
918 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
919 aniState->iniDef.firstepLow;
920 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
921 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
922 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
923 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
924
925 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
926 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
927
928 if (level != aniState->firstepLevel) {
226afe68
JP		 929 ath_dbg(common, ATH_DBG_ANI,
930 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
931 chan->channel,
932 aniState->firstepLevel,
933 level,
934 ATH9K_ANI_FIRSTEP_LVL_NEW,
935 value,
936 aniState->iniDef.firstep);
937 ath_dbg(common, ATH_DBG_ANI,
938 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
939 chan->channel,
940 aniState->firstepLevel,
941 level,
942 ATH9K_ANI_FIRSTEP_LVL_NEW,
943 value2,
944 aniState->iniDef.firstepLow);
e36b27af
LR		 945 if (level > aniState->firstepLevel)
946 ah->stats.ast_ani_stepup++;
947 else if (level < aniState->firstepLevel)
948 ah->stats.ast_ani_stepdown++;
949 aniState->firstepLevel = level;
950 }
af914a9f
LR		 951 break;
952 }
953 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 954 u32 level = param;
955
e36b27af 956 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
226afe68
JP		 957 ath_dbg(common, ATH_DBG_ANI,
958 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
959 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 960 return false;
961 }
e36b27af
LR		 962 /*
963 * make register setting relative to default
964 * from INI file & cap value
965 */
966 value = cycpwrThr1_table[level] -
967 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
968 aniState->iniDef.cycpwrThr1;
969 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
970 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
971 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
972 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 973 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
974 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 975 value);
976
977 /*
978 * set AR_PHY_EXT_CCA for extension channel
979 * make register setting relative to default
980 * from INI file & cap value
981 */
982 value2 = cycpwrThr1_table[level] -
983 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
984 aniState->iniDef.cycpwrThr1Ext;
985 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
986 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
987 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
988 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
989 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
990 AR_PHY_EXT_CYCPWR_THR1, value2);
991
992 if (level != aniState->spurImmunityLevel) {
226afe68
JP		 993 ath_dbg(common, ATH_DBG_ANI,
994 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
995 chan->channel,
996 aniState->spurImmunityLevel,
997 level,
998 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
999 value,
1000 aniState->iniDef.cycpwrThr1);
1001 ath_dbg(common, ATH_DBG_ANI,
1002 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1003 chan->channel,
1004 aniState->spurImmunityLevel,
1005 level,
1006 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1007 value2,
1008 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1009 if (level > aniState->spurImmunityLevel)
1010 ah->stats.ast_ani_spurup++;
1011 else if (level < aniState->spurImmunityLevel)
1012 ah->stats.ast_ani_spurdown++;
1013 aniState->spurImmunityLevel = level;
1014 }
af914a9f
LR		 1015 break;
1016 }
e36b27af
LR		 1017 case ATH9K_ANI_MRC_CCK:{
1018 /*
1019 * is_on == 1 means MRC CCK ON (default, less noise imm)
1020 * is_on == 0 means MRC CCK is OFF (more noise imm)
1021 */
1022 bool is_on = param ? 1 : 0;
1023 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1024 AR_PHY_MRC_CCK_ENABLE, is_on);
1025 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1026 AR_PHY_MRC_CCK_MUX_REG, is_on);
1027 if (!is_on != aniState->mrcCCKOff) {
226afe68
JP		 1028 ath_dbg(common, ATH_DBG_ANI,
1029 "** ch %d: MRC CCK: %s=>%s\n",
1030 chan->channel,
1031 !aniState->mrcCCKOff ? "on" : "off",
1032 is_on ? "on" : "off");
e36b27af
LR		 1033 if (is_on)
1034 ah->stats.ast_ani_ccklow++;
1035 else
1036 ah->stats.ast_ani_cckhigh++;
1037 aniState->mrcCCKOff = !is_on;
1038 }
1039 break;
1040 }
af914a9f
LR		 1041 case ATH9K_ANI_PRESENT:
1042 break;
1043 default:
226afe68 1044 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1045 return false;
1046 }
1047
226afe68
JP		 1048 ath_dbg(common, ATH_DBG_ANI,
1049 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1050 aniState->spurImmunityLevel,
1051 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1052 aniState->firstepLevel,
1053 !aniState->mrcCCKOff ? "on" : "off",
1054 aniState->listenTime,
1055 aniState->ofdmPhyErrCount,
1056 aniState->cckPhyErrCount);
af914a9f 1057 return true;
c16fcb49
FF		 1058}
1059
641d9921
FF		 1060static void ar9003_hw_do_getnf(struct ath_hw *ah,
1061 int16_t nfarray[NUM_NF_READINGS])
1062{
b06af7a5
VT		 1063#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1064#define AR_PHY_CH_MINCCA_PWR_S 20
1065#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1066#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1067
b06af7a5
VT		 1068 int16_t nf;
1069 int i;
866b7780 1070
b06af7a5
VT		 1071 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1072 if (ah->rxchainmask & BIT(i)) {
1073 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1074 AR_PHY_CH_MINCCA_PWR);
1075 nfarray[i] = sign_extend32(nf, 8);
641d9921 1076
b06af7a5
VT		 1077 if (IS_CHAN_HT40(ah->curchan)) {
1078 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1079
b06af7a5
VT		 1080 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1081 AR_PHY_CH_EXT_MINCCA_PWR);
1082 nfarray[ext_idx] = sign_extend32(nf, 8);
1083 }
1084 }
1085 }
641d9921
FF		 1086}
1087
f2552e28 1088static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1089{
f2552e28
FF		 1090 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1091 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
0c453732
GJ		 1092 if (AR_SREV_9330(ah))
1093 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1094 else
1095 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1096 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1097 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1098 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
641d9921
FF		 1099}
1100
e36b27af
LR		 1101/*
1102 * Initialize the ANI register values with default (ini) values.
1103 * This routine is called during a (full) hardware reset after
1104 * all the registers are initialised from the INI.
1105 */
1106static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1107{
1108 struct ar5416AniState *aniState;
1109 struct ath_common *common = ath9k_hw_common(ah);
1110 struct ath9k_channel *chan = ah->curchan;
1111 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1112 u32 val;
1113
093115b7 1114 aniState = &ah->curchan->ani;
e36b27af
LR		 1115 iniDef = &aniState->iniDef;
1116
226afe68
JP		 1117 ath_dbg(common, ATH_DBG_ANI,
1118 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1119 ah->hw_version.macVersion,
1120 ah->hw_version.macRev,
1121 ah->opmode,
1122 chan->channel,
1123 chan->channelFlags);
e36b27af
LR		 1124
1125 val = REG_READ(ah, AR_PHY_SFCORR);
1126 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1127 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1128 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1129
1130 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1131 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1132 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1133 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1134
1135 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1136 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1137 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1138 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1139 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1140 iniDef->firstep = REG_READ_FIELD(ah,
1141 AR_PHY_FIND_SIG,
1142 AR_PHY_FIND_SIG_FIRSTEP);
1143 iniDef->firstepLow = REG_READ_FIELD(ah,
1144 AR_PHY_FIND_SIG_LOW,
1145 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1146 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1147 AR_PHY_TIMING5,
1148 AR_PHY_TIMING5_CYCPWR_THR1);
1149 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1150 AR_PHY_EXT_CCA,
1151 AR_PHY_EXT_CYCPWR_THR1);
1152
1153 /* these levels just got reset to defaults by the INI */
1154 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1155 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1156 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1157 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
e36b27af
LR		 1158}
1159
4e8c14e9
FF		 1160static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1161 struct ath_hw_radar_conf *conf)
1162{
1163 u32 radar_0 = 0, radar_1 = 0;
1164
1165 if (!conf) {
1166 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1167 return;
1168 }
1169
1170 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1171 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1172 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1173 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1174 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1175 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1176
1177 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1178 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1179 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1180 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1181 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1182
1183 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1184 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1185 if (conf->ext_channel)
1186 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1187 else
1188 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1189}
1190
c5d0855a
FF		 1191static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1192{
1193 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1194
1195 conf->fir_power = -28;
1196 conf->radar_rssi = 0;
1197 conf->pulse_height = 10;
1198 conf->pulse_rssi = 24;
1199 conf->pulse_inband = 8;
1200 conf->pulse_maxlen = 255;
1201 conf->pulse_inband_step = 12;
1202 conf->radar_inband = 8;
1203}
1204
6bcbc062
MSS		 1205static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1206 struct ath_hw_antcomb_conf *antconf)
1207{
1208 u32 regval;
1209
1210 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1211 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1212 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1213 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1214 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1215 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1216 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1217
c4cf2c58
GJ		 1218 if (AR_SREV_9330_11(ah)) {
1219 antconf->lna1_lna2_delta = -9;
1220 antconf->div_group = 1;
1221 } else if (AR_SREV_9485(ah)) {
cd0ed1b5
GJ		 1222 antconf->lna1_lna2_delta = -9;
1223 antconf->div_group = 2;
1224 } else {
1225 antconf->lna1_lna2_delta = -3;
1226 antconf->div_group = 0;
1227 }
6bcbc062
MSS		 1228}
1229
1230static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1231 struct ath_hw_antcomb_conf *antconf)
1232{
1233 u32 regval;
1234
1235 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1236 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1237 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1238 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1239 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1240 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1241 regval |= ((antconf->main_lna_conf <<
1242 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1243 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1244 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1245 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1246 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1247 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1248 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1249 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1250 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1251 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1252
1253 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1254}
1255
8525f280
LR		 1256void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1257{
1258 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 1259 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 1260 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 1261 AR_PHY_CCA_0,
1262 AR_PHY_CCA_1,
1263 AR_PHY_CCA_2,
1264 AR_PHY_EXT_CCA,
1265 AR_PHY_EXT_CCA_1,
1266 AR_PHY_EXT_CCA_2,
1267 };
8525f280
LR		 1268
1269 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1270 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1271 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1272 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1273 priv_ops->init_bb = ar9003_hw_init_bb;
1274 priv_ops->process_ini = ar9003_hw_process_ini;
1275 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1276 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1277 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1278 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1279 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
8525f280 1280 priv_ops->set_diversity = ar9003_hw_set_diversity;
c16fcb49 1281 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1282 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 1283 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 1284 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
f2552e28 1285
6bcbc062
MSS		 1286 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1287 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1288
f2552e28 1289 ar9003_hw_set_nf_limits(ah);
c5d0855a 1290 ar9003_hw_set_radar_conf(ah);
bbacee13 1291 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 1292}
aea702b7
LR		 1293
1294void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1295{
1296 struct ath_common *common = ath9k_hw_common(ah);
1297 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1298 u32 val, idle_count;
1299
1300 if (!idle_tmo_ms) {
1301 /* disable IRQ, disable chip-reset for BB panic */
1302 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1303 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1304 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1305 AR_PHY_WATCHDOG_IRQ_ENABLE));
1306
1307 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1308 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1309 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1310 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1311 AR_PHY_WATCHDOG_IDLE_ENABLE));
1312
226afe68 1313 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 1314 return;
1315 }
1316
1317 /* enable IRQ, disable chip-reset for BB watchdog */
1318 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1319 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1320 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1321 ~AR_PHY_WATCHDOG_RST_ENABLE);
1322
1323 /* bound limit to 10 secs */
1324 if (idle_tmo_ms > 10000)
1325 idle_tmo_ms = 10000;
1326
1327 /*
1328 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1329 *
1330 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1331 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1332 *
1333 * Given we use fast clock now in 5 GHz, these time units should
1334 * be common for both 2 GHz and 5 GHz.
1335 */
1336 idle_count = (100 * idle_tmo_ms) / 74;
1337 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1338 idle_count = (100 * idle_tmo_ms) / 37;
1339
1340 /*
1341 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1342 * set idle time-out.
1343 */
1344 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1345 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1346 AR_PHY_WATCHDOG_IDLE_MASK |
1347 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1348
226afe68
JP		 1349 ath_dbg(common, ATH_DBG_RESET,
1350 "Enabled BB Watchdog timeout (%u ms)\n",
1351 idle_tmo_ms);
aea702b7
LR		 1352}
1353
1354void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1355{
1356 /*
1357 * we want to avoid printing in ISR context so we save the
1358 * watchdog status to be printed later in bottom half context.
1359 */
1360 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1361
1362 /*
1363 * the watchdog timer should reset on status read but to be sure
1364 * sure we write 0 to the watchdog status bit.
1365 */
1366 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1367 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1368}
1369
1370void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1371{
1372 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 1373 u32 status;
aea702b7
LR		 1374
1375 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1376 return;
1377
1378 status = ah->bb_watchdog_last_status;
226afe68
JP		 1379 ath_dbg(common, ATH_DBG_RESET,
1380 "\n==== BB update: BB status=0x%08x ====\n", status);
1381 ath_dbg(common, ATH_DBG_RESET,
1382 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1383 MS(status, AR_PHY_WATCHDOG_INFO),
1384 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1385 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1386 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1387 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1388 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1389 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1390 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1391 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1392
1393 ath_dbg(common, ATH_DBG_RESET,
1394 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1395 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1396 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1397 ath_dbg(common, ATH_DBG_RESET,
1398 "** BB mode: BB_gen_controls=0x%08x **\n",
1399 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 1400
b5bfc568
FF		 1401#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1402 if (common->cc_survey.cycles)
226afe68
JP		 1403 ath_dbg(common, ATH_DBG_RESET,
1404 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1405 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 1406
226afe68
JP		 1407 ath_dbg(common, ATH_DBG_RESET,
1408 "==== BB update: done ====\n\n");
aea702b7
LR		 1409}
1410EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 1411
1412void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1413{
1414 u32 val;
1415
1416 /* While receiving unsupported rate frame rx state machine
1417 * gets into a state 0xb and if phy_restart happens in that
1418 * state, BB would go hang. If RXSM is in 0xb state after
1419 * first bb panic, ensure to disable the phy_restart.
1420 */
1421 if (!((MS(ah->bb_watchdog_last_status,
1422 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1423 ah->bb_hang_rx_ofdm))
1424 return;
1425
1426 ah->bb_hang_rx_ofdm = true;
1427 val = REG_READ(ah, AR_PHY_RESTART);
1428 val &= ~AR_PHY_RESTART_ENA;
1429
1430 REG_WRITE(ah, AR_PHY_RESTART, val);
1431}
1432EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Linux kernel - Deliverables
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