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ath9k: add mode register initialization code for AR9550
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
ee40fa06 17#include <linux/export.h>
8525f280 18#include "hw.h"
da6f1d7f 19#include "ar9003_phy.h"
8525f280 20
e36b27af
LR		 21static const int firstep_table[] =
22/* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25static const int cycpwrThr1_table[] =
26/* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29/*
30 * register values to turn OFDM weak signal detection OFF
31 */
32static const int m1ThreshLow_off = 127;
33static const int m2ThreshLow_off = 127;
34static const int m1Thresh_off = 127;
35static const int m2Thresh_off = 127;
36static const int m2CountThr_off = 31;
37static const int m2CountThrLow_off = 63;
38static const int m1ThreshLowExt_off = 127;
39static const int m2ThreshLowExt_off = 127;
40static const int m1ThreshExt_off = 127;
41static const int m2ThreshExt_off = 127;
42
8525f280
LR		 43/**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
e4922f2b 49 * for AR9300 family of chipsets.
8525f280
LR		 50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69{
f7abf0c1
FF		 70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93
GJ		 79 if (AR_SREV_9330(ah)) {
80 u32 chan_frac;
81 u32 div;
82
83 if (ah->is_clk_25mhz)
84 div = 75;
85 else
86 div = 120;
87
88 channelSel = (freq * 4) / div;
89 chan_frac = (((freq * 4) % div) * 0x20000) / div;
90 channelSel = (channelSel << 17) | chan_frac;
91 } else if (AR_SREV_9485(ah)) {
3dfd7f60
VT		 92 u32 chan_frac;
93
94 /*
95 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
96 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
97 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
98 */
99 channelSel = (freq * 4) / 120;
100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
101 channelSel = (channelSel << 17) | chan_frac;
17869f4f
VT		 102 } else if (AR_SREV_9340(ah)) {
103 if (ah->is_clk_25mhz) {
104 u32 chan_frac;
105
106 channelSel = (freq * 2) / 75;
107 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
108 channelSel = (channelSel << 17) | chan_frac;
109 } else
110 channelSel = CHANSEL_2G(freq) >> 1;
3dfd7f60 111 } else
85dd0921 112 channelSel = CHANSEL_2G(freq);
f7abf0c1
FF		 113 /* Set to 2G mode */
114 bMode = 1;
115 } else {
17869f4f
VT		 116 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
117 u32 chan_frac;
118
119 channelSel = (freq * 2) / 75;
dbb204e3 120 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
17869f4f
VT		 121 channelSel = (channelSel << 17) | chan_frac;
122 } else {
123 channelSel = CHANSEL_5G(freq);
124 /* Doubler is ON, so, divide channelSel by 2. */
125 channelSel >>= 1;
126 }
f7abf0c1
FF		 127 /* Set to 5G mode */
128 bMode = 0;
129 }
130
131 /* Enable fractional mode for all channels */
132 fracMode = 1;
133 aModeRefSel = 0;
134 loadSynthChannel = 0;
135
136 reg32 = (bMode << 29);
137 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
138
139 /* Enable Long shift Select for Synthesizer */
140 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
141 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
142
143 /* Program Synth. setting */
144 reg32 = (channelSel << 2) | (fracMode << 30) |
145 (aModeRefSel << 28) | (loadSynthChannel << 31);
146 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
147
148 /* Toggle Load Synth channel bit */
149 loadSynthChannel = 1;
150 reg32 = (channelSel << 2) | (fracMode << 30) |
151 (aModeRefSel << 28) | (loadSynthChannel << 31);
152 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
153
154 ah->curchan = chan;
f7abf0c1 155
8525f280
LR		 156 return 0;
157}
158
159/**
e36b27af 160 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 161 * @ah: atheros hardware structure
162 * @chan:
163 *
164 * For single-chip solutions. Converts to baseband spur frequency given the
165 * input channel frequency and compute register settings below.
166 *
167 * Spur mitigation for MRC CCK
168 */
1547da37
LR		 169static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
170 struct ath9k_channel *chan)
8525f280 171{
07b2fa5a 172 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 173 int cur_bb_spur, negative = 0, cck_spur_freq;
174 int i;
d9a2545a 175 int range, max_spur_cnts, synth_freq;
4b5237cc 176 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
ca375554
FF		 177
178 /*
179 * Need to verify range +/- 10 MHz in control channel, otherwise spur
180 * is out-of-band and can be ignored.
181 */
182
c1acfbe8 183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
d9a2545a
VT		 184 if (spur_fbin_ptr[0] == 0) /* No spur */
185 return;
186 max_spur_cnts = 5;
187 if (IS_CHAN_HT40(chan)) {
188 range = 19;
189 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
190 AR_PHY_GC_DYN2040_PRI_CH) == 0)
191 synth_freq = chan->channel + 10;
192 else
193 synth_freq = chan->channel - 10;
194 } else {
195 range = 10;
196 synth_freq = chan->channel;
197 }
198 } else {
38df2f07 199 range = AR_SREV_9462(ah) ? 5 : 10;
d9a2545a
VT		 200 max_spur_cnts = 4;
201 synth_freq = chan->channel;
202 }
203
204 for (i = 0; i < max_spur_cnts; i++) {
38df2f07
RM		 205 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
206 continue;
ca375554 207 negative = 0;
c1acfbe8 208 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
8edb254c
GJ		 209 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
210 IS_CHAN_2GHZ(chan));
d9a2545a 211 else
8edb254c 212 cur_bb_spur = spur_freq[i];
ca375554 213
8edb254c 214 cur_bb_spur -= synth_freq;
ca375554
FF		 215 if (cur_bb_spur < 0) {
216 negative = 1;
217 cur_bb_spur = -cur_bb_spur;
218 }
d9a2545a 219 if (cur_bb_spur < range) {
ca375554
FF		 220 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
221
222 if (negative == 1)
223 cck_spur_freq = -cck_spur_freq;
224
225 cck_spur_freq = cck_spur_freq & 0xfffff;
226
227 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
228 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
229 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
230 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
231 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
232 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
233 0x2);
234 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
235 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
236 0x1);
237 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
238 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
239 cck_spur_freq);
240
241 return;
242 }
243 }
244
245 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
246 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
247 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
248 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
249 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
250 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 251}
252
1547da37
LR		 253/* Clean all spur register fields */
254static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
255{
256 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
257 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
258 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
259 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
260 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
261 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
262 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
263 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
264 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
265 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
266 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
267 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
268 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
269 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
270 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
271 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
272 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
273 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
274
275 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
276 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
277 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
278 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
279 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
280 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
281 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
282 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
283 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
284 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
285 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
286 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
287 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
288 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
289 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
290 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
291 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
292 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
293 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
294 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
295}
296
297static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
298 int freq_offset,
299 int spur_freq_sd,
300 int spur_delta_phase,
301 int spur_subchannel_sd)
302{
303 int mask_index = 0;
304
305 /* OFDM Spur mitigation */
306 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
307 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
308 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
309 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
310 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
311 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
312 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
313 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
314 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
315 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
316 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
317 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
318 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
319 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
320 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
321 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
322 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
323 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
324
325 if (REG_READ_FIELD(ah, AR_PHY_MODE,
326 AR_PHY_MODE_DYNAMIC) == 0x1)
327 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
328 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
329
330 mask_index = (freq_offset << 4) / 5;
331 if (mask_index < 0)
332 mask_index = mask_index - 1;
333
334 mask_index = mask_index & 0x7f;
335
336 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
337 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
338 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
339 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
341 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
342 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
343 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
344 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
345 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
346 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
347 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
348 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
349 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
350 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
351 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
352 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
353 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
354 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
355 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
356}
357
358static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
359 struct ath9k_channel *chan,
360 int freq_offset)
361{
362 int spur_freq_sd = 0;
363 int spur_subchannel_sd = 0;
364 int spur_delta_phase = 0;
365
366 if (IS_CHAN_HT40(chan)) {
367 if (freq_offset < 0) {
368 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
369 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
370 spur_subchannel_sd = 1;
371 else
372 spur_subchannel_sd = 0;
373
9d1ceac5 374 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
1547da37
LR		 375
376 } else {
377 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
378 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
379 spur_subchannel_sd = 0;
380 else
381 spur_subchannel_sd = 1;
382
9d1ceac5 383 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
1547da37
LR		 384
385 }
386
387 spur_delta_phase = (freq_offset << 17) / 5;
388
389 } else {
390 spur_subchannel_sd = 0;
391 spur_freq_sd = (freq_offset << 9) /11;
392 spur_delta_phase = (freq_offset << 18) / 5;
393 }
394
395 spur_freq_sd = spur_freq_sd & 0x3ff;
396 spur_delta_phase = spur_delta_phase & 0xfffff;
397
398 ar9003_hw_spur_ofdm(ah,
399 freq_offset,
400 spur_freq_sd,
401 spur_delta_phase,
402 spur_subchannel_sd);
403}
404
405/* Spur mitigation for OFDM */
406static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
407 struct ath9k_channel *chan)
408{
409 int synth_freq;
410 int range = 10;
411 int freq_offset = 0;
412 int mode;
413 u8* spurChansPtr;
414 unsigned int i;
415 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
416
417 if (IS_CHAN_5GHZ(chan)) {
418 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
419 mode = 0;
420 }
421 else {
422 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
423 mode = 1;
424 }
425
426 if (spurChansPtr[0] == 0)
427 return; /* No spur in the mode */
428
429 if (IS_CHAN_HT40(chan)) {
430 range = 19;
431 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
432 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
433 synth_freq = chan->channel - 10;
434 else
435 synth_freq = chan->channel + 10;
436 } else {
437 range = 10;
438 synth_freq = chan->channel;
439 }
440
441 ar9003_hw_spur_ofdm_clear(ah);
442
0f8e94d2 443 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
8edb254c
GJ		 444 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
445 freq_offset -= synth_freq;
1547da37
LR		 446 if (abs(freq_offset) < range) {
447 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
448 break;
449 }
450 }
451}
452
453static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
454 struct ath9k_channel *chan)
455{
456 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
457 ar9003_hw_spur_mitigate_ofdm(ah, chan);
458}
459
8525f280
LR		 460static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
461 struct ath9k_channel *chan)
462{
317d3328
FF		 463 u32 pll;
464
465 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
466
467 if (chan && IS_CHAN_HALF_RATE(chan))
468 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
469 else if (chan && IS_CHAN_QUARTER_RATE(chan))
470 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
471
14bc1104 472 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 473
474 return pll;
8525f280
LR		 475}
476
477static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
478 struct ath9k_channel *chan)
479{
cffb5e49
LR		 480 u32 phymode;
481 u32 enableDacFifo = 0;
482
483 enableDacFifo =
484 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
485
486 /* Enable 11n HT, 20 MHz */
8ad38d22 487 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
cffb5e49
LR		 488 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
489
490 /* Configure baseband for dynamic 20/40 operation */
491 if (IS_CHAN_HT40(chan)) {
492 phymode |= AR_PHY_GC_DYN2040_EN;
493 /* Configure control (primary) channel at +-10MHz */
494 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
495 (chan->chanmode == CHANNEL_G_HT40PLUS))
496 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
497
498 }
499
500 /* make sure we preserve INI settings */
501 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
502 /* turn off Green Field detection for STA for now */
503 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
504
505 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
506
507 /* Configure MAC for 20/40 operation */
508 ath9k_hw_set11nmac2040(ah);
509
510 /* global transmit timeout (25 TUs default)*/
511 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
512 /* carrier sense timeout */
513 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 514}
515
516static void ar9003_hw_init_bb(struct ath_hw *ah,
517 struct ath9k_channel *chan)
518{
af914a9f
LR		 519 u32 synthDelay;
520
521 /*
522 * Wait for the frequency synth to settle (synth goes on
523 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
524 * Value is in 100ns increments.
525 */
526 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f
LR		 527
528 /* Activate the PHY (includes baseband activate + synthesizer on) */
529 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7c5adc8d 530 ath9k_hw_synth_delay(ah, chan, synthDelay);
8525f280
LR		 531}
532
56266bff 533static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
cffb5e49
LR		 534{
535 switch (rx) {
536 case 0x5:
537 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
538 AR_PHY_SWAP_ALT_CHAIN);
539 case 0x3:
540 case 0x1:
541 case 0x2:
542 case 0x7:
543 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
544 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
545 break;
546 default:
547 break;
548 }
549
ea066d5a
MSS		 550 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
551 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
423e38e8 552 else if (AR_SREV_9462(ah))
2577c6e8
SB		 553 /* xxx only when MCI support is enabled */
554 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
ea066d5a
MSS		 555 else
556 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
557
cffb5e49
LR		 558 if (tx == 0x5) {
559 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
560 AR_PHY_SWAP_ALT_CHAIN);
561 }
562}
563
564/*
565 * Override INI values with chip specific configuration.
566 */
567static void ar9003_hw_override_ini(struct ath_hw *ah)
568{
569 u32 val;
570
571 /*
572 * Set the RX_ABORT and RX_DIS and clear it only after
573 * RXE is set for MAC. This prevents frames with
574 * corrupted descriptor status.
575 */
576 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
577
578 /*
579 * For AR9280 and above, there is a new feature that allows
580 * Multicast search based on both MAC Address and Key ID. By default,
581 * this feature is enabled. But since the driver is not using this
582 * feature, we switch it off; otherwise multicast search based on
583 * MAC addr only will fail.
584 */
585 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
586 REG_WRITE(ah, AR_PCU_MISC_MODE2,
587 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
bf3f204b
FF		 588
589 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
590 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
cffb5e49
LR		 591}
592
593static void ar9003_hw_prog_ini(struct ath_hw *ah,
594 struct ar5416IniArray *iniArr,
595 int column)
596{
597 unsigned int i, regWrites = 0;
598
599 /* New INI format: Array may be undefined (pre, core, post arrays) */
600 if (!iniArr->ia_array)
601 return;
602
603 /*
604 * New INI format: Pre, core, and post arrays for a given subsystem
605 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
606 * the array is non-modal and force the column to 1.
607 */
608 if (column >= iniArr->ia_columns)
609 column = 1;
610
611 for (i = 0; i < iniArr->ia_rows; i++) {
612 u32 reg = INI_RA(iniArr, i, 0);
613 u32 val = INI_RA(iniArr, i, column);
614
7e68b746 615 REG_WRITE(ah, reg, val);
b2ccc507 616
cffb5e49
LR		 617 DO_DELAY(regWrites);
618 }
619}
620
8bc45c6b
GJ		 621static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
622 struct ath9k_channel *chan)
623{
624 int ret;
625
626 switch (chan->chanmode) {
627 case CHANNEL_A:
628 case CHANNEL_A_HT20:
629 if (chan->channel <= 5350)
630 ret = 1;
631 else if ((chan->channel > 5350) && (chan->channel <= 5600))
632 ret = 3;
633 else
634 ret = 5;
635 break;
636
637 case CHANNEL_A_HT40PLUS:
638 case CHANNEL_A_HT40MINUS:
639 if (chan->channel <= 5350)
640 ret = 2;
641 else if ((chan->channel > 5350) && (chan->channel <= 5600))
642 ret = 4;
643 else
644 ret = 6;
645 break;
646
647 case CHANNEL_G:
648 case CHANNEL_G_HT20:
649 case CHANNEL_B:
650 ret = 8;
651 break;
652
653 case CHANNEL_G_HT40PLUS:
654 case CHANNEL_G_HT40MINUS:
655 ret = 7;
656 break;
657
658 default:
659 ret = -EINVAL;
660 }
661
662 return ret;
663}
664
8525f280
LR		 665static int ar9003_hw_process_ini(struct ath_hw *ah,
666 struct ath9k_channel *chan)
667{
cffb5e49 668 unsigned int regWrites = 0, i;
0ff2b5c0 669 u32 modesIndex;
cffb5e49
LR		 670
671 switch (chan->chanmode) {
672 case CHANNEL_A:
673 case CHANNEL_A_HT20:
674 modesIndex = 1;
cffb5e49
LR		 675 break;
676 case CHANNEL_A_HT40PLUS:
677 case CHANNEL_A_HT40MINUS:
678 modesIndex = 2;
cffb5e49
LR		 679 break;
680 case CHANNEL_G:
681 case CHANNEL_G_HT20:
682 case CHANNEL_B:
683 modesIndex = 4;
cffb5e49
LR		 684 break;
685 case CHANNEL_G_HT40PLUS:
686 case CHANNEL_G_HT40MINUS:
687 modesIndex = 3;
cffb5e49
LR		 688 break;
689
690 default:
691 return -EINVAL;
692 }
693
694 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
695 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
696 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
697 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
698 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
423e38e8 699 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
2577c6e8
SB		 700 ar9003_hw_prog_ini(ah,
701 &ah->ini_radio_post_sys2ant,
702 modesIndex);
cffb5e49
LR		 703 }
704
705 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
8bc45c6b
GJ		 706 if (AR_SREV_9550(ah))
707 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
708 regWrites);
709
710 if (AR_SREV_9550(ah)) {
711 int modes_txgain_index;
712
713 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
714 if (modes_txgain_index < 0)
715 return -EINVAL;
716
717 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
718 regWrites);
719 } else {
720 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
721 }
cffb5e49
LR		 722
723 /*
724 * For 5GHz channels requiring Fast Clock, apply
725 * different modal values.
726 */
6b42e8d0 727 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 728 REG_WRITE_ARRAY(&ah->iniModesFastClock,
cffb5e49
LR		 729 modesIndex, regWrites);
730
c7d36f9f 731 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
d89baac8 732
9951c4d0
FF		 733 if (chan->channel == 2484)
734 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
735
c8b6fbe1
RM		 736 if (AR_SREV_9462(ah))
737 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
738 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
739
5f0c04ea 740 ah->modes_index = modesIndex;
cffb5e49
LR		 741 ar9003_hw_override_ini(ah);
742 ar9003_hw_set_channel_regs(ah, chan);
743 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
64ea57d0 744 ath9k_hw_apply_txpower(ah, chan, false);
cffb5e49 745
423e38e8 746 if (AR_SREV_9462(ah)) {
8ad74c4d
RM		 747 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
748 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
749 ah->enabled_cals |= TX_IQ_CAL;
750 else
751 ah->enabled_cals &= ~TX_IQ_CAL;
752
753 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
754 ah->enabled_cals |= TX_CL_CAL;
755 else
756 ah->enabled_cals &= ~TX_CL_CAL;
757 }
758
cffb5e49 759 return 0;
8525f280
LR		 760}
761
762static void ar9003_hw_set_rfmode(struct ath_hw *ah,
763 struct ath9k_channel *chan)
764{
af914a9f
LR		 765 u32 rfMode = 0;
766
767 if (chan == NULL)
768 return;
769
770 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
771 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
772
6b42e8d0 773 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f 774 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
08685ce3
FF		 775 if (IS_CHAN_QUARTER_RATE(chan))
776 rfMode |= AR_PHY_MODE_QUARTER;
777 if (IS_CHAN_HALF_RATE(chan))
778 rfMode |= AR_PHY_MODE_HALF;
af914a9f 779
3e61d3f9
FF		 780 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
781 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
782 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
783
af914a9f 784 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 785}
786
787static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
788{
af914a9f 789 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 790}
791
792static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
793 struct ath9k_channel *chan)
794{
af914a9f
LR		 795 u32 coef_scaled, ds_coef_exp, ds_coef_man;
796 u32 clockMhzScaled = 0x64000000;
797 struct chan_centers centers;
798
799 /*
800 * half and quarter rate can divide the scaled clock by 2 or 4
801 * scale for selected channel bandwidth
802 */
803 if (IS_CHAN_HALF_RATE(chan))
804 clockMhzScaled = clockMhzScaled >> 1;
805 else if (IS_CHAN_QUARTER_RATE(chan))
806 clockMhzScaled = clockMhzScaled >> 2;
807
808 /*
809 * ALGO -> coef = 1e8/fcarrier*fclock/40;
810 * scaled coef to provide precision for this floating calculation
811 */
812 ath9k_hw_get_channel_centers(ah, chan, &centers);
813 coef_scaled = clockMhzScaled / centers.synth_center;
814
815 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
816 &ds_coef_exp);
817
818 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
819 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
820 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
821 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
822
823 /*
824 * For Short GI,
825 * scaled coeff is 9/10 that of normal coeff
826 */
827 coef_scaled = (9 * coef_scaled) / 10;
828
829 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
830 &ds_coef_exp);
831
832 /* for short gi */
833 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
834 AR_PHY_SGI_DSC_MAN, ds_coef_man);
835 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
836 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 837}
838
839static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
840{
af914a9f
LR		 841 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
842 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
843 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 844}
845
af914a9f
LR		 846/*
847 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
848 * Read the phy active delay register. Value is in 100ns increments.
849 */
8525f280
LR		 850static void ar9003_hw_rfbus_done(struct ath_hw *ah)
851{
af914a9f 852 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f 853
7c5adc8d 854 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
af914a9f
LR		 855
856 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 857}
858
c16fcb49
FF		 859static bool ar9003_hw_ani_control(struct ath_hw *ah,
860 enum ath9k_ani_cmd cmd, int param)
861{
af914a9f 862 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 863 struct ath9k_channel *chan = ah->curchan;
093115b7 864 struct ar5416AniState *aniState = &chan->ani;
e36b27af 865 s32 value, value2;
af914a9f
LR		 866
867 switch (cmd & ah->ani_function) {
af914a9f 868 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 869 /*
870 * on == 1 means ofdm weak signal detection is ON
871 * on == 1 is the default, for less noise immunity
872 *
873 * on == 0 means ofdm weak signal detection is OFF
874 * on == 0 means more noise imm
875 */
af914a9f 876 u32 on = param ? 1 : 0;
af914a9f
LR		 877
878 if (on)
879 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
880 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
881 else
882 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
883 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
884
7067e701 885 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 886 ath_dbg(common, ANI,
226afe68
JP		 887 "** ch %d: ofdm weak signal: %s=>%s\n",
888 chan->channel,
7067e701 889 aniState->ofdmWeakSigDetect ?
226afe68
JP		 890 "on" : "off",
891 on ? "on" : "off");
af914a9f
LR		 892 if (on)
893 ah->stats.ast_ani_ofdmon++;
894 else
895 ah->stats.ast_ani_ofdmoff++;
7067e701 896 aniState->ofdmWeakSigDetect = on;
af914a9f
LR		 897 }
898 break;
899 }
af914a9f 900 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 901 u32 level = param;
902
e36b27af 903 if (level >= ARRAY_SIZE(firstep_table)) {
d2182b69 904 ath_dbg(common, ANI,
226afe68
JP		 905 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
906 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 907 return false;
908 }
e36b27af
LR		 909
910 /*
911 * make register setting relative to default
912 * from INI file & cap value
913 */
914 value = firstep_table[level] -
465dce62 915 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 916 aniState->iniDef.firstep;
917 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
918 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
919 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
920 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 921 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
922 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 923 value);
924 /*
925 * we need to set first step low register too
926 * make register setting relative to default
927 * from INI file & cap value
928 */
929 value2 = firstep_table[level] -
465dce62 930 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 931 aniState->iniDef.firstepLow;
932 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
933 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
934 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
935 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
936
937 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
938 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
939
940 if (level != aniState->firstepLevel) {
d2182b69 941 ath_dbg(common, ANI,
226afe68
JP		 942 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
943 chan->channel,
944 aniState->firstepLevel,
945 level,
465dce62 946 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 947 value,
948 aniState->iniDef.firstep);
d2182b69 949 ath_dbg(common, ANI,
226afe68
JP		 950 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
951 chan->channel,
952 aniState->firstepLevel,
953 level,
465dce62 954 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 955 value2,
956 aniState->iniDef.firstepLow);
e36b27af
LR		 957 if (level > aniState->firstepLevel)
958 ah->stats.ast_ani_stepup++;
959 else if (level < aniState->firstepLevel)
960 ah->stats.ast_ani_stepdown++;
961 aniState->firstepLevel = level;
962 }
af914a9f
LR		 963 break;
964 }
965 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 966 u32 level = param;
967
e36b27af 968 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
d2182b69 969 ath_dbg(common, ANI,
226afe68
JP		 970 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
971 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 972 return false;
973 }
e36b27af
LR		 974 /*
975 * make register setting relative to default
976 * from INI file & cap value
977 */
978 value = cycpwrThr1_table[level] -
465dce62 979 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 980 aniState->iniDef.cycpwrThr1;
981 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
982 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
983 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
984 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 985 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
986 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 987 value);
988
989 /*
990 * set AR_PHY_EXT_CCA for extension channel
991 * make register setting relative to default
992 * from INI file & cap value
993 */
994 value2 = cycpwrThr1_table[level] -
465dce62 995 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 996 aniState->iniDef.cycpwrThr1Ext;
997 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
998 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
999 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1000 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1001 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1002 AR_PHY_EXT_CYCPWR_THR1, value2);
1003
1004 if (level != aniState->spurImmunityLevel) {
d2182b69 1005 ath_dbg(common, ANI,
226afe68
JP		 1006 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1007 chan->channel,
1008 aniState->spurImmunityLevel,
1009 level,
465dce62 1010 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1011 value,
1012 aniState->iniDef.cycpwrThr1);
d2182b69 1013 ath_dbg(common, ANI,
226afe68
JP		 1014 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1015 chan->channel,
1016 aniState->spurImmunityLevel,
1017 level,
465dce62 1018 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1019 value2,
1020 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1021 if (level > aniState->spurImmunityLevel)
1022 ah->stats.ast_ani_spurup++;
1023 else if (level < aniState->spurImmunityLevel)
1024 ah->stats.ast_ani_spurdown++;
1025 aniState->spurImmunityLevel = level;
1026 }
af914a9f
LR		 1027 break;
1028 }
e36b27af
LR		 1029 case ATH9K_ANI_MRC_CCK:{
1030 /*
1031 * is_on == 1 means MRC CCK ON (default, less noise imm)
1032 * is_on == 0 means MRC CCK is OFF (more noise imm)
1033 */
1034 bool is_on = param ? 1 : 0;
1035 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1036 AR_PHY_MRC_CCK_ENABLE, is_on);
1037 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1038 AR_PHY_MRC_CCK_MUX_REG, is_on);
81b67fd6 1039 if (is_on != aniState->mrcCCK) {
d2182b69 1040 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
226afe68 1041 chan->channel,
81b67fd6 1042 aniState->mrcCCK ? "on" : "off",
226afe68 1043 is_on ? "on" : "off");
e36b27af
LR		 1044 if (is_on)
1045 ah->stats.ast_ani_ccklow++;
1046 else
1047 ah->stats.ast_ani_cckhigh++;
81b67fd6 1048 aniState->mrcCCK = is_on;
e36b27af
LR		 1049 }
1050 break;
1051 }
af914a9f
LR		 1052 case ATH9K_ANI_PRESENT:
1053 break;
1054 default:
d2182b69 1055 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1056 return false;
1057 }
1058
d2182b69 1059 ath_dbg(common, ANI,
226afe68
JP		 1060 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1061 aniState->spurImmunityLevel,
7067e701 1062 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1063 aniState->firstepLevel,
81b67fd6 1064 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1065 aniState->listenTime,
1066 aniState->ofdmPhyErrCount,
1067 aniState->cckPhyErrCount);
af914a9f 1068 return true;
c16fcb49
FF		 1069}
1070
641d9921
FF		 1071static void ar9003_hw_do_getnf(struct ath_hw *ah,
1072 int16_t nfarray[NUM_NF_READINGS])
1073{
b06af7a5
VT		 1074#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1075#define AR_PHY_CH_MINCCA_PWR_S 20
1076#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1077#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1078
b06af7a5
VT		 1079 int16_t nf;
1080 int i;
866b7780 1081
b06af7a5
VT		 1082 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1083 if (ah->rxchainmask & BIT(i)) {
1084 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1085 AR_PHY_CH_MINCCA_PWR);
1086 nfarray[i] = sign_extend32(nf, 8);
641d9921 1087
b06af7a5
VT		 1088 if (IS_CHAN_HT40(ah->curchan)) {
1089 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1090
b06af7a5
VT		 1091 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1092 AR_PHY_CH_EXT_MINCCA_PWR);
1093 nfarray[ext_idx] = sign_extend32(nf, 8);
1094 }
1095 }
1096 }
641d9921
FF		 1097}
1098
f2552e28 1099static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1100{
f2552e28
FF		 1101 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1102 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
ae245cde 1103 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1104 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1105 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1106 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
ae245cde
SM		 1107
1108 if (AR_SREV_9330(ah))
1109 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1110
1111 if (AR_SREV_9462(ah)) {
1112 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1113 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1114 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1115 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1116 }
641d9921
FF		 1117}
1118
e36b27af
LR		 1119/*
1120 * Initialize the ANI register values with default (ini) values.
1121 * This routine is called during a (full) hardware reset after
1122 * all the registers are initialised from the INI.
1123 */
1124static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1125{
1126 struct ar5416AniState *aniState;
1127 struct ath_common *common = ath9k_hw_common(ah);
1128 struct ath9k_channel *chan = ah->curchan;
1129 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1130 u32 val;
1131
093115b7 1132 aniState = &ah->curchan->ani;
e36b27af
LR		 1133 iniDef = &aniState->iniDef;
1134
d2182b69 1135 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
226afe68
JP		 1136 ah->hw_version.macVersion,
1137 ah->hw_version.macRev,
1138 ah->opmode,
1139 chan->channel,
1140 chan->channelFlags);
e36b27af
LR		 1141
1142 val = REG_READ(ah, AR_PHY_SFCORR);
1143 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1144 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1145 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1146
1147 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1148 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1149 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1150 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1151
1152 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1153 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1154 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1155 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1156 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1157 iniDef->firstep = REG_READ_FIELD(ah,
1158 AR_PHY_FIND_SIG,
1159 AR_PHY_FIND_SIG_FIRSTEP);
1160 iniDef->firstepLow = REG_READ_FIELD(ah,
1161 AR_PHY_FIND_SIG_LOW,
1162 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1163 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1164 AR_PHY_TIMING5,
1165 AR_PHY_TIMING5_CYCPWR_THR1);
1166 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1167 AR_PHY_EXT_CCA,
1168 AR_PHY_EXT_CYCPWR_THR1);
1169
1170 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1171 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1172 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
7067e701 1173 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
81b67fd6 1174 aniState->mrcCCK = true;
e36b27af
LR		 1175}
1176
4e8c14e9
FF		 1177static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1178 struct ath_hw_radar_conf *conf)
1179{
1180 u32 radar_0 = 0, radar_1 = 0;
1181
1182 if (!conf) {
1183 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1184 return;
1185 }
1186
1187 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1188 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1189 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1190 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1191 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1192 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1193
1194 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1195 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1196 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1197 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1198 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1199
1200 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1201 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1202 if (conf->ext_channel)
1203 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1204 else
1205 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1206}
1207
c5d0855a
FF		 1208static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1209{
1210 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1211
1212 conf->fir_power = -28;
1213 conf->radar_rssi = 0;
1214 conf->pulse_height = 10;
1215 conf->pulse_rssi = 24;
1216 conf->pulse_inband = 8;
1217 conf->pulse_maxlen = 255;
1218 conf->pulse_inband_step = 12;
1219 conf->radar_inband = 8;
1220}
1221
6bcbc062
MSS		 1222static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1223 struct ath_hw_antcomb_conf *antconf)
1224{
1225 u32 regval;
1226
1227 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1228 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1229 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1230 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1231 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1232 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1233 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1234
c4cf2c58
GJ		 1235 if (AR_SREV_9330_11(ah)) {
1236 antconf->lna1_lna2_delta = -9;
1237 antconf->div_group = 1;
1238 } else if (AR_SREV_9485(ah)) {
cd0ed1b5
GJ		 1239 antconf->lna1_lna2_delta = -9;
1240 antconf->div_group = 2;
1241 } else {
1242 antconf->lna1_lna2_delta = -3;
1243 antconf->div_group = 0;
1244 }
6bcbc062
MSS		 1245}
1246
1247static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1248 struct ath_hw_antcomb_conf *antconf)
1249{
1250 u32 regval;
1251
1252 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1253 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1254 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1255 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1256 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1257 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1258 regval |= ((antconf->main_lna_conf <<
1259 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1260 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1261 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1262 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1263 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1264 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1265 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1266 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1267 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1268 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1269
1270 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1271}
1272
5f0c04ea
RM		 1273static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1274 struct ath9k_channel *chan,
1275 u8 *ini_reloaded)
1276{
1277 unsigned int regWrites = 0;
1278 u32 modesIndex;
1279
1280 switch (chan->chanmode) {
1281 case CHANNEL_A:
1282 case CHANNEL_A_HT20:
1283 modesIndex = 1;
1284 break;
1285 case CHANNEL_A_HT40PLUS:
1286 case CHANNEL_A_HT40MINUS:
1287 modesIndex = 2;
1288 break;
1289 case CHANNEL_G:
1290 case CHANNEL_G_HT20:
1291 case CHANNEL_B:
1292 modesIndex = 4;
1293 break;
1294 case CHANNEL_G_HT40PLUS:
1295 case CHANNEL_G_HT40MINUS:
1296 modesIndex = 3;
1297 break;
1298
1299 default:
1300 return -EINVAL;
1301 }
1302
1303 if (modesIndex == ah->modes_index) {
1304 *ini_reloaded = false;
1305 goto set_rfmode;
1306 }
1307
1308 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1309 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1310 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1311 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
423e38e8 1312 if (AR_SREV_9462_20(ah))
5f0c04ea
RM		 1313 ar9003_hw_prog_ini(ah,
1314 &ah->ini_radio_post_sys2ant,
1315 modesIndex);
1316
1317 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1318
1319 /*
1320 * For 5GHz channels requiring Fast Clock, apply
1321 * different modal values.
1322 */
1323 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 1324 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
5f0c04ea 1325
c7d36f9f 1326 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
5f0c04ea
RM		 1327
1328 ah->modes_index = modesIndex;
1329 *ini_reloaded = true;
1330
1331set_rfmode:
1332 ar9003_hw_set_rfmode(ah, chan);
1333 return 0;
1334}
1335
8525f280
LR		 1336void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1337{
1338 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 1339 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 1340 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 1341 AR_PHY_CCA_0,
1342 AR_PHY_CCA_1,
1343 AR_PHY_CCA_2,
1344 AR_PHY_EXT_CCA,
1345 AR_PHY_EXT_CCA_1,
1346 AR_PHY_EXT_CCA_2,
1347 };
8525f280
LR		 1348
1349 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1350 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1351 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1352 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1353 priv_ops->init_bb = ar9003_hw_init_bb;
1354 priv_ops->process_ini = ar9003_hw_process_ini;
1355 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1356 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1357 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1358 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1359 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
c16fcb49 1360 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1361 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 1362 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 1363 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
5f0c04ea 1364 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
f2552e28 1365
6bcbc062
MSS		 1366 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1367 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1368
f2552e28 1369 ar9003_hw_set_nf_limits(ah);
c5d0855a 1370 ar9003_hw_set_radar_conf(ah);
bbacee13 1371 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 1372}
aea702b7
LR		 1373
1374void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1375{
1376 struct ath_common *common = ath9k_hw_common(ah);
1377 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1378 u32 val, idle_count;
1379
1380 if (!idle_tmo_ms) {
1381 /* disable IRQ, disable chip-reset for BB panic */
1382 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1383 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1384 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1385 AR_PHY_WATCHDOG_IRQ_ENABLE));
1386
1387 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1388 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1389 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1390 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1391 AR_PHY_WATCHDOG_IDLE_ENABLE));
1392
d2182b69 1393 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 1394 return;
1395 }
1396
1397 /* enable IRQ, disable chip-reset for BB watchdog */
1398 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1399 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1400 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1401 ~AR_PHY_WATCHDOG_RST_ENABLE);
1402
1403 /* bound limit to 10 secs */
1404 if (idle_tmo_ms > 10000)
1405 idle_tmo_ms = 10000;
1406
1407 /*
1408 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1409 *
1410 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1411 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1412 *
1413 * Given we use fast clock now in 5 GHz, these time units should
1414 * be common for both 2 GHz and 5 GHz.
1415 */
1416 idle_count = (100 * idle_tmo_ms) / 74;
1417 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1418 idle_count = (100 * idle_tmo_ms) / 37;
1419
1420 /*
1421 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1422 * set idle time-out.
1423 */
1424 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1425 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1426 AR_PHY_WATCHDOG_IDLE_MASK |
1427 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1428
d2182b69 1429 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
226afe68 1430 idle_tmo_ms);
aea702b7
LR		 1431}
1432
1433void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1434{
1435 /*
1436 * we want to avoid printing in ISR context so we save the
1437 * watchdog status to be printed later in bottom half context.
1438 */
1439 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1440
1441 /*
1442 * the watchdog timer should reset on status read but to be sure
1443 * sure we write 0 to the watchdog status bit.
1444 */
1445 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1446 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1447}
1448
1449void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1450{
1451 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 1452 u32 status;
aea702b7
LR		 1453
1454 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1455 return;
1456
1457 status = ah->bb_watchdog_last_status;
d2182b69 1458 ath_dbg(common, RESET,
226afe68 1459 "\n==== BB update: BB status=0x%08x ====\n", status);
d2182b69 1460 ath_dbg(common, RESET,
226afe68
JP		 1461 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1462 MS(status, AR_PHY_WATCHDOG_INFO),
1463 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1464 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1465 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1466 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1467 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1468 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1469 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1470 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1471
d2182b69 1472 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
226afe68
JP		 1473 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1474 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
d2182b69 1475 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
226afe68 1476 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 1477
b5bfc568
FF		 1478#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1479 if (common->cc_survey.cycles)
d2182b69 1480 ath_dbg(common, RESET,
226afe68
JP		 1481 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1482 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 1483
d2182b69 1484 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
aea702b7
LR		 1485}
1486EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 1487
1488void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1489{
1490 u32 val;
1491
1492 /* While receiving unsupported rate frame rx state machine
1493 * gets into a state 0xb and if phy_restart happens in that
1494 * state, BB would go hang. If RXSM is in 0xb state after
1495 * first bb panic, ensure to disable the phy_restart.
1496 */
1497 if (!((MS(ah->bb_watchdog_last_status,
1498 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1499 ah->bb_hang_rx_ofdm))
1500 return;
1501
1502 ah->bb_hang_rx_ofdm = true;
1503 val = REG_READ(ah, AR_PHY_RESTART);
1504 val &= ~AR_PHY_RESTART_ENA;
1505
1506 REG_WRITE(ah, AR_PHY_RESTART, val);
1507}
1508EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Linux kernel - Deliverables
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