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ath9k: Remove a couple of unused variables
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
ee40fa06 17#include <linux/export.h>
8525f280 18#include "hw.h"
da6f1d7f 19#include "ar9003_phy.h"
8525f280 20
e36b27af
LR		 21static const int firstep_table[] =
22/* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25static const int cycpwrThr1_table[] =
26/* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29/*
30 * register values to turn OFDM weak signal detection OFF
31 */
32static const int m1ThreshLow_off = 127;
33static const int m2ThreshLow_off = 127;
34static const int m1Thresh_off = 127;
35static const int m2Thresh_off = 127;
36static const int m2CountThr_off = 31;
37static const int m2CountThrLow_off = 63;
38static const int m1ThreshLowExt_off = 127;
39static const int m2ThreshLowExt_off = 127;
40static const int m1ThreshExt_off = 127;
41static const int m2ThreshExt_off = 127;
42
8525f280
LR		 43/**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
e4922f2b 49 * for AR9300 family of chipsets.
8525f280
LR		 50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69{
f7abf0c1
FF		 70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93
GJ		 79 if (AR_SREV_9330(ah)) {
80 u32 chan_frac;
81 u32 div;
82
83 if (ah->is_clk_25mhz)
84 div = 75;
85 else
86 div = 120;
87
88 channelSel = (freq * 4) / div;
89 chan_frac = (((freq * 4) % div) * 0x20000) / div;
90 channelSel = (channelSel << 17) | chan_frac;
a4a2954f 91 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 92 u32 chan_frac;
93
94 /*
95 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
96 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
97 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
98 */
99 channelSel = (freq * 4) / 120;
100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
101 channelSel = (channelSel << 17) | chan_frac;
db4a3de9 102 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
17869f4f
VT		 103 if (ah->is_clk_25mhz) {
104 u32 chan_frac;
105
106 channelSel = (freq * 2) / 75;
107 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
108 channelSel = (channelSel << 17) | chan_frac;
109 } else
110 channelSel = CHANSEL_2G(freq) >> 1;
3dfd7f60 111 } else
85dd0921 112 channelSel = CHANSEL_2G(freq);
f7abf0c1
FF		 113 /* Set to 2G mode */
114 bMode = 1;
115 } else {
db4a3de9
GJ		 116 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
117 ah->is_clk_25mhz) {
17869f4f
VT		 118 u32 chan_frac;
119
530275e5
FF		 120 channelSel = freq / 75;
121 chan_frac = ((freq % 75) * 0x20000) / 75;
17869f4f
VT		 122 channelSel = (channelSel << 17) | chan_frac;
123 } else {
124 channelSel = CHANSEL_5G(freq);
125 /* Doubler is ON, so, divide channelSel by 2. */
126 channelSel >>= 1;
127 }
f7abf0c1
FF		 128 /* Set to 5G mode */
129 bMode = 0;
130 }
131
132 /* Enable fractional mode for all channels */
133 fracMode = 1;
134 aModeRefSel = 0;
135 loadSynthChannel = 0;
136
137 reg32 = (bMode << 29);
138 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
139
140 /* Enable Long shift Select for Synthesizer */
141 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
142 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
143
144 /* Program Synth. setting */
145 reg32 = (channelSel << 2) | (fracMode << 30) |
146 (aModeRefSel << 28) | (loadSynthChannel << 31);
147 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
148
149 /* Toggle Load Synth channel bit */
150 loadSynthChannel = 1;
151 reg32 = (channelSel << 2) | (fracMode << 30) |
152 (aModeRefSel << 28) | (loadSynthChannel << 31);
153 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
154
155 ah->curchan = chan;
f7abf0c1 156
8525f280
LR		 157 return 0;
158}
159
160/**
e36b27af 161 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 162 * @ah: atheros hardware structure
163 * @chan:
164 *
165 * For single-chip solutions. Converts to baseband spur frequency given the
166 * input channel frequency and compute register settings below.
167 *
168 * Spur mitigation for MRC CCK
169 */
1547da37
LR		 170static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
171 struct ath9k_channel *chan)
8525f280 172{
07b2fa5a 173 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 174 int cur_bb_spur, negative = 0, cck_spur_freq;
175 int i;
d9a2545a 176 int range, max_spur_cnts, synth_freq;
4b5237cc 177 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
ca375554
FF		 178
179 /*
180 * Need to verify range +/- 10 MHz in control channel, otherwise spur
181 * is out-of-band and can be ignored.
182 */
183
8528f12e
GJ		 184 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
185 AR_SREV_9550(ah)) {
d9a2545a
VT		 186 if (spur_fbin_ptr[0] == 0) /* No spur */
187 return;
188 max_spur_cnts = 5;
189 if (IS_CHAN_HT40(chan)) {
190 range = 19;
191 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
192 AR_PHY_GC_DYN2040_PRI_CH) == 0)
193 synth_freq = chan->channel + 10;
194 else
195 synth_freq = chan->channel - 10;
196 } else {
197 range = 10;
198 synth_freq = chan->channel;
199 }
200 } else {
38df2f07 201 range = AR_SREV_9462(ah) ? 5 : 10;
d9a2545a
VT		 202 max_spur_cnts = 4;
203 synth_freq = chan->channel;
204 }
205
206 for (i = 0; i < max_spur_cnts; i++) {
38df2f07
RM		 207 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
208 continue;
d43d04a9 209
ca375554 210 negative = 0;
8528f12e
GJ		 211 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
212 AR_SREV_9550(ah))
8edb254c
GJ		 213 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
214 IS_CHAN_2GHZ(chan));
d9a2545a 215 else
8edb254c 216 cur_bb_spur = spur_freq[i];
ca375554 217
8edb254c 218 cur_bb_spur -= synth_freq;
ca375554
FF		 219 if (cur_bb_spur < 0) {
220 negative = 1;
221 cur_bb_spur = -cur_bb_spur;
222 }
d9a2545a 223 if (cur_bb_spur < range) {
ca375554
FF		 224 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
225
226 if (negative == 1)
227 cck_spur_freq = -cck_spur_freq;
228
229 cck_spur_freq = cck_spur_freq & 0xfffff;
230
231 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
232 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
233 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
234 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
235 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
236 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
237 0x2);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
240 0x1);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
243 cck_spur_freq);
244
245 return;
246 }
247 }
248
249 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
250 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
251 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
252 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
253 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
254 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 255}
256
1547da37
LR		 257/* Clean all spur register fields */
258static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
259{
260 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
261 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
262 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
263 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
264 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
265 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
266 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
267 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
268 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
269 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
270 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
271 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
272 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
273 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
274 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
275 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
276 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
277 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
278
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
281 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
282 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
283 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
284 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
285 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
286 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
287 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
288 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
289 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
290 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
291 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
292 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
293 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
294 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
295 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
296 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
297 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
298 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
299}
300
301static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
302 int freq_offset,
303 int spur_freq_sd,
304 int spur_delta_phase,
d43d04a9
SM		 305 int spur_subchannel_sd,
306 int range,
307 int synth_freq)
1547da37
LR		 308{
309 int mask_index = 0;
310
311 /* OFDM Spur mitigation */
312 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
313 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
314 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
315 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
316 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
317 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
318 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
319 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
320 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
321 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
d43d04a9
SM		 322
323 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
324 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
325 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
326
1547da37
LR		 327 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
328 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
329 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
330 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
331 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
332 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
333
334 if (REG_READ_FIELD(ah, AR_PHY_MODE,
335 AR_PHY_MODE_DYNAMIC) == 0x1)
336 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
337 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
338
339 mask_index = (freq_offset << 4) / 5;
340 if (mask_index < 0)
341 mask_index = mask_index - 1;
342
343 mask_index = mask_index & 0x7f;
344
345 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
346 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
347 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
348 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
349 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
350 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
352 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
353 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
354 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
355 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
356 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
358 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
361 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
362 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
363 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
364 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
365}
366
d43d04a9
SM		 367static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
368 int freq_offset)
369{
370 int mask_index = 0;
371
372 mask_index = (freq_offset << 4) / 5;
373 if (mask_index < 0)
374 mask_index = mask_index - 1;
375
376 mask_index = mask_index & 0x7f;
377
378 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
379 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
380 mask_index);
381
382 /* A == B */
383 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
384 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
385 mask_index);
386
387 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
388 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
389 mask_index);
390 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
391 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
392 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
393 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
394
395 /* A == B */
396 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
397 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
398}
399
1547da37
LR		 400static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
401 struct ath9k_channel *chan,
d43d04a9
SM		 402 int freq_offset,
403 int range,
404 int synth_freq)
1547da37
LR		 405{
406 int spur_freq_sd = 0;
407 int spur_subchannel_sd = 0;
408 int spur_delta_phase = 0;
409
410 if (IS_CHAN_HT40(chan)) {
411 if (freq_offset < 0) {
412 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
413 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
414 spur_subchannel_sd = 1;
415 else
416 spur_subchannel_sd = 0;
417
9d1ceac5 418 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
1547da37
LR		 419
420 } else {
421 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
422 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
423 spur_subchannel_sd = 0;
424 else
425 spur_subchannel_sd = 1;
426
9d1ceac5 427 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
1547da37
LR		 428
429 }
430
431 spur_delta_phase = (freq_offset << 17) / 5;
432
433 } else {
434 spur_subchannel_sd = 0;
435 spur_freq_sd = (freq_offset << 9) /11;
436 spur_delta_phase = (freq_offset << 18) / 5;
437 }
438
439 spur_freq_sd = spur_freq_sd & 0x3ff;
440 spur_delta_phase = spur_delta_phase & 0xfffff;
441
442 ar9003_hw_spur_ofdm(ah,
443 freq_offset,
444 spur_freq_sd,
445 spur_delta_phase,
d43d04a9
SM		 446 spur_subchannel_sd,
447 range, synth_freq);
1547da37
LR		 448}
449
450/* Spur mitigation for OFDM */
451static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
452 struct ath9k_channel *chan)
453{
454 int synth_freq;
455 int range = 10;
456 int freq_offset = 0;
457 int mode;
458 u8* spurChansPtr;
459 unsigned int i;
460 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
461
462 if (IS_CHAN_5GHZ(chan)) {
463 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
464 mode = 0;
465 }
466 else {
467 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
468 mode = 1;
469 }
470
471 if (spurChansPtr[0] == 0)
472 return; /* No spur in the mode */
473
474 if (IS_CHAN_HT40(chan)) {
475 range = 19;
476 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
477 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
478 synth_freq = chan->channel - 10;
479 else
480 synth_freq = chan->channel + 10;
481 } else {
482 range = 10;
483 synth_freq = chan->channel;
484 }
485
486 ar9003_hw_spur_ofdm_clear(ah);
487
0f8e94d2 488 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
8edb254c
GJ		 489 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
490 freq_offset -= synth_freq;
1547da37 491 if (abs(freq_offset) < range) {
d43d04a9
SM		 492 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
493 range, synth_freq);
494
495 if (AR_SREV_9565(ah) && (i < 4)) {
496 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
497 mode);
498 freq_offset -= synth_freq;
499 if (abs(freq_offset) < range)
500 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
501 }
502
1547da37
LR		 503 break;
504 }
505 }
506}
507
508static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
509 struct ath9k_channel *chan)
510{
d43d04a9
SM		 511 if (!AR_SREV_9565(ah))
512 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
1547da37
LR		 513 ar9003_hw_spur_mitigate_ofdm(ah, chan);
514}
515
8525f280
LR		 516static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
517 struct ath9k_channel *chan)
518{
317d3328
FF		 519 u32 pll;
520
521 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
522
523 if (chan && IS_CHAN_HALF_RATE(chan))
524 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
525 else if (chan && IS_CHAN_QUARTER_RATE(chan))
526 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
527
14bc1104 528 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 529
530 return pll;
8525f280
LR		 531}
532
533static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
534 struct ath9k_channel *chan)
535{
cffb5e49
LR		 536 u32 phymode;
537 u32 enableDacFifo = 0;
538
539 enableDacFifo =
540 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
541
542 /* Enable 11n HT, 20 MHz */
8ad38d22 543 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
cffb5e49
LR		 544 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
545
546 /* Configure baseband for dynamic 20/40 operation */
547 if (IS_CHAN_HT40(chan)) {
548 phymode |= AR_PHY_GC_DYN2040_EN;
549 /* Configure control (primary) channel at +-10MHz */
550 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
551 (chan->chanmode == CHANNEL_G_HT40PLUS))
552 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
553
554 }
555
556 /* make sure we preserve INI settings */
557 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
558 /* turn off Green Field detection for STA for now */
559 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
560
561 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
562
563 /* Configure MAC for 20/40 operation */
564 ath9k_hw_set11nmac2040(ah);
565
566 /* global transmit timeout (25 TUs default)*/
567 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
568 /* carrier sense timeout */
569 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 570}
571
572static void ar9003_hw_init_bb(struct ath_hw *ah,
573 struct ath9k_channel *chan)
574{
af914a9f
LR		 575 u32 synthDelay;
576
577 /*
578 * Wait for the frequency synth to settle (synth goes on
579 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
580 * Value is in 100ns increments.
581 */
582 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f
LR		 583
584 /* Activate the PHY (includes baseband activate + synthesizer on) */
585 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7c5adc8d 586 ath9k_hw_synth_delay(ah, chan, synthDelay);
8525f280
LR		 587}
588
56266bff 589static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
cffb5e49
LR		 590{
591 switch (rx) {
592 case 0x5:
593 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
594 AR_PHY_SWAP_ALT_CHAIN);
595 case 0x3:
596 case 0x1:
597 case 0x2:
598 case 0x7:
599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
601 break;
602 default:
603 break;
604 }
605
ea066d5a
MSS		 606 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
607 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
608 else
609 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
610
cffb5e49
LR		 611 if (tx == 0x5) {
612 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
613 AR_PHY_SWAP_ALT_CHAIN);
614 }
615}
616
617/*
618 * Override INI values with chip specific configuration.
619 */
620static void ar9003_hw_override_ini(struct ath_hw *ah)
621{
622 u32 val;
623
624 /*
625 * Set the RX_ABORT and RX_DIS and clear it only after
626 * RXE is set for MAC. This prevents frames with
627 * corrupted descriptor status.
628 */
629 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
630
631 /*
632 * For AR9280 and above, there is a new feature that allows
633 * Multicast search based on both MAC Address and Key ID. By default,
634 * this feature is enabled. But since the driver is not using this
635 * feature, we switch it off; otherwise multicast search based on
636 * MAC addr only will fail.
637 */
638 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
639 REG_WRITE(ah, AR_PCU_MISC_MODE2,
640 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
bf3f204b
FF		 641
642 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
643 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
cffb5e49
LR		 644}
645
646static void ar9003_hw_prog_ini(struct ath_hw *ah,
647 struct ar5416IniArray *iniArr,
648 int column)
649{
650 unsigned int i, regWrites = 0;
651
652 /* New INI format: Array may be undefined (pre, core, post arrays) */
653 if (!iniArr->ia_array)
654 return;
655
656 /*
657 * New INI format: Pre, core, and post arrays for a given subsystem
658 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
659 * the array is non-modal and force the column to 1.
660 */
661 if (column >= iniArr->ia_columns)
662 column = 1;
663
664 for (i = 0; i < iniArr->ia_rows; i++) {
665 u32 reg = INI_RA(iniArr, i, 0);
666 u32 val = INI_RA(iniArr, i, column);
667
7e68b746 668 REG_WRITE(ah, reg, val);
b2ccc507 669
cffb5e49
LR		 670 DO_DELAY(regWrites);
671 }
672}
673
8bc45c6b
GJ		 674static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
675 struct ath9k_channel *chan)
676{
677 int ret;
678
679 switch (chan->chanmode) {
680 case CHANNEL_A:
681 case CHANNEL_A_HT20:
682 if (chan->channel <= 5350)
683 ret = 1;
684 else if ((chan->channel > 5350) && (chan->channel <= 5600))
685 ret = 3;
686 else
687 ret = 5;
688 break;
689
690 case CHANNEL_A_HT40PLUS:
691 case CHANNEL_A_HT40MINUS:
692 if (chan->channel <= 5350)
693 ret = 2;
694 else if ((chan->channel > 5350) && (chan->channel <= 5600))
695 ret = 4;
696 else
697 ret = 6;
698 break;
699
700 case CHANNEL_G:
701 case CHANNEL_G_HT20:
702 case CHANNEL_B:
703 ret = 8;
704 break;
705
706 case CHANNEL_G_HT40PLUS:
707 case CHANNEL_G_HT40MINUS:
708 ret = 7;
709 break;
710
711 default:
712 ret = -EINVAL;
713 }
714
715 return ret;
716}
717
8525f280
LR		 718static int ar9003_hw_process_ini(struct ath_hw *ah,
719 struct ath9k_channel *chan)
720{
cffb5e49 721 unsigned int regWrites = 0, i;
0ff2b5c0 722 u32 modesIndex;
cffb5e49
LR		 723
724 switch (chan->chanmode) {
725 case CHANNEL_A:
726 case CHANNEL_A_HT20:
727 modesIndex = 1;
cffb5e49
LR		 728 break;
729 case CHANNEL_A_HT40PLUS:
730 case CHANNEL_A_HT40MINUS:
731 modesIndex = 2;
cffb5e49
LR		 732 break;
733 case CHANNEL_G:
734 case CHANNEL_G_HT20:
735 case CHANNEL_B:
736 modesIndex = 4;
cffb5e49
LR		 737 break;
738 case CHANNEL_G_HT40PLUS:
739 case CHANNEL_G_HT40MINUS:
740 modesIndex = 3;
cffb5e49
LR		 741 break;
742
743 default:
744 return -EINVAL;
745 }
746
747 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
748 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
749 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
750 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
751 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
423e38e8 752 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
2577c6e8
SB		 753 ar9003_hw_prog_ini(ah,
754 &ah->ini_radio_post_sys2ant,
755 modesIndex);
cffb5e49
LR		 756 }
757
758 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
8bc45c6b
GJ		 759 if (AR_SREV_9550(ah))
760 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
761 regWrites);
762
763 if (AR_SREV_9550(ah)) {
764 int modes_txgain_index;
765
766 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
767 if (modes_txgain_index < 0)
768 return -EINVAL;
769
770 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
771 regWrites);
772 } else {
773 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
774 }
cffb5e49
LR		 775
776 /*
777 * For 5GHz channels requiring Fast Clock, apply
778 * different modal values.
779 */
6b42e8d0 780 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 781 REG_WRITE_ARRAY(&ah->iniModesFastClock,
cffb5e49
LR		 782 modesIndex, regWrites);
783
c7d36f9f 784 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
d89baac8 785
9951c4d0
FF		 786 if (chan->channel == 2484)
787 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
788
a4a2954f 789 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
c8b6fbe1
RM		 790 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
791 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
792
5f0c04ea 793 ah->modes_index = modesIndex;
cffb5e49
LR		 794 ar9003_hw_override_ini(ah);
795 ar9003_hw_set_channel_regs(ah, chan);
796 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
64ea57d0 797 ath9k_hw_apply_txpower(ah, chan, false);
cffb5e49 798
a4a2954f 799 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
8ad74c4d 800 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
a4a2954f 801 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
8ad74c4d
RM		 802 ah->enabled_cals |= TX_IQ_CAL;
803 else
804 ah->enabled_cals &= ~TX_IQ_CAL;
805
806 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
807 ah->enabled_cals |= TX_CL_CAL;
808 else
809 ah->enabled_cals &= ~TX_CL_CAL;
810 }
811
cffb5e49 812 return 0;
8525f280
LR		 813}
814
815static void ar9003_hw_set_rfmode(struct ath_hw *ah,
816 struct ath9k_channel *chan)
817{
af914a9f
LR		 818 u32 rfMode = 0;
819
820 if (chan == NULL)
821 return;
822
823 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
824 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
825
6b42e8d0 826 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f 827 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
08685ce3
FF		 828 if (IS_CHAN_QUARTER_RATE(chan))
829 rfMode |= AR_PHY_MODE_QUARTER;
830 if (IS_CHAN_HALF_RATE(chan))
831 rfMode |= AR_PHY_MODE_HALF;
af914a9f 832
3e61d3f9
FF		 833 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
834 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
835 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
836
af914a9f 837 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 838}
839
840static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
841{
af914a9f 842 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 843}
844
845static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
846 struct ath9k_channel *chan)
847{
af914a9f
LR		 848 u32 coef_scaled, ds_coef_exp, ds_coef_man;
849 u32 clockMhzScaled = 0x64000000;
850 struct chan_centers centers;
851
852 /*
853 * half and quarter rate can divide the scaled clock by 2 or 4
854 * scale for selected channel bandwidth
855 */
856 if (IS_CHAN_HALF_RATE(chan))
857 clockMhzScaled = clockMhzScaled >> 1;
858 else if (IS_CHAN_QUARTER_RATE(chan))
859 clockMhzScaled = clockMhzScaled >> 2;
860
861 /*
862 * ALGO -> coef = 1e8/fcarrier*fclock/40;
863 * scaled coef to provide precision for this floating calculation
864 */
865 ath9k_hw_get_channel_centers(ah, chan, &centers);
866 coef_scaled = clockMhzScaled / centers.synth_center;
867
868 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
869 &ds_coef_exp);
870
871 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
872 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
873 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
874 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
875
876 /*
877 * For Short GI,
878 * scaled coeff is 9/10 that of normal coeff
879 */
880 coef_scaled = (9 * coef_scaled) / 10;
881
882 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
883 &ds_coef_exp);
884
885 /* for short gi */
886 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
887 AR_PHY_SGI_DSC_MAN, ds_coef_man);
888 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
889 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 890}
891
892static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
893{
af914a9f
LR		 894 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
895 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
896 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 897}
898
af914a9f
LR		 899/*
900 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
901 * Read the phy active delay register. Value is in 100ns increments.
902 */
8525f280
LR		 903static void ar9003_hw_rfbus_done(struct ath_hw *ah)
904{
af914a9f 905 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f 906
7c5adc8d 907 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
af914a9f
LR		 908
909 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 910}
911
c16fcb49
FF		 912static bool ar9003_hw_ani_control(struct ath_hw *ah,
913 enum ath9k_ani_cmd cmd, int param)
914{
af914a9f 915 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 916 struct ath9k_channel *chan = ah->curchan;
093115b7 917 struct ar5416AniState *aniState = &chan->ani;
e36b27af 918 s32 value, value2;
af914a9f
LR		 919
920 switch (cmd & ah->ani_function) {
af914a9f 921 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 922 /*
923 * on == 1 means ofdm weak signal detection is ON
924 * on == 1 is the default, for less noise immunity
925 *
926 * on == 0 means ofdm weak signal detection is OFF
927 * on == 0 means more noise imm
928 */
af914a9f 929 u32 on = param ? 1 : 0;
af914a9f
LR		 930
931 if (on)
932 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
933 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
934 else
935 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
936 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
937
7067e701 938 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 939 ath_dbg(common, ANI,
226afe68
JP		 940 "** ch %d: ofdm weak signal: %s=>%s\n",
941 chan->channel,
7067e701 942 aniState->ofdmWeakSigDetect ?
226afe68
JP		 943 "on" : "off",
944 on ? "on" : "off");
af914a9f
LR		 945 if (on)
946 ah->stats.ast_ani_ofdmon++;
947 else
948 ah->stats.ast_ani_ofdmoff++;
7067e701 949 aniState->ofdmWeakSigDetect = on;
af914a9f
LR		 950 }
951 break;
952 }
af914a9f 953 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 954 u32 level = param;
955
e36b27af 956 if (level >= ARRAY_SIZE(firstep_table)) {
d2182b69 957 ath_dbg(common, ANI,
226afe68
JP		 958 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
959 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 960 return false;
961 }
e36b27af
LR		 962
963 /*
964 * make register setting relative to default
965 * from INI file & cap value
966 */
967 value = firstep_table[level] -
465dce62 968 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 969 aniState->iniDef.firstep;
970 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
971 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
972 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
973 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 974 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
975 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 976 value);
977 /*
978 * we need to set first step low register too
979 * make register setting relative to default
980 * from INI file & cap value
981 */
982 value2 = firstep_table[level] -
465dce62 983 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 984 aniState->iniDef.firstepLow;
985 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
986 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
987 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
988 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
989
990 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
991 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
992
993 if (level != aniState->firstepLevel) {
d2182b69 994 ath_dbg(common, ANI,
226afe68
JP		 995 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
996 chan->channel,
997 aniState->firstepLevel,
998 level,
465dce62 999 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1000 value,
1001 aniState->iniDef.firstep);
d2182b69 1002 ath_dbg(common, ANI,
226afe68
JP		 1003 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1004 chan->channel,
1005 aniState->firstepLevel,
1006 level,
465dce62 1007 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1008 value2,
1009 aniState->iniDef.firstepLow);
e36b27af
LR		 1010 if (level > aniState->firstepLevel)
1011 ah->stats.ast_ani_stepup++;
1012 else if (level < aniState->firstepLevel)
1013 ah->stats.ast_ani_stepdown++;
1014 aniState->firstepLevel = level;
1015 }
af914a9f
LR		 1016 break;
1017 }
1018 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 1019 u32 level = param;
1020
e36b27af 1021 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
d2182b69 1022 ath_dbg(common, ANI,
226afe68
JP		 1023 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1024 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 1025 return false;
1026 }
e36b27af
LR		 1027 /*
1028 * make register setting relative to default
1029 * from INI file & cap value
1030 */
1031 value = cycpwrThr1_table[level] -
465dce62 1032 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1033 aniState->iniDef.cycpwrThr1;
1034 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1035 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1036 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1037 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 1038 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1039 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 1040 value);
1041
1042 /*
1043 * set AR_PHY_EXT_CCA for extension channel
1044 * make register setting relative to default
1045 * from INI file & cap value
1046 */
1047 value2 = cycpwrThr1_table[level] -
465dce62 1048 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1049 aniState->iniDef.cycpwrThr1Ext;
1050 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1051 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1052 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1053 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1054 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1055 AR_PHY_EXT_CYCPWR_THR1, value2);
1056
1057 if (level != aniState->spurImmunityLevel) {
d2182b69 1058 ath_dbg(common, ANI,
226afe68
JP		 1059 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1060 chan->channel,
1061 aniState->spurImmunityLevel,
1062 level,
465dce62 1063 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1064 value,
1065 aniState->iniDef.cycpwrThr1);
d2182b69 1066 ath_dbg(common, ANI,
226afe68
JP		 1067 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1068 chan->channel,
1069 aniState->spurImmunityLevel,
1070 level,
465dce62 1071 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1072 value2,
1073 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1074 if (level > aniState->spurImmunityLevel)
1075 ah->stats.ast_ani_spurup++;
1076 else if (level < aniState->spurImmunityLevel)
1077 ah->stats.ast_ani_spurdown++;
1078 aniState->spurImmunityLevel = level;
1079 }
af914a9f
LR		 1080 break;
1081 }
e36b27af
LR		 1082 case ATH9K_ANI_MRC_CCK:{
1083 /*
1084 * is_on == 1 means MRC CCK ON (default, less noise imm)
1085 * is_on == 0 means MRC CCK is OFF (more noise imm)
1086 */
1087 bool is_on = param ? 1 : 0;
1088 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1089 AR_PHY_MRC_CCK_ENABLE, is_on);
1090 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1091 AR_PHY_MRC_CCK_MUX_REG, is_on);
81b67fd6 1092 if (is_on != aniState->mrcCCK) {
d2182b69 1093 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
226afe68 1094 chan->channel,
81b67fd6 1095 aniState->mrcCCK ? "on" : "off",
226afe68 1096 is_on ? "on" : "off");
e36b27af
LR		 1097 if (is_on)
1098 ah->stats.ast_ani_ccklow++;
1099 else
1100 ah->stats.ast_ani_cckhigh++;
81b67fd6 1101 aniState->mrcCCK = is_on;
e36b27af
LR		 1102 }
1103 break;
1104 }
af914a9f
LR		 1105 case ATH9K_ANI_PRESENT:
1106 break;
1107 default:
d2182b69 1108 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1109 return false;
1110 }
1111
d2182b69 1112 ath_dbg(common, ANI,
226afe68
JP		 1113 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1114 aniState->spurImmunityLevel,
7067e701 1115 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1116 aniState->firstepLevel,
81b67fd6 1117 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1118 aniState->listenTime,
1119 aniState->ofdmPhyErrCount,
1120 aniState->cckPhyErrCount);
af914a9f 1121 return true;
c16fcb49
FF		 1122}
1123
641d9921
FF		 1124static void ar9003_hw_do_getnf(struct ath_hw *ah,
1125 int16_t nfarray[NUM_NF_READINGS])
1126{
b06af7a5
VT		 1127#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1128#define AR_PHY_CH_MINCCA_PWR_S 20
1129#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1130#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1131
b06af7a5
VT		 1132 int16_t nf;
1133 int i;
866b7780 1134
b06af7a5
VT		 1135 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1136 if (ah->rxchainmask & BIT(i)) {
1137 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1138 AR_PHY_CH_MINCCA_PWR);
1139 nfarray[i] = sign_extend32(nf, 8);
641d9921 1140
b06af7a5
VT		 1141 if (IS_CHAN_HT40(ah->curchan)) {
1142 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1143
b06af7a5
VT		 1144 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1145 AR_PHY_CH_EXT_MINCCA_PWR);
1146 nfarray[ext_idx] = sign_extend32(nf, 8);
1147 }
1148 }
1149 }
641d9921
FF		 1150}
1151
f2552e28 1152static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1153{
f2552e28
FF		 1154 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1155 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
ae245cde 1156 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1157 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1158 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1159 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
ae245cde
SM		 1160
1161 if (AR_SREV_9330(ah))
1162 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1163
a4a2954f 1164 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
ae245cde
SM		 1165 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1166 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1167 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1168 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1169 }
641d9921
FF		 1170}
1171
e36b27af
LR		 1172/*
1173 * Initialize the ANI register values with default (ini) values.
1174 * This routine is called during a (full) hardware reset after
1175 * all the registers are initialised from the INI.
1176 */
1177static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1178{
1179 struct ar5416AniState *aniState;
1180 struct ath_common *common = ath9k_hw_common(ah);
1181 struct ath9k_channel *chan = ah->curchan;
1182 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1183 u32 val;
1184
093115b7 1185 aniState = &ah->curchan->ani;
e36b27af
LR		 1186 iniDef = &aniState->iniDef;
1187
d2182b69 1188 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
226afe68
JP		 1189 ah->hw_version.macVersion,
1190 ah->hw_version.macRev,
1191 ah->opmode,
1192 chan->channel,
1193 chan->channelFlags);
e36b27af
LR		 1194
1195 val = REG_READ(ah, AR_PHY_SFCORR);
1196 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1197 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1198 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1199
1200 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1201 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1202 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1203 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1204
1205 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1206 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1207 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1208 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1209 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1210 iniDef->firstep = REG_READ_FIELD(ah,
1211 AR_PHY_FIND_SIG,
1212 AR_PHY_FIND_SIG_FIRSTEP);
1213 iniDef->firstepLow = REG_READ_FIELD(ah,
1214 AR_PHY_FIND_SIG_LOW,
1215 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1216 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1217 AR_PHY_TIMING5,
1218 AR_PHY_TIMING5_CYCPWR_THR1);
1219 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1220 AR_PHY_EXT_CCA,
1221 AR_PHY_EXT_CYCPWR_THR1);
1222
1223 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1224 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1225 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
7067e701 1226 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
81b67fd6 1227 aniState->mrcCCK = true;
e36b27af
LR		 1228}
1229
4e8c14e9
FF		 1230static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1231 struct ath_hw_radar_conf *conf)
1232{
1233 u32 radar_0 = 0, radar_1 = 0;
1234
1235 if (!conf) {
1236 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1237 return;
1238 }
1239
1240 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1241 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1242 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1243 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1244 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1245 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1246
1247 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1248 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1249 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1250 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1251 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1252
1253 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1254 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1255 if (conf->ext_channel)
1256 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1257 else
1258 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1259}
1260
c5d0855a
FF		 1261static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1262{
1263 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1264
1265 conf->fir_power = -28;
1266 conf->radar_rssi = 0;
1267 conf->pulse_height = 10;
1268 conf->pulse_rssi = 24;
1269 conf->pulse_inband = 8;
1270 conf->pulse_maxlen = 255;
1271 conf->pulse_inband_step = 12;
1272 conf->radar_inband = 8;
1273}
1274
6bcbc062 1275static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
9aa49ea3 1276 struct ath_hw_antcomb_conf *antconf)
6bcbc062
MSS		 1277{
1278 u32 regval;
1279
1280 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1281 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1282 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1283 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1284 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1285 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1286 AR_PHY_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1287
c4cf2c58
GJ		 1288 if (AR_SREV_9330_11(ah)) {
1289 antconf->lna1_lna2_delta = -9;
1290 antconf->div_group = 1;
1291 } else if (AR_SREV_9485(ah)) {
cd0ed1b5
GJ		 1292 antconf->lna1_lna2_delta = -9;
1293 antconf->div_group = 2;
1294 } else {
1295 antconf->lna1_lna2_delta = -3;
1296 antconf->div_group = 0;
1297 }
6bcbc062
MSS		 1298}
1299
1300static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1301 struct ath_hw_antcomb_conf *antconf)
1302{
1303 u32 regval;
1304
1305 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1306 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1307 AR_PHY_ANT_DIV_ALT_LNACONF |
1308 AR_PHY_ANT_FAST_DIV_BIAS |
1309 AR_PHY_ANT_DIV_MAIN_GAINTB |
1310 AR_PHY_ANT_DIV_ALT_GAINTB);
1311 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1312 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1313 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1314 & AR_PHY_ANT_DIV_ALT_LNACONF);
1315 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1316 & AR_PHY_ANT_FAST_DIV_BIAS);
1317 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1318 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1319 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1320 & AR_PHY_ANT_DIV_ALT_GAINTB);
6bcbc062
MSS		 1321
1322 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1323}
1324
5f0c04ea
RM		 1325static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1326 struct ath9k_channel *chan,
1327 u8 *ini_reloaded)
1328{
1329 unsigned int regWrites = 0;
1330 u32 modesIndex;
1331
1332 switch (chan->chanmode) {
1333 case CHANNEL_A:
1334 case CHANNEL_A_HT20:
1335 modesIndex = 1;
1336 break;
1337 case CHANNEL_A_HT40PLUS:
1338 case CHANNEL_A_HT40MINUS:
1339 modesIndex = 2;
1340 break;
1341 case CHANNEL_G:
1342 case CHANNEL_G_HT20:
1343 case CHANNEL_B:
1344 modesIndex = 4;
1345 break;
1346 case CHANNEL_G_HT40PLUS:
1347 case CHANNEL_G_HT40MINUS:
1348 modesIndex = 3;
1349 break;
1350
1351 default:
1352 return -EINVAL;
1353 }
1354
1355 if (modesIndex == ah->modes_index) {
1356 *ini_reloaded = false;
1357 goto set_rfmode;
1358 }
1359
1360 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1361 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1362 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1363 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
aaa53ee9 1364
423e38e8 1365 if (AR_SREV_9462_20(ah))
aaa53ee9
SM		 1366 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1367 modesIndex);
5f0c04ea
RM		 1368
1369 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1370
1371 /*
1372 * For 5GHz channels requiring Fast Clock, apply
1373 * different modal values.
1374 */
1375 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 1376 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
5f0c04ea 1377
aaa53ee9
SM		 1378 if (AR_SREV_9565(ah))
1379 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1380
c7d36f9f 1381 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
5f0c04ea
RM		 1382
1383 ah->modes_index = modesIndex;
1384 *ini_reloaded = true;
1385
1386set_rfmode:
1387 ar9003_hw_set_rfmode(ah, chan);
1388 return 0;
1389}
1390
8525f280
LR		 1391void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1392{
1393 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 1394 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 1395 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 1396 AR_PHY_CCA_0,
1397 AR_PHY_CCA_1,
1398 AR_PHY_CCA_2,
1399 AR_PHY_EXT_CCA,
1400 AR_PHY_EXT_CCA_1,
1401 AR_PHY_EXT_CCA_2,
1402 };
8525f280
LR		 1403
1404 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1405 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1406 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1407 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1408 priv_ops->init_bb = ar9003_hw_init_bb;
1409 priv_ops->process_ini = ar9003_hw_process_ini;
1410 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1411 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1412 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1413 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1414 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
c16fcb49 1415 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1416 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 1417 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 1418 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
5f0c04ea 1419 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
f2552e28 1420
6bcbc062
MSS		 1421 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1422 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1423
f2552e28 1424 ar9003_hw_set_nf_limits(ah);
c5d0855a 1425 ar9003_hw_set_radar_conf(ah);
bbacee13 1426 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 1427}
aea702b7
LR		 1428
1429void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1430{
1431 struct ath_common *common = ath9k_hw_common(ah);
1432 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1433 u32 val, idle_count;
1434
1435 if (!idle_tmo_ms) {
1436 /* disable IRQ, disable chip-reset for BB panic */
1437 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1438 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1439 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1440 AR_PHY_WATCHDOG_IRQ_ENABLE));
1441
1442 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1443 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1444 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1445 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1446 AR_PHY_WATCHDOG_IDLE_ENABLE));
1447
d2182b69 1448 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 1449 return;
1450 }
1451
1452 /* enable IRQ, disable chip-reset for BB watchdog */
1453 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1454 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1455 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1456 ~AR_PHY_WATCHDOG_RST_ENABLE);
1457
1458 /* bound limit to 10 secs */
1459 if (idle_tmo_ms > 10000)
1460 idle_tmo_ms = 10000;
1461
1462 /*
1463 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1464 *
1465 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1466 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1467 *
1468 * Given we use fast clock now in 5 GHz, these time units should
1469 * be common for both 2 GHz and 5 GHz.
1470 */
1471 idle_count = (100 * idle_tmo_ms) / 74;
1472 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1473 idle_count = (100 * idle_tmo_ms) / 37;
1474
1475 /*
1476 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1477 * set idle time-out.
1478 */
1479 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1480 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1481 AR_PHY_WATCHDOG_IDLE_MASK |
1482 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1483
d2182b69 1484 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
226afe68 1485 idle_tmo_ms);
aea702b7
LR		 1486}
1487
1488void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1489{
1490 /*
1491 * we want to avoid printing in ISR context so we save the
1492 * watchdog status to be printed later in bottom half context.
1493 */
1494 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1495
1496 /*
1497 * the watchdog timer should reset on status read but to be sure
1498 * sure we write 0 to the watchdog status bit.
1499 */
1500 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1501 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1502}
1503
1504void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1505{
1506 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 1507 u32 status;
aea702b7
LR		 1508
1509 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1510 return;
1511
1512 status = ah->bb_watchdog_last_status;
d2182b69 1513 ath_dbg(common, RESET,
226afe68 1514 "\n==== BB update: BB status=0x%08x ====\n", status);
d2182b69 1515 ath_dbg(common, RESET,
226afe68
JP		 1516 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1517 MS(status, AR_PHY_WATCHDOG_INFO),
1518 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1519 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1520 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1521 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1522 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1523 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1524 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1525 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1526
d2182b69 1527 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
226afe68
JP		 1528 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1529 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
d2182b69 1530 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
226afe68 1531 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 1532
b5bfc568
FF		 1533#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1534 if (common->cc_survey.cycles)
d2182b69 1535 ath_dbg(common, RESET,
226afe68
JP		 1536 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1537 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 1538
d2182b69 1539 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
aea702b7
LR		 1540}
1541EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 1542
1543void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1544{
1545 u32 val;
1546
1547 /* While receiving unsupported rate frame rx state machine
1548 * gets into a state 0xb and if phy_restart happens in that
1549 * state, BB would go hang. If RXSM is in 0xb state after
1550 * first bb panic, ensure to disable the phy_restart.
1551 */
1552 if (!((MS(ah->bb_watchdog_last_status,
1553 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1554 ah->bb_hang_rx_ofdm))
1555 return;
1556
1557 ah->bb_hang_rx_ofdm = true;
1558 val = REG_READ(ah, AR_PHY_RESTART);
1559 val &= ~AR_PHY_RESTART_ENA;
1560
1561 REG_WRITE(ah, AR_PHY_RESTART, val);
1562}
1563EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Linux kernel - Deliverables
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