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ath9k_hw: Updated AR9003 tx gain table for 5GHz
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
da6f1d7f 18#include "ar9003_phy.h"
8525f280 19
e36b27af
LR		 20static const int firstep_table[] =
21/* level: 0 1 2 3 4 5 6 7 8 */
22 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
23
24static const int cycpwrThr1_table[] =
25/* level: 0 1 2 3 4 5 6 7 8 */
26 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
27
28/*
29 * register values to turn OFDM weak signal detection OFF
30 */
31static const int m1ThreshLow_off = 127;
32static const int m2ThreshLow_off = 127;
33static const int m1Thresh_off = 127;
34static const int m2Thresh_off = 127;
35static const int m2CountThr_off = 31;
36static const int m2CountThrLow_off = 63;
37static const int m1ThreshLowExt_off = 127;
38static const int m2ThreshLowExt_off = 127;
39static const int m1ThreshExt_off = 127;
40static const int m2ThreshExt_off = 127;
41
8525f280
LR		 42/**
43 * ar9003_hw_set_channel - set channel on single-chip device
44 * @ah: atheros hardware structure
45 * @chan:
46 *
47 * This is the function to change channel on single-chip devices, that is
48 * all devices after ar9280.
49 *
50 * This function takes the channel value in MHz and sets
51 * hardware channel value. Assumes writes have been enabled to analog bus.
52 *
53 * Actual Expression,
54 *
55 * For 2GHz channel,
56 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
57 * (freq_ref = 40MHz)
58 *
59 * For 5GHz channel,
60 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
61 * (freq_ref = 40MHz/(24>>amodeRefSel))
62 *
63 * For 5GHz channels which are 5MHz spaced,
64 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65 * (freq_ref = 40MHz)
66 */
67static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68{
f7abf0c1
FF		 69 u16 bMode, fracMode = 0, aModeRefSel = 0;
70 u32 freq, channelSel = 0, reg32 = 0;
71 struct chan_centers centers;
72 int loadSynthChannel;
73
74 ath9k_hw_get_channel_centers(ah, chan, &centers);
75 freq = centers.synth_center;
76
77 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93
GJ		 78 if (AR_SREV_9330(ah)) {
79 u32 chan_frac;
80 u32 div;
81
82 if (ah->is_clk_25mhz)
83 div = 75;
84 else
85 div = 120;
86
87 channelSel = (freq * 4) / div;
88 chan_frac = (((freq * 4) % div) * 0x20000) / div;
89 channelSel = (channelSel << 17) | chan_frac;
90 } else if (AR_SREV_9485(ah)) {
3dfd7f60
VT		 91 u32 chan_frac;
92
93 /*
94 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
95 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
96 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
97 */
98 channelSel = (freq * 4) / 120;
99 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
100 channelSel = (channelSel << 17) | chan_frac;
17869f4f
VT		 101 } else if (AR_SREV_9340(ah)) {
102 if (ah->is_clk_25mhz) {
103 u32 chan_frac;
104
105 channelSel = (freq * 2) / 75;
106 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
107 channelSel = (channelSel << 17) | chan_frac;
108 } else
109 channelSel = CHANSEL_2G(freq) >> 1;
3dfd7f60 110 } else
85dd0921 111 channelSel = CHANSEL_2G(freq);
f7abf0c1
FF		 112 /* Set to 2G mode */
113 bMode = 1;
114 } else {
17869f4f
VT		 115 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
116 u32 chan_frac;
117
118 channelSel = (freq * 2) / 75;
dbb204e3 119 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
17869f4f
VT		 120 channelSel = (channelSel << 17) | chan_frac;
121 } else {
122 channelSel = CHANSEL_5G(freq);
123 /* Doubler is ON, so, divide channelSel by 2. */
124 channelSel >>= 1;
125 }
f7abf0c1
FF		 126 /* Set to 5G mode */
127 bMode = 0;
128 }
129
130 /* Enable fractional mode for all channels */
131 fracMode = 1;
132 aModeRefSel = 0;
133 loadSynthChannel = 0;
134
135 reg32 = (bMode << 29);
136 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
137
138 /* Enable Long shift Select for Synthesizer */
139 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
140 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
141
142 /* Program Synth. setting */
143 reg32 = (channelSel << 2) | (fracMode << 30) |
144 (aModeRefSel << 28) | (loadSynthChannel << 31);
145 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
146
147 /* Toggle Load Synth channel bit */
148 loadSynthChannel = 1;
149 reg32 = (channelSel << 2) | (fracMode << 30) |
150 (aModeRefSel << 28) | (loadSynthChannel << 31);
151 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
152
153 ah->curchan = chan;
154 ah->curchan_rad_index = -1;
155
8525f280
LR		 156 return 0;
157}
158
159/**
e36b27af 160 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 161 * @ah: atheros hardware structure
162 * @chan:
163 *
164 * For single-chip solutions. Converts to baseband spur frequency given the
165 * input channel frequency and compute register settings below.
166 *
167 * Spur mitigation for MRC CCK
168 */
1547da37
LR		 169static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
170 struct ath9k_channel *chan)
8525f280 171{
07b2fa5a 172 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 173 int cur_bb_spur, negative = 0, cck_spur_freq;
174 int i;
d9a2545a
VT		 175 int range, max_spur_cnts, synth_freq;
176 u8 *spur_fbin_ptr = NULL;
ca375554
FF		 177
178 /*
179 * Need to verify range +/- 10 MHz in control channel, otherwise spur
180 * is out-of-band and can be ignored.
181 */
182
c1acfbe8 183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
d9a2545a
VT		 184 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
185 IS_CHAN_2GHZ(chan));
186 if (spur_fbin_ptr[0] == 0) /* No spur */
187 return;
188 max_spur_cnts = 5;
189 if (IS_CHAN_HT40(chan)) {
190 range = 19;
191 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
192 AR_PHY_GC_DYN2040_PRI_CH) == 0)
193 synth_freq = chan->channel + 10;
194 else
195 synth_freq = chan->channel - 10;
196 } else {
197 range = 10;
198 synth_freq = chan->channel;
199 }
200 } else {
201 range = 10;
202 max_spur_cnts = 4;
203 synth_freq = chan->channel;
204 }
205
206 for (i = 0; i < max_spur_cnts; i++) {
ca375554 207 negative = 0;
c1acfbe8 208 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
d9a2545a
VT		 209 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
210 IS_CHAN_2GHZ(chan)) - synth_freq;
211 else
212 cur_bb_spur = spur_freq[i] - synth_freq;
ca375554
FF		 213
214 if (cur_bb_spur < 0) {
215 negative = 1;
216 cur_bb_spur = -cur_bb_spur;
217 }
d9a2545a 218 if (cur_bb_spur < range) {
ca375554
FF		 219 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
220
221 if (negative == 1)
222 cck_spur_freq = -cck_spur_freq;
223
224 cck_spur_freq = cck_spur_freq & 0xfffff;
225
226 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
227 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
228 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
229 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
230 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
231 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
232 0x2);
233 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
234 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
235 0x1);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
238 cck_spur_freq);
239
240 return;
241 }
242 }
243
244 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
245 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
246 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
247 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
248 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
249 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 250}
251
1547da37
LR		 252/* Clean all spur register fields */
253static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
254{
255 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
256 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
257 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
258 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
259 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
260 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
261 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
262 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
263 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
264 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
268 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
270 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
271 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
272 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
273
274 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
275 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
276 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
277 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
278 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
279 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
280 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
281 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
283 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
284 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
285 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
286 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
287 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
288 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
289 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
293 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
294}
295
296static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
297 int freq_offset,
298 int spur_freq_sd,
299 int spur_delta_phase,
300 int spur_subchannel_sd)
301{
302 int mask_index = 0;
303
304 /* OFDM Spur mitigation */
305 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
306 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
307 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
308 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
309 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
310 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
311 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
312 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
313 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
314 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
315 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
316 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
318 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
319 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
320 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
321 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
322 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
323
324 if (REG_READ_FIELD(ah, AR_PHY_MODE,
325 AR_PHY_MODE_DYNAMIC) == 0x1)
326 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
327 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
328
329 mask_index = (freq_offset << 4) / 5;
330 if (mask_index < 0)
331 mask_index = mask_index - 1;
332
333 mask_index = mask_index & 0x7f;
334
335 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
336 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
337 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
338 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
339 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
340 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
341 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
342 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
343 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
344 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
345 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
346 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
347 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
348 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
349 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
350 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
351 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
352 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
353 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
354 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
355}
356
357static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
358 struct ath9k_channel *chan,
359 int freq_offset)
360{
361 int spur_freq_sd = 0;
362 int spur_subchannel_sd = 0;
363 int spur_delta_phase = 0;
364
365 if (IS_CHAN_HT40(chan)) {
366 if (freq_offset < 0) {
367 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
368 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
369 spur_subchannel_sd = 1;
370 else
371 spur_subchannel_sd = 0;
372
a844adfd 373 spur_freq_sd = (freq_offset << 9) / 11;
1547da37
LR		 374
375 } else {
376 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
377 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
378 spur_subchannel_sd = 0;
379 else
380 spur_subchannel_sd = 1;
381
a844adfd 382 spur_freq_sd = (freq_offset << 9) / 11;
1547da37
LR		 383
384 }
385
386 spur_delta_phase = (freq_offset << 17) / 5;
387
388 } else {
389 spur_subchannel_sd = 0;
390 spur_freq_sd = (freq_offset << 9) /11;
391 spur_delta_phase = (freq_offset << 18) / 5;
392 }
393
394 spur_freq_sd = spur_freq_sd & 0x3ff;
395 spur_delta_phase = spur_delta_phase & 0xfffff;
396
397 ar9003_hw_spur_ofdm(ah,
398 freq_offset,
399 spur_freq_sd,
400 spur_delta_phase,
401 spur_subchannel_sd);
402}
403
404/* Spur mitigation for OFDM */
405static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
406 struct ath9k_channel *chan)
407{
408 int synth_freq;
409 int range = 10;
410 int freq_offset = 0;
411 int mode;
412 u8* spurChansPtr;
413 unsigned int i;
414 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
415
416 if (IS_CHAN_5GHZ(chan)) {
417 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
418 mode = 0;
419 }
420 else {
421 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
422 mode = 1;
423 }
424
425 if (spurChansPtr[0] == 0)
426 return; /* No spur in the mode */
427
428 if (IS_CHAN_HT40(chan)) {
429 range = 19;
430 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
431 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
432 synth_freq = chan->channel - 10;
433 else
434 synth_freq = chan->channel + 10;
435 } else {
436 range = 10;
437 synth_freq = chan->channel;
438 }
439
440 ar9003_hw_spur_ofdm_clear(ah);
441
0f8e94d2 442 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
1547da37
LR		 443 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
444 if (abs(freq_offset) < range) {
445 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
446 break;
447 }
448 }
449}
450
451static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
452 struct ath9k_channel *chan)
453{
454 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
455 ar9003_hw_spur_mitigate_ofdm(ah, chan);
456}
457
8525f280
LR		 458static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
459 struct ath9k_channel *chan)
460{
317d3328
FF		 461 u32 pll;
462
463 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
464
465 if (chan && IS_CHAN_HALF_RATE(chan))
466 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
467 else if (chan && IS_CHAN_QUARTER_RATE(chan))
468 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
469
14bc1104 470 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 471
472 return pll;
8525f280
LR		 473}
474
475static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
476 struct ath9k_channel *chan)
477{
cffb5e49
LR		 478 u32 phymode;
479 u32 enableDacFifo = 0;
480
481 enableDacFifo =
482 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
483
484 /* Enable 11n HT, 20 MHz */
8ad38d22 485 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
cffb5e49
LR		 486 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
487
488 /* Configure baseband for dynamic 20/40 operation */
489 if (IS_CHAN_HT40(chan)) {
490 phymode |= AR_PHY_GC_DYN2040_EN;
491 /* Configure control (primary) channel at +-10MHz */
492 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
493 (chan->chanmode == CHANNEL_G_HT40PLUS))
494 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
495
496 }
497
498 /* make sure we preserve INI settings */
499 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
500 /* turn off Green Field detection for STA for now */
501 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
502
503 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
504
505 /* Configure MAC for 20/40 operation */
506 ath9k_hw_set11nmac2040(ah);
507
508 /* global transmit timeout (25 TUs default)*/
509 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
510 /* carrier sense timeout */
511 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 512}
513
514static void ar9003_hw_init_bb(struct ath_hw *ah,
515 struct ath9k_channel *chan)
516{
af914a9f
LR		 517 u32 synthDelay;
518
519 /*
520 * Wait for the frequency synth to settle (synth goes on
521 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
522 * Value is in 100ns increments.
523 */
524 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
525 if (IS_CHAN_B(chan))
526 synthDelay = (4 * synthDelay) / 22;
527 else
528 synthDelay /= 10;
529
530 /* Activate the PHY (includes baseband activate + synthesizer on) */
531 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
532
533 /*
534 * There is an issue if the AP starts the calibration before
535 * the base band timeout completes. This could result in the
536 * rx_clear false triggering. As a workaround we add delay an
537 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
538 * does not happen.
539 */
540 udelay(synthDelay + BASE_ACTIVATE_DELAY);
8525f280
LR		 541}
542
56266bff 543static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
cffb5e49
LR		 544{
545 switch (rx) {
546 case 0x5:
547 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
548 AR_PHY_SWAP_ALT_CHAIN);
549 case 0x3:
550 case 0x1:
551 case 0x2:
552 case 0x7:
553 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
554 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
555 break;
556 default:
557 break;
558 }
559
ea066d5a
MSS		 560 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
561 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
2577c6e8
SB		 562 else if (AR_SREV_9480(ah))
563 /* xxx only when MCI support is enabled */
564 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
ea066d5a
MSS		 565 else
566 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
567
cffb5e49
LR		 568 if (tx == 0x5) {
569 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
570 AR_PHY_SWAP_ALT_CHAIN);
571 }
572}
573
574/*
575 * Override INI values with chip specific configuration.
576 */
577static void ar9003_hw_override_ini(struct ath_hw *ah)
578{
579 u32 val;
580
581 /*
582 * Set the RX_ABORT and RX_DIS and clear it only after
583 * RXE is set for MAC. This prevents frames with
584 * corrupted descriptor status.
585 */
586 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
587
588 /*
589 * For AR9280 and above, there is a new feature that allows
590 * Multicast search based on both MAC Address and Key ID. By default,
591 * this feature is enabled. But since the driver is not using this
592 * feature, we switch it off; otherwise multicast search based on
593 * MAC addr only will fail.
594 */
595 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
596 REG_WRITE(ah, AR_PCU_MISC_MODE2,
597 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
bf3f204b
FF		 598
599 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
600 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
cffb5e49
LR		 601}
602
603static void ar9003_hw_prog_ini(struct ath_hw *ah,
604 struct ar5416IniArray *iniArr,
605 int column)
606{
607 unsigned int i, regWrites = 0;
608
609 /* New INI format: Array may be undefined (pre, core, post arrays) */
610 if (!iniArr->ia_array)
611 return;
612
613 /*
614 * New INI format: Pre, core, and post arrays for a given subsystem
615 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
616 * the array is non-modal and force the column to 1.
617 */
618 if (column >= iniArr->ia_columns)
619 column = 1;
620
621 for (i = 0; i < iniArr->ia_rows; i++) {
622 u32 reg = INI_RA(iniArr, i, 0);
623 u32 val = INI_RA(iniArr, i, column);
624
7e68b746 625 REG_WRITE(ah, reg, val);
b2ccc507 626
cffb5e49
LR		 627 DO_DELAY(regWrites);
628 }
629}
630
8525f280
LR		 631static int ar9003_hw_process_ini(struct ath_hw *ah,
632 struct ath9k_channel *chan)
633{
cffb5e49 634 unsigned int regWrites = 0, i;
0ff2b5c0 635 u32 modesIndex;
cffb5e49
LR		 636
637 switch (chan->chanmode) {
638 case CHANNEL_A:
639 case CHANNEL_A_HT20:
640 modesIndex = 1;
cffb5e49
LR		 641 break;
642 case CHANNEL_A_HT40PLUS:
643 case CHANNEL_A_HT40MINUS:
644 modesIndex = 2;
cffb5e49
LR		 645 break;
646 case CHANNEL_G:
647 case CHANNEL_G_HT20:
648 case CHANNEL_B:
649 modesIndex = 4;
cffb5e49
LR		 650 break;
651 case CHANNEL_G_HT40PLUS:
652 case CHANNEL_G_HT40MINUS:
653 modesIndex = 3;
cffb5e49
LR		 654 break;
655
656 default:
657 return -EINVAL;
658 }
659
660 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
661 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
662 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
663 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
664 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
2577c6e8
SB		 665 if (i == ATH_INI_POST && AR_SREV_9480_20(ah))
666 ar9003_hw_prog_ini(ah,
667 &ah->ini_radio_post_sys2ant,
668 modesIndex);
cffb5e49
LR		 669 }
670
671 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
672 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
673
674 /*
675 * For 5GHz channels requiring Fast Clock, apply
676 * different modal values.
677 */
6b42e8d0 678 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
cffb5e49
LR		 679 REG_WRITE_ARRAY(&ah->iniModesAdditional,
680 modesIndex, regWrites);
681
1c1bdd32 682 if (AR_SREV_9330(ah))
172805ad
GJ		 683 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
684
d89baac8
VT		 685 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
686 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
687
2577c6e8
SB		 688 if (AR_SREV_9480(ah))
689 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
690
cffb5e49
LR		 691 ar9003_hw_override_ini(ah);
692 ar9003_hw_set_channel_regs(ah, chan);
693 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
ca2c68cc 694 ath9k_hw_apply_txpower(ah, chan);
cffb5e49
LR		 695
696 return 0;
8525f280
LR		 697}
698
699static void ar9003_hw_set_rfmode(struct ath_hw *ah,
700 struct ath9k_channel *chan)
701{
af914a9f
LR		 702 u32 rfMode = 0;
703
704 if (chan == NULL)
705 return;
706
707 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
708 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
709
6b42e8d0 710 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f
LR		 711 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
712
713 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 714}
715
716static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
717{
af914a9f 718 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 719}
720
721static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
722 struct ath9k_channel *chan)
723{
af914a9f
LR		 724 u32 coef_scaled, ds_coef_exp, ds_coef_man;
725 u32 clockMhzScaled = 0x64000000;
726 struct chan_centers centers;
727
728 /*
729 * half and quarter rate can divide the scaled clock by 2 or 4
730 * scale for selected channel bandwidth
731 */
732 if (IS_CHAN_HALF_RATE(chan))
733 clockMhzScaled = clockMhzScaled >> 1;
734 else if (IS_CHAN_QUARTER_RATE(chan))
735 clockMhzScaled = clockMhzScaled >> 2;
736
737 /*
738 * ALGO -> coef = 1e8/fcarrier*fclock/40;
739 * scaled coef to provide precision for this floating calculation
740 */
741 ath9k_hw_get_channel_centers(ah, chan, &centers);
742 coef_scaled = clockMhzScaled / centers.synth_center;
743
744 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
745 &ds_coef_exp);
746
747 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
748 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
749 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
750 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
751
752 /*
753 * For Short GI,
754 * scaled coeff is 9/10 that of normal coeff
755 */
756 coef_scaled = (9 * coef_scaled) / 10;
757
758 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
759 &ds_coef_exp);
760
761 /* for short gi */
762 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
763 AR_PHY_SGI_DSC_MAN, ds_coef_man);
764 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
765 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 766}
767
768static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
769{
af914a9f
LR		 770 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
771 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
772 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 773}
774
af914a9f
LR		 775/*
776 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
777 * Read the phy active delay register. Value is in 100ns increments.
778 */
8525f280
LR		 779static void ar9003_hw_rfbus_done(struct ath_hw *ah)
780{
af914a9f
LR		 781 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
782 if (IS_CHAN_B(ah->curchan))
783 synthDelay = (4 * synthDelay) / 22;
784 else
785 synthDelay /= 10;
786
787 udelay(synthDelay + BASE_ACTIVATE_DELAY);
788
789 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 790}
791
c16fcb49
FF		 792static bool ar9003_hw_ani_control(struct ath_hw *ah,
793 enum ath9k_ani_cmd cmd, int param)
794{
af914a9f 795 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 796 struct ath9k_channel *chan = ah->curchan;
093115b7 797 struct ar5416AniState *aniState = &chan->ani;
e36b27af 798 s32 value, value2;
af914a9f
LR		 799
800 switch (cmd & ah->ani_function) {
af914a9f 801 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 802 /*
803 * on == 1 means ofdm weak signal detection is ON
804 * on == 1 is the default, for less noise immunity
805 *
806 * on == 0 means ofdm weak signal detection is OFF
807 * on == 0 means more noise imm
808 */
af914a9f 809 u32 on = param ? 1 : 0;
e36b27af
LR		 810 /*
811 * make register setting for default
812 * (weak sig detect ON) come from INI file
813 */
814 int m1ThreshLow = on ?
815 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
816 int m2ThreshLow = on ?
817 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
818 int m1Thresh = on ?
819 aniState->iniDef.m1Thresh : m1Thresh_off;
820 int m2Thresh = on ?
821 aniState->iniDef.m2Thresh : m2Thresh_off;
822 int m2CountThr = on ?
823 aniState->iniDef.m2CountThr : m2CountThr_off;
824 int m2CountThrLow = on ?
825 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
826 int m1ThreshLowExt = on ?
827 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
828 int m2ThreshLowExt = on ?
829 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
830 int m1ThreshExt = on ?
831 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
832 int m2ThreshExt = on ?
833 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
af914a9f
LR		 834
835 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
836 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
e36b27af 837 m1ThreshLow);
af914a9f
LR		 838 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
839 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
e36b27af 840 m2ThreshLow);
af914a9f 841 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 842 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
af914a9f 843 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 844 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
af914a9f 845 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 846 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
af914a9f
LR		 847 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
848 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
e36b27af 849 m2CountThrLow);
af914a9f
LR		 850
851 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 852 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
af914a9f 853 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 854 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
af914a9f 855 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 856 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
af914a9f 857 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 858 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
af914a9f
LR		 859
860 if (on)
861 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
862 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
863 else
864 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
865 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
866
867 if (!on != aniState->ofdmWeakSigDetectOff) {
226afe68
JP		 868 ath_dbg(common, ATH_DBG_ANI,
869 "** ch %d: ofdm weak signal: %s=>%s\n",
870 chan->channel,
871 !aniState->ofdmWeakSigDetectOff ?
872 "on" : "off",
873 on ? "on" : "off");
af914a9f
LR		 874 if (on)
875 ah->stats.ast_ani_ofdmon++;
876 else
877 ah->stats.ast_ani_ofdmoff++;
878 aniState->ofdmWeakSigDetectOff = !on;
879 }
880 break;
881 }
af914a9f 882 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 883 u32 level = param;
884
e36b27af 885 if (level >= ARRAY_SIZE(firstep_table)) {
226afe68
JP		 886 ath_dbg(common, ATH_DBG_ANI,
887 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
888 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 889 return false;
890 }
e36b27af
LR		 891
892 /*
893 * make register setting relative to default
894 * from INI file & cap value
895 */
896 value = firstep_table[level] -
897 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
898 aniState->iniDef.firstep;
899 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
900 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
901 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
902 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 903 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
904 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 905 value);
906 /*
907 * we need to set first step low register too
908 * make register setting relative to default
909 * from INI file & cap value
910 */
911 value2 = firstep_table[level] -
912 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
913 aniState->iniDef.firstepLow;
914 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
915 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
916 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
917 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
918
919 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
920 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
921
922 if (level != aniState->firstepLevel) {
226afe68
JP		 923 ath_dbg(common, ATH_DBG_ANI,
924 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
925 chan->channel,
926 aniState->firstepLevel,
927 level,
928 ATH9K_ANI_FIRSTEP_LVL_NEW,
929 value,
930 aniState->iniDef.firstep);
931 ath_dbg(common, ATH_DBG_ANI,
932 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
933 chan->channel,
934 aniState->firstepLevel,
935 level,
936 ATH9K_ANI_FIRSTEP_LVL_NEW,
937 value2,
938 aniState->iniDef.firstepLow);
e36b27af
LR		 939 if (level > aniState->firstepLevel)
940 ah->stats.ast_ani_stepup++;
941 else if (level < aniState->firstepLevel)
942 ah->stats.ast_ani_stepdown++;
943 aniState->firstepLevel = level;
944 }
af914a9f
LR		 945 break;
946 }
947 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 948 u32 level = param;
949
e36b27af 950 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
226afe68
JP		 951 ath_dbg(common, ATH_DBG_ANI,
952 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
953 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 954 return false;
955 }
e36b27af
LR		 956 /*
957 * make register setting relative to default
958 * from INI file & cap value
959 */
960 value = cycpwrThr1_table[level] -
961 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
962 aniState->iniDef.cycpwrThr1;
963 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
964 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
965 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
966 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 967 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
968 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 969 value);
970
971 /*
972 * set AR_PHY_EXT_CCA for extension channel
973 * make register setting relative to default
974 * from INI file & cap value
975 */
976 value2 = cycpwrThr1_table[level] -
977 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
978 aniState->iniDef.cycpwrThr1Ext;
979 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
980 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
981 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
982 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
983 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
984 AR_PHY_EXT_CYCPWR_THR1, value2);
985
986 if (level != aniState->spurImmunityLevel) {
226afe68
JP		 987 ath_dbg(common, ATH_DBG_ANI,
988 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
989 chan->channel,
990 aniState->spurImmunityLevel,
991 level,
992 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
993 value,
994 aniState->iniDef.cycpwrThr1);
995 ath_dbg(common, ATH_DBG_ANI,
996 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
997 chan->channel,
998 aniState->spurImmunityLevel,
999 level,
1000 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1001 value2,
1002 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1003 if (level > aniState->spurImmunityLevel)
1004 ah->stats.ast_ani_spurup++;
1005 else if (level < aniState->spurImmunityLevel)
1006 ah->stats.ast_ani_spurdown++;
1007 aniState->spurImmunityLevel = level;
1008 }
af914a9f
LR		 1009 break;
1010 }
e36b27af
LR		 1011 case ATH9K_ANI_MRC_CCK:{
1012 /*
1013 * is_on == 1 means MRC CCK ON (default, less noise imm)
1014 * is_on == 0 means MRC CCK is OFF (more noise imm)
1015 */
1016 bool is_on = param ? 1 : 0;
1017 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1018 AR_PHY_MRC_CCK_ENABLE, is_on);
1019 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1020 AR_PHY_MRC_CCK_MUX_REG, is_on);
1021 if (!is_on != aniState->mrcCCKOff) {
226afe68
JP		 1022 ath_dbg(common, ATH_DBG_ANI,
1023 "** ch %d: MRC CCK: %s=>%s\n",
1024 chan->channel,
1025 !aniState->mrcCCKOff ? "on" : "off",
1026 is_on ? "on" : "off");
e36b27af
LR		 1027 if (is_on)
1028 ah->stats.ast_ani_ccklow++;
1029 else
1030 ah->stats.ast_ani_cckhigh++;
1031 aniState->mrcCCKOff = !is_on;
1032 }
1033 break;
1034 }
af914a9f
LR		 1035 case ATH9K_ANI_PRESENT:
1036 break;
1037 default:
226afe68 1038 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1039 return false;
1040 }
1041
226afe68
JP		 1042 ath_dbg(common, ATH_DBG_ANI,
1043 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1044 aniState->spurImmunityLevel,
1045 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1046 aniState->firstepLevel,
1047 !aniState->mrcCCKOff ? "on" : "off",
1048 aniState->listenTime,
1049 aniState->ofdmPhyErrCount,
1050 aniState->cckPhyErrCount);
af914a9f 1051 return true;
c16fcb49
FF		 1052}
1053
641d9921
FF		 1054static void ar9003_hw_do_getnf(struct ath_hw *ah,
1055 int16_t nfarray[NUM_NF_READINGS])
1056{
b06af7a5
VT		 1057#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1058#define AR_PHY_CH_MINCCA_PWR_S 20
1059#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1060#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1061
b06af7a5
VT		 1062 int16_t nf;
1063 int i;
866b7780 1064
b06af7a5
VT		 1065 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1066 if (ah->rxchainmask & BIT(i)) {
1067 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1068 AR_PHY_CH_MINCCA_PWR);
1069 nfarray[i] = sign_extend32(nf, 8);
641d9921 1070
b06af7a5
VT		 1071 if (IS_CHAN_HT40(ah->curchan)) {
1072 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1073
b06af7a5
VT		 1074 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1075 AR_PHY_CH_EXT_MINCCA_PWR);
1076 nfarray[ext_idx] = sign_extend32(nf, 8);
1077 }
1078 }
1079 }
641d9921
FF		 1080}
1081
f2552e28 1082static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1083{
f2552e28
FF		 1084 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1085 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
0c453732
GJ		 1086 if (AR_SREV_9330(ah))
1087 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1088 else
1089 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1090 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1091 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1092 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
641d9921
FF		 1093}
1094
e36b27af
LR		 1095/*
1096 * Initialize the ANI register values with default (ini) values.
1097 * This routine is called during a (full) hardware reset after
1098 * all the registers are initialised from the INI.
1099 */
1100static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1101{
1102 struct ar5416AniState *aniState;
1103 struct ath_common *common = ath9k_hw_common(ah);
1104 struct ath9k_channel *chan = ah->curchan;
1105 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1106 u32 val;
1107
093115b7 1108 aniState = &ah->curchan->ani;
e36b27af
LR		 1109 iniDef = &aniState->iniDef;
1110
226afe68
JP		 1111 ath_dbg(common, ATH_DBG_ANI,
1112 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1113 ah->hw_version.macVersion,
1114 ah->hw_version.macRev,
1115 ah->opmode,
1116 chan->channel,
1117 chan->channelFlags);
e36b27af
LR		 1118
1119 val = REG_READ(ah, AR_PHY_SFCORR);
1120 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1121 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1122 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1123
1124 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1125 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1126 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1127 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1128
1129 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1130 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1131 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1132 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1133 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1134 iniDef->firstep = REG_READ_FIELD(ah,
1135 AR_PHY_FIND_SIG,
1136 AR_PHY_FIND_SIG_FIRSTEP);
1137 iniDef->firstepLow = REG_READ_FIELD(ah,
1138 AR_PHY_FIND_SIG_LOW,
1139 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1140 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1141 AR_PHY_TIMING5,
1142 AR_PHY_TIMING5_CYCPWR_THR1);
1143 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1144 AR_PHY_EXT_CCA,
1145 AR_PHY_EXT_CYCPWR_THR1);
1146
1147 /* these levels just got reset to defaults by the INI */
1148 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1149 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1150 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1151 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
e36b27af
LR		 1152}
1153
4e8c14e9
FF		 1154static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1155 struct ath_hw_radar_conf *conf)
1156{
1157 u32 radar_0 = 0, radar_1 = 0;
1158
1159 if (!conf) {
1160 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1161 return;
1162 }
1163
1164 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1165 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1166 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1167 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1168 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1169 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1170
1171 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1172 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1173 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1174 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1175 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1176
1177 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1178 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1179 if (conf->ext_channel)
1180 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1181 else
1182 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1183}
1184
c5d0855a
FF		 1185static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1186{
1187 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1188
1189 conf->fir_power = -28;
1190 conf->radar_rssi = 0;
1191 conf->pulse_height = 10;
1192 conf->pulse_rssi = 24;
1193 conf->pulse_inband = 8;
1194 conf->pulse_maxlen = 255;
1195 conf->pulse_inband_step = 12;
1196 conf->radar_inband = 8;
1197}
1198
6bcbc062
MSS		 1199static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1200 struct ath_hw_antcomb_conf *antconf)
1201{
1202 u32 regval;
1203
1204 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1205 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1206 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1207 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1208 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1209 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1210 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1211
c4cf2c58
GJ		 1212 if (AR_SREV_9330_11(ah)) {
1213 antconf->lna1_lna2_delta = -9;
1214 antconf->div_group = 1;
1215 } else if (AR_SREV_9485(ah)) {
cd0ed1b5
GJ		 1216 antconf->lna1_lna2_delta = -9;
1217 antconf->div_group = 2;
1218 } else {
1219 antconf->lna1_lna2_delta = -3;
1220 antconf->div_group = 0;
1221 }
6bcbc062
MSS		 1222}
1223
1224static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1225 struct ath_hw_antcomb_conf *antconf)
1226{
1227 u32 regval;
1228
1229 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1230 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1231 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1232 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1233 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1234 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1235 regval |= ((antconf->main_lna_conf <<
1236 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1237 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1238 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1239 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1240 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1241 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1242 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1243 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1244 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1245 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1246
1247 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1248}
1249
8525f280
LR		 1250void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1251{
1252 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 1253 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 1254 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 1255 AR_PHY_CCA_0,
1256 AR_PHY_CCA_1,
1257 AR_PHY_CCA_2,
1258 AR_PHY_EXT_CCA,
1259 AR_PHY_EXT_CCA_1,
1260 AR_PHY_EXT_CCA_2,
1261 };
8525f280
LR		 1262
1263 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1264 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1265 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1266 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1267 priv_ops->init_bb = ar9003_hw_init_bb;
1268 priv_ops->process_ini = ar9003_hw_process_ini;
1269 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1270 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1271 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1272 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1273 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
c16fcb49 1274 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1275 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 1276 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 1277 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
f2552e28 1278
6bcbc062
MSS		 1279 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1280 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1281
f2552e28 1282 ar9003_hw_set_nf_limits(ah);
c5d0855a 1283 ar9003_hw_set_radar_conf(ah);
bbacee13 1284 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 1285}
aea702b7
LR		 1286
1287void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1288{
1289 struct ath_common *common = ath9k_hw_common(ah);
1290 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1291 u32 val, idle_count;
1292
1293 if (!idle_tmo_ms) {
1294 /* disable IRQ, disable chip-reset for BB panic */
1295 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1296 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1297 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1298 AR_PHY_WATCHDOG_IRQ_ENABLE));
1299
1300 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1301 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1302 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1303 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1304 AR_PHY_WATCHDOG_IDLE_ENABLE));
1305
226afe68 1306 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 1307 return;
1308 }
1309
1310 /* enable IRQ, disable chip-reset for BB watchdog */
1311 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1312 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1313 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1314 ~AR_PHY_WATCHDOG_RST_ENABLE);
1315
1316 /* bound limit to 10 secs */
1317 if (idle_tmo_ms > 10000)
1318 idle_tmo_ms = 10000;
1319
1320 /*
1321 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1322 *
1323 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1324 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1325 *
1326 * Given we use fast clock now in 5 GHz, these time units should
1327 * be common for both 2 GHz and 5 GHz.
1328 */
1329 idle_count = (100 * idle_tmo_ms) / 74;
1330 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1331 idle_count = (100 * idle_tmo_ms) / 37;
1332
1333 /*
1334 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1335 * set idle time-out.
1336 */
1337 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1338 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1339 AR_PHY_WATCHDOG_IDLE_MASK |
1340 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1341
226afe68
JP		 1342 ath_dbg(common, ATH_DBG_RESET,
1343 "Enabled BB Watchdog timeout (%u ms)\n",
1344 idle_tmo_ms);
aea702b7
LR		 1345}
1346
1347void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1348{
1349 /*
1350 * we want to avoid printing in ISR context so we save the
1351 * watchdog status to be printed later in bottom half context.
1352 */
1353 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1354
1355 /*
1356 * the watchdog timer should reset on status read but to be sure
1357 * sure we write 0 to the watchdog status bit.
1358 */
1359 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1360 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1361}
1362
1363void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1364{
1365 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 1366 u32 status;
aea702b7
LR		 1367
1368 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1369 return;
1370
1371 status = ah->bb_watchdog_last_status;
226afe68
JP		 1372 ath_dbg(common, ATH_DBG_RESET,
1373 "\n==== BB update: BB status=0x%08x ====\n", status);
1374 ath_dbg(common, ATH_DBG_RESET,
1375 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1376 MS(status, AR_PHY_WATCHDOG_INFO),
1377 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1378 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1379 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1380 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1381 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1382 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1383 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1384 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1385
1386 ath_dbg(common, ATH_DBG_RESET,
1387 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1388 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1389 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1390 ath_dbg(common, ATH_DBG_RESET,
1391 "** BB mode: BB_gen_controls=0x%08x **\n",
1392 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 1393
b5bfc568
FF		 1394#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1395 if (common->cc_survey.cycles)
226afe68
JP		 1396 ath_dbg(common, ATH_DBG_RESET,
1397 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1398 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 1399
226afe68
JP		 1400 ath_dbg(common, ATH_DBG_RESET,
1401 "==== BB update: done ====\n\n");
aea702b7
LR		 1402}
1403EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 1404
1405void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1406{
1407 u32 val;
1408
1409 /* While receiving unsupported rate frame rx state machine
1410 * gets into a state 0xb and if phy_restart happens in that
1411 * state, BB would go hang. If RXSM is in 0xb state after
1412 * first bb panic, ensure to disable the phy_restart.
1413 */
1414 if (!((MS(ah->bb_watchdog_last_status,
1415 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1416 ah->bb_hang_rx_ofdm))
1417 return;
1418
1419 ah->bb_hang_rx_ofdm = true;
1420 val = REG_READ(ah, AR_PHY_RESTART);
1421 val &= ~AR_PHY_RESTART_ENA;
1422
1423 REG_WRITE(ah, AR_PHY_RESTART, val);
1424}
1425EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Linux kernel - Deliverables
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