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1 | /* |
2 | * Copyright (c) 2002-2010 Atheros Communications, Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef AR9003_PHY_H | |
18 | #define AR9003_PHY_H | |
19 | ||
20 | /* | |
21 | * Channel Register Map | |
22 | */ | |
23 | #define AR_CHAN_BASE 0x9800 | |
24 | ||
25 | #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0) | |
26 | #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4) | |
27 | #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8) | |
28 | #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc) | |
29 | #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10) | |
30 | #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14) | |
31 | #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18) | |
32 | #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c) | |
33 | #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc) | |
34 | #define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0) | |
35 | ||
36 | #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000 | |
37 | #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29 | |
38 | ||
39 | #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 | |
40 | #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31 | |
41 | ||
42 | #define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20) | |
43 | ||
44 | #define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24) | |
45 | #define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28) | |
46 | #define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c) | |
47 | ||
48 | #define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30) | |
49 | #define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34) | |
50 | #define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38) | |
51 | #define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c) | |
52 | #define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80) | |
53 | #define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84) | |
54 | ||
55 | #define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0) | |
56 | #define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4) | |
57 | #define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0) | |
58 | #define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4) | |
59 | #define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8) | |
60 | #define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc) | |
61 | ||
62 | /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */ | |
63 | #define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10) | |
64 | #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10) | |
65 | #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8) | |
66 | #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8) | |
67 | #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8) | |
68 | #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8) | |
69 | ||
70 | #define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0) | |
71 | #define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4) | |
72 | #define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8) | |
73 | #define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300) | |
74 | ||
75 | /* | |
76 | * Channel Field Definitions | |
77 | */ | |
78 | #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000 | |
79 | #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff | |
80 | #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 | |
81 | #define AR_PHY_TIMING3_DSC_MAN_S 17 | |
82 | #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 | |
83 | #define AR_PHY_TIMING3_DSC_EXP_S 13 | |
84 | #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000 | |
85 | #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12 | |
86 | #define AR_PHY_TIMING4_DO_CAL 0x10000 | |
87 | #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 | |
88 | #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 | |
89 | #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 | |
90 | #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 | |
91 | #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 | |
92 | #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 | |
93 | #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 | |
94 | #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 | |
95 | #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 | |
96 | #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F | |
97 | #define AR_PHY_SFCORR_M2COUNT_THR_S 0 | |
98 | #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 | |
99 | #define AR_PHY_SFCORR_M1_THRESH_S 17 | |
100 | #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 | |
101 | #define AR_PHY_SFCORR_M2_THRESH_S 24 | |
102 | #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F | |
103 | #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 | |
104 | #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 | |
105 | #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 | |
106 | #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 | |
107 | #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 | |
108 | #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 | |
109 | #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 | |
110 | #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 | |
111 | #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 | |
112 | #define AR_PHY_EXT_CCA_THRESH62_S 16 | |
113 | #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000 | |
114 | #define AR_PHY_EXT_MINCCA_PWR_S 16 | |
115 | #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE | |
116 | #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 | |
117 | #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 | |
118 | #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0 | |
119 | #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000 | |
120 | #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16 | |
121 | #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16) | |
122 | #define AR_PHY_TIMING5_RSSI_THR1A_S 16 | |
123 | #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15) | |
124 | #define AR_PHY_RADAR_0_ENA 0x00000001 | |
125 | #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 | |
126 | #define AR_PHY_RADAR_0_INBAND 0x0000003e | |
127 | #define AR_PHY_RADAR_0_INBAND_S 1 | |
128 | #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 | |
129 | #define AR_PHY_RADAR_0_PRSSI_S 6 | |
130 | #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 | |
131 | #define AR_PHY_RADAR_0_HEIGHT_S 12 | |
132 | #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 | |
133 | #define AR_PHY_RADAR_0_RRSSI_S 18 | |
134 | #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 | |
135 | #define AR_PHY_RADAR_0_FIRPWR_S 24 | |
136 | #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 | |
137 | #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 | |
138 | #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 | |
139 | #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 | |
140 | #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 | |
141 | #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 | |
142 | #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 | |
143 | #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 | |
144 | #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 | |
145 | #define AR_PHY_RADAR_1_MAXLEN 0x000000FF | |
146 | #define AR_PHY_RADAR_1_MAXLEN_S 0 | |
147 | #define AR_PHY_RADAR_EXT_ENA 0x00004000 | |
148 | #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000 | |
149 | #define AR_PHY_RADAR_DC_PWR_THRESH_S 15 | |
150 | #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000 | |
151 | #define AR_PHY_RADAR_LB_DC_CAP_S 23 | |
152 | #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6) | |
153 | #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6 | |
154 | #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12) | |
155 | #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12 | |
156 | #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19 | |
157 | #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f | |
158 | #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0 | |
159 | #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5 | |
160 | #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008 | |
161 | #define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3 | |
162 | #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F | |
163 | #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 | |
164 | #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80 | |
165 | #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7 | |
166 | #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 | |
167 | #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000 | |
168 | #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15 | |
169 | #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000 | |
170 | #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22 | |
171 | ||
172 | /* | |
173 | * MRC Register Map | |
174 | */ | |
175 | #define AR_MRC_BASE 0x9c00 | |
176 | ||
177 | #define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0) | |
178 | #define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4) | |
179 | #define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8) | |
180 | #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc) | |
181 | #define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10) | |
182 | #define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14) | |
183 | #define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18) | |
184 | #define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c) | |
185 | #define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20) | |
186 | ||
187 | /* | |
188 | * MRC Feild Definitions | |
189 | */ | |
190 | #define AR_PHY_SGI_DSC_MAN 0x0007FFF0 | |
191 | #define AR_PHY_SGI_DSC_MAN_S 4 | |
192 | #define AR_PHY_SGI_DSC_EXP 0x0000000F | |
193 | #define AR_PHY_SGI_DSC_EXP_S 0 | |
194 | /* | |
195 | * BBB Register Map | |
196 | */ | |
197 | #define AR_BBB_BASE 0x9d00 | |
198 | ||
199 | /* | |
200 | * AGC Register Map | |
201 | */ | |
202 | #define AR_AGC_BASE 0x9e00 | |
203 | ||
204 | #define AR_PHY_SETTLING (AR_AGC_BASE + 0x0) | |
205 | #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4) | |
206 | #define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8) | |
207 | #define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc) | |
208 | #define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10) | |
209 | #define AR_PHY_AGC (AR_AGC_BASE + 0x14) | |
210 | #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18) | |
211 | #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c) | |
212 | #define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20) | |
213 | #define AR_PHY_RESTART (AR_AGC_BASE + 0x24) | |
214 | #define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28) | |
215 | #define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c) | |
216 | #define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30) | |
217 | #define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34) | |
218 | #define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38) | |
219 | #define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c) | |
220 | #define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40) | |
221 | #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44) | |
222 | #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48) | |
223 | #define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180) | |
224 | #define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184) | |
225 | #define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0) | |
226 | #define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4) | |
227 | #define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8) | |
228 | ||
229 | #define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc) | |
230 | #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe | |
231 | #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 | |
232 | #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000 | |
233 | #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29 | |
234 | #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001 | |
235 | #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0 | |
236 | #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00 | |
237 | #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 | |
238 | ||
239 | #define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200) | |
240 | ||
241 | #define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110 | |
242 | #define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115 | |
243 | #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125 | |
244 | #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125 | |
245 | #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 | |
246 | #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 | |
247 | ||
248 | /* | |
249 | * AGC Field Definitions | |
250 | */ | |
251 | #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000 | |
252 | #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18 | |
253 | #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00 | |
254 | #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10 | |
255 | #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F | |
256 | #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0 | |
257 | #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000 | |
258 | #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17 | |
259 | #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000 | |
260 | #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12 | |
261 | #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0 | |
262 | #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6 | |
263 | #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F | |
264 | #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0 | |
265 | #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 | |
266 | #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 | |
267 | #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 | |
268 | #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 | |
269 | #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 | |
270 | #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 | |
271 | #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 | |
272 | #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 | |
273 | #define AR_PHY_SETTLING_SWITCH 0x00003F80 | |
274 | #define AR_PHY_SETTLING_SWITCH_S 7 | |
275 | #define AR_PHY_DESIRED_SZ_ADC 0x000000FF | |
276 | #define AR_PHY_DESIRED_SZ_ADC_S 0 | |
277 | #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 | |
278 | #define AR_PHY_DESIRED_SZ_PGA_S 8 | |
279 | #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 | |
280 | #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 | |
281 | #define AR_PHY_MINCCA_PWR 0x1FF00000 | |
282 | #define AR_PHY_MINCCA_PWR_S 20 | |
283 | #define AR_PHY_CCA_THRESH62 0x0007F000 | |
284 | #define AR_PHY_CCA_THRESH62_S 12 | |
285 | #define AR9280_PHY_MINCCA_PWR 0x1FF00000 | |
286 | #define AR9280_PHY_MINCCA_PWR_S 20 | |
287 | #define AR9280_PHY_CCA_THRESH62 0x000FF000 | |
288 | #define AR9280_PHY_CCA_THRESH62_S 12 | |
289 | #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF | |
290 | #define AR_PHY_EXT_CCA0_THRESH62_S 0 | |
291 | #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F | |
292 | #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 | |
293 | #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 | |
294 | #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 | |
295 | #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 | |
296 | ||
297 | #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 | |
298 | #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9 | |
299 | #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 | |
300 | #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 | |
301 | ||
302 | #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000 | |
303 | #define AR_PHY_AGC_COARSE_LOW 0x00007F80 | |
304 | #define AR_PHY_AGC_COARSE_LOW_S 7 | |
305 | #define AR_PHY_AGC_COARSE_HIGH 0x003F8000 | |
306 | #define AR_PHY_AGC_COARSE_HIGH_S 15 | |
307 | #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F | |
308 | #define AR_PHY_AGC_COARSE_PWR_CONST_S 0 | |
309 | #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 | |
310 | #define AR_PHY_FIND_SIG_FIRSTEP_S 12 | |
311 | #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 | |
312 | #define AR_PHY_FIND_SIG_FIRPWR_S 18 | |
313 | #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25 | |
314 | #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6) | |
315 | #define AR_PHY_FIND_SIG_RELPWR_S 6 | |
316 | #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11 | |
317 | #define AR_PHY_FIND_SIG_RELSTEP 0x1f | |
318 | #define AR_PHY_FIND_SIG_RELSTEP_S 0 | |
319 | #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5 | |
320 | #define AR_PHY_RESTART_DIV_GC 0x001C0000 | |
321 | #define AR_PHY_RESTART_DIV_GC_S 18 | |
322 | #define AR_PHY_RESTART_ENA 0x01 | |
323 | #define AR_PHY_DC_RESTART_DIS 0x40000000 | |
324 | ||
325 | #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000 | |
326 | #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24 | |
327 | #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000 | |
328 | #define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16 | |
329 | ||
330 | #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000 | |
331 | #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24 | |
332 | ||
333 | /* | |
334 | * SM Register Map | |
335 | */ | |
336 | #define AR_SM_BASE 0xa200 | |
337 | ||
338 | #define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0) | |
339 | #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4) | |
340 | #define AR_PHY_MODE (AR_SM_BASE + 0x8) | |
341 | #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc) | |
342 | #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20) | |
343 | #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24) | |
344 | #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28) | |
345 | #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c) | |
346 | #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30) | |
347 | #define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34) | |
348 | #define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38) | |
349 | #define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c) | |
350 | #define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40) | |
351 | #define AR_PHY_RIFS (AR_SM_BASE + 0x44) | |
352 | #define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50) | |
353 | #define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54) | |
354 | ||
355 | #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64) | |
356 | #define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80) | |
357 | #define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84) | |
358 | #define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88) | |
359 | #define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c) | |
360 | #define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0) | |
361 | #define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0) | |
da6f1d7f FF |
362 | #define AR_PHY_CALMODE (AR_SM_BASE + 0xc8) |
363 | #define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc) | |
364 | #define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0) | |
365 | #define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4) | |
366 | #define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8) | |
367 | #define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100) | |
368 | #define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140) | |
369 | #define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144) | |
370 | #define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148) | |
371 | #define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c) | |
372 | #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150) | |
373 | #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158) | |
374 | ||
375 | #define AR_PHY_TEST (AR_SM_BASE + 0x160) | |
376 | ||
377 | #define AR_PHY_TEST_BBB_OBS_SEL 0x780000 | |
378 | #define AR_PHY_TEST_BBB_OBS_SEL_S 19 | |
379 | ||
380 | #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23 | |
381 | #define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S) | |
382 | ||
383 | #define AR_PHY_TEST_CHAIN_SEL 0xC0000000 | |
384 | #define AR_PHY_TEST_CHAIN_SEL_S 30 | |
385 | ||
386 | #define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164) | |
387 | #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 | |
388 | #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 | |
389 | #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C | |
390 | #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2 | |
391 | #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60 | |
392 | #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5 | |
393 | #define AR_PHY_TEST_CTL_TSTADC_EN 0x100 | |
394 | #define AR_PHY_TEST_CTL_TSTADC_EN_S 8 | |
395 | #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00 | |
396 | #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 | |
397 | ||
398 | ||
399 | #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168) | |
400 | ||
401 | #define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c) | |
402 | #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170) | |
403 | #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174) | |
404 | #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178) | |
405 | #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c) | |
406 | #define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180) | |
407 | #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190) | |
408 | #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194) | |
409 | ||
410 | #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4) | |
411 | #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8) | |
412 | #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac) | |
413 | #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0) | |
414 | ||
415 | #define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0) | |
416 | #define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4) | |
417 | ||
418 | #define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204) | |
419 | #define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208) | |
420 | #define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c) | |
421 | #define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220) | |
422 | #define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c) | |
423 | #define AR_PHY_TPC_19 (AR_SM_BASE + 0x240) | |
424 | ||
425 | #define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258) | |
426 | ||
427 | #define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280) | |
428 | ||
429 | #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448) | |
430 | #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440) | |
431 | #define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c) | |
432 | #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450) | |
433 | ||
434 | #define AR_PHY_PANIC_WD_STATUS (AR_SM_BASE + 0x5c0) | |
435 | #define AR_PHY_PANIC_WD_CTL_1 (AR_SM_BASE + 0x5c4) | |
436 | #define AR_PHY_PANIC_WD_CTL_2 (AR_SM_BASE + 0x5c8) | |
437 | #define AR_PHY_BT_CTL (AR_SM_BASE + 0x5cc) | |
438 | #define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0) | |
439 | #define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4) | |
440 | #define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc) | |
441 | #define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248) | |
442 | ||
443 | #define AR_PHY_65NM_CH0_SYNTH4 0x1608c | |
444 | #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 | |
445 | #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1 | |
446 | #define AR_PHY_65NM_CH0_SYNTH7 0x16098 | |
447 | #define AR_PHY_65NM_CH0_BIAS1 0x160c0 | |
448 | #define AR_PHY_65NM_CH0_BIAS2 0x160c4 | |
449 | #define AR_PHY_65NM_CH0_BIAS4 0x160cc | |
450 | #define AR_PHY_65NM_CH0_RXTX4 0x1610c | |
451 | #define AR_PHY_65NM_CH0_THERM 0x16290 | |
452 | ||
453 | #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 | |
454 | #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 | |
455 | #define AR_PHY_65NM_CH0_THERM_START 0x20000000 | |
456 | #define AR_PHY_65NM_CH0_THERM_START_S 29 | |
457 | #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00 | |
458 | #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8 | |
459 | ||
460 | #define AR_PHY_65NM_CH0_RXTX1 0x16100 | |
461 | #define AR_PHY_65NM_CH0_RXTX2 0x16104 | |
462 | #define AR_PHY_65NM_CH1_RXTX1 0x16500 | |
463 | #define AR_PHY_65NM_CH1_RXTX2 0x16504 | |
464 | #define AR_PHY_65NM_CH2_RXTX1 0x16900 | |
465 | #define AR_PHY_65NM_CH2_RXTX2 0x16904 | |
466 | ||
467 | #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000 | |
468 | #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19 | |
469 | #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000 | |
470 | #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22 | |
471 | #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000 | |
472 | #define AR_PHY_LNAGAIN_LONG_SHIFT_S 29 | |
473 | #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000 | |
474 | #define AR_PHY_MXRGAIN_LONG_SHIFT_S 24 | |
475 | #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000 | |
476 | #define AR_PHY_VGAGAIN_LONG_SHIFT_S 26 | |
477 | #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001 | |
478 | #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0 | |
479 | #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002 | |
480 | #define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1 | |
481 | ||
482 | /* | |
483 | * SM Field Definitions | |
484 | */ | |
485 | #define AR_PHY_CL_CAL_ENABLE 0x00000002 | |
486 | #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 | |
487 | #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 | |
488 | #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 | |
489 | ||
490 | #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000 | |
491 | ||
492 | #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000 | |
493 | #define AR_PHY_FCAL20_CAP_STATUS_0_S 20 | |
494 | ||
495 | #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */ | |
496 | #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */ | |
497 | #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */ | |
498 | #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */ | |
499 | #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */ | |
500 | #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ | |
501 | #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ | |
502 | #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ | |
503 | #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */ | |
504 | #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ | |
505 | #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ | |
506 | #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ | |
507 | #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */ | |
508 | #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */ | |
509 | #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ | |
510 | ||
da6f1d7f FF |
511 | #define AR_PHY_CALMODE_IQ 0x00000000 |
512 | #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 | |
513 | #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 | |
514 | #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 | |
515 | #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 | |
516 | #define AR_PHY_MODE_OFDM 0x00000000 | |
517 | #define AR_PHY_MODE_CCK 0x00000001 | |
518 | #define AR_PHY_MODE_DYNAMIC 0x00000004 | |
519 | #define AR_PHY_MODE_HALF 0x00000020 | |
520 | #define AR_PHY_MODE_QUARTER 0x00000040 | |
521 | #define AR_PHY_MAC_CLK_MODE 0x00000080 | |
522 | #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 | |
523 | #define AR_PHY_MODE_SVD_HALF 0x00000200 | |
524 | #define AR_PHY_ACTIVE_EN 0x00000001 | |
525 | #define AR_PHY_ACTIVE_DIS 0x00000000 | |
526 | #define AR_PHY_FORCE_XPA_CFG 0x000000001 | |
527 | #define AR_PHY_FORCE_XPA_CFG_S 0 | |
528 | #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000 | |
529 | #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24 | |
530 | #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000 | |
531 | #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16 | |
532 | #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00 | |
533 | #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8 | |
534 | #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF | |
535 | #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0 | |
536 | #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 | |
537 | #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 | |
538 | #define AR_PHY_TX_END_DATA_START 0x000000FF | |
539 | #define AR_PHY_TX_END_DATA_START_S 0 | |
540 | #define AR_PHY_TX_END_PA_ON 0x0000FF00 | |
541 | #define AR_PHY_TX_END_PA_ON_S 8 | |
542 | #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F | |
543 | #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 | |
544 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 | |
545 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 | |
546 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 | |
547 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 | |
548 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 | |
549 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 | |
550 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 | |
551 | #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 | |
552 | #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 | |
553 | #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 | |
554 | #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 | |
555 | #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 | |
556 | #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 | |
557 | #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 | |
558 | #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 | |
559 | #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 | |
560 | #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e | |
561 | #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1 | |
562 | #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001 | |
563 | #define AR_PHY_TXGAIN_FORCE 0x00000001 | |
564 | #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00 | |
565 | #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10 | |
566 | #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000 | |
567 | #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14 | |
568 | #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000 | |
569 | #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22 | |
570 | #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0 | |
571 | #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6 | |
572 | #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e | |
573 | #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1 | |
574 | ||
575 | #define AR_PHY_POWER_TX_RATE1 0x9934 | |
576 | #define AR_PHY_POWER_TX_RATE2 0x9938 | |
577 | #define AR_PHY_POWER_TX_RATE_MAX 0x993c | |
578 | #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 | |
579 | #define PHY_AGC_CLR 0x10000000 | |
580 | #define RFSILENT_BB 0x00002000 | |
581 | #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF | |
582 | #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800 | |
583 | #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 | |
584 | #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 | |
585 | #define AR_PHY_RX_DELAY_DELAY 0x00003FFF | |
586 | #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 | |
587 | #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 | |
588 | #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0 | |
589 | #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 | |
590 | #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 | |
591 | #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 | |
592 | #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 | |
593 | #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 | |
594 | #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 | |
595 | #define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 | |
596 | #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 | |
597 | #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 | |
598 | #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 | |
599 | #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 | |
600 | #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000 | |
601 | #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 | |
602 | #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 | |
603 | #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0 | |
604 | ||
605 | #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 | |
606 | #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff | |
607 | #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0 | |
608 | ||
609 | #define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff | |
610 | #define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0 | |
611 | #define AR_PHY_TPC_19_ALPHA_THERM 0xff | |
612 | #define AR_PHY_TPC_19_ALPHA_THERM_S 0 | |
613 | ||
614 | #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 | |
615 | #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 | |
616 | ||
617 | #define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff | |
618 | #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0 | |
619 | ||
620 | /* | |
621 | * Channel 1 Register Map | |
622 | */ | |
623 | #define AR_CHAN1_BASE 0xa800 | |
624 | ||
625 | #define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30) | |
626 | #define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0) | |
627 | #define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4) | |
628 | ||
629 | #define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8) | |
630 | #define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300) | |
631 | #define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc) | |
632 | ||
633 | /* | |
634 | * Channel 1 Field Definitions | |
635 | */ | |
636 | #define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 | |
637 | #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16 | |
638 | ||
639 | /* | |
640 | * AGC 1 Register Map | |
641 | */ | |
642 | #define AR_AGC1_BASE 0xae00 | |
643 | ||
644 | #define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4) | |
645 | #define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18) | |
646 | #define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c) | |
647 | #define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20) | |
648 | #define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180) | |
649 | #define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184) | |
650 | #define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200) | |
651 | ||
652 | /* | |
653 | * AGC 1 Field Definitions | |
654 | */ | |
655 | #define AR_PHY_CH1_MINCCA_PWR 0x1FF00000 | |
656 | #define AR_PHY_CH1_MINCCA_PWR_S 20 | |
657 | ||
658 | /* | |
659 | * SM 1 Register Map | |
660 | */ | |
661 | #define AR_SM1_BASE 0xb200 | |
662 | ||
663 | #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84) | |
664 | #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0) | |
665 | #define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4) | |
666 | #define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100) | |
667 | #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180) | |
668 | #define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204) | |
669 | #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208) | |
670 | #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c) | |
671 | #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) | |
672 | #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240) | |
673 | #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c) | |
674 | #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 (AR_SM1_BASE + 0x450) | |
675 | ||
676 | /* | |
677 | * Channel 2 Register Map | |
678 | */ | |
679 | #define AR_CHAN2_BASE 0xb800 | |
680 | ||
681 | #define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30) | |
682 | #define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0) | |
683 | #define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4) | |
684 | ||
685 | #define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8) | |
686 | #define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300) | |
687 | #define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc) | |
688 | ||
689 | /* | |
690 | * Channel 2 Field Definitions | |
691 | */ | |
692 | #define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000 | |
693 | #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16 | |
694 | /* | |
695 | * AGC 2 Register Map | |
696 | */ | |
697 | #define AR_AGC2_BASE 0xbe00 | |
698 | ||
699 | #define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4) | |
700 | #define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18) | |
701 | #define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c) | |
702 | #define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20) | |
703 | #define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180) | |
704 | ||
705 | /* | |
706 | * AGC 2 Field Definitions | |
707 | */ | |
708 | #define AR_PHY_CH2_MINCCA_PWR 0x1FF00000 | |
709 | #define AR_PHY_CH2_MINCCA_PWR_S 20 | |
710 | ||
711 | /* | |
712 | * SM 2 Register Map | |
713 | */ | |
714 | #define AR_SM2_BASE 0xc200 | |
715 | ||
716 | #define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84) | |
717 | #define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0) | |
718 | #define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4) | |
719 | #define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100) | |
720 | #define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180) | |
721 | #define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204) | |
722 | #define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208) | |
723 | #define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c) | |
724 | #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220) | |
725 | #define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240) | |
726 | #define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c) | |
727 | #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 (AR_SM2_BASE + 0x450) | |
728 | ||
729 | #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001 | |
730 | ||
731 | /* | |
732 | * AGC 3 Register Map | |
733 | */ | |
734 | #define AR_AGC3_BASE 0xce00 | |
735 | ||
736 | #define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180) | |
737 | ||
738 | /* | |
739 | * Misc helper defines | |
740 | */ | |
741 | #define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE) | |
742 | ||
743 | #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
744 | #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
745 | #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
746 | #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
747 | ||
748 | #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
749 | #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
750 | #define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
751 | ||
752 | #define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
753 | #define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
754 | #define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
755 | #define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
756 | #define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
757 | #define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
758 | #define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
759 | #define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) | |
760 | ||
761 | #define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001 | |
762 | #define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002 | |
763 | #define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000 | |
764 | #define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC | |
765 | ||
766 | #define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002 | |
767 | #define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004 | |
768 | #define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9 | |
769 | ||
770 | #define AR_PHY_BB_WD_STATUS 0x00000007 | |
771 | #define AR_PHY_BB_WD_STATUS_S 0 | |
772 | #define AR_PHY_BB_WD_DET_HANG 0x00000008 | |
773 | #define AR_PHY_BB_WD_DET_HANG_S 3 | |
774 | #define AR_PHY_BB_WD_RADAR_SM 0x000000F0 | |
775 | #define AR_PHY_BB_WD_RADAR_SM_S 4 | |
776 | #define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00 | |
777 | #define AR_PHY_BB_WD_RX_OFDM_SM_S 8 | |
778 | #define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000 | |
779 | #define AR_PHY_BB_WD_RX_CCK_SM_S 12 | |
780 | #define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000 | |
781 | #define AR_PHY_BB_WD_TX_OFDM_SM_S 16 | |
782 | #define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000 | |
783 | #define AR_PHY_BB_WD_TX_CCK_SM_S 20 | |
784 | #define AR_PHY_BB_WD_AGC_SM 0x0F000000 | |
785 | #define AR_PHY_BB_WD_AGC_SM_S 24 | |
786 | #define AR_PHY_BB_WD_SRCH_SM 0xF0000000 | |
787 | #define AR_PHY_BB_WD_SRCH_SM_S 28 | |
788 | ||
789 | #define AR_PHY_BB_WD_STATUS_CLR 0x00000008 | |
790 | ||
cffb5e49 LR |
791 | void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); |
792 | ||
da6f1d7f | 793 | #endif /* AR9003_PHY_H */ |