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64875c63 MSS |
1 | /* |
2 | * Copyright (c) 2012 Qualcomm Atheros, Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/export.h> | |
18 | #include "ath9k.h" | |
19 | #include "reg.h" | |
ce6e982b | 20 | #include "reg_wow.h" |
64875c63 MSS |
21 | #include "hw-ops.h" |
22 | ||
64875c63 MSS |
23 | static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah) |
24 | { | |
25 | struct ath_common *common = ath9k_hw_common(ah); | |
26 | ||
27 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); | |
28 | ||
29 | /* set rx disable bit */ | |
30 | REG_WRITE(ah, AR_CR, AR_CR_RXD); | |
31 | ||
32 | if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) { | |
33 | ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", | |
34 | REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); | |
35 | return; | |
64875c63 MSS |
36 | } |
37 | ||
64875c63 MSS |
38 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); |
39 | } | |
40 | ||
41 | static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah) | |
42 | { | |
43 | struct ath_common *common = ath9k_hw_common(ah); | |
44 | u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN]; | |
45 | u32 ctl[13] = {0}; | |
46 | u32 data_word[KAL_NUM_DATA_WORDS]; | |
47 | u8 i; | |
48 | u32 wow_ka_data_word0; | |
49 | ||
50 | memcpy(sta_mac_addr, common->macaddr, ETH_ALEN); | |
51 | memcpy(ap_mac_addr, common->curbssid, ETH_ALEN); | |
52 | ||
53 | /* set the transmit buffer */ | |
54 | ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16)); | |
64875c63 MSS |
55 | ctl[1] = 0; |
56 | ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */ | |
57 | ctl[4] = 0; | |
58 | ctl[7] = (ah->txchainmask) << 2; | |
846e438f | 59 | ctl[2] = 0xf << 16; /* tx_tries 0 */ |
64875c63 MSS |
60 | |
61 | for (i = 0; i < KAL_NUM_DESC_WORDS; i++) | |
62 | REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); | |
63 | ||
846e438f | 64 | REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); |
64875c63 MSS |
65 | |
66 | data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) | | |
67 | (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16); | |
68 | data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) | | |
69 | (ap_mac_addr[1] << 8) | (ap_mac_addr[0]); | |
70 | data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) | | |
71 | (ap_mac_addr[5] << 8) | (ap_mac_addr[4]); | |
72 | data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) | | |
73 | (sta_mac_addr[3] << 8) | (sta_mac_addr[2]); | |
74 | data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) | | |
75 | (ap_mac_addr[1] << 8) | (ap_mac_addr[0]); | |
76 | data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]); | |
77 | ||
506ed95c | 78 | if (AR_SREV_9462_20(ah)) { |
64875c63 MSS |
79 | /* AR9462 2.0 has an extra descriptor word (time based |
80 | * discard) compared to other chips */ | |
81 | REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); | |
82 | wow_ka_data_word0 = AR_WOW_TXBUF(13); | |
83 | } else { | |
84 | wow_ka_data_word0 = AR_WOW_TXBUF(12); | |
85 | } | |
86 | ||
87 | for (i = 0; i < KAL_NUM_DATA_WORDS; i++) | |
88 | REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); | |
89 | ||
90 | } | |
91 | ||
6af75e4d SM |
92 | int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, |
93 | u8 *user_mask, int pattern_count, | |
94 | int pattern_len) | |
64875c63 MSS |
95 | { |
96 | int i; | |
97 | u32 pattern_val, mask_val; | |
98 | u32 set, clr; | |
99 | ||
6af75e4d SM |
100 | if (pattern_count >= ah->wow.max_patterns) |
101 | return -ENOSPC; | |
64875c63 | 102 | |
a28815db SM |
103 | if (pattern_count < MAX_NUM_PATTERN_LEGACY) |
104 | REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count)); | |
105 | else | |
106 | REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8)); | |
64875c63 | 107 | |
64875c63 MSS |
108 | for (i = 0; i < MAX_PATTERN_SIZE; i += 4) { |
109 | memcpy(&pattern_val, user_pattern, 4); | |
110 | REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), | |
111 | pattern_val); | |
112 | user_pattern += 4; | |
113 | } | |
114 | ||
64875c63 MSS |
115 | for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) { |
116 | memcpy(&mask_val, user_mask, 4); | |
117 | REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); | |
118 | user_mask += 4; | |
119 | } | |
120 | ||
a28815db SM |
121 | if (pattern_count < MAX_NUM_PATTERN_LEGACY) |
122 | ah->wow.wow_event_mask |= | |
123 | BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT); | |
124 | else | |
125 | ah->wow.wow_event_mask2 |= | |
126 | BIT((pattern_count - 8) + AR_WOW_PAT_FOUND_SHIFT); | |
64875c63 | 127 | |
64875c63 | 128 | if (pattern_count < 4) { |
64875c63 MSS |
129 | set = (pattern_len & AR_WOW_LENGTH_MAX) << |
130 | AR_WOW_LEN1_SHIFT(pattern_count); | |
131 | clr = AR_WOW_LENGTH1_MASK(pattern_count); | |
132 | REG_RMW(ah, AR_WOW_LENGTH1, set, clr); | |
a28815db | 133 | } else if (pattern_count < 8) { |
64875c63 MSS |
134 | set = (pattern_len & AR_WOW_LENGTH_MAX) << |
135 | AR_WOW_LEN2_SHIFT(pattern_count); | |
136 | clr = AR_WOW_LENGTH2_MASK(pattern_count); | |
137 | REG_RMW(ah, AR_WOW_LENGTH2, set, clr); | |
a28815db SM |
138 | } else if (pattern_count < 12) { |
139 | set = (pattern_len & AR_WOW_LENGTH_MAX) << | |
140 | AR_WOW_LEN3_SHIFT(pattern_count); | |
141 | clr = AR_WOW_LENGTH3_MASK(pattern_count); | |
142 | REG_RMW(ah, AR_WOW_LENGTH3, set, clr); | |
143 | } else if (pattern_count < MAX_NUM_PATTERN) { | |
144 | set = (pattern_len & AR_WOW_LENGTH_MAX) << | |
145 | AR_WOW_LEN4_SHIFT(pattern_count); | |
146 | clr = AR_WOW_LENGTH4_MASK(pattern_count); | |
147 | REG_RMW(ah, AR_WOW_LENGTH4, set, clr); | |
64875c63 MSS |
148 | } |
149 | ||
6af75e4d | 150 | return 0; |
64875c63 MSS |
151 | } |
152 | EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern); | |
153 | ||
154 | u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) | |
155 | { | |
156 | u32 wow_status = 0; | |
157 | u32 val = 0, rval; | |
846e438f | 158 | |
64875c63 MSS |
159 | /* |
160 | * read the WoW status register to know | |
161 | * the wakeup reason | |
162 | */ | |
163 | rval = REG_READ(ah, AR_WOW_PATTERN); | |
164 | val = AR_WOW_STATUS(rval); | |
165 | ||
166 | /* | |
167 | * mask only the WoW events that we have enabled. Sometimes | |
168 | * we have spurious WoW events from the AR_WOW_PATTERN | |
169 | * register. This mask will clean it up. | |
170 | */ | |
171 | ||
41fe8837 | 172 | val &= ah->wow.wow_event_mask; |
64875c63 MSS |
173 | |
174 | if (val) { | |
64875c63 MSS |
175 | if (val & AR_WOW_MAGIC_PAT_FOUND) |
176 | wow_status |= AH_WOW_MAGIC_PATTERN_EN; | |
64875c63 MSS |
177 | if (AR_WOW_PATTERN_FOUND(val)) |
178 | wow_status |= AH_WOW_USER_PATTERN_EN; | |
64875c63 MSS |
179 | if (val & AR_WOW_KEEP_ALIVE_FAIL) |
180 | wow_status |= AH_WOW_LINK_CHANGE; | |
64875c63 MSS |
181 | if (val & AR_WOW_BEACON_FAIL) |
182 | wow_status |= AH_WOW_BEACON_MISS; | |
64875c63 MSS |
183 | } |
184 | ||
185 | /* | |
186 | * set and clear WOW_PME_CLEAR registers for the chip to | |
187 | * generate next wow signal. | |
188 | * disable D3 before accessing other registers ? | |
189 | */ | |
190 | ||
191 | /* do we need to check the bit value 0x01000000 (7-10) ?? */ | |
192 | REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR, | |
193 | AR_PMCTRL_PWR_STATE_D1D3); | |
194 | ||
195 | /* | |
196 | * clear all events | |
197 | */ | |
198 | REG_WRITE(ah, AR_WOW_PATTERN, | |
199 | AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); | |
200 | ||
64875c63 MSS |
201 | /* |
202 | * restore the beacon threshold to init value | |
203 | */ | |
204 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); | |
205 | ||
206 | /* | |
207 | * Restore the way the PCI-E reset, Power-On-Reset, external | |
208 | * PCIE_POR_SHORT pins are tied to its original value. | |
209 | * Previously just before WoW sleep, we untie the PCI-E | |
210 | * reset to our Chip's Power On Reset so that any PCI-E | |
211 | * reset from the bus will not reset our chip | |
212 | */ | |
846e438f | 213 | if (ah->is_pciexpress) |
64875c63 MSS |
214 | ath9k_hw_configpcipowersave(ah, false); |
215 | ||
41fe8837 | 216 | ah->wow.wow_event_mask = 0; |
64875c63 MSS |
217 | |
218 | return wow_status; | |
219 | } | |
220 | EXPORT_SYMBOL(ath9k_hw_wow_wakeup); | |
221 | ||
b6f68b1e SM |
222 | static void ath9k_hw_wow_set_arwr_reg(struct ath_hw *ah) |
223 | { | |
224 | u32 wa_reg; | |
225 | ||
226 | if (!ah->is_pciexpress) | |
227 | return; | |
228 | ||
229 | /* | |
230 | * We need to untie the internal POR (power-on-reset) | |
231 | * to the external PCI-E reset. We also need to tie | |
232 | * the PCI-E Phy reset to the PCI-E reset. | |
233 | */ | |
234 | wa_reg = REG_READ(ah, AR_WA); | |
235 | wa_reg &= ~AR_WA_UNTIE_RESET_EN; | |
236 | wa_reg |= AR_WA_RESET_EN; | |
237 | wa_reg |= AR_WA_POR_SHORT; | |
238 | ||
239 | REG_WRITE(ah, AR_WA, wa_reg); | |
240 | } | |
241 | ||
64875c63 MSS |
242 | void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) |
243 | { | |
244 | u32 wow_event_mask; | |
bb631314 | 245 | u32 keep_alive, magic_pattern, host_pm_ctrl; |
64875c63 | 246 | |
41fe8837 | 247 | wow_event_mask = ah->wow.wow_event_mask; |
64875c63 | 248 | |
64875c63 | 249 | /* |
bb631314 SM |
250 | * AR_PMCTRL_HOST_PME_EN - Override PME enable in configuration |
251 | * space and allow MAC to generate WoW anyway. | |
252 | * | |
253 | * AR_PMCTRL_PWR_PM_CTRL_ENA - ??? | |
254 | * | |
255 | * AR_PMCTRL_AUX_PWR_DET - PCI core SYS_AUX_PWR_DET signal, | |
256 | * needs to be set for WoW in PCI mode. | |
257 | * | |
258 | * AR_PMCTRL_WOW_PME_CLR - WoW Clear Signal going to the MAC. | |
259 | * | |
260 | * Set the power states appropriately and enable PME. | |
261 | * | |
262 | * Set and clear WOW_PME_CLEAR for the chip | |
263 | * to generate next wow signal. | |
64875c63 | 264 | */ |
bb631314 SM |
265 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_HOST_PME_EN | |
266 | AR_PMCTRL_PWR_PM_CTRL_ENA | | |
267 | AR_PMCTRL_AUX_PWR_DET | | |
268 | AR_PMCTRL_WOW_PME_CLR); | |
269 | REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR); | |
64875c63 MSS |
270 | |
271 | /* | |
bb631314 SM |
272 | * Random Backoff. |
273 | * | |
274 | * 31:28 in AR_WOW_PATTERN : Indicates the number of bits used in the | |
275 | * contention window. For value N, | |
276 | * the random backoff will be selected between | |
277 | * 0 and (2 ^ N) - 1. | |
64875c63 | 278 | */ |
bb631314 SM |
279 | REG_SET_BIT(ah, AR_WOW_PATTERN, |
280 | AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF)); | |
64875c63 MSS |
281 | |
282 | /* | |
bb631314 | 283 | * AIFS time, Slot time, Keep Alive count. |
64875c63 | 284 | */ |
bb631314 SM |
285 | REG_SET_BIT(ah, AR_WOW_COUNT, AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) | |
286 | AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) | | |
287 | AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT)); | |
64875c63 | 288 | /* |
bb631314 | 289 | * Beacon timeout. |
64875c63 | 290 | */ |
64875c63 | 291 | if (pattern_enable & AH_WOW_BEACON_MISS) |
bb631314 | 292 | REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO); |
64875c63 | 293 | else |
bb631314 | 294 | REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO_MAX); |
64875c63 MSS |
295 | |
296 | /* | |
bb631314 | 297 | * Keep alive timeout in ms. |
64875c63 | 298 | */ |
846e438f | 299 | if (!pattern_enable) |
bb631314 | 300 | REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, AR_WOW_KEEP_ALIVE_NEVER); |
64875c63 | 301 | else |
bb631314 | 302 | REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, KAL_TIMEOUT * 32); |
64875c63 MSS |
303 | |
304 | /* | |
bb631314 | 305 | * Keep alive delay in us. |
64875c63 | 306 | */ |
bb631314 | 307 | REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, KAL_DELAY * 1000); |
64875c63 MSS |
308 | |
309 | /* | |
bb631314 | 310 | * Create keep alive pattern to respond to beacons. |
64875c63 MSS |
311 | */ |
312 | ath9k_wow_create_keep_alive_pattern(ah); | |
313 | ||
314 | /* | |
bb631314 | 315 | * Configure keep alive register. |
64875c63 | 316 | */ |
bb631314 SM |
317 | keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); |
318 | ||
64875c63 | 319 | /* Send keep alive timeouts anyway */ |
bb631314 | 320 | keep_alive &= ~AR_WOW_KEEP_ALIVE_AUTO_DIS; |
64875c63 | 321 | |
bb631314 SM |
322 | if (pattern_enable & AH_WOW_LINK_CHANGE) { |
323 | keep_alive &= ~AR_WOW_KEEP_ALIVE_FAIL_DIS; | |
64875c63 | 324 | wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL; |
bb631314 SM |
325 | } else { |
326 | keep_alive |= AR_WOW_KEEP_ALIVE_FAIL_DIS; | |
327 | } | |
64875c63 | 328 | |
bb631314 | 329 | REG_WRITE(ah, AR_WOW_KEEP_ALIVE, keep_alive); |
64875c63 | 330 | |
64875c63 | 331 | /* |
bb631314 SM |
332 | * We are relying on a bmiss failure, ensure we have |
333 | * enough threshold to prevent false positives. | |
64875c63 MSS |
334 | */ |
335 | REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, | |
336 | AR_WOW_BMISSTHRESHOLD); | |
337 | ||
64875c63 | 338 | if (pattern_enable & AH_WOW_BEACON_MISS) { |
64875c63 | 339 | wow_event_mask |= AR_WOW_BEACON_FAIL; |
bb631314 | 340 | REG_SET_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN); |
64875c63 | 341 | } else { |
bb631314 | 342 | REG_CLR_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN); |
64875c63 MSS |
343 | } |
344 | ||
64875c63 | 345 | /* |
bb631314 | 346 | * Enable the magic packet registers. |
64875c63 | 347 | */ |
bb631314 SM |
348 | magic_pattern = REG_READ(ah, AR_WOW_PATTERN); |
349 | magic_pattern |= AR_WOW_MAC_INTR_EN; | |
350 | ||
64875c63 | 351 | if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) { |
bb631314 | 352 | magic_pattern |= AR_WOW_MAGIC_EN; |
64875c63 MSS |
353 | wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND; |
354 | } else { | |
bb631314 | 355 | magic_pattern &= ~AR_WOW_MAGIC_EN; |
64875c63 | 356 | } |
64875c63 | 357 | |
bb631314 SM |
358 | REG_WRITE(ah, AR_WOW_PATTERN, magic_pattern); |
359 | ||
360 | /* | |
361 | * Enable pattern matching for packets which are less | |
362 | * than 256 bytes. | |
363 | */ | |
846e438f SM |
364 | REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B, |
365 | AR_WOW_PATTERN_SUPPORTED); | |
64875c63 MSS |
366 | |
367 | /* | |
bb631314 | 368 | * Set the power states appropriately and enable PME. |
64875c63 | 369 | */ |
bb631314 SM |
370 | host_pm_ctrl = REG_READ(ah, AR_PCIE_PM_CTRL); |
371 | host_pm_ctrl |= AR_PMCTRL_PWR_STATE_D1D3 | | |
372 | AR_PMCTRL_HOST_PME_EN | | |
373 | AR_PMCTRL_PWR_PM_CTRL_ENA; | |
374 | host_pm_ctrl &= ~AR_PCIE_PM_CTRL_ENA; | |
64875c63 | 375 | |
bb631314 SM |
376 | if (AR_SREV_9462(ah)) { |
377 | /* | |
378 | * This is needed to prevent the chip waking up | |
379 | * the host within 3-4 seconds with certain | |
380 | * platform/BIOS. | |
381 | */ | |
382 | host_pm_ctrl &= ~AR_PMCTRL_PWR_STATE_D1D3; | |
383 | host_pm_ctrl |= AR_PMCTRL_PWR_STATE_D1D3_REAL; | |
384 | } | |
385 | ||
386 | REG_WRITE(ah, AR_PCIE_PM_CTRL, host_pm_ctrl); | |
64875c63 | 387 | |
846e438f | 388 | /* |
bb631314 | 389 | * Enable sequence number generation when asleep. |
846e438f | 390 | */ |
64875c63 MSS |
391 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); |
392 | ||
bb631314 SM |
393 | /* To bring down WOW power low margin */ |
394 | REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13)); | |
395 | ||
b6f68b1e SM |
396 | ath9k_hw_wow_set_arwr_reg(ah); |
397 | ||
846e438f | 398 | /* HW WoW */ |
bb631314 | 399 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5)); |
64875c63 MSS |
400 | |
401 | ath9k_hw_set_powermode_wow_sleep(ah); | |
41fe8837 | 402 | ah->wow.wow_event_mask = wow_event_mask; |
64875c63 MSS |
403 | } |
404 | EXPORT_SYMBOL(ath9k_hw_wow_enable); |