Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
394cf0a1 | 22 | #include <linux/leds.h> |
394cf0a1 | 23 | |
394cf0a1 | 24 | #include "debug.h" |
db86f07e LR |
25 | #include "common.h" |
26 | ||
27 | /* | |
28 | * Header for the ath9k.ko driver core *only* -- hw code nor any other driver | |
29 | * should rely on this file or its contents. | |
30 | */ | |
394cf0a1 S |
31 | |
32 | struct ath_node; | |
33 | ||
34 | /* Macro to expand scalars to 64-bit objects */ | |
35 | ||
13bda122 | 36 | #define ito64(x) (sizeof(x) == 1) ? \ |
394cf0a1 | 37 | (((unsigned long long int)(x)) & (0xff)) : \ |
13bda122 | 38 | (sizeof(x) == 2) ? \ |
394cf0a1 | 39 | (((unsigned long long int)(x)) & 0xffff) : \ |
13bda122 | 40 | ((sizeof(x) == 4) ? \ |
394cf0a1 S |
41 | (((unsigned long long int)(x)) & 0xffffffff) : \ |
42 | (unsigned long long int)(x)) | |
43 | ||
44 | /* increment with wrap-around */ | |
45 | #define INCR(_l, _sz) do { \ | |
46 | (_l)++; \ | |
47 | (_l) &= ((_sz) - 1); \ | |
48 | } while (0) | |
49 | ||
50 | /* decrement with wrap-around */ | |
51 | #define DECR(_l, _sz) do { \ | |
52 | (_l)--; \ | |
53 | (_l) &= ((_sz) - 1); \ | |
54 | } while (0) | |
55 | ||
56 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
57 | ||
394cf0a1 S |
58 | #define TSF_TO_TU(_h,_l) \ |
59 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
60 | ||
61 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
62 | ||
394cf0a1 S |
63 | struct ath_config { |
64 | u32 ath_aggr_prot; | |
65 | u16 txpowlimit; | |
66 | u8 cabqReadytime; | |
394cf0a1 S |
67 | }; |
68 | ||
69 | /*************************/ | |
70 | /* Descriptor Management */ | |
71 | /*************************/ | |
72 | ||
73 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 74 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
75 | (_bf)->bf_lastbf = NULL; \ |
76 | (_bf)->bf_next = NULL; \ | |
77 | memset(&((_bf)->bf_state), 0, \ | |
78 | sizeof(struct ath_buf_state)); \ | |
79 | } while (0) | |
80 | ||
a119cc49 S |
81 | #define ATH_RXBUF_RESET(_bf) do { \ |
82 | (_bf)->bf_stale = false; \ | |
83 | } while (0) | |
84 | ||
394cf0a1 S |
85 | /** |
86 | * enum buffer_type - Buffer type flags | |
87 | * | |
88 | * @BUF_HT: Send this buffer using HT capabilities | |
89 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
90 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
91 | * (used in aggregation scheduling) | |
92 | * @BUF_RETRY: Indicates whether the buffer is retried | |
93 | * @BUF_XRETRY: To denote excessive retries of the buffer | |
94 | */ | |
95 | enum buffer_type { | |
96 | BUF_HT = BIT(1), | |
97 | BUF_AMPDU = BIT(2), | |
98 | BUF_AGGR = BIT(3), | |
99 | BUF_RETRY = BIT(4), | |
100 | BUF_XRETRY = BIT(5), | |
101 | }; | |
102 | ||
394cf0a1 S |
103 | #define bf_nframes bf_state.bfs_nframes |
104 | #define bf_al bf_state.bfs_al | |
105 | #define bf_frmlen bf_state.bfs_frmlen | |
106 | #define bf_retries bf_state.bfs_retries | |
107 | #define bf_seqno bf_state.bfs_seqno | |
108 | #define bf_tidno bf_state.bfs_tidno | |
109 | #define bf_keyix bf_state.bfs_keyix | |
110 | #define bf_keytype bf_state.bfs_keytype | |
111 | #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) | |
112 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
113 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
114 | #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) | |
115 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) | |
f078f209 | 116 | |
5088c2f1 VT |
117 | #define ATH_TXSTATUS_RING_SIZE 64 |
118 | ||
394cf0a1 | 119 | struct ath_descdma { |
5088c2f1 | 120 | void *dd_desc; |
17d7904d S |
121 | dma_addr_t dd_desc_paddr; |
122 | u32 dd_desc_len; | |
123 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
124 | }; |
125 | ||
126 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
127 | struct list_head *head, const char *name, | |
4adfcded | 128 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
129 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, |
130 | struct list_head *head); | |
131 | ||
132 | /***********/ | |
133 | /* RX / TX */ | |
134 | /***********/ | |
135 | ||
136 | #define ATH_MAX_ANTENNA 3 | |
137 | #define ATH_RXBUF 512 | |
394cf0a1 | 138 | #define ATH_TXBUF 512 |
84642d6b FF |
139 | #define ATH_TXBUF_RESERVE 5 |
140 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 141 | #define ATH_TXMAXTRY 13 |
394cf0a1 | 142 | #define ATH_MGT_TXMAXTRY 4 |
394cf0a1 S |
143 | |
144 | #define TID_TO_WME_AC(_tid) \ | |
145 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
146 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
147 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
148 | WME_AC_VO) | |
149 | ||
394cf0a1 S |
150 | #define ADDBA_EXCHANGE_ATTEMPTS 10 |
151 | #define ATH_AGGR_DELIM_SZ 4 | |
152 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
153 | /* number of delimiters for encryption padding */ | |
154 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
155 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
156 | #define ATH_AGGR_MIN_QDEPTH 2 | |
157 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
394cf0a1 S |
158 | |
159 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
160 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
161 | #define IEEE80211_WEP_IVLEN 3 |
162 | #define IEEE80211_WEP_KIDLEN 1 | |
163 | #define IEEE80211_WEP_CRCLEN 4 | |
164 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
165 | (IEEE80211_WEP_IVLEN + \ | |
166 | IEEE80211_WEP_KIDLEN + \ | |
167 | IEEE80211_WEP_CRCLEN)) | |
168 | ||
169 | /* return whether a bit at index _n in bitmap _bm is set | |
170 | * _sz is the size of the bitmap */ | |
171 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
172 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
173 | ||
174 | /* return block-ack bitmap index given sequence and starting sequence */ | |
175 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
176 | ||
177 | /* returns delimiter padding required given the packet length */ | |
178 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
179 | (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ | |
180 | (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) | |
181 | ||
182 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
183 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
184 | ||
394cf0a1 S |
185 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
186 | ||
164ace38 SB |
187 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
188 | ||
394cf0a1 S |
189 | enum ATH_AGGR_STATUS { |
190 | ATH_AGGR_DONE, | |
191 | ATH_AGGR_BAW_CLOSED, | |
192 | ATH_AGGR_LIMITED, | |
193 | }; | |
194 | ||
e5003249 | 195 | #define ATH_TXFIFO_DEPTH 8 |
394cf0a1 | 196 | struct ath_txq { |
293f2ba8 | 197 | int axq_class; |
17d7904d S |
198 | u32 axq_qnum; |
199 | u32 *axq_link; | |
200 | struct list_head axq_q; | |
394cf0a1 | 201 | spinlock_t axq_lock; |
17d7904d | 202 | u32 axq_depth; |
17d7904d | 203 | bool stopped; |
164ace38 | 204 | bool axq_tx_inprogress; |
394cf0a1 | 205 | struct list_head axq_acq; |
e5003249 VT |
206 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
207 | struct list_head txq_fifo_pending; | |
208 | u8 txq_headidx; | |
209 | u8 txq_tailidx; | |
84642d6b | 210 | int pending_frames; |
394cf0a1 S |
211 | }; |
212 | ||
93ef24b2 S |
213 | struct ath_atx_ac { |
214 | int sched; | |
215 | int qnum; | |
216 | struct list_head list; | |
217 | struct list_head tid_q; | |
218 | }; | |
219 | ||
220 | struct ath_buf_state { | |
221 | int bfs_nframes; | |
222 | u16 bfs_al; | |
223 | u16 bfs_frmlen; | |
224 | int bfs_seqno; | |
225 | int bfs_tidno; | |
226 | int bfs_retries; | |
227 | u8 bf_type; | |
228 | u32 bfs_keyix; | |
229 | enum ath9k_key_type bfs_keytype; | |
230 | }; | |
231 | ||
232 | struct ath_buf { | |
233 | struct list_head list; | |
234 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
235 | an aggregate) */ | |
236 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
237 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
238 | void *bf_desc; /* virtual addr of desc */ | |
239 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
240 | dma_addr_t bf_buf_addr; /* physical addr of data buffer */ | |
241 | bool bf_stale; | |
242 | bool bf_isnullfunc; | |
243 | bool bf_tx_aborted; | |
244 | u16 bf_flags; | |
245 | struct ath_buf_state bf_state; | |
246 | dma_addr_t bf_dmacontext; | |
247 | struct ath_wiphy *aphy; | |
84642d6b | 248 | struct ath_txq *txq; |
93ef24b2 S |
249 | }; |
250 | ||
251 | struct ath_atx_tid { | |
252 | struct list_head list; | |
253 | struct list_head buf_q; | |
254 | struct ath_node *an; | |
255 | struct ath_atx_ac *ac; | |
256 | struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; | |
257 | u16 seq_start; | |
258 | u16 seq_next; | |
259 | u16 baw_size; | |
260 | int tidno; | |
261 | int baw_head; /* first un-acked tx buffer */ | |
262 | int baw_tail; /* next unused tx buffer slot */ | |
263 | int sched; | |
264 | int paused; | |
265 | u8 state; | |
266 | }; | |
267 | ||
268 | struct ath_node { | |
269 | struct ath_common *common; | |
270 | struct ath_atx_tid tid[WME_NUM_TID]; | |
271 | struct ath_atx_ac ac[WME_NUM_AC]; | |
272 | u16 maxampdu; | |
273 | u8 mpdudensity; | |
274 | int last_rssi; | |
275 | }; | |
276 | ||
394cf0a1 S |
277 | #define AGGR_CLEANUP BIT(1) |
278 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
279 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
280 | ||
394cf0a1 S |
281 | struct ath_tx_control { |
282 | struct ath_txq *txq; | |
283 | int if_id; | |
f0ed85c6 | 284 | enum ath9k_internal_frame_type frame_type; |
394cf0a1 S |
285 | }; |
286 | ||
394cf0a1 S |
287 | #define ATH_TX_ERROR 0x01 |
288 | #define ATH_TX_XRETRY 0x02 | |
289 | #define ATH_TX_BAR 0x04 | |
394cf0a1 | 290 | |
394cf0a1 S |
291 | struct ath_tx { |
292 | u16 seq_no; | |
293 | u32 txqsetup; | |
1d2231e2 | 294 | int hwq_map[WME_NUM_AC]; |
394cf0a1 S |
295 | spinlock_t txbuflock; |
296 | struct list_head txbuf; | |
297 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
298 | struct ath_descdma txdma; | |
299 | }; | |
300 | ||
b5c80475 FF |
301 | struct ath_rx_edma { |
302 | struct sk_buff_head rx_fifo; | |
303 | struct sk_buff_head rx_buffers; | |
304 | u32 rx_fifo_hwsize; | |
305 | }; | |
306 | ||
394cf0a1 S |
307 | struct ath_rx { |
308 | u8 defant; | |
309 | u8 rxotherant; | |
310 | u32 *rxlink; | |
394cf0a1 S |
311 | unsigned int rxfilter; |
312 | spinlock_t rxflushlock; | |
313 | spinlock_t rxbuflock; | |
314 | struct list_head rxbuf; | |
315 | struct ath_descdma rxdma; | |
b5c80475 FF |
316 | struct ath_buf *rx_bufptr; |
317 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; | |
394cf0a1 S |
318 | }; |
319 | ||
320 | int ath_startrecv(struct ath_softc *sc); | |
321 | bool ath_stoprecv(struct ath_softc *sc); | |
322 | void ath_flushrecv(struct ath_softc *sc); | |
323 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
324 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
325 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 326 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 S |
327 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
328 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
329 | int ath_tx_setup(struct ath_softc *sc, int haltype); | |
330 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); | |
331 | void ath_draintxq(struct ath_softc *sc, | |
332 | struct ath_txq *txq, bool retry_tx); | |
333 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
334 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
335 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
336 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
797fe5cb | 337 | void ath_tx_cleanup(struct ath_softc *sc); |
394cf0a1 S |
338 | int ath_txq_update(struct ath_softc *sc, int qnum, |
339 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 340 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
341 | struct ath_tx_control *txctl); |
342 | void ath_tx_tasklet(struct ath_softc *sc); | |
e5003249 | 343 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
c52f33d0 | 344 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); |
394cf0a1 | 345 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); |
f83da965 S |
346 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
347 | u16 tid, u16 *ssn); | |
348 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
394cf0a1 | 349 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
3f7c5c10 | 350 | void ath9k_enable_ps(struct ath_softc *sc); |
394cf0a1 S |
351 | |
352 | /********/ | |
17d7904d | 353 | /* VIFs */ |
394cf0a1 | 354 | /********/ |
f078f209 | 355 | |
17d7904d | 356 | struct ath_vif { |
394cf0a1 | 357 | int av_bslot; |
4ed96f04 | 358 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 S |
359 | enum nl80211_iftype av_opmode; |
360 | struct ath_buf *av_bcbuf; | |
361 | struct ath_tx_control av_btxctl; | |
f0ed85c6 | 362 | u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ |
f078f209 LR |
363 | }; |
364 | ||
394cf0a1 S |
365 | /*******************/ |
366 | /* Beacon Handling */ | |
367 | /*******************/ | |
f078f209 | 368 | |
394cf0a1 S |
369 | /* |
370 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
371 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
372 | * number of beacon intervals, the game's up. | |
373 | */ | |
374 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | |
4ed96f04 | 375 | #define ATH_BCBUF 4 |
394cf0a1 S |
376 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
377 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
378 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
379 | ||
380 | struct ath_beacon_config { | |
381 | u16 beacon_interval; | |
382 | u16 listen_interval; | |
383 | u16 dtim_period; | |
384 | u16 bmiss_timeout; | |
385 | u8 dtim_count; | |
394cf0a1 S |
386 | }; |
387 | ||
388 | struct ath_beacon { | |
389 | enum { | |
390 | OK, /* no change needed */ | |
391 | UPDATE, /* update pending */ | |
392 | COMMIT /* beacon sent, commit change */ | |
393 | } updateslot; /* slot time update fsm */ | |
394 | ||
395 | u32 beaconq; | |
396 | u32 bmisscnt; | |
397 | u32 ast_be_xmit; | |
398 | u64 bc_tstamp; | |
2c3db3d5 | 399 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
c52f33d0 | 400 | struct ath_wiphy *bslot_aphy[ATH_BCBUF]; |
394cf0a1 S |
401 | int slottime; |
402 | int slotupdate; | |
403 | struct ath9k_tx_queue_info beacon_qi; | |
404 | struct ath_descdma bdma; | |
405 | struct ath_txq *cabq; | |
406 | struct list_head bbuf; | |
407 | }; | |
408 | ||
9fc9ab0a | 409 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 410 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
c52f33d0 | 411 | int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); |
17d7904d | 412 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
94db2936 | 413 | int ath_beaconq_config(struct ath_softc *sc); |
394cf0a1 S |
414 | |
415 | /*******/ | |
416 | /* ANI */ | |
417 | /*******/ | |
f078f209 | 418 | |
20977d3e S |
419 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
420 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
421 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
422 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
20977d3e S |
423 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
424 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 425 | |
55624204 S |
426 | void ath_ani_calibrate(unsigned long data); |
427 | ||
0fca65c1 S |
428 | /**********/ |
429 | /* BTCOEX */ | |
430 | /**********/ | |
431 | ||
e08a6ace LR |
432 | /* Defines the BT AR_BT_COEX_WGHT used */ |
433 | enum ath_stomp_type { | |
434 | ATH_BTCOEX_NO_STOMP, | |
435 | ATH_BTCOEX_STOMP_ALL, | |
436 | ATH_BTCOEX_STOMP_LOW, | |
437 | ATH_BTCOEX_STOMP_NONE | |
438 | }; | |
439 | ||
2e20250a LR |
440 | struct ath_btcoex { |
441 | bool hw_timer_enabled; | |
442 | spinlock_t btcoex_lock; | |
443 | struct timer_list period_timer; /* Timer for BT period */ | |
444 | u32 bt_priority_cnt; | |
445 | unsigned long bt_priority_time; | |
e08a6ace | 446 | int bt_stomp_type; /* Types of BT stomping */ |
2e20250a LR |
447 | u32 btcoex_no_stomp; /* in usec */ |
448 | u32 btcoex_period; /* in usec */ | |
58da1318 | 449 | u32 btscan_no_stomp; /* in usec */ |
75d7839f | 450 | struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ |
2e20250a LR |
451 | }; |
452 | ||
0fca65c1 S |
453 | int ath_init_btcoex_timer(struct ath_softc *sc); |
454 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); | |
455 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
456 | ||
394cf0a1 S |
457 | /********************/ |
458 | /* LED Control */ | |
459 | /********************/ | |
f078f209 | 460 | |
08fc5c1b VN |
461 | #define ATH_LED_PIN_DEF 1 |
462 | #define ATH_LED_PIN_9287 8 | |
394cf0a1 S |
463 | #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ |
464 | #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ | |
f078f209 | 465 | |
394cf0a1 S |
466 | enum ath_led_type { |
467 | ATH_LED_RADIO, | |
468 | ATH_LED_ASSOC, | |
469 | ATH_LED_TX, | |
470 | ATH_LED_RX | |
f078f209 LR |
471 | }; |
472 | ||
394cf0a1 S |
473 | struct ath_led { |
474 | struct ath_softc *sc; | |
475 | struct led_classdev led_cdev; | |
476 | enum ath_led_type led_type; | |
477 | char name[32]; | |
478 | bool registered; | |
f078f209 LR |
479 | }; |
480 | ||
0fca65c1 S |
481 | void ath_init_leds(struct ath_softc *sc); |
482 | void ath_deinit_leds(struct ath_softc *sc); | |
483 | ||
394cf0a1 S |
484 | /********************/ |
485 | /* Main driver core */ | |
486 | /********************/ | |
f078f209 | 487 | |
394cf0a1 S |
488 | /* |
489 | * Default cache line size, in bytes. | |
490 | * Used when PCI device not fully initialized by bootrom/BIOS | |
491 | */ | |
492 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 S |
493 | #define ATH_REGCLASSIDS_MAX 10 |
494 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
495 | #define ATH_MAX_SW_RETRIES 10 | |
496 | #define ATH_CHAN_MAX 255 | |
497 | #define IEEE80211_WEP_NKID 4 /* number of key ids */ | |
f1dc5600 | 498 | |
394cf0a1 | 499 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
394cf0a1 S |
500 | #define ATH_RATE_DUMMY_MARKER 0 |
501 | ||
1b04b930 S |
502 | #define SC_OP_INVALID BIT(0) |
503 | #define SC_OP_BEACONS BIT(1) | |
504 | #define SC_OP_RXAGGR BIT(2) | |
505 | #define SC_OP_TXAGGR BIT(3) | |
506 | #define SC_OP_FULL_RESET BIT(4) | |
507 | #define SC_OP_PREAMBLE_SHORT BIT(5) | |
508 | #define SC_OP_PROTECT_ENABLE BIT(6) | |
509 | #define SC_OP_RXFLUSH BIT(7) | |
510 | #define SC_OP_LED_ASSOCIATED BIT(8) | |
511 | #define SC_OP_LED_ON BIT(9) | |
512 | #define SC_OP_SCANNING BIT(10) | |
513 | #define SC_OP_TSF_RESET BIT(11) | |
514 | #define SC_OP_BT_PRIORITY_DETECTED BIT(12) | |
58da1318 | 515 | #define SC_OP_BT_SCAN BIT(13) |
1b04b930 S |
516 | |
517 | /* Powersave flags */ | |
518 | #define PS_WAIT_FOR_BEACON BIT(0) | |
519 | #define PS_WAIT_FOR_CAB BIT(1) | |
520 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
521 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
522 | #define PS_BEACON_SYNC BIT(4) | |
523 | #define PS_NULLFUNC_COMPLETED BIT(5) | |
524 | #define PS_ENABLED BIT(6) | |
394cf0a1 | 525 | |
bce048d7 | 526 | struct ath_wiphy; |
545750d3 | 527 | struct ath_rate_table; |
bce048d7 | 528 | |
394cf0a1 S |
529 | struct ath_softc { |
530 | struct ieee80211_hw *hw; | |
531 | struct device *dev; | |
c52f33d0 JM |
532 | |
533 | spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ | |
bce048d7 | 534 | struct ath_wiphy *pri_wiphy; |
c52f33d0 JM |
535 | struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may |
536 | * have NULL entries */ | |
537 | int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ | |
0e2dedf9 JM |
538 | int chan_idx; |
539 | int chan_is_ht; | |
540 | struct ath_wiphy *next_wiphy; | |
541 | struct work_struct chan_work; | |
7ec3e514 JM |
542 | int wiphy_select_failures; |
543 | unsigned long wiphy_select_first_fail; | |
f98c3bd2 JM |
544 | struct delayed_work wiphy_work; |
545 | unsigned long wiphy_scheduler_int; | |
546 | int wiphy_scheduler_index; | |
0e2dedf9 | 547 | |
394cf0a1 S |
548 | struct tasklet_struct intr_tq; |
549 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 550 | struct ath_hw *sc_ah; |
394cf0a1 S |
551 | void __iomem *mem; |
552 | int irq; | |
553 | spinlock_t sc_resetlock; | |
2d6a5e95 | 554 | spinlock_t sc_serial_rw; |
04717ccd | 555 | spinlock_t sc_pm_lock; |
394cf0a1 S |
556 | struct mutex mutex; |
557 | ||
17d7904d | 558 | u32 intrstatus; |
394cf0a1 | 559 | u32 sc_flags; /* SC_OP_* */ |
1b04b930 | 560 | u16 ps_flags; /* PS_* */ |
17d7904d | 561 | u16 curtxpow; |
17d7904d S |
562 | u8 nbcnvifs; |
563 | u16 nvifs; | |
96148326 | 564 | bool ps_enabled; |
1dbfd9d4 | 565 | bool ps_idle; |
709ade9e | 566 | unsigned long ps_usecount; |
394cf0a1 | 567 | |
17d7904d | 568 | struct ath_config config; |
394cf0a1 S |
569 | struct ath_rx rx; |
570 | struct ath_tx tx; | |
571 | struct ath_beacon beacon; | |
4f0fc7c3 | 572 | const struct ath_rate_table *cur_rate_table; |
545750d3 | 573 | enum wireless_mode cur_rate_mode; |
394cf0a1 S |
574 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
575 | ||
576 | struct ath_led radio_led; | |
577 | struct ath_led assoc_led; | |
578 | struct ath_led tx_led; | |
579 | struct ath_led rx_led; | |
580 | struct delayed_work ath_led_blink_work; | |
581 | int led_on_duration; | |
582 | int led_off_duration; | |
583 | int led_on_cnt; | |
584 | int led_off_cnt; | |
585 | ||
57c4d7b4 JB |
586 | int beacon_interval; |
587 | ||
a830df07 | 588 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 589 | struct ath9k_debug debug; |
394cf0a1 | 590 | #endif |
6b96f93e | 591 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 592 | struct delayed_work tx_complete_work; |
2e20250a | 593 | struct ath_btcoex btcoex; |
5088c2f1 VT |
594 | |
595 | struct ath_descdma txsdma; | |
394cf0a1 S |
596 | }; |
597 | ||
bce048d7 JM |
598 | struct ath_wiphy { |
599 | struct ath_softc *sc; /* shared for all virtual wiphys */ | |
600 | struct ieee80211_hw *hw; | |
f0ed85c6 | 601 | enum ath_wiphy_state { |
9580a222 | 602 | ATH_WIPHY_INACTIVE, |
f0ed85c6 JM |
603 | ATH_WIPHY_ACTIVE, |
604 | ATH_WIPHY_PAUSING, | |
605 | ATH_WIPHY_PAUSED, | |
8089cc47 | 606 | ATH_WIPHY_SCAN, |
f0ed85c6 | 607 | } state; |
194b7c13 | 608 | bool idle; |
0e2dedf9 JM |
609 | int chan_idx; |
610 | int chan_is_ht; | |
bce048d7 JM |
611 | }; |
612 | ||
55624204 | 613 | void ath9k_tasklet(unsigned long data); |
394cf0a1 S |
614 | int ath_reset(struct ath_softc *sc, bool retry_tx); |
615 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); | |
616 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); | |
617 | int ath_cabq_update(struct ath_softc *); | |
618 | ||
5bb12791 | 619 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 620 | { |
5bb12791 | 621 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
622 | } |
623 | ||
394cf0a1 | 624 | extern struct ieee80211_ops ath9k_ops; |
55624204 | 625 | extern int modparam_nohwcrypt; |
394cf0a1 S |
626 | |
627 | irqreturn_t ath_isr(int irq, void *dev); | |
285f2dda | 628 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
5bb12791 | 629 | const struct ath_bus_ops *bus_ops); |
285f2dda | 630 | void ath9k_deinit_device(struct ath_softc *sc); |
394cf0a1 S |
631 | const char *ath_mac_bb_name(u32 mac_bb_version); |
632 | const char *ath_rf_name(u16 rf_version); | |
285f2dda | 633 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
0e2dedf9 JM |
634 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
635 | struct ath9k_channel *ichan); | |
636 | void ath_update_chainmask(struct ath_softc *sc, int is_ht); | |
637 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
638 | struct ath9k_channel *hchan); | |
68a89116 LR |
639 | |
640 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
641 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
55624204 | 642 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode); |
394cf0a1 S |
643 | |
644 | #ifdef CONFIG_PCI | |
645 | int ath_pci_init(void); | |
646 | void ath_pci_exit(void); | |
647 | #else | |
648 | static inline int ath_pci_init(void) { return 0; }; | |
649 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 650 | #endif |
f1dc5600 | 651 | |
394cf0a1 S |
652 | #ifdef CONFIG_ATHEROS_AR71XX |
653 | int ath_ahb_init(void); | |
654 | void ath_ahb_exit(void); | |
655 | #else | |
656 | static inline int ath_ahb_init(void) { return 0; }; | |
657 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 658 | #endif |
394cf0a1 | 659 | |
0bc0798b GJ |
660 | void ath9k_ps_wakeup(struct ath_softc *sc); |
661 | void ath9k_ps_restore(struct ath_softc *sc); | |
8ca21f01 JM |
662 | |
663 | void ath9k_set_bssid_mask(struct ieee80211_hw *hw); | |
c52f33d0 JM |
664 | int ath9k_wiphy_add(struct ath_softc *sc); |
665 | int ath9k_wiphy_del(struct ath_wiphy *aphy); | |
f0ed85c6 JM |
666 | void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); |
667 | int ath9k_wiphy_pause(struct ath_wiphy *aphy); | |
668 | int ath9k_wiphy_unpause(struct ath_wiphy *aphy); | |
0e2dedf9 | 669 | int ath9k_wiphy_select(struct ath_wiphy *aphy); |
f98c3bd2 | 670 | void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); |
0e2dedf9 | 671 | void ath9k_wiphy_chan_work(struct work_struct *work); |
9580a222 | 672 | bool ath9k_wiphy_started(struct ath_softc *sc); |
18eb62f8 JM |
673 | void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, |
674 | struct ath_wiphy *selected); | |
8089cc47 | 675 | bool ath9k_wiphy_scanning(struct ath_softc *sc); |
f98c3bd2 | 676 | void ath9k_wiphy_work(struct work_struct *work); |
64839170 | 677 | bool ath9k_all_wiphys_idle(struct ath_softc *sc); |
194b7c13 | 678 | void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle); |
8ca21f01 | 679 | |
f52de03b LR |
680 | void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue); |
681 | void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue); | |
682 | ||
0fca65c1 S |
683 | void ath_start_rfkill_poll(struct ath_softc *sc); |
684 | extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
685 | ||
394cf0a1 | 686 | #endif /* ATH9K_H */ |