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ath9k_htc: catch fw panic pattern
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ath9k.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
394cf0a1
S		 20#include <linux/etherdevice.h>
21#include <linux/device.h>
a6b7a407 22#include <linux/interrupt.h>
394cf0a1 23#include <linux/leds.h>
9f42c2b6 24#include <linux/completion.h>
394cf0a1 25
394cf0a1 26#include "debug.h"
db86f07e 27#include "common.h"
7dc181c2 28#include "mci.h"
8e92d3f2 29#include "dfs.h"
f65c0825 30#include "spectral.h"
db86f07e 31
394cf0a1 32struct ath_node;
7b6ef998 33struct ath_rate_table;
394cf0a1 34
7b6ef998
SM		 35extern struct ieee80211_ops ath9k_ops;
36extern int ath9k_modparam_nohwcrypt;
37extern int led_blink;
38extern bool is_ath9k_unloaded;
394cf0a1 39
394cf0a1 40struct ath_config {
394cf0a1 41 u16 txpowlimit;
394cf0a1
S		 42};
43
44/*************************/
45/* Descriptor Management */
46/*************************/
47
7b6ef998
SM		 48#define ATH_TXSTATUS_RING_SIZE 512
49
50/* Macro to expand scalars to 64-bit objects */
51#define ito64(x) (sizeof(x) == 1) ? \
52 (((unsigned long long int)(x)) & (0xff)) : \
53 (sizeof(x) == 2) ? \
54 (((unsigned long long int)(x)) & 0xffff) : \
55 ((sizeof(x) == 4) ? \
56 (((unsigned long long int)(x)) & 0xffffffff) : \
57 (unsigned long long int)(x))
58
394cf0a1 59#define ATH_TXBUF_RESET(_bf) do { \
394cf0a1
S		 60 (_bf)->bf_lastbf = NULL; \
61 (_bf)->bf_next = NULL; \
62 memset(&((_bf)->bf_state), 0, \
63 sizeof(struct ath_buf_state)); \
64 } while (0)
65
c3d77696
MSS		 66#define DS2PHYS(_dd, _ds) \
67 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
68#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
69#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
70
394cf0a1 71struct ath_descdma {
5088c2f1 72 void *dd_desc;
17d7904d
S		 73 dma_addr_t dd_desc_paddr;
74 u32 dd_desc_len;
394cf0a1
S		 75};
76
77int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
78 struct list_head *head, const char *name,
4adfcded 79 int nbuf, int ndesc, bool is_tx);
394cf0a1
S		 80
81/***********/
82/* RX / TX */
83/***********/
84
7b6ef998
SM		 85#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
86
87/* increment with wrap-around */
88#define INCR(_l, _sz) do { \
89 (_l)++; \
90 (_l) &= ((_sz) - 1); \
91 } while (0)
92
394cf0a1 93#define ATH_RXBUF 512
394cf0a1 94#define ATH_TXBUF 512
84642d6b
FF		 95#define ATH_TXBUF_RESERVE 5
96#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
394cf0a1 97#define ATH_TXMAXTRY 13
7b6ef998 98#define ATH_MAX_SW_RETRIES 30
394cf0a1
S		 99
100#define TID_TO_WME_AC(_tid) \
bea843c7
SM		 101 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
102 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \
103 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \
104 IEEE80211_AC_VO)
394cf0a1 105
394cf0a1
S		 106#define ATH_AGGR_DELIM_SZ 4
107#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
108/* number of delimiters for encryption padding */
109#define ATH_AGGR_ENCRYPTDELIM 10
110/* minimum h/w qdepth to be sustained to maximize aggregation */
111#define ATH_AGGR_MIN_QDEPTH 2
2800e82b
FF		 112/* minimum h/w qdepth for non-aggregated traffic */
113#define ATH_NON_AGGR_MIN_QDEPTH 8
7b6ef998
SM		 114#define ATH_TX_COMPLETE_POLL_INT 1000
115#define ATH_TXFIFO_DEPTH 8
116#define ATH_TX_ERROR 0x01
394cf0a1
S		 117
118#define IEEE80211_SEQ_SEQ_SHIFT 4
119#define IEEE80211_SEQ_MAX 4096
394cf0a1
S		 120#define IEEE80211_WEP_IVLEN 3
121#define IEEE80211_WEP_KIDLEN 1
122#define IEEE80211_WEP_CRCLEN 4
123#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
124 (IEEE80211_WEP_IVLEN + \
125 IEEE80211_WEP_KIDLEN + \
126 IEEE80211_WEP_CRCLEN))
127
128/* return whether a bit at index _n in bitmap _bm is set
129 * _sz is the size of the bitmap */
130#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
131 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
132
133/* return block-ack bitmap index given sequence and starting sequence */
134#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
135
156369fa
FF		 136/* return the seqno for _start + _offset */
137#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
138
394cf0a1
S		 139/* returns delimiter padding required given the packet length */
140#define ATH_AGGR_GET_NDELIM(_len) \
39ec2997
VT		 141 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
142 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
394cf0a1
S		 143
144#define BAW_WITHIN(_start, _bawsz, _seqno) \
145 ((((_seqno) - (_start)) & 4095) < (_bawsz))
146
394cf0a1
S		 147#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
148
350e2dcb
SM		 149#define IS_HT_RATE(rate) (rate & 0x80)
150#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
151#define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf))
365d2ebc 152
394cf0a1 153struct ath_txq {
60f2d1d5
BG		 154 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
155 u32 axq_qnum; /* ath9k hardware queue number */
fce041be 156 void *axq_link;
17d7904d 157 struct list_head axq_q;
394cf0a1 158 spinlock_t axq_lock;
17d7904d 159 u32 axq_depth;
4b3ba66a 160 u32 axq_ampdu_depth;
17d7904d 161 bool stopped;
164ace38 162 bool axq_tx_inprogress;
394cf0a1 163 struct list_head axq_acq;
e5003249 164 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
e5003249
VT		 165 u8 txq_headidx;
166 u8 txq_tailidx;
066dae93 167 int pending_frames;
23de5dc9 168 struct sk_buff_head complete_q;
394cf0a1
S		 169};
170
93ef24b2 171struct ath_atx_ac {
066dae93 172 struct ath_txq *txq;
93ef24b2
S		 173 struct list_head list;
174 struct list_head tid_q;
5519541d 175 bool clear_ps_filter;
50676b81 176 bool sched;
93ef24b2
S		 177};
178
2d42efc4 179struct ath_frame_info {
56dc6336 180 struct ath_buf *bf;
2d42efc4 181 int framelen;
2d42efc4 182 enum ath9k_key_type keytype;
a75c0629 183 u8 keyix;
80b08a8d 184 u8 rtscts_rate;
8fed1408
FF		 185 u8 retries : 7;
186 u8 baw_tracked : 1;
2d42efc4
FF		 187};
188
1a04d59d
FF		 189struct ath_rxbuf {
190 struct list_head list;
191 struct sk_buff *bf_mpdu;
192 void *bf_desc;
193 dma_addr_t bf_daddr;
194 dma_addr_t bf_buf_addr;
195};
196
7b6ef998
SM		 197/**
198 * enum buffer_type - Buffer type flags
199 *
200 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
201 * @BUF_AGGR: Indicates whether the buffer can be aggregated
202 * (used in aggregation scheduling)
203 */
204enum buffer_type {
205 BUF_AMPDU = BIT(0),
206 BUF_AGGR = BIT(1),
207};
208
209#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
210#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
211
93ef24b2 212struct ath_buf_state {
93ef24b2 213 u8 bf_type;
9f42c2b6 214 u8 bfs_paprd;
399c6489 215 u8 ndelim;
50676b81 216 bool stale;
6a0ddaef 217 u16 seqno;
9cf04dcc 218 unsigned long bfs_paprd_timestamp;
93ef24b2
S		 219};
220
221struct ath_buf {
222 struct list_head list;
223 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
224 an aggregate) */
225 struct ath_buf *bf_next; /* next subframe in the aggregate */
226 struct sk_buff *bf_mpdu; /* enclosing frame structure */
227 void *bf_desc; /* virtual addr of desc */
228 dma_addr_t bf_daddr; /* physical addr of desc */
c1739eb3 229 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
79acac07 230 struct ieee80211_tx_rate rates[4];
93ef24b2 231 struct ath_buf_state bf_state;
93ef24b2
S		 232};
233
234struct ath_atx_tid {
235 struct list_head list;
56dc6336 236 struct sk_buff_head buf_q;
bb195ff6 237 struct sk_buff_head retry_q;
93ef24b2
S		 238 struct ath_node *an;
239 struct ath_atx_ac *ac;
81ee13ba 240 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
93ef24b2
S		 241 u16 seq_start;
242 u16 seq_next;
243 u16 baw_size;
50676b81 244 u8 tidno;
93ef24b2
S		 245 int baw_head; /* first un-acked tx buffer */
246 int baw_tail; /* next unused tx buffer slot */
50676b81
FF		 247
248 s8 bar_index;
08c96abd
FF		 249 bool sched;
250 bool paused;
251 bool active;
93ef24b2
S		 252};
253
254struct ath_node {
a145daf7 255 struct ath_softc *sc;
7f010c93 256 struct ieee80211_sta *sta; /* station struct we're part of */
7e1e3864 257 struct ieee80211_vif *vif; /* interface with which we're associated */
de7b7604 258 struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
bea843c7 259 struct ath_atx_ac ac[IEEE80211_NUM_ACS];
93ae2dd2 260
93ef24b2
S		 261 u16 maxampdu;
262 u8 mpdudensity;
50676b81 263 s8 ps_key;
5519541d
FF		 264
265 bool sleeping;
f89d1bc4 266 bool no_ps_filter;
350e2dcb
SM		 267
268#ifdef CONFIG_ATH9K_STATION_STATISTICS
269 struct ath_rx_rate_stats rx_rate_stats;
270#endif
93ef24b2
S		 271};
272
394cf0a1
S		 273struct ath_tx_control {
274 struct ath_txq *txq;
2d42efc4 275 struct ath_node *an;
9f42c2b6 276 u8 paprd;
36323f81 277 struct ieee80211_sta *sta;
394cf0a1
S		 278};
279
394cf0a1 280
60f2d1d5
BG		 281/**
282 * @txq_map: Index is mac80211 queue number. This is
283 * not necessarily the same as the hardware queue number
284 * (axq_qnum).
285 */
394cf0a1
S		 286struct ath_tx {
287 u16 seq_no;
288 u32 txqsetup;
394cf0a1
S		 289 spinlock_t txbuflock;
290 struct list_head txbuf;
291 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
292 struct ath_descdma txdma;
bea843c7 293 struct ath_txq *txq_map[IEEE80211_NUM_ACS];
f2c7a793 294 struct ath_txq *uapsdq;
bea843c7
SM		 295 u32 txq_max_pending[IEEE80211_NUM_ACS];
296 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
394cf0a1
S		 297};
298
b5c80475
FF		 299struct ath_rx_edma {
300 struct sk_buff_head rx_fifo;
b5c80475
FF		 301 u32 rx_fifo_hwsize;
302};
303
394cf0a1
S		 304struct ath_rx {
305 u8 defant;
306 u8 rxotherant;
723e7113 307 bool discard_next;
394cf0a1 308 u32 *rxlink;
6995fb80 309 u32 num_pkts;
394cf0a1 310 unsigned int rxfilter;
394cf0a1
S		 311 struct list_head rxbuf;
312 struct ath_descdma rxdma;
b5c80475 313 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
0d95521e 314
1a04d59d 315 struct ath_rxbuf *buf_hold;
0d95521e 316 struct sk_buff *frag;
21fbbca3
CL		 317
318 u32 ampdu_ref;
394cf0a1
S		 319};
320
321int ath_startrecv(struct ath_softc *sc);
322bool ath_stoprecv(struct ath_softc *sc);
394cf0a1
S		 323u32 ath_calcrxfilter(struct ath_softc *sc);
324int ath_rx_init(struct ath_softc *sc, int nbufs);
325void ath_rx_cleanup(struct ath_softc *sc);
b5c80475 326int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
394cf0a1 327struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
ef1b6cd9
SM		 328void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
329void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
330void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1 331void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
1381559b
FF		 332bool ath_drain_all_txq(struct ath_softc *sc);
333void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1
S		 334void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
335void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
336void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
337int ath_tx_init(struct ath_softc *sc, int nbufs);
394cf0a1
S		 338int ath_txq_update(struct ath_softc *sc, int qnum,
339 struct ath9k_tx_queue_info *q);
aa5955c3 340void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
c52f33d0 341int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
394cf0a1 342 struct ath_tx_control *txctl);
59505c02
FF		 343void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
344 struct sk_buff *skb);
394cf0a1 345void ath_tx_tasklet(struct ath_softc *sc);
e5003249 346void ath_tx_edma_tasklet(struct ath_softc *sc);
231c3a1f
FF		 347int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
348 u16 tid, u16 *ssn);
f83da965 349void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
394cf0a1
S		 350void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
351
5519541d 352void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
042ec453
JB		 353void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
354 struct ath_node *an);
86a22acf
FF		 355void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
356 struct ieee80211_sta *sta,
357 u16 tids, int nframes,
358 enum ieee80211_frame_release_type reason,
359 bool more_data);
5519541d 360
394cf0a1 361/********/
17d7904d 362/* VIFs */
394cf0a1 363/********/
f078f209 364
17d7904d 365struct ath_vif {
f89d1bc4 366 struct ath_node mcast_node;
394cf0a1 367 int av_bslot;
aa45fe96 368 bool primary_sta_vif;
4ed96f04 369 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
394cf0a1 370 struct ath_buf *av_bcbuf;
f078f209
LR		 371};
372
7b6ef998
SM		 373struct ath9k_vif_iter_data {
374 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
375 u8 mask[ETH_ALEN]; /* bssid mask */
376 bool has_hw_macaddr;
377
378 int naps; /* number of AP vifs */
379 int nmeshes; /* number of mesh vifs */
380 int nstations; /* number of station vifs */
381 int nwds; /* number of WDS vifs */
382 int nadhocs; /* number of adhoc vifs */
383};
384
385void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
386 struct ieee80211_vif *vif,
387 struct ath9k_vif_iter_data *iter_data);
388
394cf0a1
S		 389/*******************/
390/* Beacon Handling */
391/*******************/
f078f209 392
394cf0a1
S		 393/*
394 * Regardless of the number of beacons we stagger, (i.e. regardless of the
395 * number of BSSIDs) if a given beacon does not go out even after waiting this
396 * number of beacon intervals, the game's up.
397 */
c944daf4 398#define BSTUCK_THRESH 9
689e756f 399#define ATH_BCBUF 8
394cf0a1
S		 400#define ATH_DEFAULT_BINTVAL 100 /* TU */
401#define ATH_DEFAULT_BMISS_LIMIT 10
402#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
403
7b6ef998
SM		 404#define TSF_TO_TU(_h,_l) \
405 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
406
394cf0a1 407struct ath_beacon_config {
9814f6b3 408 int beacon_interval;
394cf0a1
S		 409 u16 listen_interval;
410 u16 dtim_period;
411 u16 bmiss_timeout;
412 u8 dtim_count;
ef4ad633 413 bool enable_beacon;
1a6404a1 414 bool ibss_creator;
394cf0a1
S		 415};
416
417struct ath_beacon {
418 enum {
419 OK, /* no change needed */
420 UPDATE, /* update pending */
421 COMMIT /* beacon sent, commit change */
422 } updateslot; /* slot time update fsm */
423
424 u32 beaconq;
425 u32 bmisscnt;
dd347f2f 426 u32 bc_tstamp;
2c3db3d5 427 struct ieee80211_vif *bslot[ATH_BCBUF];
394cf0a1
S		 428 int slottime;
429 int slotupdate;
430 struct ath9k_tx_queue_info beacon_qi;
431 struct ath_descdma bdma;
432 struct ath_txq *cabq;
433 struct list_head bbuf;
ba4903f9
FF		 434
435 bool tx_processed;
436 bool tx_last;
394cf0a1
S		 437};
438
fb6e252f 439void ath9k_beacon_tasklet(unsigned long data);
ef4ad633
SM		 440void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
441 u32 changed);
130ef6e9
SM		 442void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
443void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
ef4ad633 444void ath9k_set_beacon(struct ath_softc *sc);
4effc6fd
MK		 445bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif);
446void ath9k_csa_update(struct ath_softc *sc);
394cf0a1 447
ef1b6cd9
SM		 448/*******************/
449/* Link Monitoring */
450/*******************/
f078f209 451
20977d3e
S		 452#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
453#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
e36b27af
LR		 454#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
455#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
6044474e 456#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
20977d3e
S		 457#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
458#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
7b6ef998
SM		 459#define ATH_ANI_MAX_SKIP_COUNT 10
460#define ATH_PAPRD_TIMEOUT 100 /* msecs */
461#define ATH_PLL_WORK_INTERVAL 100
ca369eb4 462
ef1b6cd9 463void ath_tx_complete_poll_work(struct work_struct *work);
236de514 464void ath_reset_work(struct work_struct *work);
415ec61b 465bool ath_hw_check(struct ath_softc *sc);
9eab61c2 466void ath_hw_pll_work(struct work_struct *work);
9f42c2b6 467void ath_paprd_calibrate(struct work_struct *work);
55624204 468void ath_ani_calibrate(unsigned long data);
da0d45f7
SM		 469void ath_start_ani(struct ath_softc *sc);
470void ath_stop_ani(struct ath_softc *sc);
471void ath_check_ani(struct ath_softc *sc);
ef1b6cd9
SM		 472int ath_update_survey_stats(struct ath_softc *sc);
473void ath_update_survey_nf(struct ath_softc *sc, int channel);
124b979b 474void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
bf3dac5a 475void ath_ps_full_sleep(unsigned long data);
55624204 476
0fca65c1
S		 477/**********/
478/* BTCOEX */
479/**********/
480
ac46ba43
SM		 481#define ATH_DUMP_BTCOEX(_s, _val) \
482 do { \
5e88ba62
ZK		 483 len += scnprintf(buf + len, size - len, \
484 "%20s : %10d\n", _s, (_val)); \
ac46ba43
SM		 485 } while (0)
486
e6930c4b
SM		 487enum bt_op_flags {
488 BT_OP_PRIORITY_DETECTED,
489 BT_OP_SCAN,
490};
491
2e20250a 492struct ath_btcoex {
2e20250a
LR		 493 spinlock_t btcoex_lock;
494 struct timer_list period_timer; /* Timer for BT period */
168c6f89 495 struct timer_list no_stomp_timer;
2e20250a
LR		 496 u32 bt_priority_cnt;
497 unsigned long bt_priority_time;
e6930c4b 498 unsigned long op_flags;
e08a6ace 499 int bt_stomp_type; /* Types of BT stomping */
168c6f89 500 u32 btcoex_no_stomp; /* in msec */
94ae77ea 501 u32 btcoex_period; /* in msec */
168c6f89 502 u32 btscan_no_stomp; /* in msec */
7dc181c2 503 u32 duty_cycle;
6995fb80 504 u32 bt_wait_time;
e82cb03f 505 int rssi_count;
7dc181c2 506 struct ath_mci_profile mci;
2884561a 507 u8 stomp_audio;
2e20250a
LR		 508};
509
4daa7760 510#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
5908120f
SM		 511int ath9k_init_btcoex(struct ath_softc *sc);
512void ath9k_deinit_btcoex(struct ath_softc *sc);
df198b17
SM		 513void ath9k_start_btcoex(struct ath_softc *sc);
514void ath9k_stop_btcoex(struct ath_softc *sc);
0fca65c1
S		 515void ath9k_btcoex_timer_resume(struct ath_softc *sc);
516void ath9k_btcoex_timer_pause(struct ath_softc *sc);
56ca0dba 517void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
c0ac53fa 518u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
08d4df41 519void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
ac46ba43 520int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
4daa7760
SM		 521#else
522static inline int ath9k_init_btcoex(struct ath_softc *sc)
523{
524 return 0;
525}
526static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
527{
528}
529static inline void ath9k_start_btcoex(struct ath_softc *sc)
530{
531}
532static inline void ath9k_stop_btcoex(struct ath_softc *sc)
533{
534}
535static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
536 u32 status)
537{
538}
539static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
540 u32 max_4ms_framelen)
541{
542 return 0;
543}
08d4df41
RM		 544static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
545{
546}
ac46ba43 547static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
4df50ca8
RM		 548{
549 return 0;
550}
4daa7760 551#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0fca65c1 552
394cf0a1
S		 553/********************/
554/* LED Control */
555/********************/
f078f209 556
08fc5c1b
VN		 557#define ATH_LED_PIN_DEF 1
558#define ATH_LED_PIN_9287 8
353e5019 559#define ATH_LED_PIN_9300 10
15178535 560#define ATH_LED_PIN_9485 6
1a68abb0 561#define ATH_LED_PIN_9462 4
f078f209 562
0cf55c21 563#ifdef CONFIG_MAC80211_LEDS
0fca65c1
S		 564void ath_init_leds(struct ath_softc *sc);
565void ath_deinit_leds(struct ath_softc *sc);
8f176a3a 566void ath_fill_led_pin(struct ath_softc *sc);
0cf55c21
FF		 567#else
568static inline void ath_init_leds(struct ath_softc *sc)
569{
570}
571
572static inline void ath_deinit_leds(struct ath_softc *sc)
8f176a3a
RM		 573{
574}
575static inline void ath_fill_led_pin(struct ath_softc *sc)
0cf55c21
FF		 576{
577}
578#endif
579
e60001e7
SM		 580/************************/
581/* Wake on Wireless LAN */
582/************************/
583
7b6ef998
SM		 584struct ath9k_wow_pattern {
585 u8 pattern_bytes[MAX_PATTERN_SIZE];
586 u8 mask_bytes[MAX_PATTERN_SIZE];
587 u32 pattern_len;
588};
589
e60001e7 590#ifdef CONFIG_ATH9K_WOW
babaa80a 591void ath9k_init_wow(struct ieee80211_hw *hw);
e60001e7
SM		 592int ath9k_suspend(struct ieee80211_hw *hw,
593 struct cfg80211_wowlan *wowlan);
594int ath9k_resume(struct ieee80211_hw *hw);
595void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
596#else
babaa80a
SM		 597static inline void ath9k_init_wow(struct ieee80211_hw *hw)
598{
599}
e60001e7
SM		 600static inline int ath9k_suspend(struct ieee80211_hw *hw,
601 struct cfg80211_wowlan *wowlan)
602{
603 return 0;
604}
605static inline int ath9k_resume(struct ieee80211_hw *hw)
606{
607 return 0;
608}
609static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
610{
611}
612#endif /* CONFIG_ATH9K_WOW */
613
8da07830 614/*******************************/
102885a5 615/* Antenna diversity/combining */
8da07830
SM		 616/*******************************/
617
102885a5
VT		 618#define ATH_ANT_RX_CURRENT_SHIFT 4
619#define ATH_ANT_RX_MAIN_SHIFT 2
620#define ATH_ANT_RX_MASK 0x3
621
622#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
623#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
624#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
625#define ATH_ANT_DIV_COMB_INIT_COUNT 95
626#define ATH_ANT_DIV_COMB_MAX_COUNT 100
627#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
628#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
3afa6b4f
SM		 629#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50
630#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50
102885a5 631
102885a5
VT		 632#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
633#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
634#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
635
102885a5
VT		 636struct ath_ant_comb {
637 u16 count;
638 u16 total_pkt_count;
639 bool scan;
640 bool scan_not_start;
641 int main_total_rssi;
642 int alt_total_rssi;
643 int alt_recv_cnt;
644 int main_recv_cnt;
645 int rssi_lna1;
646 int rssi_lna2;
647 int rssi_add;
648 int rssi_sub;
649 int rssi_first;
650 int rssi_second;
651 int rssi_third;
3afa6b4f
SM		 652 int ant_ratio;
653 int ant_ratio2;
102885a5
VT		 654 bool alt_good;
655 int quick_scan_cnt;
3fbaf4c5 656 enum ath9k_ant_div_comb_lna_conf main_conf;
102885a5
VT		 657 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
658 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
102885a5
VT		 659 bool first_ratio;
660 bool second_ratio;
661 unsigned long scan_start_time;
3afa6b4f
SM		 662
663 /*
664 * Card-specific config values.
665 */
666 int low_rssi_thresh;
667 int fast_div_bias;
102885a5
VT		 668};
669
8da07830 670void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
8da07830 671
394cf0a1
S		 672/********************/
673/* Main driver core */
674/********************/
f078f209 675
2d22c7dd
SM		 676#define ATH9K_PCI_CUS198 0x0001
677#define ATH9K_PCI_CUS230 0x0002
678#define ATH9K_PCI_CUS217 0x0004
679#define ATH9K_PCI_CUS252 0x0008
680#define ATH9K_PCI_WOW 0x0010
681#define ATH9K_PCI_BT_ANT_DIV 0x0020
682#define ATH9K_PCI_D3_L1_WAR 0x0040
683#define ATH9K_PCI_AR9565_1ANT 0x0080
684#define ATH9K_PCI_AR9565_2ANT 0x0100
685#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
4dd35640 686#define ATH9K_PCI_KILLER 0x0400
9b60b64b 687
394cf0a1
S		 688/*
689 * Default cache line size, in bytes.
690 * Used when PCI device not fully initialized by bootrom/BIOS
691*/
692#define DEFAULT_CACHELINE 32
394cf0a1 693#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
394cf0a1 694#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
071aa9a8 695#define MAX_GTT_CNT 5
394cf0a1 696
781b14a3
SM		 697enum sc_op_flags {
698 SC_OP_INVALID,
699 SC_OP_BEACONS,
781b14a3
SM		 700 SC_OP_ANI_RUN,
701 SC_OP_PRIM_STA_VIF,
b74713d0 702 SC_OP_HW_RESET,
73900cb0 703 SC_OP_SCANNING,
781b14a3 704};
1b04b930
S		 705
706/* Powersave flags */
707#define PS_WAIT_FOR_BEACON BIT(0)
708#define PS_WAIT_FOR_CAB BIT(1)
709#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
710#define PS_WAIT_FOR_TX_ACK BIT(3)
711#define PS_BEACON_SYNC BIT(4)
424749c7 712#define PS_WAIT_FOR_ANI BIT(5)
394cf0a1 713
394cf0a1
S		 714struct ath_softc {
715 struct ieee80211_hw *hw;
716 struct device *dev;
c52f33d0 717
3430098a
FF		 718 struct survey_info *cur_survey;
719 struct survey_info survey[ATH9K_NUM_CHANNELS];
0e2dedf9 720
394cf0a1
S		 721 struct tasklet_struct intr_tq;
722 struct tasklet_struct bcon_tasklet;
cbe61d8a 723 struct ath_hw *sc_ah;
394cf0a1
S		 724 void __iomem *mem;
725 int irq;
2d6a5e95 726 spinlock_t sc_serial_rw;
04717ccd 727 spinlock_t sc_pm_lock;
4bdd1e97 728 spinlock_t sc_pcu_lock;
394cf0a1 729 struct mutex mutex;
9f42c2b6 730 struct work_struct paprd_work;
236de514 731 struct work_struct hw_reset_work;
9f42c2b6 732 struct completion paprd_complete;
10e23181 733 wait_queue_head_t tx_wait;
394cf0a1 734
781b14a3 735 unsigned long sc_flags;
9b60b64b 736 unsigned long driver_data;
cb8d61de 737
071aa9a8 738 u8 gtt_cnt;
17d7904d 739 u32 intrstatus;
1b04b930 740 u16 ps_flags; /* PS_* */
17d7904d 741 u16 curtxpow;
96148326 742 bool ps_enabled;
1dbfd9d4 743 bool ps_idle;
4801416c
BG		 744 short nbcnvifs;
745 short nvifs;
709ade9e 746 unsigned long ps_usecount;
394cf0a1 747
17d7904d 748 struct ath_config config;
394cf0a1
S		 749 struct ath_rx rx;
750 struct ath_tx tx;
751 struct ath_beacon beacon;
394cf0a1
S		 752 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
753
0cf55c21
FF		 754#ifdef CONFIG_MAC80211_LEDS
755 bool led_registered;
756 char led_name[32];
757 struct led_classdev led_cdev;
758#endif
394cf0a1 759
9ac58615 760 struct ath9k_hw_cal_data caldata;
9ac58615 761
a830df07 762#ifdef CONFIG_ATH9K_DEBUGFS
17d7904d 763 struct ath9k_debug debug;
394cf0a1 764#endif
6b96f93e 765 struct ath_beacon_config cur_beacon_conf;
164ace38 766 struct delayed_work tx_complete_work;
181fb18d 767 struct delayed_work hw_pll_work;
bf3dac5a 768 struct timer_list sleep_timer;
4daa7760
SM		 769
770#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2e20250a 771 struct ath_btcoex btcoex;
9e25365f 772 struct ath_mci_coex mci_coex;
3c7992e3 773 struct work_struct mci_work;
4daa7760 774#endif
5088c2f1
VT		 775
776 struct ath_descdma txsdma;
102885a5
VT		 777
778 struct ath_ant_comb ant_comb;
43c35284 779 u8 ant_tx, ant_rx;
8e92d3f2 780 struct dfs_pattern_detector *dfs_detector;
b11e640a 781 u32 wow_enabled;
e93d083f
SW		 782 /* relay(fs) channel for spectral scan */
783 struct rchan *rfs_chan_spec_scan;
784 enum spectral_mode spectral_mode;
04ccd4a1 785 struct ath_spec_scan spec_config;
01c78533 786
89f927af
LR		 787 struct ieee80211_vif *tx99_vif;
788 struct sk_buff *tx99_skb;
789 bool tx99_state;
790 s16 tx99_power;
791
e60001e7 792#ifdef CONFIG_ATH9K_WOW
01c78533
MSS		 793 atomic_t wow_got_bmiss_intr;
794 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
795 u32 wow_intr_before_sleep;
796#endif
394cf0a1
S		 797};
798
ef6b19e4
SM		 799/********/
800/* TX99 */
801/********/
802
803#ifdef CONFIG_ATH9K_TX99
804void ath9k_tx99_init_debug(struct ath_softc *sc);
89f927af
LR		 805int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
806 struct ath_tx_control *txctl);
ef6b19e4
SM		 807#else
808static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
809{
810}
811static inline int ath9k_tx99_send(struct ath_softc *sc,
812 struct sk_buff *skb,
813 struct ath_tx_control *txctl)
814{
815 return 0;
816}
817#endif /* CONFIG_ATH9K_TX99 */
89f927af 818
5bb12791 819static inline void ath_read_cachesize(struct ath_common *common, int *csz)
394cf0a1 820{
5bb12791 821 common->bus_ops->read_cachesize(common, csz);
394cf0a1
S		 822}
823
7b6ef998
SM		 824void ath9k_tasklet(unsigned long data);
825int ath_cabq_update(struct ath_softc *);
313eb87f 826u8 ath9k_parse_mpdudensity(u8 mpdudensity);
394cf0a1 827irqreturn_t ath_isr(int irq, void *dev);
ef6b19e4 828int ath_reset(struct ath_softc *sc);
e60001e7
SM		 829void ath_cancel_work(struct ath_softc *sc);
830void ath_restart_work(struct ath_softc *sc);
eb93e891 831int ath9k_init_device(u16 devid, struct ath_softc *sc,
5bb12791 832 const struct ath_bus_ops *bus_ops);
285f2dda 833void ath9k_deinit_device(struct ath_softc *sc);
43c35284 834void ath9k_reload_chainmask_settings(struct ath_softc *sc);
7b6ef998
SM		 835u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
836void ath_start_rfkill_poll(struct ath_softc *sc);
837void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
838void ath9k_ps_wakeup(struct ath_softc *sc);
839void ath9k_ps_restore(struct ath_softc *sc);
68a89116 840
8e26a030 841#ifdef CONFIG_ATH9K_PCI
394cf0a1
S		 842int ath_pci_init(void);
843void ath_pci_exit(void);
844#else
845static inline int ath_pci_init(void) { return 0; };
846static inline void ath_pci_exit(void) {};
f1dc5600 847#endif
f1dc5600 848
8e26a030 849#ifdef CONFIG_ATH9K_AHB
394cf0a1
S		 850int ath_ahb_init(void);
851void ath_ahb_exit(void);
852#else
853static inline int ath_ahb_init(void) { return 0; };
854static inline void ath_ahb_exit(void) {};
f078f209 855#endif
394cf0a1 856
394cf0a1 857#endif /* ATH9K_H */
Linux kernel - Deliverables
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