Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
394cf0a1 | 22 | #include <linux/leds.h> |
9f42c2b6 | 23 | #include <linux/completion.h> |
98c316e3 | 24 | #include <linux/pm_qos_params.h> |
394cf0a1 | 25 | |
394cf0a1 | 26 | #include "debug.h" |
db86f07e LR |
27 | #include "common.h" |
28 | ||
29 | /* | |
30 | * Header for the ath9k.ko driver core *only* -- hw code nor any other driver | |
31 | * should rely on this file or its contents. | |
32 | */ | |
394cf0a1 S |
33 | |
34 | struct ath_node; | |
35 | ||
36 | /* Macro to expand scalars to 64-bit objects */ | |
37 | ||
13bda122 | 38 | #define ito64(x) (sizeof(x) == 1) ? \ |
394cf0a1 | 39 | (((unsigned long long int)(x)) & (0xff)) : \ |
13bda122 | 40 | (sizeof(x) == 2) ? \ |
394cf0a1 | 41 | (((unsigned long long int)(x)) & 0xffff) : \ |
13bda122 | 42 | ((sizeof(x) == 4) ? \ |
394cf0a1 S |
43 | (((unsigned long long int)(x)) & 0xffffffff) : \ |
44 | (unsigned long long int)(x)) | |
45 | ||
46 | /* increment with wrap-around */ | |
47 | #define INCR(_l, _sz) do { \ | |
48 | (_l)++; \ | |
49 | (_l) &= ((_sz) - 1); \ | |
50 | } while (0) | |
51 | ||
52 | /* decrement with wrap-around */ | |
53 | #define DECR(_l, _sz) do { \ | |
54 | (_l)--; \ | |
55 | (_l) &= ((_sz) - 1); \ | |
56 | } while (0) | |
57 | ||
58 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
59 | ||
4dc3530d MSS |
60 | #define ATH9K_PM_QOS_DEFAULT_VALUE 55 |
61 | ||
394cf0a1 S |
62 | #define TSF_TO_TU(_h,_l) \ |
63 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
64 | ||
65 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
66 | ||
394cf0a1 S |
67 | struct ath_config { |
68 | u32 ath_aggr_prot; | |
69 | u16 txpowlimit; | |
70 | u8 cabqReadytime; | |
394cf0a1 S |
71 | }; |
72 | ||
73 | /*************************/ | |
74 | /* Descriptor Management */ | |
75 | /*************************/ | |
76 | ||
77 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 78 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
79 | (_bf)->bf_lastbf = NULL; \ |
80 | (_bf)->bf_next = NULL; \ | |
81 | memset(&((_bf)->bf_state), 0, \ | |
82 | sizeof(struct ath_buf_state)); \ | |
83 | } while (0) | |
84 | ||
a119cc49 S |
85 | #define ATH_RXBUF_RESET(_bf) do { \ |
86 | (_bf)->bf_stale = false; \ | |
87 | } while (0) | |
88 | ||
394cf0a1 S |
89 | /** |
90 | * enum buffer_type - Buffer type flags | |
91 | * | |
394cf0a1 S |
92 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) |
93 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
94 | * (used in aggregation scheduling) | |
394cf0a1 S |
95 | * @BUF_XRETRY: To denote excessive retries of the buffer |
96 | */ | |
97 | enum buffer_type { | |
436d0d98 MSS |
98 | BUF_AMPDU = BIT(0), |
99 | BUF_AGGR = BIT(1), | |
100 | BUF_XRETRY = BIT(2), | |
394cf0a1 S |
101 | }; |
102 | ||
394cf0a1 S |
103 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) |
104 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
394cf0a1 | 105 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) |
f078f209 | 106 | |
5088c2f1 VT |
107 | #define ATH_TXSTATUS_RING_SIZE 64 |
108 | ||
394cf0a1 | 109 | struct ath_descdma { |
5088c2f1 | 110 | void *dd_desc; |
17d7904d S |
111 | dma_addr_t dd_desc_paddr; |
112 | u32 dd_desc_len; | |
113 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
114 | }; |
115 | ||
116 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
117 | struct list_head *head, const char *name, | |
4adfcded | 118 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
119 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, |
120 | struct list_head *head); | |
121 | ||
122 | /***********/ | |
123 | /* RX / TX */ | |
124 | /***********/ | |
125 | ||
126 | #define ATH_MAX_ANTENNA 3 | |
127 | #define ATH_RXBUF 512 | |
394cf0a1 | 128 | #define ATH_TXBUF 512 |
84642d6b FF |
129 | #define ATH_TXBUF_RESERVE 5 |
130 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 131 | #define ATH_TXMAXTRY 13 |
394cf0a1 | 132 | #define ATH_MGT_TXMAXTRY 4 |
394cf0a1 S |
133 | |
134 | #define TID_TO_WME_AC(_tid) \ | |
135 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
136 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
137 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
138 | WME_AC_VO) | |
139 | ||
394cf0a1 S |
140 | #define ATH_AGGR_DELIM_SZ 4 |
141 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
142 | /* number of delimiters for encryption padding */ | |
143 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
144 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
145 | #define ATH_AGGR_MIN_QDEPTH 2 | |
146 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
394cf0a1 S |
147 | |
148 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
149 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
150 | #define IEEE80211_WEP_IVLEN 3 |
151 | #define IEEE80211_WEP_KIDLEN 1 | |
152 | #define IEEE80211_WEP_CRCLEN 4 | |
153 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
154 | (IEEE80211_WEP_IVLEN + \ | |
155 | IEEE80211_WEP_KIDLEN + \ | |
156 | IEEE80211_WEP_CRCLEN)) | |
157 | ||
158 | /* return whether a bit at index _n in bitmap _bm is set | |
159 | * _sz is the size of the bitmap */ | |
160 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
161 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
162 | ||
163 | /* return block-ack bitmap index given sequence and starting sequence */ | |
164 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
165 | ||
166 | /* returns delimiter padding required given the packet length */ | |
167 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
39ec2997 VT |
168 | (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ |
169 | DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) | |
394cf0a1 S |
170 | |
171 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
172 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
173 | ||
394cf0a1 S |
174 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
175 | ||
164ace38 SB |
176 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
177 | ||
394cf0a1 S |
178 | enum ATH_AGGR_STATUS { |
179 | ATH_AGGR_DONE, | |
180 | ATH_AGGR_BAW_CLOSED, | |
181 | ATH_AGGR_LIMITED, | |
182 | }; | |
183 | ||
e5003249 | 184 | #define ATH_TXFIFO_DEPTH 8 |
394cf0a1 | 185 | struct ath_txq { |
60f2d1d5 BG |
186 | int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ |
187 | u32 axq_qnum; /* ath9k hardware queue number */ | |
17d7904d S |
188 | u32 *axq_link; |
189 | struct list_head axq_q; | |
394cf0a1 | 190 | spinlock_t axq_lock; |
17d7904d | 191 | u32 axq_depth; |
4b3ba66a | 192 | u32 axq_ampdu_depth; |
17d7904d | 193 | bool stopped; |
164ace38 | 194 | bool axq_tx_inprogress; |
394cf0a1 | 195 | struct list_head axq_acq; |
e5003249 VT |
196 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
197 | struct list_head txq_fifo_pending; | |
198 | u8 txq_headidx; | |
199 | u8 txq_tailidx; | |
066dae93 | 200 | int pending_frames; |
394cf0a1 S |
201 | }; |
202 | ||
93ef24b2 | 203 | struct ath_atx_ac { |
066dae93 | 204 | struct ath_txq *txq; |
93ef24b2 | 205 | int sched; |
93ef24b2 S |
206 | struct list_head list; |
207 | struct list_head tid_q; | |
208 | }; | |
209 | ||
2d42efc4 FF |
210 | struct ath_frame_info { |
211 | int framelen; | |
212 | u32 keyix; | |
213 | enum ath9k_key_type keytype; | |
214 | u8 retries; | |
215 | u16 seqno; | |
216 | }; | |
217 | ||
93ef24b2 | 218 | struct ath_buf_state { |
93ef24b2 | 219 | u8 bf_type; |
9f42c2b6 | 220 | u8 bfs_paprd; |
61117f01 | 221 | enum ath9k_internal_frame_type bfs_ftype; |
93ef24b2 S |
222 | }; |
223 | ||
224 | struct ath_buf { | |
225 | struct list_head list; | |
226 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
227 | an aggregate) */ | |
228 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
229 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
230 | void *bf_desc; /* virtual addr of desc */ | |
231 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
c1739eb3 | 232 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
93ef24b2 | 233 | bool bf_stale; |
93ef24b2 S |
234 | u16 bf_flags; |
235 | struct ath_buf_state bf_state; | |
93ef24b2 S |
236 | }; |
237 | ||
238 | struct ath_atx_tid { | |
239 | struct list_head list; | |
240 | struct list_head buf_q; | |
241 | struct ath_node *an; | |
242 | struct ath_atx_ac *ac; | |
81ee13ba | 243 | unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; |
93ef24b2 S |
244 | u16 seq_start; |
245 | u16 seq_next; | |
246 | u16 baw_size; | |
247 | int tidno; | |
248 | int baw_head; /* first un-acked tx buffer */ | |
249 | int baw_tail; /* next unused tx buffer slot */ | |
250 | int sched; | |
251 | int paused; | |
252 | u8 state; | |
253 | }; | |
254 | ||
255 | struct ath_node { | |
7f010c93 BG |
256 | #ifdef CONFIG_ATH9K_DEBUGFS |
257 | struct list_head list; /* for sc->nodes */ | |
258 | struct ieee80211_sta *sta; /* station struct we're part of */ | |
259 | #endif | |
93ef24b2 S |
260 | struct ath_atx_tid tid[WME_NUM_TID]; |
261 | struct ath_atx_ac ac[WME_NUM_AC]; | |
262 | u16 maxampdu; | |
263 | u8 mpdudensity; | |
93ef24b2 S |
264 | }; |
265 | ||
394cf0a1 S |
266 | #define AGGR_CLEANUP BIT(1) |
267 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
268 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
269 | ||
394cf0a1 S |
270 | struct ath_tx_control { |
271 | struct ath_txq *txq; | |
2d42efc4 | 272 | struct ath_node *an; |
394cf0a1 | 273 | int if_id; |
f0ed85c6 | 274 | enum ath9k_internal_frame_type frame_type; |
9f42c2b6 | 275 | u8 paprd; |
394cf0a1 S |
276 | }; |
277 | ||
394cf0a1 S |
278 | #define ATH_TX_ERROR 0x01 |
279 | #define ATH_TX_XRETRY 0x02 | |
280 | #define ATH_TX_BAR 0x04 | |
394cf0a1 | 281 | |
60f2d1d5 BG |
282 | /** |
283 | * @txq_map: Index is mac80211 queue number. This is | |
284 | * not necessarily the same as the hardware queue number | |
285 | * (axq_qnum). | |
286 | */ | |
394cf0a1 S |
287 | struct ath_tx { |
288 | u16 seq_no; | |
289 | u32 txqsetup; | |
394cf0a1 S |
290 | spinlock_t txbuflock; |
291 | struct list_head txbuf; | |
292 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
293 | struct ath_descdma txdma; | |
066dae93 | 294 | struct ath_txq *txq_map[WME_NUM_AC]; |
394cf0a1 S |
295 | }; |
296 | ||
b5c80475 FF |
297 | struct ath_rx_edma { |
298 | struct sk_buff_head rx_fifo; | |
299 | struct sk_buff_head rx_buffers; | |
300 | u32 rx_fifo_hwsize; | |
301 | }; | |
302 | ||
394cf0a1 S |
303 | struct ath_rx { |
304 | u8 defant; | |
305 | u8 rxotherant; | |
306 | u32 *rxlink; | |
394cf0a1 | 307 | unsigned int rxfilter; |
394cf0a1 S |
308 | spinlock_t rxbuflock; |
309 | struct list_head rxbuf; | |
310 | struct ath_descdma rxdma; | |
b5c80475 FF |
311 | struct ath_buf *rx_bufptr; |
312 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; | |
0d95521e FF |
313 | |
314 | struct sk_buff *frag; | |
394cf0a1 S |
315 | }; |
316 | ||
317 | int ath_startrecv(struct ath_softc *sc); | |
318 | bool ath_stoprecv(struct ath_softc *sc); | |
319 | void ath_flushrecv(struct ath_softc *sc); | |
320 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
321 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
322 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 323 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 S |
324 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
325 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
080e1a25 | 326 | bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); |
394cf0a1 S |
327 | void ath_draintxq(struct ath_softc *sc, |
328 | struct ath_txq *txq, bool retry_tx); | |
329 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
330 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
331 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
332 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
797fe5cb | 333 | void ath_tx_cleanup(struct ath_softc *sc); |
394cf0a1 S |
334 | int ath_txq_update(struct ath_softc *sc, int qnum, |
335 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 336 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
337 | struct ath_tx_control *txctl); |
338 | void ath_tx_tasklet(struct ath_softc *sc); | |
e5003249 | 339 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
231c3a1f FF |
340 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
341 | u16 tid, u16 *ssn); | |
f83da965 | 342 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
394cf0a1 S |
343 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
344 | ||
345 | /********/ | |
17d7904d | 346 | /* VIFs */ |
394cf0a1 | 347 | /********/ |
f078f209 | 348 | |
17d7904d | 349 | struct ath_vif { |
394cf0a1 | 350 | int av_bslot; |
4ed96f04 | 351 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 S |
352 | enum nl80211_iftype av_opmode; |
353 | struct ath_buf *av_bcbuf; | |
f0ed85c6 | 354 | u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ |
f078f209 LR |
355 | }; |
356 | ||
394cf0a1 S |
357 | /*******************/ |
358 | /* Beacon Handling */ | |
359 | /*******************/ | |
f078f209 | 360 | |
394cf0a1 S |
361 | /* |
362 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
363 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
364 | * number of beacon intervals, the game's up. | |
365 | */ | |
366 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | |
4ed96f04 | 367 | #define ATH_BCBUF 4 |
394cf0a1 S |
368 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
369 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
370 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
371 | ||
372 | struct ath_beacon_config { | |
373 | u16 beacon_interval; | |
374 | u16 listen_interval; | |
375 | u16 dtim_period; | |
376 | u16 bmiss_timeout; | |
377 | u8 dtim_count; | |
394cf0a1 S |
378 | }; |
379 | ||
380 | struct ath_beacon { | |
381 | enum { | |
382 | OK, /* no change needed */ | |
383 | UPDATE, /* update pending */ | |
384 | COMMIT /* beacon sent, commit change */ | |
385 | } updateslot; /* slot time update fsm */ | |
386 | ||
387 | u32 beaconq; | |
388 | u32 bmisscnt; | |
389 | u32 ast_be_xmit; | |
390 | u64 bc_tstamp; | |
2c3db3d5 | 391 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
394cf0a1 S |
392 | int slottime; |
393 | int slotupdate; | |
394 | struct ath9k_tx_queue_info beacon_qi; | |
395 | struct ath_descdma bdma; | |
396 | struct ath_txq *cabq; | |
397 | struct list_head bbuf; | |
398 | }; | |
399 | ||
9fc9ab0a | 400 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 401 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
9ac58615 | 402 | int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif); |
17d7904d | 403 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
94db2936 | 404 | int ath_beaconq_config(struct ath_softc *sc); |
394cf0a1 S |
405 | |
406 | /*******/ | |
407 | /* ANI */ | |
408 | /*******/ | |
f078f209 | 409 | |
20977d3e S |
410 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
411 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
412 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
413 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
6044474e | 414 | #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ |
20977d3e S |
415 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
416 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 417 | |
ca369eb4 VT |
418 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ |
419 | ||
347809fc | 420 | void ath_hw_check(struct work_struct *work); |
9f42c2b6 | 421 | void ath_paprd_calibrate(struct work_struct *work); |
55624204 S |
422 | void ath_ani_calibrate(unsigned long data); |
423 | ||
0fca65c1 S |
424 | /**********/ |
425 | /* BTCOEX */ | |
426 | /**********/ | |
427 | ||
2e20250a LR |
428 | struct ath_btcoex { |
429 | bool hw_timer_enabled; | |
430 | spinlock_t btcoex_lock; | |
431 | struct timer_list period_timer; /* Timer for BT period */ | |
432 | u32 bt_priority_cnt; | |
433 | unsigned long bt_priority_time; | |
e08a6ace | 434 | int bt_stomp_type; /* Types of BT stomping */ |
2e20250a LR |
435 | u32 btcoex_no_stomp; /* in usec */ |
436 | u32 btcoex_period; /* in usec */ | |
58da1318 | 437 | u32 btscan_no_stomp; /* in usec */ |
75d7839f | 438 | struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ |
2e20250a LR |
439 | }; |
440 | ||
0fca65c1 S |
441 | int ath_init_btcoex_timer(struct ath_softc *sc); |
442 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); | |
443 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
444 | ||
394cf0a1 S |
445 | /********************/ |
446 | /* LED Control */ | |
447 | /********************/ | |
f078f209 | 448 | |
08fc5c1b VN |
449 | #define ATH_LED_PIN_DEF 1 |
450 | #define ATH_LED_PIN_9287 8 | |
394cf0a1 S |
451 | #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ |
452 | #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ | |
f078f209 | 453 | |
394cf0a1 S |
454 | enum ath_led_type { |
455 | ATH_LED_RADIO, | |
456 | ATH_LED_ASSOC, | |
457 | ATH_LED_TX, | |
458 | ATH_LED_RX | |
f078f209 LR |
459 | }; |
460 | ||
394cf0a1 S |
461 | struct ath_led { |
462 | struct ath_softc *sc; | |
463 | struct led_classdev led_cdev; | |
464 | enum ath_led_type led_type; | |
465 | char name[32]; | |
466 | bool registered; | |
f078f209 LR |
467 | }; |
468 | ||
0fca65c1 S |
469 | void ath_init_leds(struct ath_softc *sc); |
470 | void ath_deinit_leds(struct ath_softc *sc); | |
471 | ||
102885a5 VT |
472 | /* Antenna diversity/combining */ |
473 | #define ATH_ANT_RX_CURRENT_SHIFT 4 | |
474 | #define ATH_ANT_RX_MAIN_SHIFT 2 | |
475 | #define ATH_ANT_RX_MASK 0x3 | |
476 | ||
477 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 | |
478 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 | |
479 | #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 | |
480 | #define ATH_ANT_DIV_COMB_INIT_COUNT 95 | |
481 | #define ATH_ANT_DIV_COMB_MAX_COUNT 100 | |
482 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 | |
483 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 | |
484 | ||
485 | #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3 | |
486 | #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 | |
487 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 | |
488 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 | |
489 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 | |
490 | ||
491 | enum ath9k_ant_div_comb_lna_conf { | |
492 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, | |
493 | ATH_ANT_DIV_COMB_LNA2, | |
494 | ATH_ANT_DIV_COMB_LNA1, | |
495 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, | |
496 | }; | |
497 | ||
498 | struct ath_ant_comb { | |
499 | u16 count; | |
500 | u16 total_pkt_count; | |
501 | bool scan; | |
502 | bool scan_not_start; | |
503 | int main_total_rssi; | |
504 | int alt_total_rssi; | |
505 | int alt_recv_cnt; | |
506 | int main_recv_cnt; | |
507 | int rssi_lna1; | |
508 | int rssi_lna2; | |
509 | int rssi_add; | |
510 | int rssi_sub; | |
511 | int rssi_first; | |
512 | int rssi_second; | |
513 | int rssi_third; | |
514 | bool alt_good; | |
515 | int quick_scan_cnt; | |
516 | int main_conf; | |
517 | enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; | |
518 | enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; | |
519 | int first_bias; | |
520 | int second_bias; | |
521 | bool first_ratio; | |
522 | bool second_ratio; | |
523 | unsigned long scan_start_time; | |
524 | }; | |
525 | ||
394cf0a1 S |
526 | /********************/ |
527 | /* Main driver core */ | |
528 | /********************/ | |
f078f209 | 529 | |
394cf0a1 S |
530 | /* |
531 | * Default cache line size, in bytes. | |
532 | * Used when PCI device not fully initialized by bootrom/BIOS | |
533 | */ | |
534 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 S |
535 | #define ATH_REGCLASSIDS_MAX 10 |
536 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
537 | #define ATH_MAX_SW_RETRIES 10 | |
538 | #define ATH_CHAN_MAX 255 | |
f1dc5600 | 539 | |
394cf0a1 | 540 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
394cf0a1 S |
541 | #define ATH_RATE_DUMMY_MARKER 0 |
542 | ||
1b04b930 S |
543 | #define SC_OP_INVALID BIT(0) |
544 | #define SC_OP_BEACONS BIT(1) | |
545 | #define SC_OP_RXAGGR BIT(2) | |
546 | #define SC_OP_TXAGGR BIT(3) | |
5ee08656 | 547 | #define SC_OP_OFFCHANNEL BIT(4) |
1b04b930 S |
548 | #define SC_OP_PREAMBLE_SHORT BIT(5) |
549 | #define SC_OP_PROTECT_ENABLE BIT(6) | |
550 | #define SC_OP_RXFLUSH BIT(7) | |
551 | #define SC_OP_LED_ASSOCIATED BIT(8) | |
552 | #define SC_OP_LED_ON BIT(9) | |
1b04b930 S |
553 | #define SC_OP_TSF_RESET BIT(11) |
554 | #define SC_OP_BT_PRIORITY_DETECTED BIT(12) | |
58da1318 | 555 | #define SC_OP_BT_SCAN BIT(13) |
6c3118e2 | 556 | #define SC_OP_ANI_RUN BIT(14) |
ea066d5a | 557 | #define SC_OP_ENABLE_APM BIT(15) |
1b04b930 S |
558 | |
559 | /* Powersave flags */ | |
560 | #define PS_WAIT_FOR_BEACON BIT(0) | |
561 | #define PS_WAIT_FOR_CAB BIT(1) | |
562 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
563 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
564 | #define PS_BEACON_SYNC BIT(4) | |
394cf0a1 | 565 | |
545750d3 | 566 | struct ath_rate_table; |
bce048d7 | 567 | |
4801416c BG |
568 | struct ath9k_vif_iter_data { |
569 | const u8 *hw_macaddr; /* phy's hardware address, set | |
570 | * before starting iteration for | |
571 | * valid bssid mask. | |
572 | */ | |
573 | u8 mask[ETH_ALEN]; /* bssid mask */ | |
574 | int naps; /* number of AP vifs */ | |
575 | int nmeshes; /* number of mesh vifs */ | |
576 | int nstations; /* number of station vifs */ | |
577 | int nwds; /* number of nwd vifs */ | |
578 | int nadhocs; /* number of adhoc vifs */ | |
579 | int nothers; /* number of vifs not specified above. */ | |
580 | }; | |
581 | ||
394cf0a1 S |
582 | struct ath_softc { |
583 | struct ieee80211_hw *hw; | |
584 | struct device *dev; | |
c52f33d0 | 585 | |
0e2dedf9 JM |
586 | int chan_idx; |
587 | int chan_is_ht; | |
3430098a FF |
588 | struct survey_info *cur_survey; |
589 | struct survey_info survey[ATH9K_NUM_CHANNELS]; | |
0e2dedf9 | 590 | |
394cf0a1 S |
591 | struct tasklet_struct intr_tq; |
592 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 593 | struct ath_hw *sc_ah; |
394cf0a1 S |
594 | void __iomem *mem; |
595 | int irq; | |
2d6a5e95 | 596 | spinlock_t sc_serial_rw; |
04717ccd | 597 | spinlock_t sc_pm_lock; |
4bdd1e97 | 598 | spinlock_t sc_pcu_lock; |
394cf0a1 | 599 | struct mutex mutex; |
9f42c2b6 | 600 | struct work_struct paprd_work; |
347809fc | 601 | struct work_struct hw_check_work; |
9f42c2b6 | 602 | struct completion paprd_complete; |
82259b77 | 603 | bool paprd_pending; |
394cf0a1 | 604 | |
cb8d61de FF |
605 | unsigned int hw_busy_count; |
606 | ||
17d7904d | 607 | u32 intrstatus; |
394cf0a1 | 608 | u32 sc_flags; /* SC_OP_* */ |
1b04b930 | 609 | u16 ps_flags; /* PS_* */ |
17d7904d | 610 | u16 curtxpow; |
96148326 | 611 | bool ps_enabled; |
1dbfd9d4 | 612 | bool ps_idle; |
4801416c BG |
613 | short nbcnvifs; |
614 | short nvifs; | |
709ade9e | 615 | unsigned long ps_usecount; |
394cf0a1 | 616 | |
17d7904d | 617 | struct ath_config config; |
394cf0a1 S |
618 | struct ath_rx rx; |
619 | struct ath_tx tx; | |
620 | struct ath_beacon beacon; | |
394cf0a1 S |
621 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
622 | ||
623 | struct ath_led radio_led; | |
624 | struct ath_led assoc_led; | |
625 | struct ath_led tx_led; | |
626 | struct ath_led rx_led; | |
627 | struct delayed_work ath_led_blink_work; | |
628 | int led_on_duration; | |
629 | int led_off_duration; | |
630 | int led_on_cnt; | |
631 | int led_off_cnt; | |
632 | ||
9ac58615 FF |
633 | struct ath9k_hw_cal_data caldata; |
634 | int last_rssi; | |
635 | ||
57c4d7b4 JB |
636 | int beacon_interval; |
637 | ||
a830df07 | 638 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 639 | struct ath9k_debug debug; |
7f010c93 BG |
640 | spinlock_t nodes_lock; |
641 | struct list_head nodes; /* basically, stations */ | |
60f2d1d5 | 642 | unsigned int tx_complete_poll_work_seen; |
394cf0a1 | 643 | #endif |
6b96f93e | 644 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 645 | struct delayed_work tx_complete_work; |
181fb18d | 646 | struct delayed_work hw_pll_work; |
2e20250a | 647 | struct ath_btcoex btcoex; |
5088c2f1 VT |
648 | |
649 | struct ath_descdma txsdma; | |
102885a5 VT |
650 | |
651 | struct ath_ant_comb ant_comb; | |
98c316e3 GJ |
652 | |
653 | struct pm_qos_request_list pm_qos_req; | |
394cf0a1 S |
654 | }; |
655 | ||
55624204 | 656 | void ath9k_tasklet(unsigned long data); |
394cf0a1 | 657 | int ath_reset(struct ath_softc *sc, bool retry_tx); |
394cf0a1 S |
658 | int ath_cabq_update(struct ath_softc *); |
659 | ||
5bb12791 | 660 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 661 | { |
5bb12791 | 662 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
663 | } |
664 | ||
394cf0a1 | 665 | extern struct ieee80211_ops ath9k_ops; |
3e6109c5 | 666 | extern int ath9k_modparam_nohwcrypt; |
9a75c2ff | 667 | extern int led_blink; |
4dc3530d | 668 | extern int ath9k_pm_qos_value; |
d584747b | 669 | extern bool is_ath9k_unloaded; |
394cf0a1 S |
670 | |
671 | irqreturn_t ath_isr(int irq, void *dev); | |
db7ec38d | 672 | void ath9k_init_crypto(struct ath_softc *sc); |
285f2dda | 673 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
5bb12791 | 674 | const struct ath_bus_ops *bus_ops); |
285f2dda | 675 | void ath9k_deinit_device(struct ath_softc *sc); |
285f2dda | 676 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
0e2dedf9 JM |
677 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
678 | struct ath9k_channel *hchan); | |
68a89116 LR |
679 | |
680 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
681 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
55624204 | 682 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode); |
4801416c | 683 | bool ath9k_uses_beacons(int type); |
394cf0a1 S |
684 | |
685 | #ifdef CONFIG_PCI | |
686 | int ath_pci_init(void); | |
687 | void ath_pci_exit(void); | |
688 | #else | |
689 | static inline int ath_pci_init(void) { return 0; }; | |
690 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 691 | #endif |
f1dc5600 | 692 | |
394cf0a1 S |
693 | #ifdef CONFIG_ATHEROS_AR71XX |
694 | int ath_ahb_init(void); | |
695 | void ath_ahb_exit(void); | |
696 | #else | |
697 | static inline int ath_ahb_init(void) { return 0; }; | |
698 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 699 | #endif |
394cf0a1 | 700 | |
0bc0798b GJ |
701 | void ath9k_ps_wakeup(struct ath_softc *sc); |
702 | void ath9k_ps_restore(struct ath_softc *sc); | |
8ca21f01 | 703 | |
ea066d5a MSS |
704 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); |
705 | ||
31a01645 | 706 | void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif); |
f52de03b | 707 | |
0fca65c1 S |
708 | void ath_start_rfkill_poll(struct ath_softc *sc); |
709 | extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
4801416c BG |
710 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, |
711 | struct ieee80211_vif *vif, | |
712 | struct ath9k_vif_iter_data *iter_data); | |
713 | ||
0fca65c1 | 714 | |
394cf0a1 | 715 | #endif /* ATH9K_H */ |