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ath9k: Fix baseband watchdog reset
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ath9k.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
394cf0a1
S		 20#include <linux/etherdevice.h>
21#include <linux/device.h>
a6b7a407 22#include <linux/interrupt.h>
394cf0a1 23#include <linux/leds.h>
9f42c2b6 24#include <linux/completion.h>
394cf0a1 25
394cf0a1 26#include "debug.h"
db86f07e 27#include "common.h"
7dc181c2 28#include "mci.h"
8e92d3f2 29#include "dfs.h"
f65c0825 30#include "spectral.h"
db86f07e 31
394cf0a1 32struct ath_node;
7b6ef998 33struct ath_rate_table;
394cf0a1 34
7b6ef998
SM		 35extern struct ieee80211_ops ath9k_ops;
36extern int ath9k_modparam_nohwcrypt;
37extern int led_blink;
38extern bool is_ath9k_unloaded;
394cf0a1 39
394cf0a1 40struct ath_config {
394cf0a1 41 u16 txpowlimit;
394cf0a1
S		 42};
43
44/*************************/
45/* Descriptor Management */
46/*************************/
47
7b6ef998
SM		 48#define ATH_TXSTATUS_RING_SIZE 512
49
50/* Macro to expand scalars to 64-bit objects */
51#define ito64(x) (sizeof(x) == 1) ? \
52 (((unsigned long long int)(x)) & (0xff)) : \
53 (sizeof(x) == 2) ? \
54 (((unsigned long long int)(x)) & 0xffff) : \
55 ((sizeof(x) == 4) ? \
56 (((unsigned long long int)(x)) & 0xffffffff) : \
57 (unsigned long long int)(x))
58
394cf0a1 59#define ATH_TXBUF_RESET(_bf) do { \
394cf0a1
S		 60 (_bf)->bf_lastbf = NULL; \
61 (_bf)->bf_next = NULL; \
62 memset(&((_bf)->bf_state), 0, \
63 sizeof(struct ath_buf_state)); \
64 } while (0)
65
c3d77696
MSS		 66#define DS2PHYS(_dd, _ds) \
67 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
68#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
69#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
70
394cf0a1 71struct ath_descdma {
5088c2f1 72 void *dd_desc;
17d7904d
S		 73 dma_addr_t dd_desc_paddr;
74 u32 dd_desc_len;
394cf0a1
S		 75};
76
77int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
78 struct list_head *head, const char *name,
4adfcded 79 int nbuf, int ndesc, bool is_tx);
394cf0a1
S		 80
81/***********/
82/* RX / TX */
83/***********/
84
7b6ef998
SM		 85#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
86
87/* increment with wrap-around */
88#define INCR(_l, _sz) do { \
89 (_l)++; \
90 (_l) &= ((_sz) - 1); \
91 } while (0)
92
394cf0a1 93#define ATH_RXBUF 512
394cf0a1 94#define ATH_TXBUF 512
84642d6b
FF		 95#define ATH_TXBUF_RESERVE 5
96#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
394cf0a1 97#define ATH_TXMAXTRY 13
7b6ef998 98#define ATH_MAX_SW_RETRIES 30
394cf0a1
S		 99
100#define TID_TO_WME_AC(_tid) \
bea843c7
SM		 101 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
102 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \
103 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \
104 IEEE80211_AC_VO)
394cf0a1 105
394cf0a1
S		 106#define ATH_AGGR_DELIM_SZ 4
107#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
108/* number of delimiters for encryption padding */
109#define ATH_AGGR_ENCRYPTDELIM 10
110/* minimum h/w qdepth to be sustained to maximize aggregation */
111#define ATH_AGGR_MIN_QDEPTH 2
2800e82b
FF		 112/* minimum h/w qdepth for non-aggregated traffic */
113#define ATH_NON_AGGR_MIN_QDEPTH 8
7b6ef998
SM		 114#define ATH_TX_COMPLETE_POLL_INT 1000
115#define ATH_TXFIFO_DEPTH 8
116#define ATH_TX_ERROR 0x01
394cf0a1
S		 117
118#define IEEE80211_SEQ_SEQ_SHIFT 4
119#define IEEE80211_SEQ_MAX 4096
394cf0a1
S		 120#define IEEE80211_WEP_IVLEN 3
121#define IEEE80211_WEP_KIDLEN 1
122#define IEEE80211_WEP_CRCLEN 4
123#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
124 (IEEE80211_WEP_IVLEN + \
125 IEEE80211_WEP_KIDLEN + \
126 IEEE80211_WEP_CRCLEN))
127
128/* return whether a bit at index _n in bitmap _bm is set
129 * _sz is the size of the bitmap */
130#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
131 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
132
133/* return block-ack bitmap index given sequence and starting sequence */
134#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
135
156369fa
FF		 136/* return the seqno for _start + _offset */
137#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
138
394cf0a1
S		 139/* returns delimiter padding required given the packet length */
140#define ATH_AGGR_GET_NDELIM(_len) \
39ec2997
VT		 141 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
142 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
394cf0a1
S		 143
144#define BAW_WITHIN(_start, _bawsz, _seqno) \
145 ((((_seqno) - (_start)) & 4095) < (_bawsz))
146
394cf0a1
S		 147#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
148
365d2ebc
SM		 149#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
150
394cf0a1 151struct ath_txq {
60f2d1d5
BG		 152 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
153 u32 axq_qnum; /* ath9k hardware queue number */
fce041be 154 void *axq_link;
17d7904d 155 struct list_head axq_q;
394cf0a1 156 spinlock_t axq_lock;
17d7904d 157 u32 axq_depth;
4b3ba66a 158 u32 axq_ampdu_depth;
17d7904d 159 bool stopped;
164ace38 160 bool axq_tx_inprogress;
394cf0a1 161 struct list_head axq_acq;
e5003249 162 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
e5003249
VT		 163 u8 txq_headidx;
164 u8 txq_tailidx;
066dae93 165 int pending_frames;
23de5dc9 166 struct sk_buff_head complete_q;
394cf0a1
S		 167};
168
93ef24b2 169struct ath_atx_ac {
066dae93 170 struct ath_txq *txq;
93ef24b2
S		 171 struct list_head list;
172 struct list_head tid_q;
5519541d 173 bool clear_ps_filter;
50676b81 174 bool sched;
93ef24b2
S		 175};
176
2d42efc4 177struct ath_frame_info {
56dc6336 178 struct ath_buf *bf;
2d42efc4 179 int framelen;
2d42efc4 180 enum ath9k_key_type keytype;
a75c0629 181 u8 keyix;
80b08a8d 182 u8 rtscts_rate;
8fed1408
FF		 183 u8 retries : 7;
184 u8 baw_tracked : 1;
2d42efc4
FF		 185};
186
1a04d59d
FF		 187struct ath_rxbuf {
188 struct list_head list;
189 struct sk_buff *bf_mpdu;
190 void *bf_desc;
191 dma_addr_t bf_daddr;
192 dma_addr_t bf_buf_addr;
193};
194
7b6ef998
SM		 195/**
196 * enum buffer_type - Buffer type flags
197 *
198 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
199 * @BUF_AGGR: Indicates whether the buffer can be aggregated
200 * (used in aggregation scheduling)
201 */
202enum buffer_type {
203 BUF_AMPDU = BIT(0),
204 BUF_AGGR = BIT(1),
205};
206
207#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
208#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
209
93ef24b2 210struct ath_buf_state {
93ef24b2 211 u8 bf_type;
9f42c2b6 212 u8 bfs_paprd;
399c6489 213 u8 ndelim;
50676b81 214 bool stale;
6a0ddaef 215 u16 seqno;
9cf04dcc 216 unsigned long bfs_paprd_timestamp;
93ef24b2
S		 217};
218
219struct ath_buf {
220 struct list_head list;
221 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
222 an aggregate) */
223 struct ath_buf *bf_next; /* next subframe in the aggregate */
224 struct sk_buff *bf_mpdu; /* enclosing frame structure */
225 void *bf_desc; /* virtual addr of desc */
226 dma_addr_t bf_daddr; /* physical addr of desc */
c1739eb3 227 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
79acac07 228 struct ieee80211_tx_rate rates[4];
93ef24b2 229 struct ath_buf_state bf_state;
93ef24b2
S		 230};
231
232struct ath_atx_tid {
233 struct list_head list;
56dc6336 234 struct sk_buff_head buf_q;
bb195ff6 235 struct sk_buff_head retry_q;
93ef24b2
S		 236 struct ath_node *an;
237 struct ath_atx_ac *ac;
81ee13ba 238 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
93ef24b2
S		 239 u16 seq_start;
240 u16 seq_next;
241 u16 baw_size;
50676b81 242 u8 tidno;
93ef24b2
S		 243 int baw_head; /* first un-acked tx buffer */
244 int baw_tail; /* next unused tx buffer slot */
50676b81
FF		 245
246 s8 bar_index;
08c96abd
FF		 247 bool sched;
248 bool paused;
249 bool active;
93ef24b2
S		 250};
251
252struct ath_node {
a145daf7 253 struct ath_softc *sc;
7f010c93 254 struct ieee80211_sta *sta; /* station struct we're part of */
7e1e3864 255 struct ieee80211_vif *vif; /* interface with which we're associated */
de7b7604 256 struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
bea843c7 257 struct ath_atx_ac ac[IEEE80211_NUM_ACS];
93ae2dd2 258
93ef24b2
S		 259 u16 maxampdu;
260 u8 mpdudensity;
50676b81 261 s8 ps_key;
5519541d
FF		 262
263 bool sleeping;
f89d1bc4 264 bool no_ps_filter;
93ef24b2
S		 265};
266
394cf0a1
S		 267struct ath_tx_control {
268 struct ath_txq *txq;
2d42efc4 269 struct ath_node *an;
9f42c2b6 270 u8 paprd;
36323f81 271 struct ieee80211_sta *sta;
394cf0a1
S		 272};
273
394cf0a1 274
60f2d1d5
BG		 275/**
276 * @txq_map: Index is mac80211 queue number. This is
277 * not necessarily the same as the hardware queue number
278 * (axq_qnum).
279 */
394cf0a1
S		 280struct ath_tx {
281 u16 seq_no;
282 u32 txqsetup;
394cf0a1
S		 283 spinlock_t txbuflock;
284 struct list_head txbuf;
285 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
286 struct ath_descdma txdma;
bea843c7 287 struct ath_txq *txq_map[IEEE80211_NUM_ACS];
f2c7a793 288 struct ath_txq *uapsdq;
bea843c7
SM		 289 u32 txq_max_pending[IEEE80211_NUM_ACS];
290 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
394cf0a1
S		 291};
292
b5c80475
FF		 293struct ath_rx_edma {
294 struct sk_buff_head rx_fifo;
b5c80475
FF		 295 u32 rx_fifo_hwsize;
296};
297
394cf0a1
S		 298struct ath_rx {
299 u8 defant;
300 u8 rxotherant;
723e7113 301 bool discard_next;
394cf0a1 302 u32 *rxlink;
6995fb80 303 u32 num_pkts;
394cf0a1 304 unsigned int rxfilter;
394cf0a1
S		 305 struct list_head rxbuf;
306 struct ath_descdma rxdma;
b5c80475 307 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
0d95521e 308
1a04d59d 309 struct ath_rxbuf *buf_hold;
0d95521e 310 struct sk_buff *frag;
21fbbca3
CL		 311
312 u32 ampdu_ref;
394cf0a1
S		 313};
314
315int ath_startrecv(struct ath_softc *sc);
316bool ath_stoprecv(struct ath_softc *sc);
394cf0a1
S		 317u32 ath_calcrxfilter(struct ath_softc *sc);
318int ath_rx_init(struct ath_softc *sc, int nbufs);
319void ath_rx_cleanup(struct ath_softc *sc);
b5c80475 320int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
394cf0a1 321struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
ef1b6cd9
SM		 322void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
323void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
324void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1 325void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
1381559b
FF		 326bool ath_drain_all_txq(struct ath_softc *sc);
327void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1
S		 328void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
329void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
330void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
331int ath_tx_init(struct ath_softc *sc, int nbufs);
394cf0a1
S		 332int ath_txq_update(struct ath_softc *sc, int qnum,
333 struct ath9k_tx_queue_info *q);
aa5955c3 334void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
c52f33d0 335int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
394cf0a1 336 struct ath_tx_control *txctl);
59505c02
FF		 337void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
338 struct sk_buff *skb);
394cf0a1 339void ath_tx_tasklet(struct ath_softc *sc);
e5003249 340void ath_tx_edma_tasklet(struct ath_softc *sc);
231c3a1f
FF		 341int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
342 u16 tid, u16 *ssn);
f83da965 343void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
394cf0a1
S		 344void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
345
5519541d 346void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
042ec453
JB		 347void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
348 struct ath_node *an);
86a22acf
FF		 349void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
350 struct ieee80211_sta *sta,
351 u16 tids, int nframes,
352 enum ieee80211_frame_release_type reason,
353 bool more_data);
5519541d 354
394cf0a1 355/********/
17d7904d 356/* VIFs */
394cf0a1 357/********/
f078f209 358
17d7904d 359struct ath_vif {
f89d1bc4 360 struct ath_node mcast_node;
394cf0a1 361 int av_bslot;
aa45fe96 362 bool primary_sta_vif;
4ed96f04 363 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
394cf0a1 364 struct ath_buf *av_bcbuf;
f078f209
LR		 365};
366
7b6ef998
SM		 367struct ath9k_vif_iter_data {
368 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
369 u8 mask[ETH_ALEN]; /* bssid mask */
370 bool has_hw_macaddr;
371
372 int naps; /* number of AP vifs */
373 int nmeshes; /* number of mesh vifs */
374 int nstations; /* number of station vifs */
375 int nwds; /* number of WDS vifs */
376 int nadhocs; /* number of adhoc vifs */
377};
378
379void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
380 struct ieee80211_vif *vif,
381 struct ath9k_vif_iter_data *iter_data);
382
394cf0a1
S		 383/*******************/
384/* Beacon Handling */
385/*******************/
f078f209 386
394cf0a1
S		 387/*
388 * Regardless of the number of beacons we stagger, (i.e. regardless of the
389 * number of BSSIDs) if a given beacon does not go out even after waiting this
390 * number of beacon intervals, the game's up.
391 */
c944daf4 392#define BSTUCK_THRESH 9
689e756f 393#define ATH_BCBUF 8
394cf0a1
S		 394#define ATH_DEFAULT_BINTVAL 100 /* TU */
395#define ATH_DEFAULT_BMISS_LIMIT 10
396#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
397
7b6ef998
SM		 398#define TSF_TO_TU(_h,_l) \
399 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
400
394cf0a1 401struct ath_beacon_config {
9814f6b3 402 int beacon_interval;
394cf0a1
S		 403 u16 listen_interval;
404 u16 dtim_period;
405 u16 bmiss_timeout;
406 u8 dtim_count;
ef4ad633 407 bool enable_beacon;
1a6404a1 408 bool ibss_creator;
394cf0a1
S		 409};
410
411struct ath_beacon {
412 enum {
413 OK, /* no change needed */
414 UPDATE, /* update pending */
415 COMMIT /* beacon sent, commit change */
416 } updateslot; /* slot time update fsm */
417
418 u32 beaconq;
419 u32 bmisscnt;
dd347f2f 420 u32 bc_tstamp;
2c3db3d5 421 struct ieee80211_vif *bslot[ATH_BCBUF];
394cf0a1
S		 422 int slottime;
423 int slotupdate;
424 struct ath9k_tx_queue_info beacon_qi;
425 struct ath_descdma bdma;
426 struct ath_txq *cabq;
427 struct list_head bbuf;
ba4903f9
FF		 428
429 bool tx_processed;
430 bool tx_last;
394cf0a1
S		 431};
432
fb6e252f 433void ath9k_beacon_tasklet(unsigned long data);
ef4ad633
SM		 434void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
435 u32 changed);
130ef6e9
SM		 436void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
437void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
ef4ad633 438void ath9k_set_beacon(struct ath_softc *sc);
d074e8d5 439bool ath9k_csa_is_finished(struct ath_softc *sc);
394cf0a1 440
ef1b6cd9
SM		 441/*******************/
442/* Link Monitoring */
443/*******************/
f078f209 444
20977d3e
S		 445#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
446#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
e36b27af
LR		 447#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
448#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
6044474e 449#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
20977d3e
S		 450#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
451#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
7b6ef998
SM		 452#define ATH_ANI_MAX_SKIP_COUNT 10
453#define ATH_PAPRD_TIMEOUT 100 /* msecs */
454#define ATH_PLL_WORK_INTERVAL 100
ca369eb4 455
ef1b6cd9 456void ath_tx_complete_poll_work(struct work_struct *work);
236de514 457void ath_reset_work(struct work_struct *work);
347809fc 458void ath_hw_check(struct work_struct *work);
9eab61c2 459void ath_hw_pll_work(struct work_struct *work);
01e18918
RM		 460void ath_rx_poll(unsigned long data);
461void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
9f42c2b6 462void ath_paprd_calibrate(struct work_struct *work);
55624204 463void ath_ani_calibrate(unsigned long data);
da0d45f7
SM		 464void ath_start_ani(struct ath_softc *sc);
465void ath_stop_ani(struct ath_softc *sc);
466void ath_check_ani(struct ath_softc *sc);
ef1b6cd9
SM		 467int ath_update_survey_stats(struct ath_softc *sc);
468void ath_update_survey_nf(struct ath_softc *sc, int channel);
124b979b 469void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
bf3dac5a 470void ath_ps_full_sleep(unsigned long data);
55624204 471
0fca65c1
S		 472/**********/
473/* BTCOEX */
474/**********/
475
ac46ba43
SM		 476#define ATH_DUMP_BTCOEX(_s, _val) \
477 do { \
5e88ba62
ZK		 478 len += scnprintf(buf + len, size - len, \
479 "%20s : %10d\n", _s, (_val)); \
ac46ba43
SM		 480 } while (0)
481
e6930c4b
SM		 482enum bt_op_flags {
483 BT_OP_PRIORITY_DETECTED,
484 BT_OP_SCAN,
485};
486
2e20250a 487struct ath_btcoex {
2e20250a
LR		 488 spinlock_t btcoex_lock;
489 struct timer_list period_timer; /* Timer for BT period */
168c6f89 490 struct timer_list no_stomp_timer;
2e20250a
LR		 491 u32 bt_priority_cnt;
492 unsigned long bt_priority_time;
e6930c4b 493 unsigned long op_flags;
e08a6ace 494 int bt_stomp_type; /* Types of BT stomping */
168c6f89 495 u32 btcoex_no_stomp; /* in msec */
94ae77ea 496 u32 btcoex_period; /* in msec */
168c6f89 497 u32 btscan_no_stomp; /* in msec */
7dc181c2 498 u32 duty_cycle;
6995fb80 499 u32 bt_wait_time;
e82cb03f 500 int rssi_count;
7dc181c2 501 struct ath_mci_profile mci;
2884561a 502 u8 stomp_audio;
2e20250a
LR		 503};
504
4daa7760 505#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
5908120f
SM		 506int ath9k_init_btcoex(struct ath_softc *sc);
507void ath9k_deinit_btcoex(struct ath_softc *sc);
df198b17
SM		 508void ath9k_start_btcoex(struct ath_softc *sc);
509void ath9k_stop_btcoex(struct ath_softc *sc);
0fca65c1
S		 510void ath9k_btcoex_timer_resume(struct ath_softc *sc);
511void ath9k_btcoex_timer_pause(struct ath_softc *sc);
56ca0dba 512void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
c0ac53fa 513u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
08d4df41 514void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
ac46ba43 515int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
4daa7760
SM		 516#else
517static inline int ath9k_init_btcoex(struct ath_softc *sc)
518{
519 return 0;
520}
521static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
522{
523}
524static inline void ath9k_start_btcoex(struct ath_softc *sc)
525{
526}
527static inline void ath9k_stop_btcoex(struct ath_softc *sc)
528{
529}
530static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
531 u32 status)
532{
533}
534static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
535 u32 max_4ms_framelen)
536{
537 return 0;
538}
08d4df41
RM		 539static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
540{
541}
ac46ba43 542static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
4df50ca8
RM		 543{
544 return 0;
545}
4daa7760 546#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0fca65c1 547
394cf0a1
S		 548/********************/
549/* LED Control */
550/********************/
f078f209 551
08fc5c1b
VN		 552#define ATH_LED_PIN_DEF 1
553#define ATH_LED_PIN_9287 8
353e5019 554#define ATH_LED_PIN_9300 10
15178535 555#define ATH_LED_PIN_9485 6
1a68abb0 556#define ATH_LED_PIN_9462 4
f078f209 557
0cf55c21 558#ifdef CONFIG_MAC80211_LEDS
0fca65c1
S		 559void ath_init_leds(struct ath_softc *sc);
560void ath_deinit_leds(struct ath_softc *sc);
8f176a3a 561void ath_fill_led_pin(struct ath_softc *sc);
0cf55c21
FF		 562#else
563static inline void ath_init_leds(struct ath_softc *sc)
564{
565}
566
567static inline void ath_deinit_leds(struct ath_softc *sc)
8f176a3a
RM		 568{
569}
570static inline void ath_fill_led_pin(struct ath_softc *sc)
0cf55c21
FF		 571{
572}
573#endif
574
e60001e7
SM		 575/************************/
576/* Wake on Wireless LAN */
577/************************/
578
7b6ef998
SM		 579struct ath9k_wow_pattern {
580 u8 pattern_bytes[MAX_PATTERN_SIZE];
581 u8 mask_bytes[MAX_PATTERN_SIZE];
582 u32 pattern_len;
583};
584
e60001e7 585#ifdef CONFIG_ATH9K_WOW
babaa80a 586void ath9k_init_wow(struct ieee80211_hw *hw);
e60001e7
SM		 587int ath9k_suspend(struct ieee80211_hw *hw,
588 struct cfg80211_wowlan *wowlan);
589int ath9k_resume(struct ieee80211_hw *hw);
590void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
591#else
babaa80a
SM		 592static inline void ath9k_init_wow(struct ieee80211_hw *hw)
593{
594}
e60001e7
SM		 595static inline int ath9k_suspend(struct ieee80211_hw *hw,
596 struct cfg80211_wowlan *wowlan)
597{
598 return 0;
599}
600static inline int ath9k_resume(struct ieee80211_hw *hw)
601{
602 return 0;
603}
604static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
605{
606}
607#endif /* CONFIG_ATH9K_WOW */
608
8da07830 609/*******************************/
102885a5 610/* Antenna diversity/combining */
8da07830
SM		 611/*******************************/
612
102885a5
VT		 613#define ATH_ANT_RX_CURRENT_SHIFT 4
614#define ATH_ANT_RX_MAIN_SHIFT 2
615#define ATH_ANT_RX_MASK 0x3
616
617#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
618#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
619#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
620#define ATH_ANT_DIV_COMB_INIT_COUNT 95
621#define ATH_ANT_DIV_COMB_MAX_COUNT 100
622#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
623#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
3afa6b4f
SM		 624#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50
625#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50
102885a5 626
102885a5
VT		 627#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
628#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
629#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
630
102885a5
VT		 631struct ath_ant_comb {
632 u16 count;
633 u16 total_pkt_count;
634 bool scan;
635 bool scan_not_start;
636 int main_total_rssi;
637 int alt_total_rssi;
638 int alt_recv_cnt;
639 int main_recv_cnt;
640 int rssi_lna1;
641 int rssi_lna2;
642 int rssi_add;
643 int rssi_sub;
644 int rssi_first;
645 int rssi_second;
646 int rssi_third;
3afa6b4f
SM		 647 int ant_ratio;
648 int ant_ratio2;
102885a5
VT		 649 bool alt_good;
650 int quick_scan_cnt;
3fbaf4c5 651 enum ath9k_ant_div_comb_lna_conf main_conf;
102885a5
VT		 652 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
653 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
102885a5
VT		 654 bool first_ratio;
655 bool second_ratio;
656 unsigned long scan_start_time;
3afa6b4f
SM		 657
658 /*
659 * Card-specific config values.
660 */
661 int low_rssi_thresh;
662 int fast_div_bias;
102885a5
VT		 663};
664
8da07830 665void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
8da07830 666
394cf0a1
S		 667/********************/
668/* Main driver core */
669/********************/
f078f209 670
2d22c7dd
SM		 671#define ATH9K_PCI_CUS198 0x0001
672#define ATH9K_PCI_CUS230 0x0002
673#define ATH9K_PCI_CUS217 0x0004
674#define ATH9K_PCI_CUS252 0x0008
675#define ATH9K_PCI_WOW 0x0010
676#define ATH9K_PCI_BT_ANT_DIV 0x0020
677#define ATH9K_PCI_D3_L1_WAR 0x0040
678#define ATH9K_PCI_AR9565_1ANT 0x0080
679#define ATH9K_PCI_AR9565_2ANT 0x0100
680#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
4dd35640 681#define ATH9K_PCI_KILLER 0x0400
9b60b64b 682
394cf0a1
S		 683/*
684 * Default cache line size, in bytes.
685 * Used when PCI device not fully initialized by bootrom/BIOS
686*/
687#define DEFAULT_CACHELINE 32
394cf0a1 688#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
394cf0a1 689#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
394cf0a1 690
781b14a3
SM		 691enum sc_op_flags {
692 SC_OP_INVALID,
693 SC_OP_BEACONS,
781b14a3
SM		 694 SC_OP_ANI_RUN,
695 SC_OP_PRIM_STA_VIF,
b74713d0 696 SC_OP_HW_RESET,
73900cb0 697 SC_OP_SCANNING,
781b14a3 698};
1b04b930
S		 699
700/* Powersave flags */
701#define PS_WAIT_FOR_BEACON BIT(0)
702#define PS_WAIT_FOR_CAB BIT(1)
703#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
704#define PS_WAIT_FOR_TX_ACK BIT(3)
705#define PS_BEACON_SYNC BIT(4)
424749c7 706#define PS_WAIT_FOR_ANI BIT(5)
394cf0a1 707
394cf0a1
S		 708struct ath_softc {
709 struct ieee80211_hw *hw;
710 struct device *dev;
c52f33d0 711
3430098a
FF		 712 struct survey_info *cur_survey;
713 struct survey_info survey[ATH9K_NUM_CHANNELS];
0e2dedf9 714
394cf0a1
S		 715 struct tasklet_struct intr_tq;
716 struct tasklet_struct bcon_tasklet;
cbe61d8a 717 struct ath_hw *sc_ah;
394cf0a1
S		 718 void __iomem *mem;
719 int irq;
2d6a5e95 720 spinlock_t sc_serial_rw;
04717ccd 721 spinlock_t sc_pm_lock;
4bdd1e97 722 spinlock_t sc_pcu_lock;
394cf0a1 723 struct mutex mutex;
9f42c2b6 724 struct work_struct paprd_work;
347809fc 725 struct work_struct hw_check_work;
236de514 726 struct work_struct hw_reset_work;
9f42c2b6 727 struct completion paprd_complete;
10e23181 728 wait_queue_head_t tx_wait;
394cf0a1 729
cb8d61de 730 unsigned int hw_busy_count;
781b14a3 731 unsigned long sc_flags;
9b60b64b 732 unsigned long driver_data;
cb8d61de 733
17d7904d 734 u32 intrstatus;
1b04b930 735 u16 ps_flags; /* PS_* */
17d7904d 736 u16 curtxpow;
96148326 737 bool ps_enabled;
1dbfd9d4 738 bool ps_idle;
4801416c
BG		 739 short nbcnvifs;
740 short nvifs;
709ade9e 741 unsigned long ps_usecount;
394cf0a1 742
17d7904d 743 struct ath_config config;
394cf0a1
S		 744 struct ath_rx rx;
745 struct ath_tx tx;
746 struct ath_beacon beacon;
394cf0a1
S		 747 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
748
0cf55c21
FF		 749#ifdef CONFIG_MAC80211_LEDS
750 bool led_registered;
751 char led_name[32];
752 struct led_classdev led_cdev;
753#endif
394cf0a1 754
9ac58615
FF		 755 struct ath9k_hw_cal_data caldata;
756 int last_rssi;
757
a830df07 758#ifdef CONFIG_ATH9K_DEBUGFS
17d7904d 759 struct ath9k_debug debug;
394cf0a1 760#endif
6b96f93e 761 struct ath_beacon_config cur_beacon_conf;
164ace38 762 struct delayed_work tx_complete_work;
181fb18d 763 struct delayed_work hw_pll_work;
01e18918 764 struct timer_list rx_poll_timer;
bf3dac5a 765 struct timer_list sleep_timer;
4daa7760
SM		 766
767#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2e20250a 768 struct ath_btcoex btcoex;
9e25365f 769 struct ath_mci_coex mci_coex;
3c7992e3 770 struct work_struct mci_work;
4daa7760 771#endif
5088c2f1
VT		 772
773 struct ath_descdma txsdma;
d074e8d5 774 struct ieee80211_vif *csa_vif;
102885a5
VT		 775
776 struct ath_ant_comb ant_comb;
43c35284 777 u8 ant_tx, ant_rx;
8e92d3f2 778 struct dfs_pattern_detector *dfs_detector;
b11e640a 779 u32 wow_enabled;
e93d083f
SW		 780 /* relay(fs) channel for spectral scan */
781 struct rchan *rfs_chan_spec_scan;
782 enum spectral_mode spectral_mode;
04ccd4a1 783 struct ath_spec_scan spec_config;
01c78533 784
89f927af
LR		 785 struct ieee80211_vif *tx99_vif;
786 struct sk_buff *tx99_skb;
787 bool tx99_state;
788 s16 tx99_power;
789
e60001e7 790#ifdef CONFIG_ATH9K_WOW
01c78533
MSS		 791 atomic_t wow_got_bmiss_intr;
792 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
793 u32 wow_intr_before_sleep;
794#endif
394cf0a1
S		 795};
796
ef6b19e4
SM		 797/********/
798/* TX99 */
799/********/
800
801#ifdef CONFIG_ATH9K_TX99
802void ath9k_tx99_init_debug(struct ath_softc *sc);
89f927af
LR		 803int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
804 struct ath_tx_control *txctl);
ef6b19e4
SM		 805#else
806static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
807{
808}
809static inline int ath9k_tx99_send(struct ath_softc *sc,
810 struct sk_buff *skb,
811 struct ath_tx_control *txctl)
812{
813 return 0;
814}
815#endif /* CONFIG_ATH9K_TX99 */
89f927af 816
5bb12791 817static inline void ath_read_cachesize(struct ath_common *common, int *csz)
394cf0a1 818{
5bb12791 819 common->bus_ops->read_cachesize(common, csz);
394cf0a1
S		 820}
821
7b6ef998
SM		 822void ath9k_tasklet(unsigned long data);
823int ath_cabq_update(struct ath_softc *);
313eb87f 824u8 ath9k_parse_mpdudensity(u8 mpdudensity);
394cf0a1 825irqreturn_t ath_isr(int irq, void *dev);
ef6b19e4 826int ath_reset(struct ath_softc *sc);
e60001e7
SM		 827void ath_cancel_work(struct ath_softc *sc);
828void ath_restart_work(struct ath_softc *sc);
eb93e891 829int ath9k_init_device(u16 devid, struct ath_softc *sc,
5bb12791 830 const struct ath_bus_ops *bus_ops);
285f2dda 831void ath9k_deinit_device(struct ath_softc *sc);
43c35284 832void ath9k_reload_chainmask_settings(struct ath_softc *sc);
7b6ef998
SM		 833u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
834void ath_start_rfkill_poll(struct ath_softc *sc);
835void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
836void ath9k_ps_wakeup(struct ath_softc *sc);
837void ath9k_ps_restore(struct ath_softc *sc);
68a89116 838
8e26a030 839#ifdef CONFIG_ATH9K_PCI
394cf0a1
S		 840int ath_pci_init(void);
841void ath_pci_exit(void);
842#else
843static inline int ath_pci_init(void) { return 0; };
844static inline void ath_pci_exit(void) {};
f1dc5600 845#endif
f1dc5600 846
8e26a030 847#ifdef CONFIG_ATH9K_AHB
394cf0a1
S		 848int ath_ahb_init(void);
849void ath_ahb_exit(void);
850#else
851static inline int ath_ahb_init(void) { return 0; };
852static inline void ath_ahb_exit(void) {};
f078f209 853#endif
394cf0a1 854
394cf0a1 855#endif /* ATH9K_H */
Linux kernel - Deliverables
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