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ath9k: Reconfigure VIF state properly
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ath9k.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
394cf0a1
S		 20#include <linux/etherdevice.h>
21#include <linux/device.h>
a6b7a407 22#include <linux/interrupt.h>
394cf0a1 23#include <linux/leds.h>
9f42c2b6 24#include <linux/completion.h>
394cf0a1 25
394cf0a1 26#include "debug.h"
db86f07e 27#include "common.h"
7dc181c2 28#include "mci.h"
8e92d3f2 29#include "dfs.h"
db86f07e
LR		 30
31/*
32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
33 * should rely on this file or its contents.
34 */
394cf0a1
S		 35
36struct ath_node;
37
38/* Macro to expand scalars to 64-bit objects */
39
13bda122 40#define ito64(x) (sizeof(x) == 1) ? \
394cf0a1 41 (((unsigned long long int)(x)) & (0xff)) : \
13bda122 42 (sizeof(x) == 2) ? \
394cf0a1 43 (((unsigned long long int)(x)) & 0xffff) : \
13bda122 44 ((sizeof(x) == 4) ? \
394cf0a1
S		 45 (((unsigned long long int)(x)) & 0xffffffff) : \
46 (unsigned long long int)(x))
47
48/* increment with wrap-around */
49#define INCR(_l, _sz) do { \
50 (_l)++; \
51 (_l) &= ((_sz) - 1); \
52 } while (0)
53
54/* decrement with wrap-around */
55#define DECR(_l, _sz) do { \
56 (_l)--; \
57 (_l) &= ((_sz) - 1); \
58 } while (0)
59
394cf0a1
S		 60#define TSF_TO_TU(_h,_l) \
61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
62
63#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
64
394cf0a1 65struct ath_config {
394cf0a1
S		 66 u16 txpowlimit;
67 u8 cabqReadytime;
394cf0a1
S		 68};
69
70/*************************/
71/* Descriptor Management */
72/*************************/
73
74#define ATH_TXBUF_RESET(_bf) do { \
a119cc49 75 (_bf)->bf_stale = false; \
394cf0a1
S		 76 (_bf)->bf_lastbf = NULL; \
77 (_bf)->bf_next = NULL; \
78 memset(&((_bf)->bf_state), 0, \
79 sizeof(struct ath_buf_state)); \
80 } while (0)
81
a119cc49
S		 82#define ATH_RXBUF_RESET(_bf) do { \
83 (_bf)->bf_stale = false; \
84 } while (0)
85
394cf0a1
S		 86/**
87 * enum buffer_type - Buffer type flags
88 *
394cf0a1
S		 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
90 * @BUF_AGGR: Indicates whether the buffer can be aggregated
91 * (used in aggregation scheduling)
394cf0a1
S		 92 */
93enum buffer_type {
436d0d98
MSS		 94 BUF_AMPDU = BIT(0),
95 BUF_AGGR = BIT(1),
394cf0a1
S		 96};
97
394cf0a1
S		 98#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
99#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
f078f209 100
016c2177 101#define ATH_TXSTATUS_RING_SIZE 512
5088c2f1 102
c3d77696
MSS		 103#define DS2PHYS(_dd, _ds) \
104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
105#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
106#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
107
394cf0a1 108struct ath_descdma {
5088c2f1 109 void *dd_desc;
17d7904d
S		 110 dma_addr_t dd_desc_paddr;
111 u32 dd_desc_len;
112 struct ath_buf *dd_bufptr;
394cf0a1
S		 113};
114
115int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
116 struct list_head *head, const char *name,
4adfcded 117 int nbuf, int ndesc, bool is_tx);
394cf0a1
S		 118void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
119 struct list_head *head);
120
121/***********/
122/* RX / TX */
123/***********/
124
394cf0a1 125#define ATH_RXBUF 512
394cf0a1 126#define ATH_TXBUF 512
84642d6b
FF		 127#define ATH_TXBUF_RESERVE 5
128#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
394cf0a1 129#define ATH_TXMAXTRY 13
394cf0a1
S		 130
131#define TID_TO_WME_AC(_tid) \
132 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
133 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
134 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
135 WME_AC_VO)
136
394cf0a1
S		 137#define ATH_AGGR_DELIM_SZ 4
138#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
139/* number of delimiters for encryption padding */
140#define ATH_AGGR_ENCRYPTDELIM 10
141/* minimum h/w qdepth to be sustained to maximize aggregation */
142#define ATH_AGGR_MIN_QDEPTH 2
143#define ATH_AMPDU_SUBFRAME_DEFAULT 32
394cf0a1
S		 144
145#define IEEE80211_SEQ_SEQ_SHIFT 4
146#define IEEE80211_SEQ_MAX 4096
394cf0a1
S		 147#define IEEE80211_WEP_IVLEN 3
148#define IEEE80211_WEP_KIDLEN 1
149#define IEEE80211_WEP_CRCLEN 4
150#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
151 (IEEE80211_WEP_IVLEN + \
152 IEEE80211_WEP_KIDLEN + \
153 IEEE80211_WEP_CRCLEN))
154
155/* return whether a bit at index _n in bitmap _bm is set
156 * _sz is the size of the bitmap */
157#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
158 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
159
160/* return block-ack bitmap index given sequence and starting sequence */
161#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
162
156369fa
FF		 163/* return the seqno for _start + _offset */
164#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
165
394cf0a1
S		 166/* returns delimiter padding required given the packet length */
167#define ATH_AGGR_GET_NDELIM(_len) \
39ec2997
VT		 168 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
169 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
394cf0a1
S		 170
171#define BAW_WITHIN(_start, _bawsz, _seqno) \
172 ((((_seqno) - (_start)) & 4095) < (_bawsz))
173
394cf0a1
S		 174#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
175
164ace38
SB		 176#define ATH_TX_COMPLETE_POLL_INT 1000
177
394cf0a1
S		 178enum ATH_AGGR_STATUS {
179 ATH_AGGR_DONE,
180 ATH_AGGR_BAW_CLOSED,
181 ATH_AGGR_LIMITED,
182};
183
e5003249 184#define ATH_TXFIFO_DEPTH 8
394cf0a1 185struct ath_txq {
60f2d1d5
BG		 186 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
187 u32 axq_qnum; /* ath9k hardware queue number */
fce041be 188 void *axq_link;
17d7904d 189 struct list_head axq_q;
394cf0a1 190 spinlock_t axq_lock;
17d7904d 191 u32 axq_depth;
4b3ba66a 192 u32 axq_ampdu_depth;
17d7904d 193 bool stopped;
164ace38 194 bool axq_tx_inprogress;
394cf0a1 195 struct list_head axq_acq;
e5003249 196 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
e5003249
VT		 197 u8 txq_headidx;
198 u8 txq_tailidx;
066dae93 199 int pending_frames;
23de5dc9 200 struct sk_buff_head complete_q;
394cf0a1
S		 201};
202
93ef24b2 203struct ath_atx_ac {
066dae93 204 struct ath_txq *txq;
93ef24b2 205 int sched;
93ef24b2
S		 206 struct list_head list;
207 struct list_head tid_q;
5519541d 208 bool clear_ps_filter;
93ef24b2
S		 209};
210
2d42efc4 211struct ath_frame_info {
56dc6336 212 struct ath_buf *bf;
2d42efc4 213 int framelen;
2d42efc4 214 enum ath9k_key_type keytype;
a75c0629 215 u8 keyix;
2d42efc4 216 u8 retries;
80b08a8d 217 u8 rtscts_rate;
2d42efc4
FF		 218};
219
93ef24b2 220struct ath_buf_state {
93ef24b2 221 u8 bf_type;
9f42c2b6 222 u8 bfs_paprd;
399c6489 223 u8 ndelim;
6a0ddaef 224 u16 seqno;
9cf04dcc 225 unsigned long bfs_paprd_timestamp;
93ef24b2
S		 226};
227
228struct ath_buf {
229 struct list_head list;
230 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
231 an aggregate) */
232 struct ath_buf *bf_next; /* next subframe in the aggregate */
233 struct sk_buff *bf_mpdu; /* enclosing frame structure */
234 void *bf_desc; /* virtual addr of desc */
235 dma_addr_t bf_daddr; /* physical addr of desc */
c1739eb3 236 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
93ef24b2 237 bool bf_stale;
93ef24b2 238 struct ath_buf_state bf_state;
93ef24b2
S		 239};
240
241struct ath_atx_tid {
242 struct list_head list;
56dc6336 243 struct sk_buff_head buf_q;
93ef24b2
S		 244 struct ath_node *an;
245 struct ath_atx_ac *ac;
81ee13ba 246 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
f9437543 247 int bar_index;
93ef24b2
S		 248 u16 seq_start;
249 u16 seq_next;
250 u16 baw_size;
251 int tidno;
252 int baw_head; /* first un-acked tx buffer */
253 int baw_tail; /* next unused tx buffer slot */
254 int sched;
255 int paused;
256 u8 state;
257};
258
259struct ath_node {
7f010c93
BG		 260#ifdef CONFIG_ATH9K_DEBUGFS
261 struct list_head list; /* for sc->nodes */
156369fa 262#endif
7f010c93 263 struct ieee80211_sta *sta; /* station struct we're part of */
7e1e3864 264 struct ieee80211_vif *vif; /* interface with which we're associated */
93ef24b2
S		 265 struct ath_atx_tid tid[WME_NUM_TID];
266 struct ath_atx_ac ac[WME_NUM_AC];
93ae2dd2
FF		 267 int ps_key;
268
93ef24b2
S		 269 u16 maxampdu;
270 u8 mpdudensity;
5519541d
FF		 271
272 bool sleeping;
93ef24b2
S		 273};
274
394cf0a1
S		 275#define AGGR_CLEANUP BIT(1)
276#define AGGR_ADDBA_COMPLETE BIT(2)
277#define AGGR_ADDBA_PROGRESS BIT(3)
278
394cf0a1
S		 279struct ath_tx_control {
280 struct ath_txq *txq;
2d42efc4 281 struct ath_node *an;
9f42c2b6 282 u8 paprd;
394cf0a1
S		 283};
284
394cf0a1 285#define ATH_TX_ERROR 0x01
394cf0a1 286
60f2d1d5
BG		 287/**
288 * @txq_map: Index is mac80211 queue number. This is
289 * not necessarily the same as the hardware queue number
290 * (axq_qnum).
291 */
394cf0a1
S		 292struct ath_tx {
293 u16 seq_no;
294 u32 txqsetup;
394cf0a1
S		 295 spinlock_t txbuflock;
296 struct list_head txbuf;
297 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
298 struct ath_descdma txdma;
066dae93 299 struct ath_txq *txq_map[WME_NUM_AC];
7702e788 300 u32 txq_max_pending[WME_NUM_AC];
aa5955c3 301 u16 max_aggr_framelen[WME_NUM_AC][4][32];
394cf0a1
S		 302};
303
b5c80475
FF		 304struct ath_rx_edma {
305 struct sk_buff_head rx_fifo;
b5c80475
FF		 306 u32 rx_fifo_hwsize;
307};
308
394cf0a1
S		 309struct ath_rx {
310 u8 defant;
311 u8 rxotherant;
312 u32 *rxlink;
6995fb80 313 u32 num_pkts;
394cf0a1 314 unsigned int rxfilter;
394cf0a1
S		 315 spinlock_t rxbuflock;
316 struct list_head rxbuf;
317 struct ath_descdma rxdma;
b5c80475
FF		 318 struct ath_buf *rx_bufptr;
319 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
0d95521e
FF		 320
321 struct sk_buff *frag;
394cf0a1
S		 322};
323
324int ath_startrecv(struct ath_softc *sc);
325bool ath_stoprecv(struct ath_softc *sc);
326void ath_flushrecv(struct ath_softc *sc);
327u32 ath_calcrxfilter(struct ath_softc *sc);
328int ath_rx_init(struct ath_softc *sc, int nbufs);
329void ath_rx_cleanup(struct ath_softc *sc);
b5c80475 330int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
394cf0a1 331struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
ef1b6cd9
SM		 332void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
333void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
334void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1 335void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
080e1a25 336bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
394cf0a1
S		 337void ath_draintxq(struct ath_softc *sc,
338 struct ath_txq *txq, bool retry_tx);
339void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
340void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
341void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
342int ath_tx_init(struct ath_softc *sc, int nbufs);
797fe5cb 343void ath_tx_cleanup(struct ath_softc *sc);
394cf0a1
S		 344int ath_txq_update(struct ath_softc *sc, int qnum,
345 struct ath9k_tx_queue_info *q);
aa5955c3 346void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
c52f33d0 347int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
394cf0a1
S		 348 struct ath_tx_control *txctl);
349void ath_tx_tasklet(struct ath_softc *sc);
e5003249 350void ath_tx_edma_tasklet(struct ath_softc *sc);
231c3a1f
FF		 351int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
352 u16 tid, u16 *ssn);
f83da965 353void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
394cf0a1
S		 354void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
355
5519541d 356void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
042ec453
JB		 357void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
358 struct ath_node *an);
5519541d 359
394cf0a1 360/********/
17d7904d 361/* VIFs */
394cf0a1 362/********/
f078f209 363
17d7904d 364struct ath_vif {
394cf0a1 365 int av_bslot;
aa45fe96 366 bool primary_sta_vif;
4ed96f04 367 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
394cf0a1 368 struct ath_buf *av_bcbuf;
f078f209
LR		 369};
370
394cf0a1
S		 371/*******************/
372/* Beacon Handling */
373/*******************/
f078f209 374
394cf0a1
S		 375/*
376 * Regardless of the number of beacons we stagger, (i.e. regardless of the
377 * number of BSSIDs) if a given beacon does not go out even after waiting this
378 * number of beacon intervals, the game's up.
379 */
c944daf4 380#define BSTUCK_THRESH 9
689e756f 381#define ATH_BCBUF 8
394cf0a1
S		 382#define ATH_DEFAULT_BINTVAL 100 /* TU */
383#define ATH_DEFAULT_BMISS_LIMIT 10
384#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
385
386struct ath_beacon_config {
9814f6b3 387 int beacon_interval;
394cf0a1
S		 388 u16 listen_interval;
389 u16 dtim_period;
390 u16 bmiss_timeout;
391 u8 dtim_count;
ef4ad633 392 bool enable_beacon;
394cf0a1
S		 393};
394
395struct ath_beacon {
396 enum {
397 OK, /* no change needed */
398 UPDATE, /* update pending */
399 COMMIT /* beacon sent, commit change */
400 } updateslot; /* slot time update fsm */
401
402 u32 beaconq;
403 u32 bmisscnt;
dd347f2f 404 u32 bc_tstamp;
2c3db3d5 405 struct ieee80211_vif *bslot[ATH_BCBUF];
394cf0a1
S		 406 int slottime;
407 int slotupdate;
408 struct ath9k_tx_queue_info beacon_qi;
409 struct ath_descdma bdma;
410 struct ath_txq *cabq;
411 struct list_head bbuf;
ba4903f9
FF		 412
413 bool tx_processed;
414 bool tx_last;
394cf0a1
S		 415};
416
fb6e252f 417void ath9k_beacon_tasklet(unsigned long data);
ef4ad633
SM		 418bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
419void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
420 u32 changed);
130ef6e9
SM		 421void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
422void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
2f8e82e8 423void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
ef4ad633 424void ath9k_set_beacon(struct ath_softc *sc);
014cf3bb 425void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
394cf0a1 426
ef1b6cd9
SM		 427/*******************/
428/* Link Monitoring */
429/*******************/
f078f209 430
20977d3e
S		 431#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
432#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
e36b27af
LR		 433#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
434#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
6044474e 435#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
20977d3e
S		 436#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
437#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
f078f209 438
ca369eb4 439#define ATH_PAPRD_TIMEOUT 100 /* msecs */
af68abad 440#define ATH_PLL_WORK_INTERVAL 100
ca369eb4 441
ef1b6cd9 442void ath_tx_complete_poll_work(struct work_struct *work);
236de514 443void ath_reset_work(struct work_struct *work);
347809fc 444void ath_hw_check(struct work_struct *work);
9eab61c2 445void ath_hw_pll_work(struct work_struct *work);
01e18918
RM		 446void ath_rx_poll(unsigned long data);
447void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
9f42c2b6 448void ath_paprd_calibrate(struct work_struct *work);
55624204 449void ath_ani_calibrate(unsigned long data);
da0d45f7
SM		 450void ath_start_ani(struct ath_softc *sc);
451void ath_stop_ani(struct ath_softc *sc);
452void ath_check_ani(struct ath_softc *sc);
ef1b6cd9
SM		 453int ath_update_survey_stats(struct ath_softc *sc);
454void ath_update_survey_nf(struct ath_softc *sc, int channel);
55624204 455
0fca65c1
S		 456/**********/
457/* BTCOEX */
458/**********/
459
e6930c4b
SM		 460enum bt_op_flags {
461 BT_OP_PRIORITY_DETECTED,
462 BT_OP_SCAN,
463};
464
2e20250a
LR		 465struct ath_btcoex {
466 bool hw_timer_enabled;
467 spinlock_t btcoex_lock;
468 struct timer_list period_timer; /* Timer for BT period */
469 u32 bt_priority_cnt;
470 unsigned long bt_priority_time;
e6930c4b 471 unsigned long op_flags;
e08a6ace 472 int bt_stomp_type; /* Types of BT stomping */
2e20250a
LR		 473 u32 btcoex_no_stomp; /* in usec */
474 u32 btcoex_period; /* in usec */
58da1318 475 u32 btscan_no_stomp; /* in usec */
7dc181c2 476 u32 duty_cycle;
6995fb80 477 u32 bt_wait_time;
75d7839f 478 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
7dc181c2 479 struct ath_mci_profile mci;
2e20250a
LR		 480};
481
4daa7760 482#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
5908120f
SM		 483int ath9k_init_btcoex(struct ath_softc *sc);
484void ath9k_deinit_btcoex(struct ath_softc *sc);
df198b17
SM		 485void ath9k_start_btcoex(struct ath_softc *sc);
486void ath9k_stop_btcoex(struct ath_softc *sc);
0fca65c1
S		 487void ath9k_btcoex_timer_resume(struct ath_softc *sc);
488void ath9k_btcoex_timer_pause(struct ath_softc *sc);
56ca0dba 489void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
c0ac53fa 490u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
08d4df41 491void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
4daa7760
SM		 492#else
493static inline int ath9k_init_btcoex(struct ath_softc *sc)
494{
495 return 0;
496}
497static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
498{
499}
500static inline void ath9k_start_btcoex(struct ath_softc *sc)
501{
502}
503static inline void ath9k_stop_btcoex(struct ath_softc *sc)
504{
505}
506static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
507 u32 status)
508{
509}
510static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
511 u32 max_4ms_framelen)
512{
513 return 0;
514}
08d4df41
RM		 515static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
516{
517}
4daa7760 518#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0fca65c1 519
01c78533
MSS		 520struct ath9k_wow_pattern {
521 u8 pattern_bytes[MAX_PATTERN_SIZE];
522 u8 mask_bytes[MAX_PATTERN_SIZE];
523 u32 pattern_len;
524};
525
394cf0a1
S		 526/********************/
527/* LED Control */
528/********************/
f078f209 529
08fc5c1b
VN		 530#define ATH_LED_PIN_DEF 1
531#define ATH_LED_PIN_9287 8
353e5019 532#define ATH_LED_PIN_9300 10
15178535 533#define ATH_LED_PIN_9485 6
1a68abb0 534#define ATH_LED_PIN_9462 4
f078f209 535
0cf55c21 536#ifdef CONFIG_MAC80211_LEDS
0fca65c1
S		 537void ath_init_leds(struct ath_softc *sc);
538void ath_deinit_leds(struct ath_softc *sc);
0cf55c21
FF		 539#else
540static inline void ath_init_leds(struct ath_softc *sc)
541{
542}
543
544static inline void ath_deinit_leds(struct ath_softc *sc)
545{
546}
547#endif
548
8da07830 549/*******************************/
102885a5 550/* Antenna diversity/combining */
8da07830
SM		 551/*******************************/
552
102885a5
VT		 553#define ATH_ANT_RX_CURRENT_SHIFT 4
554#define ATH_ANT_RX_MAIN_SHIFT 2
555#define ATH_ANT_RX_MASK 0x3
556
557#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
558#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
559#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
560#define ATH_ANT_DIV_COMB_INIT_COUNT 95
561#define ATH_ANT_DIV_COMB_MAX_COUNT 100
562#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
563#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
564
102885a5
VT		 565#define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
566#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
567#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
568#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
569
570enum ath9k_ant_div_comb_lna_conf {
571 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
572 ATH_ANT_DIV_COMB_LNA2,
573 ATH_ANT_DIV_COMB_LNA1,
574 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
575};
576
577struct ath_ant_comb {
578 u16 count;
579 u16 total_pkt_count;
580 bool scan;
581 bool scan_not_start;
582 int main_total_rssi;
583 int alt_total_rssi;
584 int alt_recv_cnt;
585 int main_recv_cnt;
586 int rssi_lna1;
587 int rssi_lna2;
588 int rssi_add;
589 int rssi_sub;
590 int rssi_first;
591 int rssi_second;
592 int rssi_third;
593 bool alt_good;
594 int quick_scan_cnt;
595 int main_conf;
596 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
597 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
598 int first_bias;
599 int second_bias;
600 bool first_ratio;
601 bool second_ratio;
602 unsigned long scan_start_time;
603};
604
8da07830
SM		 605void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
606void ath_ant_comb_update(struct ath_softc *sc);
607
394cf0a1
S		 608/********************/
609/* Main driver core */
610/********************/
f078f209 611
394cf0a1
S		 612/*
613 * Default cache line size, in bytes.
614 * Used when PCI device not fully initialized by bootrom/BIOS
615*/
616#define DEFAULT_CACHELINE 32
394cf0a1
S		 617#define ATH_REGCLASSIDS_MAX 10
618#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
da647626 619#define ATH_MAX_SW_RETRIES 30
394cf0a1 620#define ATH_CHAN_MAX 255
f1dc5600 621
394cf0a1 622#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
394cf0a1
S		 623#define ATH_RATE_DUMMY_MARKER 0
624
781b14a3
SM		 625enum sc_op_flags {
626 SC_OP_INVALID,
627 SC_OP_BEACONS,
628 SC_OP_RXFLUSH,
781b14a3
SM		 629 SC_OP_ANI_RUN,
630 SC_OP_PRIM_STA_VIF,
b74713d0 631 SC_OP_HW_RESET,
781b14a3 632};
1b04b930
S		 633
634/* Powersave flags */
635#define PS_WAIT_FOR_BEACON BIT(0)
636#define PS_WAIT_FOR_CAB BIT(1)
637#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
638#define PS_WAIT_FOR_TX_ACK BIT(3)
639#define PS_BEACON_SYNC BIT(4)
394cf0a1 640
545750d3 641struct ath_rate_table;
bce048d7 642
4801416c
BG		 643struct ath9k_vif_iter_data {
644 const u8 *hw_macaddr; /* phy's hardware address, set
645 * before starting iteration for
646 * valid bssid mask.
647 */
648 u8 mask[ETH_ALEN]; /* bssid mask */
649 int naps; /* number of AP vifs */
650 int nmeshes; /* number of mesh vifs */
651 int nstations; /* number of station vifs */
e707549a 652 int nwds; /* number of WDS vifs */
4801416c 653 int nadhocs; /* number of adhoc vifs */
4801416c
BG		 654};
655
394cf0a1
S		 656struct ath_softc {
657 struct ieee80211_hw *hw;
658 struct device *dev;
c52f33d0 659
3430098a
FF		 660 struct survey_info *cur_survey;
661 struct survey_info survey[ATH9K_NUM_CHANNELS];
0e2dedf9 662
394cf0a1
S		 663 struct tasklet_struct intr_tq;
664 struct tasklet_struct bcon_tasklet;
cbe61d8a 665 struct ath_hw *sc_ah;
394cf0a1
S		 666 void __iomem *mem;
667 int irq;
2d6a5e95 668 spinlock_t sc_serial_rw;
04717ccd 669 spinlock_t sc_pm_lock;
4bdd1e97 670 spinlock_t sc_pcu_lock;
394cf0a1 671 struct mutex mutex;
9f42c2b6 672 struct work_struct paprd_work;
347809fc 673 struct work_struct hw_check_work;
236de514 674 struct work_struct hw_reset_work;
9f42c2b6 675 struct completion paprd_complete;
394cf0a1 676
cb8d61de 677 unsigned int hw_busy_count;
781b14a3 678 unsigned long sc_flags;
cb8d61de 679
17d7904d 680 u32 intrstatus;
1b04b930 681 u16 ps_flags; /* PS_* */
17d7904d 682 u16 curtxpow;
96148326 683 bool ps_enabled;
1dbfd9d4 684 bool ps_idle;
4801416c
BG		 685 short nbcnvifs;
686 short nvifs;
709ade9e 687 unsigned long ps_usecount;
394cf0a1 688
17d7904d 689 struct ath_config config;
394cf0a1
S		 690 struct ath_rx rx;
691 struct ath_tx tx;
692 struct ath_beacon beacon;
394cf0a1
S		 693 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
694
0cf55c21
FF		 695#ifdef CONFIG_MAC80211_LEDS
696 bool led_registered;
697 char led_name[32];
698 struct led_classdev led_cdev;
699#endif
394cf0a1 700
9ac58615
FF		 701 struct ath9k_hw_cal_data caldata;
702 int last_rssi;
703
a830df07 704#ifdef CONFIG_ATH9K_DEBUGFS
17d7904d 705 struct ath9k_debug debug;
7f010c93
BG		 706 spinlock_t nodes_lock;
707 struct list_head nodes; /* basically, stations */
60f2d1d5 708 unsigned int tx_complete_poll_work_seen;
394cf0a1 709#endif
6b96f93e 710 struct ath_beacon_config cur_beacon_conf;
164ace38 711 struct delayed_work tx_complete_work;
181fb18d 712 struct delayed_work hw_pll_work;
01e18918 713 struct timer_list rx_poll_timer;
4daa7760
SM		 714
715#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2e20250a 716 struct ath_btcoex btcoex;
9e25365f 717 struct ath_mci_coex mci_coex;
3c7992e3 718 struct work_struct mci_work;
4daa7760 719#endif
5088c2f1
VT		 720
721 struct ath_descdma txsdma;
102885a5
VT		 722
723 struct ath_ant_comb ant_comb;
43c35284 724 u8 ant_tx, ant_rx;
8e92d3f2 725 struct dfs_pattern_detector *dfs_detector;
b11e640a 726 u32 wow_enabled;
01c78533
MSS		 727
728#ifdef CONFIG_PM_SLEEP
729 atomic_t wow_got_bmiss_intr;
730 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
731 u32 wow_intr_before_sleep;
732#endif
394cf0a1
S		 733};
734
55624204 735void ath9k_tasklet(unsigned long data);
394cf0a1
S		 736int ath_cabq_update(struct ath_softc *);
737
5bb12791 738static inline void ath_read_cachesize(struct ath_common *common, int *csz)
394cf0a1 739{
5bb12791 740 common->bus_ops->read_cachesize(common, csz);
394cf0a1
S		 741}
742
394cf0a1 743extern struct ieee80211_ops ath9k_ops;
3e6109c5 744extern int ath9k_modparam_nohwcrypt;
9a75c2ff 745extern int led_blink;
d584747b 746extern bool is_ath9k_unloaded;
394cf0a1 747
313eb87f 748u8 ath9k_parse_mpdudensity(u8 mpdudensity);
394cf0a1 749irqreturn_t ath_isr(int irq, void *dev);
eb93e891 750int ath9k_init_device(u16 devid, struct ath_softc *sc,
5bb12791 751 const struct ath_bus_ops *bus_ops);
285f2dda 752void ath9k_deinit_device(struct ath_softc *sc);
285f2dda 753void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
43c35284 754void ath9k_reload_chainmask_settings(struct ath_softc *sc);
68a89116 755
4801416c 756bool ath9k_uses_beacons(int type);
394cf0a1 757
8e26a030 758#ifdef CONFIG_ATH9K_PCI
394cf0a1
S		 759int ath_pci_init(void);
760void ath_pci_exit(void);
761#else
762static inline int ath_pci_init(void) { return 0; };
763static inline void ath_pci_exit(void) {};
f1dc5600 764#endif
f1dc5600 765
8e26a030 766#ifdef CONFIG_ATH9K_AHB
394cf0a1
S		 767int ath_ahb_init(void);
768void ath_ahb_exit(void);
769#else
770static inline int ath_ahb_init(void) { return 0; };
771static inline void ath_ahb_exit(void) {};
f078f209 772#endif
394cf0a1 773
0bc0798b
GJ		 774void ath9k_ps_wakeup(struct ath_softc *sc);
775void ath9k_ps_restore(struct ath_softc *sc);
8ca21f01 776
ea066d5a
MSS		 777u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
778
0fca65c1
S		 779void ath_start_rfkill_poll(struct ath_softc *sc);
780extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
4801416c
BG		 781void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
782 struct ieee80211_vif *vif,
783 struct ath9k_vif_iter_data *iter_data);
784
394cf0a1 785#endif /* ATH9K_H */
Linux kernel - Deliverables
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