Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
a6b7a407 | 22 | #include <linux/interrupt.h> |
394cf0a1 | 23 | #include <linux/leds.h> |
9f42c2b6 | 24 | #include <linux/completion.h> |
8d7e09dd | 25 | #include <linux/time.h> |
394cf0a1 | 26 | |
db86f07e | 27 | #include "common.h" |
9d83cd5c | 28 | #include "debug.h" |
7dc181c2 | 29 | #include "mci.h" |
8e92d3f2 | 30 | #include "dfs.h" |
f65c0825 | 31 | #include "spectral.h" |
db86f07e | 32 | |
394cf0a1 S |
33 | struct ath_node; |
34 | ||
7b6ef998 SM |
35 | extern struct ieee80211_ops ath9k_ops; |
36 | extern int ath9k_modparam_nohwcrypt; | |
37 | extern int led_blink; | |
38 | extern bool is_ath9k_unloaded; | |
78b21949 | 39 | extern int ath9k_use_chanctx; |
394cf0a1 | 40 | |
394cf0a1 S |
41 | /*************************/ |
42 | /* Descriptor Management */ | |
43 | /*************************/ | |
44 | ||
7b6ef998 SM |
45 | #define ATH_TXSTATUS_RING_SIZE 512 |
46 | ||
47 | /* Macro to expand scalars to 64-bit objects */ | |
48 | #define ito64(x) (sizeof(x) == 1) ? \ | |
49 | (((unsigned long long int)(x)) & (0xff)) : \ | |
50 | (sizeof(x) == 2) ? \ | |
51 | (((unsigned long long int)(x)) & 0xffff) : \ | |
52 | ((sizeof(x) == 4) ? \ | |
53 | (((unsigned long long int)(x)) & 0xffffffff) : \ | |
54 | (unsigned long long int)(x)) | |
55 | ||
394cf0a1 | 56 | #define ATH_TXBUF_RESET(_bf) do { \ |
394cf0a1 S |
57 | (_bf)->bf_lastbf = NULL; \ |
58 | (_bf)->bf_next = NULL; \ | |
59 | memset(&((_bf)->bf_state), 0, \ | |
60 | sizeof(struct ath_buf_state)); \ | |
61 | } while (0) | |
62 | ||
c3d77696 MSS |
63 | #define DS2PHYS(_dd, _ds) \ |
64 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
65 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
66 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
67 | ||
394cf0a1 | 68 | struct ath_descdma { |
5088c2f1 | 69 | void *dd_desc; |
17d7904d S |
70 | dma_addr_t dd_desc_paddr; |
71 | u32 dd_desc_len; | |
394cf0a1 S |
72 | }; |
73 | ||
74 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
75 | struct list_head *head, const char *name, | |
4adfcded | 76 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
77 | |
78 | /***********/ | |
79 | /* RX / TX */ | |
80 | /***********/ | |
81 | ||
7b6ef998 SM |
82 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) |
83 | ||
84 | /* increment with wrap-around */ | |
85 | #define INCR(_l, _sz) do { \ | |
86 | (_l)++; \ | |
87 | (_l) &= ((_sz) - 1); \ | |
88 | } while (0) | |
89 | ||
394cf0a1 | 90 | #define ATH_RXBUF 512 |
394cf0a1 | 91 | #define ATH_TXBUF 512 |
84642d6b FF |
92 | #define ATH_TXBUF_RESERVE 5 |
93 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 94 | #define ATH_TXMAXTRY 13 |
7b6ef998 | 95 | #define ATH_MAX_SW_RETRIES 30 |
394cf0a1 S |
96 | |
97 | #define TID_TO_WME_AC(_tid) \ | |
bea843c7 SM |
98 | ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ |
99 | (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ | |
100 | (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ | |
101 | IEEE80211_AC_VO) | |
394cf0a1 | 102 | |
394cf0a1 S |
103 | #define ATH_AGGR_DELIM_SZ 4 |
104 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
105 | /* number of delimiters for encryption padding */ | |
106 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
107 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
108 | #define ATH_AGGR_MIN_QDEPTH 2 | |
2800e82b FF |
109 | /* minimum h/w qdepth for non-aggregated traffic */ |
110 | #define ATH_NON_AGGR_MIN_QDEPTH 8 | |
7b6ef998 SM |
111 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
112 | #define ATH_TXFIFO_DEPTH 8 | |
113 | #define ATH_TX_ERROR 0x01 | |
394cf0a1 | 114 | |
d463af4a FF |
115 | /* Stop tx traffic 1ms before the GO goes away */ |
116 | #define ATH_P2P_PS_STOP_TIME 1000 | |
117 | ||
394cf0a1 S |
118 | #define IEEE80211_SEQ_SEQ_SHIFT 4 |
119 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
120 | #define IEEE80211_WEP_IVLEN 3 |
121 | #define IEEE80211_WEP_KIDLEN 1 | |
122 | #define IEEE80211_WEP_CRCLEN 4 | |
123 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
124 | (IEEE80211_WEP_IVLEN + \ | |
125 | IEEE80211_WEP_KIDLEN + \ | |
126 | IEEE80211_WEP_CRCLEN)) | |
127 | ||
128 | /* return whether a bit at index _n in bitmap _bm is set | |
129 | * _sz is the size of the bitmap */ | |
130 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
131 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
132 | ||
133 | /* return block-ack bitmap index given sequence and starting sequence */ | |
134 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
135 | ||
156369fa FF |
136 | /* return the seqno for _start + _offset */ |
137 | #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) | |
138 | ||
394cf0a1 S |
139 | /* returns delimiter padding required given the packet length */ |
140 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
39ec2997 VT |
141 | (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ |
142 | DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) | |
394cf0a1 S |
143 | |
144 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
145 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
146 | ||
394cf0a1 S |
147 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
148 | ||
350e2dcb SM |
149 | #define IS_HT_RATE(rate) (rate & 0x80) |
150 | #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) | |
151 | #define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf)) | |
365d2ebc | 152 | |
9e495a26 SM |
153 | enum { |
154 | WLAN_RC_PHY_OFDM, | |
155 | WLAN_RC_PHY_CCK, | |
156 | }; | |
157 | ||
394cf0a1 | 158 | struct ath_txq { |
60f2d1d5 BG |
159 | int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ |
160 | u32 axq_qnum; /* ath9k hardware queue number */ | |
fce041be | 161 | void *axq_link; |
17d7904d | 162 | struct list_head axq_q; |
394cf0a1 | 163 | spinlock_t axq_lock; |
17d7904d | 164 | u32 axq_depth; |
4b3ba66a | 165 | u32 axq_ampdu_depth; |
17d7904d | 166 | bool stopped; |
164ace38 | 167 | bool axq_tx_inprogress; |
e5003249 | 168 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
e5003249 VT |
169 | u8 txq_headidx; |
170 | u8 txq_tailidx; | |
066dae93 | 171 | int pending_frames; |
23de5dc9 | 172 | struct sk_buff_head complete_q; |
394cf0a1 S |
173 | }; |
174 | ||
93ef24b2 | 175 | struct ath_atx_ac { |
066dae93 | 176 | struct ath_txq *txq; |
93ef24b2 S |
177 | struct list_head list; |
178 | struct list_head tid_q; | |
5519541d | 179 | bool clear_ps_filter; |
50676b81 | 180 | bool sched; |
93ef24b2 S |
181 | }; |
182 | ||
2d42efc4 | 183 | struct ath_frame_info { |
56dc6336 | 184 | struct ath_buf *bf; |
2d42efc4 | 185 | int framelen; |
2d42efc4 | 186 | enum ath9k_key_type keytype; |
a75c0629 | 187 | u8 keyix; |
80b08a8d | 188 | u8 rtscts_rate; |
8fed1408 FF |
189 | u8 retries : 7; |
190 | u8 baw_tracked : 1; | |
2d42efc4 FF |
191 | }; |
192 | ||
1a04d59d FF |
193 | struct ath_rxbuf { |
194 | struct list_head list; | |
195 | struct sk_buff *bf_mpdu; | |
196 | void *bf_desc; | |
197 | dma_addr_t bf_daddr; | |
198 | dma_addr_t bf_buf_addr; | |
199 | }; | |
200 | ||
7b6ef998 SM |
201 | /** |
202 | * enum buffer_type - Buffer type flags | |
203 | * | |
204 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
205 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
206 | * (used in aggregation scheduling) | |
207 | */ | |
208 | enum buffer_type { | |
209 | BUF_AMPDU = BIT(0), | |
210 | BUF_AGGR = BIT(1), | |
211 | }; | |
212 | ||
213 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
214 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
215 | ||
93ef24b2 | 216 | struct ath_buf_state { |
93ef24b2 | 217 | u8 bf_type; |
9f42c2b6 | 218 | u8 bfs_paprd; |
399c6489 | 219 | u8 ndelim; |
50676b81 | 220 | bool stale; |
6a0ddaef | 221 | u16 seqno; |
9cf04dcc | 222 | unsigned long bfs_paprd_timestamp; |
93ef24b2 S |
223 | }; |
224 | ||
225 | struct ath_buf { | |
226 | struct list_head list; | |
227 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
228 | an aggregate) */ | |
229 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
230 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
231 | void *bf_desc; /* virtual addr of desc */ | |
232 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
c1739eb3 | 233 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
79acac07 | 234 | struct ieee80211_tx_rate rates[4]; |
93ef24b2 | 235 | struct ath_buf_state bf_state; |
93ef24b2 S |
236 | }; |
237 | ||
238 | struct ath_atx_tid { | |
239 | struct list_head list; | |
56dc6336 | 240 | struct sk_buff_head buf_q; |
bb195ff6 | 241 | struct sk_buff_head retry_q; |
93ef24b2 S |
242 | struct ath_node *an; |
243 | struct ath_atx_ac *ac; | |
81ee13ba | 244 | unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; |
93ef24b2 S |
245 | u16 seq_start; |
246 | u16 seq_next; | |
247 | u16 baw_size; | |
50676b81 | 248 | u8 tidno; |
93ef24b2 S |
249 | int baw_head; /* first un-acked tx buffer */ |
250 | int baw_tail; /* next unused tx buffer slot */ | |
50676b81 FF |
251 | |
252 | s8 bar_index; | |
08c96abd | 253 | bool sched; |
08c96abd | 254 | bool active; |
93ef24b2 S |
255 | }; |
256 | ||
257 | struct ath_node { | |
a145daf7 | 258 | struct ath_softc *sc; |
7f010c93 | 259 | struct ieee80211_sta *sta; /* station struct we're part of */ |
7e1e3864 | 260 | struct ieee80211_vif *vif; /* interface with which we're associated */ |
de7b7604 | 261 | struct ath_atx_tid tid[IEEE80211_NUM_TIDS]; |
bea843c7 | 262 | struct ath_atx_ac ac[IEEE80211_NUM_ACS]; |
93ae2dd2 | 263 | |
93ef24b2 S |
264 | u16 maxampdu; |
265 | u8 mpdudensity; | |
50676b81 | 266 | s8 ps_key; |
5519541d FF |
267 | |
268 | bool sleeping; | |
f89d1bc4 | 269 | bool no_ps_filter; |
350e2dcb SM |
270 | |
271 | #ifdef CONFIG_ATH9K_STATION_STATISTICS | |
272 | struct ath_rx_rate_stats rx_rate_stats; | |
273 | #endif | |
4bbf4414 | 274 | u8 key_idx[4]; |
93ef24b2 S |
275 | }; |
276 | ||
394cf0a1 S |
277 | struct ath_tx_control { |
278 | struct ath_txq *txq; | |
2d42efc4 | 279 | struct ath_node *an; |
36323f81 | 280 | struct ieee80211_sta *sta; |
befcf7e7 FF |
281 | u8 paprd; |
282 | bool force_channel; | |
394cf0a1 S |
283 | }; |
284 | ||
394cf0a1 | 285 | |
60f2d1d5 BG |
286 | /** |
287 | * @txq_map: Index is mac80211 queue number. This is | |
288 | * not necessarily the same as the hardware queue number | |
289 | * (axq_qnum). | |
290 | */ | |
394cf0a1 S |
291 | struct ath_tx { |
292 | u16 seq_no; | |
293 | u32 txqsetup; | |
394cf0a1 S |
294 | spinlock_t txbuflock; |
295 | struct list_head txbuf; | |
296 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
297 | struct ath_descdma txdma; | |
bea843c7 | 298 | struct ath_txq *txq_map[IEEE80211_NUM_ACS]; |
f2c7a793 | 299 | struct ath_txq *uapsdq; |
bea843c7 SM |
300 | u32 txq_max_pending[IEEE80211_NUM_ACS]; |
301 | u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; | |
394cf0a1 S |
302 | }; |
303 | ||
b5c80475 FF |
304 | struct ath_rx_edma { |
305 | struct sk_buff_head rx_fifo; | |
b5c80475 FF |
306 | u32 rx_fifo_hwsize; |
307 | }; | |
308 | ||
394cf0a1 S |
309 | struct ath_rx { |
310 | u8 defant; | |
311 | u8 rxotherant; | |
723e7113 | 312 | bool discard_next; |
394cf0a1 | 313 | u32 *rxlink; |
6995fb80 | 314 | u32 num_pkts; |
394cf0a1 | 315 | unsigned int rxfilter; |
394cf0a1 S |
316 | struct list_head rxbuf; |
317 | struct ath_descdma rxdma; | |
b5c80475 | 318 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; |
0d95521e | 319 | |
1a04d59d | 320 | struct ath_rxbuf *buf_hold; |
0d95521e | 321 | struct sk_buff *frag; |
21fbbca3 CL |
322 | |
323 | u32 ampdu_ref; | |
394cf0a1 S |
324 | }; |
325 | ||
fbbcd146 FF |
326 | struct ath_chanctx { |
327 | struct cfg80211_chan_def chandef; | |
328 | struct list_head vifs; | |
0453531e FF |
329 | struct list_head acq[IEEE80211_NUM_ACS]; |
330 | ||
9a9c4fbc RM |
331 | /* do not dereference, use for comparison only */ |
332 | struct ieee80211_vif *primary_sta; | |
333 | ||
ca900ac9 | 334 | struct ath_beacon_config beacon; |
b01459e8 | 335 | struct ath9k_hw_cal_data caldata; |
8d7e09dd FF |
336 | struct timespec tsf_ts; |
337 | u64 tsf_val; | |
58b57375 | 338 | u32 last_beacon; |
b01459e8 | 339 | |
bc7e1be7 | 340 | u16 txpower; |
fbbcd146 | 341 | bool offchannel; |
bff11766 | 342 | bool stopped; |
c083ce99 | 343 | bool active; |
39305635 | 344 | bool assigned; |
748299f2 FF |
345 | bool switch_after_beacon; |
346 | }; | |
347 | ||
348 | enum ath_chanctx_event { | |
349 | ATH_CHANCTX_EVENT_BEACON_PREPARE, | |
350 | ATH_CHANCTX_EVENT_BEACON_SENT, | |
351 | ATH_CHANCTX_EVENT_TSF_TIMER, | |
58b57375 | 352 | ATH_CHANCTX_EVENT_BEACON_RECEIVED, |
73fa2f26 FF |
353 | ATH_CHANCTX_EVENT_ASSOC, |
354 | ATH_CHANCTX_EVENT_SWITCH, | |
355 | ATH_CHANCTX_EVENT_UNASSIGN, | |
356 | ATH_CHANCTX_EVENT_ENABLE_MULTICHANNEL, | |
748299f2 FF |
357 | }; |
358 | ||
359 | enum ath_chanctx_state { | |
360 | ATH_CHANCTX_STATE_IDLE, | |
361 | ATH_CHANCTX_STATE_WAIT_FOR_BEACON, | |
362 | ATH_CHANCTX_STATE_WAIT_FOR_TIMER, | |
363 | ATH_CHANCTX_STATE_SWITCH, | |
6036c284 | 364 | ATH_CHANCTX_STATE_FORCE_ACTIVE, |
748299f2 FF |
365 | }; |
366 | ||
367 | struct ath_chanctx_sched { | |
368 | bool beacon_pending; | |
73fa2f26 | 369 | bool offchannel_pending; |
748299f2 FF |
370 | enum ath_chanctx_state state; |
371 | ||
372 | u32 next_tbtt; | |
3ae07d39 FF |
373 | u32 switch_start_time; |
374 | unsigned int offchannel_duration; | |
748299f2 | 375 | unsigned int channel_switch_time; |
fbbcd146 FF |
376 | }; |
377 | ||
78b21949 FF |
378 | enum ath_offchannel_state { |
379 | ATH_OFFCHANNEL_IDLE, | |
380 | ATH_OFFCHANNEL_PROBE_SEND, | |
381 | ATH_OFFCHANNEL_PROBE_WAIT, | |
382 | ATH_OFFCHANNEL_SUSPEND, | |
405393cf FF |
383 | ATH_OFFCHANNEL_ROC_START, |
384 | ATH_OFFCHANNEL_ROC_WAIT, | |
385 | ATH_OFFCHANNEL_ROC_DONE, | |
78b21949 FF |
386 | }; |
387 | ||
388 | struct ath_offchannel { | |
389 | struct ath_chanctx chan; | |
390 | struct timer_list timer; | |
391 | struct cfg80211_scan_request *scan_req; | |
392 | struct ieee80211_vif *scan_vif; | |
393 | int scan_idx; | |
394 | enum ath_offchannel_state state; | |
405393cf FF |
395 | struct ieee80211_channel *roc_chan; |
396 | struct ieee80211_vif *roc_vif; | |
397 | int roc_duration; | |
ea6ff2de | 398 | int duration; |
78b21949 | 399 | }; |
c4dc0d04 RM |
400 | #define ath_for_each_chanctx(_sc, _ctx) \ |
401 | for (ctx = &sc->chanctx[0]; \ | |
402 | ctx <= &sc->chanctx[ARRAY_SIZE(sc->chanctx) - 1]; \ | |
403 | ctx++) | |
78b21949 FF |
404 | |
405 | void ath9k_fill_chanctx_ops(void); | |
6036c284 FF |
406 | void ath9k_chanctx_force_active(struct ieee80211_hw *hw, |
407 | struct ieee80211_vif *vif); | |
39305635 FF |
408 | static inline struct ath_chanctx * |
409 | ath_chanctx_get(struct ieee80211_chanctx_conf *ctx) | |
410 | { | |
411 | struct ath_chanctx **ptr = (void *) ctx->drv_priv; | |
412 | return *ptr; | |
413 | } | |
fbbcd146 | 414 | void ath_chanctx_init(struct ath_softc *sc); |
bff11766 FF |
415 | void ath_chanctx_set_channel(struct ath_softc *sc, struct ath_chanctx *ctx, |
416 | struct cfg80211_chan_def *chandef); | |
417 | void ath_chanctx_switch(struct ath_softc *sc, struct ath_chanctx *ctx, | |
418 | struct cfg80211_chan_def *chandef); | |
c083ce99 | 419 | void ath_chanctx_check_active(struct ath_softc *sc, struct ath_chanctx *ctx); |
78b21949 FF |
420 | void ath_offchannel_timer(unsigned long data); |
421 | void ath_offchannel_channel_change(struct ath_softc *sc); | |
422 | void ath_chanctx_offchan_switch(struct ath_softc *sc, | |
423 | struct ieee80211_channel *chan); | |
c4dc0d04 RM |
424 | struct ath_chanctx *ath_chanctx_get_oper_chan(struct ath_softc *sc, |
425 | bool active); | |
748299f2 FF |
426 | void ath_chanctx_event(struct ath_softc *sc, struct ieee80211_vif *vif, |
427 | enum ath_chanctx_event ev); | |
c083ce99 | 428 | |
fbbcd146 | 429 | int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan); |
394cf0a1 S |
430 | int ath_startrecv(struct ath_softc *sc); |
431 | bool ath_stoprecv(struct ath_softc *sc); | |
394cf0a1 S |
432 | u32 ath_calcrxfilter(struct ath_softc *sc); |
433 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
434 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 435 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 | 436 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
ef1b6cd9 SM |
437 | void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); |
438 | void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); | |
439 | void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); | |
394cf0a1 | 440 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); |
1381559b FF |
441 | bool ath_drain_all_txq(struct ath_softc *sc); |
442 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq); | |
394cf0a1 S |
443 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); |
444 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
445 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
0453531e | 446 | void ath_txq_schedule_all(struct ath_softc *sc); |
394cf0a1 | 447 | int ath_tx_init(struct ath_softc *sc, int nbufs); |
394cf0a1 S |
448 | int ath_txq_update(struct ath_softc *sc, int qnum, |
449 | struct ath9k_tx_queue_info *q); | |
aa5955c3 | 450 | void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); |
c52f33d0 | 451 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 | 452 | struct ath_tx_control *txctl); |
59505c02 FF |
453 | void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
454 | struct sk_buff *skb); | |
394cf0a1 | 455 | void ath_tx_tasklet(struct ath_softc *sc); |
e5003249 | 456 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
231c3a1f FF |
457 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
458 | u16 tid, u16 *ssn); | |
f83da965 | 459 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
394cf0a1 S |
460 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
461 | ||
5519541d | 462 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); |
042ec453 JB |
463 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
464 | struct ath_node *an); | |
86a22acf FF |
465 | void ath9k_release_buffered_frames(struct ieee80211_hw *hw, |
466 | struct ieee80211_sta *sta, | |
467 | u16 tids, int nframes, | |
468 | enum ieee80211_frame_release_type reason, | |
469 | bool more_data); | |
5519541d | 470 | |
394cf0a1 | 471 | /********/ |
17d7904d | 472 | /* VIFs */ |
394cf0a1 | 473 | /********/ |
f078f209 | 474 | |
17d7904d | 475 | struct ath_vif { |
fbbcd146 FF |
476 | struct list_head list; |
477 | ||
d463af4a | 478 | struct ieee80211_vif *vif; |
f89d1bc4 | 479 | struct ath_node mcast_node; |
394cf0a1 | 480 | int av_bslot; |
4ed96f04 | 481 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 | 482 | struct ath_buf *av_bcbuf; |
fbbcd146 | 483 | struct ath_chanctx *chanctx; |
d463af4a FF |
484 | |
485 | /* P2P Client */ | |
486 | struct ieee80211_noa_data noa; | |
3ae07d39 FF |
487 | |
488 | /* P2P GO */ | |
489 | u8 noa_index; | |
490 | u32 offchannel_start; | |
491 | u32 offchannel_duration; | |
7414863e FF |
492 | |
493 | u32 periodic_noa_start; | |
494 | u32 periodic_noa_duration; | |
f078f209 LR |
495 | }; |
496 | ||
7b6ef998 SM |
497 | struct ath9k_vif_iter_data { |
498 | u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */ | |
499 | u8 mask[ETH_ALEN]; /* bssid mask */ | |
500 | bool has_hw_macaddr; | |
9a9c4fbc RM |
501 | u8 slottime; |
502 | bool beacons; | |
7b6ef998 SM |
503 | |
504 | int naps; /* number of AP vifs */ | |
505 | int nmeshes; /* number of mesh vifs */ | |
506 | int nstations; /* number of station vifs */ | |
507 | int nwds; /* number of WDS vifs */ | |
508 | int nadhocs; /* number of adhoc vifs */ | |
9a9c4fbc | 509 | struct ieee80211_vif *primary_sta; |
7b6ef998 SM |
510 | }; |
511 | ||
9a9c4fbc RM |
512 | void ath9k_calculate_iter_data(struct ath_softc *sc, |
513 | struct ath_chanctx *ctx, | |
7b6ef998 | 514 | struct ath9k_vif_iter_data *iter_data); |
9a9c4fbc RM |
515 | void ath9k_calculate_summary_state(struct ath_softc *sc, |
516 | struct ath_chanctx *ctx); | |
7b6ef998 | 517 | |
394cf0a1 S |
518 | /*******************/ |
519 | /* Beacon Handling */ | |
520 | /*******************/ | |
f078f209 | 521 | |
394cf0a1 S |
522 | /* |
523 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
524 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
525 | * number of beacon intervals, the game's up. | |
526 | */ | |
c944daf4 | 527 | #define BSTUCK_THRESH 9 |
689e756f | 528 | #define ATH_BCBUF 8 |
394cf0a1 S |
529 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
530 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
394cf0a1 | 531 | |
7b6ef998 SM |
532 | #define TSF_TO_TU(_h,_l) \ |
533 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
534 | ||
394cf0a1 S |
535 | struct ath_beacon { |
536 | enum { | |
537 | OK, /* no change needed */ | |
538 | UPDATE, /* update pending */ | |
539 | COMMIT /* beacon sent, commit change */ | |
540 | } updateslot; /* slot time update fsm */ | |
541 | ||
542 | u32 beaconq; | |
543 | u32 bmisscnt; | |
2c3db3d5 | 544 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
394cf0a1 S |
545 | int slottime; |
546 | int slotupdate; | |
394cf0a1 S |
547 | struct ath_descdma bdma; |
548 | struct ath_txq *cabq; | |
549 | struct list_head bbuf; | |
ba4903f9 FF |
550 | |
551 | bool tx_processed; | |
552 | bool tx_last; | |
394cf0a1 S |
553 | }; |
554 | ||
fb6e252f | 555 | void ath9k_beacon_tasklet(unsigned long data); |
ef4ad633 SM |
556 | void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, |
557 | u32 changed); | |
130ef6e9 SM |
558 | void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); |
559 | void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); | |
ef4ad633 | 560 | void ath9k_set_beacon(struct ath_softc *sc); |
4effc6fd MK |
561 | bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif); |
562 | void ath9k_csa_update(struct ath_softc *sc); | |
394cf0a1 | 563 | |
ef1b6cd9 SM |
564 | /*******************/ |
565 | /* Link Monitoring */ | |
566 | /*******************/ | |
f078f209 | 567 | |
20977d3e S |
568 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
569 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
570 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
571 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
6044474e | 572 | #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ |
20977d3e S |
573 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
574 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
7b6ef998 SM |
575 | #define ATH_ANI_MAX_SKIP_COUNT 10 |
576 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ | |
577 | #define ATH_PLL_WORK_INTERVAL 100 | |
ca369eb4 | 578 | |
bff11766 | 579 | void ath_chanctx_work(struct work_struct *work); |
ef1b6cd9 | 580 | void ath_tx_complete_poll_work(struct work_struct *work); |
236de514 | 581 | void ath_reset_work(struct work_struct *work); |
415ec61b | 582 | bool ath_hw_check(struct ath_softc *sc); |
9eab61c2 | 583 | void ath_hw_pll_work(struct work_struct *work); |
9f42c2b6 | 584 | void ath_paprd_calibrate(struct work_struct *work); |
55624204 | 585 | void ath_ani_calibrate(unsigned long data); |
da0d45f7 SM |
586 | void ath_start_ani(struct ath_softc *sc); |
587 | void ath_stop_ani(struct ath_softc *sc); | |
588 | void ath_check_ani(struct ath_softc *sc); | |
ef1b6cd9 SM |
589 | int ath_update_survey_stats(struct ath_softc *sc); |
590 | void ath_update_survey_nf(struct ath_softc *sc, int channel); | |
124b979b | 591 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); |
bf3dac5a | 592 | void ath_ps_full_sleep(unsigned long data); |
d463af4a FF |
593 | void ath9k_p2p_ps_timer(void *priv); |
594 | void ath9k_update_p2p_ps(struct ath_softc *sc, struct ieee80211_vif *vif); | |
bff11766 | 595 | void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop); |
55624204 | 596 | |
0fca65c1 S |
597 | /**********/ |
598 | /* BTCOEX */ | |
599 | /**********/ | |
600 | ||
ac46ba43 SM |
601 | #define ATH_DUMP_BTCOEX(_s, _val) \ |
602 | do { \ | |
5e88ba62 ZK |
603 | len += scnprintf(buf + len, size - len, \ |
604 | "%20s : %10d\n", _s, (_val)); \ | |
ac46ba43 SM |
605 | } while (0) |
606 | ||
e6930c4b SM |
607 | enum bt_op_flags { |
608 | BT_OP_PRIORITY_DETECTED, | |
609 | BT_OP_SCAN, | |
610 | }; | |
611 | ||
2e20250a | 612 | struct ath_btcoex { |
2e20250a LR |
613 | spinlock_t btcoex_lock; |
614 | struct timer_list period_timer; /* Timer for BT period */ | |
168c6f89 | 615 | struct timer_list no_stomp_timer; |
2e20250a LR |
616 | u32 bt_priority_cnt; |
617 | unsigned long bt_priority_time; | |
e6930c4b | 618 | unsigned long op_flags; |
e08a6ace | 619 | int bt_stomp_type; /* Types of BT stomping */ |
168c6f89 | 620 | u32 btcoex_no_stomp; /* in msec */ |
94ae77ea | 621 | u32 btcoex_period; /* in msec */ |
168c6f89 | 622 | u32 btscan_no_stomp; /* in msec */ |
7dc181c2 | 623 | u32 duty_cycle; |
6995fb80 | 624 | u32 bt_wait_time; |
e82cb03f | 625 | int rssi_count; |
7dc181c2 | 626 | struct ath_mci_profile mci; |
2884561a | 627 | u8 stomp_audio; |
2e20250a LR |
628 | }; |
629 | ||
4daa7760 | 630 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
5908120f SM |
631 | int ath9k_init_btcoex(struct ath_softc *sc); |
632 | void ath9k_deinit_btcoex(struct ath_softc *sc); | |
df198b17 SM |
633 | void ath9k_start_btcoex(struct ath_softc *sc); |
634 | void ath9k_stop_btcoex(struct ath_softc *sc); | |
0fca65c1 S |
635 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); |
636 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
56ca0dba | 637 | void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); |
c0ac53fa | 638 | u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); |
08d4df41 | 639 | void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); |
ac46ba43 | 640 | int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); |
4daa7760 SM |
641 | #else |
642 | static inline int ath9k_init_btcoex(struct ath_softc *sc) | |
643 | { | |
644 | return 0; | |
645 | } | |
646 | static inline void ath9k_deinit_btcoex(struct ath_softc *sc) | |
647 | { | |
648 | } | |
649 | static inline void ath9k_start_btcoex(struct ath_softc *sc) | |
650 | { | |
651 | } | |
652 | static inline void ath9k_stop_btcoex(struct ath_softc *sc) | |
653 | { | |
654 | } | |
655 | static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, | |
656 | u32 status) | |
657 | { | |
658 | } | |
659 | static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, | |
660 | u32 max_4ms_framelen) | |
661 | { | |
662 | return 0; | |
663 | } | |
08d4df41 RM |
664 | static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) |
665 | { | |
666 | } | |
ac46ba43 | 667 | static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) |
4df50ca8 RM |
668 | { |
669 | return 0; | |
670 | } | |
4daa7760 | 671 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |
0fca65c1 | 672 | |
394cf0a1 S |
673 | /********************/ |
674 | /* LED Control */ | |
675 | /********************/ | |
f078f209 | 676 | |
08fc5c1b VN |
677 | #define ATH_LED_PIN_DEF 1 |
678 | #define ATH_LED_PIN_9287 8 | |
353e5019 | 679 | #define ATH_LED_PIN_9300 10 |
15178535 | 680 | #define ATH_LED_PIN_9485 6 |
1a68abb0 | 681 | #define ATH_LED_PIN_9462 4 |
f078f209 | 682 | |
0cf55c21 | 683 | #ifdef CONFIG_MAC80211_LEDS |
0fca65c1 S |
684 | void ath_init_leds(struct ath_softc *sc); |
685 | void ath_deinit_leds(struct ath_softc *sc); | |
8f176a3a | 686 | void ath_fill_led_pin(struct ath_softc *sc); |
0cf55c21 FF |
687 | #else |
688 | static inline void ath_init_leds(struct ath_softc *sc) | |
689 | { | |
690 | } | |
691 | ||
692 | static inline void ath_deinit_leds(struct ath_softc *sc) | |
8f176a3a RM |
693 | { |
694 | } | |
695 | static inline void ath_fill_led_pin(struct ath_softc *sc) | |
0cf55c21 FF |
696 | { |
697 | } | |
698 | #endif | |
699 | ||
e60001e7 SM |
700 | /************************/ |
701 | /* Wake on Wireless LAN */ | |
702 | /************************/ | |
703 | ||
7b6ef998 SM |
704 | struct ath9k_wow_pattern { |
705 | u8 pattern_bytes[MAX_PATTERN_SIZE]; | |
706 | u8 mask_bytes[MAX_PATTERN_SIZE]; | |
707 | u32 pattern_len; | |
708 | }; | |
709 | ||
e60001e7 | 710 | #ifdef CONFIG_ATH9K_WOW |
babaa80a | 711 | void ath9k_init_wow(struct ieee80211_hw *hw); |
e60001e7 SM |
712 | int ath9k_suspend(struct ieee80211_hw *hw, |
713 | struct cfg80211_wowlan *wowlan); | |
714 | int ath9k_resume(struct ieee80211_hw *hw); | |
715 | void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled); | |
716 | #else | |
babaa80a SM |
717 | static inline void ath9k_init_wow(struct ieee80211_hw *hw) |
718 | { | |
719 | } | |
e60001e7 SM |
720 | static inline int ath9k_suspend(struct ieee80211_hw *hw, |
721 | struct cfg80211_wowlan *wowlan) | |
722 | { | |
723 | return 0; | |
724 | } | |
725 | static inline int ath9k_resume(struct ieee80211_hw *hw) | |
726 | { | |
727 | return 0; | |
728 | } | |
729 | static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) | |
730 | { | |
731 | } | |
732 | #endif /* CONFIG_ATH9K_WOW */ | |
733 | ||
8da07830 | 734 | /*******************************/ |
102885a5 | 735 | /* Antenna diversity/combining */ |
8da07830 SM |
736 | /*******************************/ |
737 | ||
102885a5 VT |
738 | #define ATH_ANT_RX_CURRENT_SHIFT 4 |
739 | #define ATH_ANT_RX_MAIN_SHIFT 2 | |
740 | #define ATH_ANT_RX_MASK 0x3 | |
741 | ||
742 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 | |
743 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 | |
744 | #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 | |
745 | #define ATH_ANT_DIV_COMB_INIT_COUNT 95 | |
746 | #define ATH_ANT_DIV_COMB_MAX_COUNT 100 | |
747 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 | |
748 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 | |
3afa6b4f SM |
749 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50 |
750 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50 | |
102885a5 | 751 | |
102885a5 VT |
752 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 |
753 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 | |
754 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 | |
755 | ||
102885a5 VT |
756 | struct ath_ant_comb { |
757 | u16 count; | |
758 | u16 total_pkt_count; | |
759 | bool scan; | |
760 | bool scan_not_start; | |
761 | int main_total_rssi; | |
762 | int alt_total_rssi; | |
763 | int alt_recv_cnt; | |
764 | int main_recv_cnt; | |
765 | int rssi_lna1; | |
766 | int rssi_lna2; | |
767 | int rssi_add; | |
768 | int rssi_sub; | |
769 | int rssi_first; | |
770 | int rssi_second; | |
771 | int rssi_third; | |
3afa6b4f SM |
772 | int ant_ratio; |
773 | int ant_ratio2; | |
102885a5 VT |
774 | bool alt_good; |
775 | int quick_scan_cnt; | |
3fbaf4c5 | 776 | enum ath9k_ant_div_comb_lna_conf main_conf; |
102885a5 VT |
777 | enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; |
778 | enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; | |
102885a5 VT |
779 | bool first_ratio; |
780 | bool second_ratio; | |
781 | unsigned long scan_start_time; | |
3afa6b4f SM |
782 | |
783 | /* | |
784 | * Card-specific config values. | |
785 | */ | |
786 | int low_rssi_thresh; | |
787 | int fast_div_bias; | |
102885a5 VT |
788 | }; |
789 | ||
8da07830 | 790 | void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); |
8da07830 | 791 | |
394cf0a1 S |
792 | /********************/ |
793 | /* Main driver core */ | |
794 | /********************/ | |
f078f209 | 795 | |
2d22c7dd SM |
796 | #define ATH9K_PCI_CUS198 0x0001 |
797 | #define ATH9K_PCI_CUS230 0x0002 | |
798 | #define ATH9K_PCI_CUS217 0x0004 | |
799 | #define ATH9K_PCI_CUS252 0x0008 | |
800 | #define ATH9K_PCI_WOW 0x0010 | |
801 | #define ATH9K_PCI_BT_ANT_DIV 0x0020 | |
802 | #define ATH9K_PCI_D3_L1_WAR 0x0040 | |
803 | #define ATH9K_PCI_AR9565_1ANT 0x0080 | |
804 | #define ATH9K_PCI_AR9565_2ANT 0x0100 | |
805 | #define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200 | |
4dd35640 | 806 | #define ATH9K_PCI_KILLER 0x0400 |
9b60b64b | 807 | |
394cf0a1 S |
808 | /* |
809 | * Default cache line size, in bytes. | |
810 | * Used when PCI device not fully initialized by bootrom/BIOS | |
811 | */ | |
812 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 | 813 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ |
394cf0a1 | 814 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
071aa9a8 | 815 | #define MAX_GTT_CNT 5 |
394cf0a1 | 816 | |
1b04b930 S |
817 | /* Powersave flags */ |
818 | #define PS_WAIT_FOR_BEACON BIT(0) | |
819 | #define PS_WAIT_FOR_CAB BIT(1) | |
820 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
821 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
822 | #define PS_BEACON_SYNC BIT(4) | |
424749c7 | 823 | #define PS_WAIT_FOR_ANI BIT(5) |
394cf0a1 | 824 | |
fbbcd146 FF |
825 | #define ATH9K_NUM_CHANCTX 2 /* supports 2 operating channels */ |
826 | ||
394cf0a1 S |
827 | struct ath_softc { |
828 | struct ieee80211_hw *hw; | |
829 | struct device *dev; | |
c52f33d0 | 830 | |
3430098a FF |
831 | struct survey_info *cur_survey; |
832 | struct survey_info survey[ATH9K_NUM_CHANNELS]; | |
0e2dedf9 | 833 | |
394cf0a1 S |
834 | struct tasklet_struct intr_tq; |
835 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 836 | struct ath_hw *sc_ah; |
394cf0a1 S |
837 | void __iomem *mem; |
838 | int irq; | |
2d6a5e95 | 839 | spinlock_t sc_serial_rw; |
04717ccd | 840 | spinlock_t sc_pm_lock; |
4bdd1e97 | 841 | spinlock_t sc_pcu_lock; |
394cf0a1 | 842 | struct mutex mutex; |
9f42c2b6 | 843 | struct work_struct paprd_work; |
236de514 | 844 | struct work_struct hw_reset_work; |
bff11766 | 845 | struct work_struct chanctx_work; |
9f42c2b6 | 846 | struct completion paprd_complete; |
10e23181 | 847 | wait_queue_head_t tx_wait; |
394cf0a1 | 848 | |
d463af4a FF |
849 | struct ath_gen_timer *p2p_ps_timer; |
850 | struct ath_vif *p2p_ps_vif; | |
851 | ||
9b60b64b | 852 | unsigned long driver_data; |
cb8d61de | 853 | |
071aa9a8 | 854 | u8 gtt_cnt; |
17d7904d | 855 | u32 intrstatus; |
1b04b930 | 856 | u16 ps_flags; /* PS_* */ |
17d7904d | 857 | u16 curtxpow; |
96148326 | 858 | bool ps_enabled; |
1dbfd9d4 | 859 | bool ps_idle; |
4801416c BG |
860 | short nbcnvifs; |
861 | short nvifs; | |
709ade9e | 862 | unsigned long ps_usecount; |
394cf0a1 | 863 | |
394cf0a1 S |
864 | struct ath_rx rx; |
865 | struct ath_tx tx; | |
866 | struct ath_beacon beacon; | |
394cf0a1 | 867 | |
bff11766 | 868 | struct cfg80211_chan_def cur_chandef; |
fbbcd146 FF |
869 | struct ath_chanctx chanctx[ATH9K_NUM_CHANCTX]; |
870 | struct ath_chanctx *cur_chan; | |
bff11766 FF |
871 | struct ath_chanctx *next_chan; |
872 | spinlock_t chan_lock; | |
78b21949 | 873 | struct ath_offchannel offchannel; |
748299f2 | 874 | struct ath_chanctx_sched sched; |
fbbcd146 | 875 | |
0cf55c21 FF |
876 | #ifdef CONFIG_MAC80211_LEDS |
877 | bool led_registered; | |
878 | char led_name[32]; | |
879 | struct led_classdev led_cdev; | |
880 | #endif | |
394cf0a1 | 881 | |
a830df07 | 882 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 883 | struct ath9k_debug debug; |
394cf0a1 | 884 | #endif |
164ace38 | 885 | struct delayed_work tx_complete_work; |
181fb18d | 886 | struct delayed_work hw_pll_work; |
bf3dac5a | 887 | struct timer_list sleep_timer; |
4daa7760 SM |
888 | |
889 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT | |
2e20250a | 890 | struct ath_btcoex btcoex; |
9e25365f | 891 | struct ath_mci_coex mci_coex; |
3c7992e3 | 892 | struct work_struct mci_work; |
4daa7760 | 893 | #endif |
5088c2f1 VT |
894 | |
895 | struct ath_descdma txsdma; | |
102885a5 VT |
896 | |
897 | struct ath_ant_comb ant_comb; | |
43c35284 | 898 | u8 ant_tx, ant_rx; |
8e92d3f2 | 899 | struct dfs_pattern_detector *dfs_detector; |
3f3c09f3 | 900 | u64 dfs_prev_pulse_ts; |
b11e640a | 901 | u32 wow_enabled; |
e93d083f SW |
902 | /* relay(fs) channel for spectral scan */ |
903 | struct rchan *rfs_chan_spec_scan; | |
904 | enum spectral_mode spectral_mode; | |
04ccd4a1 | 905 | struct ath_spec_scan spec_config; |
01c78533 | 906 | |
89f927af LR |
907 | struct ieee80211_vif *tx99_vif; |
908 | struct sk_buff *tx99_skb; | |
909 | bool tx99_state; | |
910 | s16 tx99_power; | |
911 | ||
e60001e7 | 912 | #ifdef CONFIG_ATH9K_WOW |
01c78533 MSS |
913 | atomic_t wow_got_bmiss_intr; |
914 | atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ | |
915 | u32 wow_intr_before_sleep; | |
916 | #endif | |
394cf0a1 S |
917 | }; |
918 | ||
ef6b19e4 SM |
919 | /********/ |
920 | /* TX99 */ | |
921 | /********/ | |
922 | ||
923 | #ifdef CONFIG_ATH9K_TX99 | |
924 | void ath9k_tx99_init_debug(struct ath_softc *sc); | |
89f927af LR |
925 | int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, |
926 | struct ath_tx_control *txctl); | |
ef6b19e4 SM |
927 | #else |
928 | static inline void ath9k_tx99_init_debug(struct ath_softc *sc) | |
929 | { | |
930 | } | |
931 | static inline int ath9k_tx99_send(struct ath_softc *sc, | |
932 | struct sk_buff *skb, | |
933 | struct ath_tx_control *txctl) | |
934 | { | |
935 | return 0; | |
936 | } | |
937 | #endif /* CONFIG_ATH9K_TX99 */ | |
89f927af | 938 | |
5bb12791 | 939 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 940 | { |
5bb12791 | 941 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
942 | } |
943 | ||
7b6ef998 SM |
944 | void ath9k_tasklet(unsigned long data); |
945 | int ath_cabq_update(struct ath_softc *); | |
313eb87f | 946 | u8 ath9k_parse_mpdudensity(u8 mpdudensity); |
394cf0a1 | 947 | irqreturn_t ath_isr(int irq, void *dev); |
ef6b19e4 | 948 | int ath_reset(struct ath_softc *sc); |
e60001e7 SM |
949 | void ath_cancel_work(struct ath_softc *sc); |
950 | void ath_restart_work(struct ath_softc *sc); | |
eb93e891 | 951 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
5bb12791 | 952 | const struct ath_bus_ops *bus_ops); |
285f2dda | 953 | void ath9k_deinit_device(struct ath_softc *sc); |
43c35284 | 954 | void ath9k_reload_chainmask_settings(struct ath_softc *sc); |
7b6ef998 SM |
955 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); |
956 | void ath_start_rfkill_poll(struct ath_softc *sc); | |
957 | void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
958 | void ath9k_ps_wakeup(struct ath_softc *sc); | |
959 | void ath9k_ps_restore(struct ath_softc *sc); | |
68a89116 | 960 | |
8e26a030 | 961 | #ifdef CONFIG_ATH9K_PCI |
394cf0a1 S |
962 | int ath_pci_init(void); |
963 | void ath_pci_exit(void); | |
964 | #else | |
965 | static inline int ath_pci_init(void) { return 0; }; | |
966 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 967 | #endif |
f1dc5600 | 968 | |
8e26a030 | 969 | #ifdef CONFIG_ATH9K_AHB |
394cf0a1 S |
970 | int ath_ahb_init(void); |
971 | void ath_ahb_exit(void); | |
972 | #else | |
973 | static inline int ath_ahb_init(void) { return 0; }; | |
974 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 975 | #endif |
394cf0a1 | 976 | |
394cf0a1 | 977 | #endif /* ATH9K_H */ |