Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
a6b7a407 | 22 | #include <linux/interrupt.h> |
394cf0a1 | 23 | #include <linux/leds.h> |
9f42c2b6 | 24 | #include <linux/completion.h> |
394cf0a1 | 25 | |
394cf0a1 | 26 | #include "debug.h" |
db86f07e | 27 | #include "common.h" |
7dc181c2 | 28 | #include "mci.h" |
8e92d3f2 | 29 | #include "dfs.h" |
db86f07e LR |
30 | |
31 | /* | |
32 | * Header for the ath9k.ko driver core *only* -- hw code nor any other driver | |
33 | * should rely on this file or its contents. | |
34 | */ | |
394cf0a1 S |
35 | |
36 | struct ath_node; | |
37 | ||
38 | /* Macro to expand scalars to 64-bit objects */ | |
39 | ||
13bda122 | 40 | #define ito64(x) (sizeof(x) == 1) ? \ |
394cf0a1 | 41 | (((unsigned long long int)(x)) & (0xff)) : \ |
13bda122 | 42 | (sizeof(x) == 2) ? \ |
394cf0a1 | 43 | (((unsigned long long int)(x)) & 0xffff) : \ |
13bda122 | 44 | ((sizeof(x) == 4) ? \ |
394cf0a1 S |
45 | (((unsigned long long int)(x)) & 0xffffffff) : \ |
46 | (unsigned long long int)(x)) | |
47 | ||
48 | /* increment with wrap-around */ | |
49 | #define INCR(_l, _sz) do { \ | |
50 | (_l)++; \ | |
51 | (_l) &= ((_sz) - 1); \ | |
52 | } while (0) | |
53 | ||
54 | /* decrement with wrap-around */ | |
55 | #define DECR(_l, _sz) do { \ | |
56 | (_l)--; \ | |
57 | (_l) &= ((_sz) - 1); \ | |
58 | } while (0) | |
59 | ||
394cf0a1 S |
60 | #define TSF_TO_TU(_h,_l) \ |
61 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
62 | ||
63 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
64 | ||
394cf0a1 | 65 | struct ath_config { |
394cf0a1 S |
66 | u16 txpowlimit; |
67 | u8 cabqReadytime; | |
394cf0a1 S |
68 | }; |
69 | ||
70 | /*************************/ | |
71 | /* Descriptor Management */ | |
72 | /*************************/ | |
73 | ||
74 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 75 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
76 | (_bf)->bf_lastbf = NULL; \ |
77 | (_bf)->bf_next = NULL; \ | |
78 | memset(&((_bf)->bf_state), 0, \ | |
79 | sizeof(struct ath_buf_state)); \ | |
80 | } while (0) | |
81 | ||
a119cc49 S |
82 | #define ATH_RXBUF_RESET(_bf) do { \ |
83 | (_bf)->bf_stale = false; \ | |
84 | } while (0) | |
85 | ||
394cf0a1 S |
86 | /** |
87 | * enum buffer_type - Buffer type flags | |
88 | * | |
394cf0a1 S |
89 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) |
90 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
91 | * (used in aggregation scheduling) | |
394cf0a1 S |
92 | */ |
93 | enum buffer_type { | |
436d0d98 MSS |
94 | BUF_AMPDU = BIT(0), |
95 | BUF_AGGR = BIT(1), | |
394cf0a1 S |
96 | }; |
97 | ||
394cf0a1 S |
98 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) |
99 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
f078f209 | 100 | |
016c2177 | 101 | #define ATH_TXSTATUS_RING_SIZE 512 |
5088c2f1 | 102 | |
c3d77696 MSS |
103 | #define DS2PHYS(_dd, _ds) \ |
104 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
105 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
106 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
107 | ||
394cf0a1 | 108 | struct ath_descdma { |
5088c2f1 | 109 | void *dd_desc; |
17d7904d S |
110 | dma_addr_t dd_desc_paddr; |
111 | u32 dd_desc_len; | |
394cf0a1 S |
112 | }; |
113 | ||
114 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
115 | struct list_head *head, const char *name, | |
4adfcded | 116 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
117 | |
118 | /***********/ | |
119 | /* RX / TX */ | |
120 | /***********/ | |
121 | ||
394cf0a1 | 122 | #define ATH_RXBUF 512 |
394cf0a1 | 123 | #define ATH_TXBUF 512 |
84642d6b FF |
124 | #define ATH_TXBUF_RESERVE 5 |
125 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 126 | #define ATH_TXMAXTRY 13 |
394cf0a1 S |
127 | |
128 | #define TID_TO_WME_AC(_tid) \ | |
bea843c7 SM |
129 | ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ |
130 | (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ | |
131 | (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ | |
132 | IEEE80211_AC_VO) | |
394cf0a1 | 133 | |
394cf0a1 S |
134 | #define ATH_AGGR_DELIM_SZ 4 |
135 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
136 | /* number of delimiters for encryption padding */ | |
137 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
138 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
139 | #define ATH_AGGR_MIN_QDEPTH 2 | |
140 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
394cf0a1 S |
141 | |
142 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
143 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
144 | #define IEEE80211_WEP_IVLEN 3 |
145 | #define IEEE80211_WEP_KIDLEN 1 | |
146 | #define IEEE80211_WEP_CRCLEN 4 | |
147 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
148 | (IEEE80211_WEP_IVLEN + \ | |
149 | IEEE80211_WEP_KIDLEN + \ | |
150 | IEEE80211_WEP_CRCLEN)) | |
151 | ||
152 | /* return whether a bit at index _n in bitmap _bm is set | |
153 | * _sz is the size of the bitmap */ | |
154 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
155 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
156 | ||
157 | /* return block-ack bitmap index given sequence and starting sequence */ | |
158 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
159 | ||
156369fa FF |
160 | /* return the seqno for _start + _offset */ |
161 | #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) | |
162 | ||
394cf0a1 S |
163 | /* returns delimiter padding required given the packet length */ |
164 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
39ec2997 VT |
165 | (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ |
166 | DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) | |
394cf0a1 S |
167 | |
168 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
169 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
170 | ||
394cf0a1 S |
171 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
172 | ||
365d2ebc SM |
173 | #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) |
174 | ||
164ace38 SB |
175 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
176 | ||
394cf0a1 S |
177 | enum ATH_AGGR_STATUS { |
178 | ATH_AGGR_DONE, | |
179 | ATH_AGGR_BAW_CLOSED, | |
180 | ATH_AGGR_LIMITED, | |
181 | }; | |
182 | ||
e5003249 | 183 | #define ATH_TXFIFO_DEPTH 8 |
394cf0a1 | 184 | struct ath_txq { |
60f2d1d5 BG |
185 | int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ |
186 | u32 axq_qnum; /* ath9k hardware queue number */ | |
fce041be | 187 | void *axq_link; |
17d7904d | 188 | struct list_head axq_q; |
394cf0a1 | 189 | spinlock_t axq_lock; |
17d7904d | 190 | u32 axq_depth; |
4b3ba66a | 191 | u32 axq_ampdu_depth; |
17d7904d | 192 | bool stopped; |
164ace38 | 193 | bool axq_tx_inprogress; |
394cf0a1 | 194 | struct list_head axq_acq; |
e5003249 | 195 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
e5003249 VT |
196 | u8 txq_headidx; |
197 | u8 txq_tailidx; | |
066dae93 | 198 | int pending_frames; |
23de5dc9 | 199 | struct sk_buff_head complete_q; |
394cf0a1 S |
200 | }; |
201 | ||
93ef24b2 | 202 | struct ath_atx_ac { |
066dae93 | 203 | struct ath_txq *txq; |
93ef24b2 | 204 | int sched; |
93ef24b2 S |
205 | struct list_head list; |
206 | struct list_head tid_q; | |
5519541d | 207 | bool clear_ps_filter; |
93ef24b2 S |
208 | }; |
209 | ||
2d42efc4 | 210 | struct ath_frame_info { |
56dc6336 | 211 | struct ath_buf *bf; |
2d42efc4 | 212 | int framelen; |
2d42efc4 | 213 | enum ath9k_key_type keytype; |
a75c0629 | 214 | u8 keyix; |
2d42efc4 | 215 | u8 retries; |
80b08a8d | 216 | u8 rtscts_rate; |
2d42efc4 FF |
217 | }; |
218 | ||
93ef24b2 | 219 | struct ath_buf_state { |
93ef24b2 | 220 | u8 bf_type; |
9f42c2b6 | 221 | u8 bfs_paprd; |
399c6489 | 222 | u8 ndelim; |
6a0ddaef | 223 | u16 seqno; |
9cf04dcc | 224 | unsigned long bfs_paprd_timestamp; |
93ef24b2 S |
225 | }; |
226 | ||
227 | struct ath_buf { | |
228 | struct list_head list; | |
229 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
230 | an aggregate) */ | |
231 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
232 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
233 | void *bf_desc; /* virtual addr of desc */ | |
234 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
c1739eb3 | 235 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
93ef24b2 | 236 | bool bf_stale; |
79acac07 | 237 | struct ieee80211_tx_rate rates[4]; |
93ef24b2 | 238 | struct ath_buf_state bf_state; |
93ef24b2 S |
239 | }; |
240 | ||
241 | struct ath_atx_tid { | |
242 | struct list_head list; | |
56dc6336 | 243 | struct sk_buff_head buf_q; |
93ef24b2 S |
244 | struct ath_node *an; |
245 | struct ath_atx_ac *ac; | |
81ee13ba | 246 | unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; |
f9437543 | 247 | int bar_index; |
93ef24b2 S |
248 | u16 seq_start; |
249 | u16 seq_next; | |
250 | u16 baw_size; | |
251 | int tidno; | |
252 | int baw_head; /* first un-acked tx buffer */ | |
253 | int baw_tail; /* next unused tx buffer slot */ | |
08c96abd FF |
254 | bool sched; |
255 | bool paused; | |
256 | bool active; | |
93ef24b2 S |
257 | }; |
258 | ||
259 | struct ath_node { | |
a145daf7 | 260 | struct ath_softc *sc; |
7f010c93 | 261 | struct ieee80211_sta *sta; /* station struct we're part of */ |
7e1e3864 | 262 | struct ieee80211_vif *vif; /* interface with which we're associated */ |
de7b7604 | 263 | struct ath_atx_tid tid[IEEE80211_NUM_TIDS]; |
bea843c7 | 264 | struct ath_atx_ac ac[IEEE80211_NUM_ACS]; |
93ae2dd2 FF |
265 | int ps_key; |
266 | ||
93ef24b2 S |
267 | u16 maxampdu; |
268 | u8 mpdudensity; | |
5519541d FF |
269 | |
270 | bool sleeping; | |
a145daf7 SM |
271 | |
272 | #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) | |
273 | struct dentry *node_stat; | |
274 | #endif | |
93ef24b2 S |
275 | }; |
276 | ||
394cf0a1 S |
277 | struct ath_tx_control { |
278 | struct ath_txq *txq; | |
2d42efc4 | 279 | struct ath_node *an; |
9f42c2b6 | 280 | u8 paprd; |
36323f81 | 281 | struct ieee80211_sta *sta; |
394cf0a1 S |
282 | }; |
283 | ||
394cf0a1 | 284 | #define ATH_TX_ERROR 0x01 |
394cf0a1 | 285 | |
60f2d1d5 BG |
286 | /** |
287 | * @txq_map: Index is mac80211 queue number. This is | |
288 | * not necessarily the same as the hardware queue number | |
289 | * (axq_qnum). | |
290 | */ | |
394cf0a1 S |
291 | struct ath_tx { |
292 | u16 seq_no; | |
293 | u32 txqsetup; | |
394cf0a1 S |
294 | spinlock_t txbuflock; |
295 | struct list_head txbuf; | |
296 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
297 | struct ath_descdma txdma; | |
bea843c7 | 298 | struct ath_txq *txq_map[IEEE80211_NUM_ACS]; |
f2c7a793 | 299 | struct ath_txq *uapsdq; |
bea843c7 SM |
300 | u32 txq_max_pending[IEEE80211_NUM_ACS]; |
301 | u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; | |
394cf0a1 S |
302 | }; |
303 | ||
b5c80475 FF |
304 | struct ath_rx_edma { |
305 | struct sk_buff_head rx_fifo; | |
b5c80475 FF |
306 | u32 rx_fifo_hwsize; |
307 | }; | |
308 | ||
394cf0a1 S |
309 | struct ath_rx { |
310 | u8 defant; | |
311 | u8 rxotherant; | |
723e7113 | 312 | bool discard_next; |
394cf0a1 | 313 | u32 *rxlink; |
6995fb80 | 314 | u32 num_pkts; |
394cf0a1 | 315 | unsigned int rxfilter; |
394cf0a1 S |
316 | struct list_head rxbuf; |
317 | struct ath_descdma rxdma; | |
b5c80475 | 318 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; |
0d95521e FF |
319 | |
320 | struct sk_buff *frag; | |
21fbbca3 CL |
321 | |
322 | u32 ampdu_ref; | |
394cf0a1 S |
323 | }; |
324 | ||
325 | int ath_startrecv(struct ath_softc *sc); | |
326 | bool ath_stoprecv(struct ath_softc *sc); | |
394cf0a1 S |
327 | u32 ath_calcrxfilter(struct ath_softc *sc); |
328 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
329 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 330 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 | 331 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
ef1b6cd9 SM |
332 | void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); |
333 | void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); | |
334 | void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); | |
394cf0a1 | 335 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); |
1381559b FF |
336 | bool ath_drain_all_txq(struct ath_softc *sc); |
337 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq); | |
394cf0a1 S |
338 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); |
339 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
340 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
341 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
394cf0a1 S |
342 | int ath_txq_update(struct ath_softc *sc, int qnum, |
343 | struct ath9k_tx_queue_info *q); | |
aa5955c3 | 344 | void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); |
c52f33d0 | 345 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
346 | struct ath_tx_control *txctl); |
347 | void ath_tx_tasklet(struct ath_softc *sc); | |
e5003249 | 348 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
231c3a1f FF |
349 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
350 | u16 tid, u16 *ssn); | |
f83da965 | 351 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
394cf0a1 S |
352 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
353 | ||
5519541d | 354 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); |
042ec453 JB |
355 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
356 | struct ath_node *an); | |
86a22acf FF |
357 | void ath9k_release_buffered_frames(struct ieee80211_hw *hw, |
358 | struct ieee80211_sta *sta, | |
359 | u16 tids, int nframes, | |
360 | enum ieee80211_frame_release_type reason, | |
361 | bool more_data); | |
5519541d | 362 | |
394cf0a1 | 363 | /********/ |
17d7904d | 364 | /* VIFs */ |
394cf0a1 | 365 | /********/ |
f078f209 | 366 | |
17d7904d | 367 | struct ath_vif { |
394cf0a1 | 368 | int av_bslot; |
aa45fe96 | 369 | bool primary_sta_vif; |
4ed96f04 | 370 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 | 371 | struct ath_buf *av_bcbuf; |
f078f209 LR |
372 | }; |
373 | ||
394cf0a1 S |
374 | /*******************/ |
375 | /* Beacon Handling */ | |
376 | /*******************/ | |
f078f209 | 377 | |
394cf0a1 S |
378 | /* |
379 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
380 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
381 | * number of beacon intervals, the game's up. | |
382 | */ | |
c944daf4 | 383 | #define BSTUCK_THRESH 9 |
689e756f | 384 | #define ATH_BCBUF 8 |
394cf0a1 S |
385 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
386 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
387 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
388 | ||
389 | struct ath_beacon_config { | |
9814f6b3 | 390 | int beacon_interval; |
394cf0a1 S |
391 | u16 listen_interval; |
392 | u16 dtim_period; | |
393 | u16 bmiss_timeout; | |
394 | u8 dtim_count; | |
ef4ad633 | 395 | bool enable_beacon; |
1a6404a1 | 396 | bool ibss_creator; |
394cf0a1 S |
397 | }; |
398 | ||
399 | struct ath_beacon { | |
400 | enum { | |
401 | OK, /* no change needed */ | |
402 | UPDATE, /* update pending */ | |
403 | COMMIT /* beacon sent, commit change */ | |
404 | } updateslot; /* slot time update fsm */ | |
405 | ||
406 | u32 beaconq; | |
407 | u32 bmisscnt; | |
dd347f2f | 408 | u32 bc_tstamp; |
2c3db3d5 | 409 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
394cf0a1 S |
410 | int slottime; |
411 | int slotupdate; | |
412 | struct ath9k_tx_queue_info beacon_qi; | |
413 | struct ath_descdma bdma; | |
414 | struct ath_txq *cabq; | |
415 | struct list_head bbuf; | |
ba4903f9 FF |
416 | |
417 | bool tx_processed; | |
418 | bool tx_last; | |
394cf0a1 S |
419 | }; |
420 | ||
fb6e252f | 421 | void ath9k_beacon_tasklet(unsigned long data); |
ef4ad633 SM |
422 | bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
423 | void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, | |
424 | u32 changed); | |
130ef6e9 SM |
425 | void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); |
426 | void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); | |
2f8e82e8 | 427 | void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif); |
ef4ad633 | 428 | void ath9k_set_beacon(struct ath_softc *sc); |
394cf0a1 | 429 | |
ef1b6cd9 SM |
430 | /*******************/ |
431 | /* Link Monitoring */ | |
432 | /*******************/ | |
f078f209 | 433 | |
20977d3e S |
434 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
435 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
436 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
437 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
6044474e | 438 | #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ |
20977d3e S |
439 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
440 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
424749c7 | 441 | #define ATH_ANI_MAX_SKIP_COUNT 10 |
f078f209 | 442 | |
ca369eb4 | 443 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ |
af68abad | 444 | #define ATH_PLL_WORK_INTERVAL 100 |
ca369eb4 | 445 | |
ef1b6cd9 | 446 | void ath_tx_complete_poll_work(struct work_struct *work); |
236de514 | 447 | void ath_reset_work(struct work_struct *work); |
347809fc | 448 | void ath_hw_check(struct work_struct *work); |
9eab61c2 | 449 | void ath_hw_pll_work(struct work_struct *work); |
01e18918 RM |
450 | void ath_rx_poll(unsigned long data); |
451 | void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); | |
9f42c2b6 | 452 | void ath_paprd_calibrate(struct work_struct *work); |
55624204 | 453 | void ath_ani_calibrate(unsigned long data); |
da0d45f7 SM |
454 | void ath_start_ani(struct ath_softc *sc); |
455 | void ath_stop_ani(struct ath_softc *sc); | |
456 | void ath_check_ani(struct ath_softc *sc); | |
ef1b6cd9 SM |
457 | int ath_update_survey_stats(struct ath_softc *sc); |
458 | void ath_update_survey_nf(struct ath_softc *sc, int channel); | |
124b979b | 459 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); |
55624204 | 460 | |
0fca65c1 S |
461 | /**********/ |
462 | /* BTCOEX */ | |
463 | /**********/ | |
464 | ||
ac46ba43 SM |
465 | #define ATH_DUMP_BTCOEX(_s, _val) \ |
466 | do { \ | |
467 | len += snprintf(buf + len, size - len, \ | |
468 | "%20s : %10d\n", _s, (_val)); \ | |
469 | } while (0) | |
470 | ||
e6930c4b SM |
471 | enum bt_op_flags { |
472 | BT_OP_PRIORITY_DETECTED, | |
473 | BT_OP_SCAN, | |
474 | }; | |
475 | ||
2e20250a LR |
476 | struct ath_btcoex { |
477 | bool hw_timer_enabled; | |
478 | spinlock_t btcoex_lock; | |
479 | struct timer_list period_timer; /* Timer for BT period */ | |
480 | u32 bt_priority_cnt; | |
481 | unsigned long bt_priority_time; | |
e6930c4b | 482 | unsigned long op_flags; |
e08a6ace | 483 | int bt_stomp_type; /* Types of BT stomping */ |
2e20250a | 484 | u32 btcoex_no_stomp; /* in usec */ |
94ae77ea | 485 | u32 btcoex_period; /* in msec */ |
58da1318 | 486 | u32 btscan_no_stomp; /* in usec */ |
7dc181c2 | 487 | u32 duty_cycle; |
6995fb80 | 488 | u32 bt_wait_time; |
e82cb03f | 489 | int rssi_count; |
75d7839f | 490 | struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ |
7dc181c2 | 491 | struct ath_mci_profile mci; |
2884561a | 492 | u8 stomp_audio; |
2e20250a LR |
493 | }; |
494 | ||
4daa7760 | 495 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
5908120f SM |
496 | int ath9k_init_btcoex(struct ath_softc *sc); |
497 | void ath9k_deinit_btcoex(struct ath_softc *sc); | |
df198b17 SM |
498 | void ath9k_start_btcoex(struct ath_softc *sc); |
499 | void ath9k_stop_btcoex(struct ath_softc *sc); | |
0fca65c1 S |
500 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); |
501 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
56ca0dba | 502 | void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); |
c0ac53fa | 503 | u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); |
08d4df41 | 504 | void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); |
ac46ba43 | 505 | int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); |
4daa7760 SM |
506 | #else |
507 | static inline int ath9k_init_btcoex(struct ath_softc *sc) | |
508 | { | |
509 | return 0; | |
510 | } | |
511 | static inline void ath9k_deinit_btcoex(struct ath_softc *sc) | |
512 | { | |
513 | } | |
514 | static inline void ath9k_start_btcoex(struct ath_softc *sc) | |
515 | { | |
516 | } | |
517 | static inline void ath9k_stop_btcoex(struct ath_softc *sc) | |
518 | { | |
519 | } | |
520 | static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, | |
521 | u32 status) | |
522 | { | |
523 | } | |
524 | static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, | |
525 | u32 max_4ms_framelen) | |
526 | { | |
527 | return 0; | |
528 | } | |
08d4df41 RM |
529 | static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) |
530 | { | |
531 | } | |
ac46ba43 | 532 | static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) |
4df50ca8 RM |
533 | { |
534 | return 0; | |
535 | } | |
4daa7760 | 536 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |
0fca65c1 | 537 | |
01c78533 MSS |
538 | struct ath9k_wow_pattern { |
539 | u8 pattern_bytes[MAX_PATTERN_SIZE]; | |
540 | u8 mask_bytes[MAX_PATTERN_SIZE]; | |
541 | u32 pattern_len; | |
542 | }; | |
543 | ||
394cf0a1 S |
544 | /********************/ |
545 | /* LED Control */ | |
546 | /********************/ | |
f078f209 | 547 | |
08fc5c1b VN |
548 | #define ATH_LED_PIN_DEF 1 |
549 | #define ATH_LED_PIN_9287 8 | |
353e5019 | 550 | #define ATH_LED_PIN_9300 10 |
15178535 | 551 | #define ATH_LED_PIN_9485 6 |
1a68abb0 | 552 | #define ATH_LED_PIN_9462 4 |
f078f209 | 553 | |
0cf55c21 | 554 | #ifdef CONFIG_MAC80211_LEDS |
0fca65c1 S |
555 | void ath_init_leds(struct ath_softc *sc); |
556 | void ath_deinit_leds(struct ath_softc *sc); | |
8f176a3a | 557 | void ath_fill_led_pin(struct ath_softc *sc); |
0cf55c21 FF |
558 | #else |
559 | static inline void ath_init_leds(struct ath_softc *sc) | |
560 | { | |
561 | } | |
562 | ||
563 | static inline void ath_deinit_leds(struct ath_softc *sc) | |
8f176a3a RM |
564 | { |
565 | } | |
566 | static inline void ath_fill_led_pin(struct ath_softc *sc) | |
0cf55c21 FF |
567 | { |
568 | } | |
569 | #endif | |
570 | ||
8da07830 | 571 | /*******************************/ |
102885a5 | 572 | /* Antenna diversity/combining */ |
8da07830 SM |
573 | /*******************************/ |
574 | ||
102885a5 VT |
575 | #define ATH_ANT_RX_CURRENT_SHIFT 4 |
576 | #define ATH_ANT_RX_MAIN_SHIFT 2 | |
577 | #define ATH_ANT_RX_MASK 0x3 | |
578 | ||
579 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 | |
580 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 | |
581 | #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 | |
582 | #define ATH_ANT_DIV_COMB_INIT_COUNT 95 | |
583 | #define ATH_ANT_DIV_COMB_MAX_COUNT 100 | |
584 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 | |
585 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 | |
586 | ||
102885a5 VT |
587 | #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 |
588 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 | |
589 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 | |
590 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 | |
591 | ||
592 | enum ath9k_ant_div_comb_lna_conf { | |
593 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, | |
594 | ATH_ANT_DIV_COMB_LNA2, | |
595 | ATH_ANT_DIV_COMB_LNA1, | |
596 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, | |
597 | }; | |
598 | ||
599 | struct ath_ant_comb { | |
600 | u16 count; | |
601 | u16 total_pkt_count; | |
602 | bool scan; | |
603 | bool scan_not_start; | |
604 | int main_total_rssi; | |
605 | int alt_total_rssi; | |
606 | int alt_recv_cnt; | |
607 | int main_recv_cnt; | |
608 | int rssi_lna1; | |
609 | int rssi_lna2; | |
610 | int rssi_add; | |
611 | int rssi_sub; | |
612 | int rssi_first; | |
613 | int rssi_second; | |
614 | int rssi_third; | |
615 | bool alt_good; | |
616 | int quick_scan_cnt; | |
617 | int main_conf; | |
618 | enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; | |
619 | enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; | |
102885a5 VT |
620 | bool first_ratio; |
621 | bool second_ratio; | |
622 | unsigned long scan_start_time; | |
623 | }; | |
624 | ||
8da07830 SM |
625 | void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); |
626 | void ath_ant_comb_update(struct ath_softc *sc); | |
627 | ||
394cf0a1 S |
628 | /********************/ |
629 | /* Main driver core */ | |
630 | /********************/ | |
f078f209 | 631 | |
394cf0a1 S |
632 | /* |
633 | * Default cache line size, in bytes. | |
634 | * Used when PCI device not fully initialized by bootrom/BIOS | |
635 | */ | |
636 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 S |
637 | #define ATH_REGCLASSIDS_MAX 10 |
638 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
da647626 | 639 | #define ATH_MAX_SW_RETRIES 30 |
394cf0a1 | 640 | #define ATH_CHAN_MAX 255 |
f1dc5600 | 641 | |
394cf0a1 | 642 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
394cf0a1 S |
643 | #define ATH_RATE_DUMMY_MARKER 0 |
644 | ||
781b14a3 SM |
645 | enum sc_op_flags { |
646 | SC_OP_INVALID, | |
647 | SC_OP_BEACONS, | |
781b14a3 SM |
648 | SC_OP_ANI_RUN, |
649 | SC_OP_PRIM_STA_VIF, | |
b74713d0 | 650 | SC_OP_HW_RESET, |
73900cb0 | 651 | SC_OP_SCANNING, |
781b14a3 | 652 | }; |
1b04b930 S |
653 | |
654 | /* Powersave flags */ | |
655 | #define PS_WAIT_FOR_BEACON BIT(0) | |
656 | #define PS_WAIT_FOR_CAB BIT(1) | |
657 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
658 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
659 | #define PS_BEACON_SYNC BIT(4) | |
424749c7 | 660 | #define PS_WAIT_FOR_ANI BIT(5) |
394cf0a1 | 661 | |
545750d3 | 662 | struct ath_rate_table; |
bce048d7 | 663 | |
4801416c | 664 | struct ath9k_vif_iter_data { |
ab11bb28 | 665 | u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */ |
4801416c | 666 | u8 mask[ETH_ALEN]; /* bssid mask */ |
ab11bb28 FF |
667 | bool has_hw_macaddr; |
668 | ||
4801416c BG |
669 | int naps; /* number of AP vifs */ |
670 | int nmeshes; /* number of mesh vifs */ | |
671 | int nstations; /* number of station vifs */ | |
e707549a | 672 | int nwds; /* number of WDS vifs */ |
4801416c | 673 | int nadhocs; /* number of adhoc vifs */ |
4801416c BG |
674 | }; |
675 | ||
e93d083f SW |
676 | /* enum spectral_mode: |
677 | * | |
678 | * @SPECTRAL_DISABLED: spectral mode is disabled | |
679 | * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with | |
680 | * something else. | |
681 | * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples | |
682 | * is performed manually. | |
683 | * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels | |
684 | * during a channel scan. | |
685 | */ | |
686 | enum spectral_mode { | |
687 | SPECTRAL_DISABLED = 0, | |
688 | SPECTRAL_BACKGROUND, | |
689 | SPECTRAL_MANUAL, | |
690 | SPECTRAL_CHANSCAN, | |
691 | }; | |
692 | ||
394cf0a1 S |
693 | struct ath_softc { |
694 | struct ieee80211_hw *hw; | |
695 | struct device *dev; | |
c52f33d0 | 696 | |
3430098a FF |
697 | struct survey_info *cur_survey; |
698 | struct survey_info survey[ATH9K_NUM_CHANNELS]; | |
0e2dedf9 | 699 | |
394cf0a1 S |
700 | struct tasklet_struct intr_tq; |
701 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 702 | struct ath_hw *sc_ah; |
394cf0a1 S |
703 | void __iomem *mem; |
704 | int irq; | |
2d6a5e95 | 705 | spinlock_t sc_serial_rw; |
04717ccd | 706 | spinlock_t sc_pm_lock; |
4bdd1e97 | 707 | spinlock_t sc_pcu_lock; |
394cf0a1 | 708 | struct mutex mutex; |
9f42c2b6 | 709 | struct work_struct paprd_work; |
347809fc | 710 | struct work_struct hw_check_work; |
236de514 | 711 | struct work_struct hw_reset_work; |
9f42c2b6 | 712 | struct completion paprd_complete; |
394cf0a1 | 713 | |
cb8d61de | 714 | unsigned int hw_busy_count; |
781b14a3 | 715 | unsigned long sc_flags; |
cb8d61de | 716 | |
17d7904d | 717 | u32 intrstatus; |
1b04b930 | 718 | u16 ps_flags; /* PS_* */ |
17d7904d | 719 | u16 curtxpow; |
96148326 | 720 | bool ps_enabled; |
1dbfd9d4 | 721 | bool ps_idle; |
4801416c BG |
722 | short nbcnvifs; |
723 | short nvifs; | |
709ade9e | 724 | unsigned long ps_usecount; |
394cf0a1 | 725 | |
17d7904d | 726 | struct ath_config config; |
394cf0a1 S |
727 | struct ath_rx rx; |
728 | struct ath_tx tx; | |
729 | struct ath_beacon beacon; | |
394cf0a1 S |
730 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
731 | ||
0cf55c21 FF |
732 | #ifdef CONFIG_MAC80211_LEDS |
733 | bool led_registered; | |
734 | char led_name[32]; | |
735 | struct led_classdev led_cdev; | |
736 | #endif | |
394cf0a1 | 737 | |
9ac58615 FF |
738 | struct ath9k_hw_cal_data caldata; |
739 | int last_rssi; | |
740 | ||
a830df07 | 741 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 742 | struct ath9k_debug debug; |
394cf0a1 | 743 | #endif |
6b96f93e | 744 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 745 | struct delayed_work tx_complete_work; |
181fb18d | 746 | struct delayed_work hw_pll_work; |
01e18918 | 747 | struct timer_list rx_poll_timer; |
4daa7760 SM |
748 | |
749 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT | |
2e20250a | 750 | struct ath_btcoex btcoex; |
9e25365f | 751 | struct ath_mci_coex mci_coex; |
3c7992e3 | 752 | struct work_struct mci_work; |
4daa7760 | 753 | #endif |
5088c2f1 VT |
754 | |
755 | struct ath_descdma txsdma; | |
102885a5 VT |
756 | |
757 | struct ath_ant_comb ant_comb; | |
43c35284 | 758 | u8 ant_tx, ant_rx; |
8e92d3f2 | 759 | struct dfs_pattern_detector *dfs_detector; |
b11e640a | 760 | u32 wow_enabled; |
e93d083f SW |
761 | /* relay(fs) channel for spectral scan */ |
762 | struct rchan *rfs_chan_spec_scan; | |
763 | enum spectral_mode spectral_mode; | |
04ccd4a1 | 764 | struct ath_spec_scan spec_config; |
01c78533 MSS |
765 | |
766 | #ifdef CONFIG_PM_SLEEP | |
767 | atomic_t wow_got_bmiss_intr; | |
768 | atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ | |
769 | u32 wow_intr_before_sleep; | |
770 | #endif | |
394cf0a1 S |
771 | }; |
772 | ||
e93d083f SW |
773 | #define SPECTRAL_SCAN_BITMASK 0x10 |
774 | /* Radar info packet format, used for DFS and spectral formats. */ | |
775 | struct ath_radar_info { | |
776 | u8 pulse_length_pri; | |
777 | u8 pulse_length_ext; | |
778 | u8 pulse_bw_info; | |
779 | } __packed; | |
780 | ||
781 | /* The HT20 spectral data has 4 bytes of additional information at it's end. | |
782 | * | |
783 | * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]} | |
784 | * [7:0]: all bins max_magnitude[9:2] | |
785 | * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]} | |
786 | * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned) | |
787 | */ | |
788 | struct ath_ht20_mag_info { | |
789 | u8 all_bins[3]; | |
790 | u8 max_exp; | |
791 | } __packed; | |
792 | ||
793 | #define SPECTRAL_HT20_NUM_BINS 56 | |
794 | ||
795 | /* WARNING: don't actually use this struct! MAC may vary the amount of | |
796 | * data by -1/+2. This struct is for reference only. | |
797 | */ | |
798 | struct ath_ht20_fft_packet { | |
799 | u8 data[SPECTRAL_HT20_NUM_BINS]; | |
800 | struct ath_ht20_mag_info mag_info; | |
801 | struct ath_radar_info radar_info; | |
802 | } __packed; | |
803 | ||
804 | #define SPECTRAL_HT20_TOTAL_DATA_LEN (sizeof(struct ath_ht20_fft_packet)) | |
805 | ||
806 | /* Dynamic 20/40 mode: | |
807 | * | |
808 | * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]} | |
809 | * [7:0]: lower bins max_magnitude[9:2] | |
810 | * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]} | |
811 | * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]} | |
812 | * [7:0]: upper bins max_magnitude[9:2] | |
813 | * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]} | |
814 | * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned) | |
815 | */ | |
816 | struct ath_ht20_40_mag_info { | |
817 | u8 lower_bins[3]; | |
818 | u8 upper_bins[3]; | |
819 | u8 max_exp; | |
820 | } __packed; | |
821 | ||
822 | #define SPECTRAL_HT20_40_NUM_BINS 128 | |
823 | ||
824 | /* WARNING: don't actually use this struct! MAC may vary the amount of | |
825 | * data. This struct is for reference only. | |
826 | */ | |
827 | struct ath_ht20_40_fft_packet { | |
828 | u8 data[SPECTRAL_HT20_40_NUM_BINS]; | |
829 | struct ath_ht20_40_mag_info mag_info; | |
830 | struct ath_radar_info radar_info; | |
831 | } __packed; | |
832 | ||
833 | ||
834 | #define SPECTRAL_HT20_40_TOTAL_DATA_LEN (sizeof(struct ath_ht20_40_fft_packet)) | |
835 | ||
836 | /* grabs the max magnitude from the all/upper/lower bins */ | |
837 | static inline u16 spectral_max_magnitude(u8 *bins) | |
838 | { | |
839 | return (bins[0] & 0xc0) >> 6 | | |
840 | (bins[1] & 0xff) << 2 | | |
841 | (bins[2] & 0x03) << 10; | |
842 | } | |
843 | ||
844 | /* return the max magnitude from the all/upper/lower bins */ | |
845 | static inline u8 spectral_max_index(u8 *bins) | |
846 | { | |
847 | s8 m = (bins[2] & 0xfc) >> 2; | |
848 | ||
849 | /* TODO: this still doesn't always report the right values ... */ | |
850 | if (m > 32) | |
851 | m |= 0xe0; | |
852 | else | |
853 | m &= ~0xe0; | |
854 | ||
855 | return m + 29; | |
856 | } | |
857 | ||
858 | /* return the bitmap weight from the all/upper/lower bins */ | |
859 | static inline u8 spectral_bitmap_weight(u8 *bins) | |
860 | { | |
861 | return bins[0] & 0x3f; | |
862 | } | |
863 | ||
864 | /* FFT sample format given to userspace via debugfs. | |
865 | * | |
866 | * Please keep the type/length at the front position and change | |
867 | * other fields after adding another sample type | |
868 | * | |
869 | * TODO: this might need rework when switching to nl80211-based | |
870 | * interface. | |
871 | */ | |
872 | enum ath_fft_sample_type { | |
4ab0b0aa | 873 | ATH_FFT_SAMPLE_HT20 = 1, |
e93d083f SW |
874 | }; |
875 | ||
876 | struct fft_sample_tlv { | |
877 | u8 type; /* see ath_fft_sample */ | |
12824374 | 878 | __be16 length; |
e93d083f SW |
879 | /* type dependent data follows */ |
880 | } __packed; | |
881 | ||
882 | struct fft_sample_ht20 { | |
883 | struct fft_sample_tlv tlv; | |
884 | ||
4ab0b0aa | 885 | u8 max_exp; |
e93d083f | 886 | |
12824374 | 887 | __be16 freq; |
e93d083f SW |
888 | s8 rssi; |
889 | s8 noise; | |
890 | ||
12824374 | 891 | __be16 max_magnitude; |
e93d083f SW |
892 | u8 max_index; |
893 | u8 bitmap_weight; | |
894 | ||
12824374 | 895 | __be64 tsf; |
e93d083f | 896 | |
4ab0b0aa | 897 | u8 data[SPECTRAL_HT20_NUM_BINS]; |
e93d083f SW |
898 | } __packed; |
899 | ||
55624204 | 900 | void ath9k_tasklet(unsigned long data); |
394cf0a1 S |
901 | int ath_cabq_update(struct ath_softc *); |
902 | ||
5bb12791 | 903 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 904 | { |
5bb12791 | 905 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
906 | } |
907 | ||
394cf0a1 | 908 | extern struct ieee80211_ops ath9k_ops; |
3e6109c5 | 909 | extern int ath9k_modparam_nohwcrypt; |
9a75c2ff | 910 | extern int led_blink; |
d584747b | 911 | extern bool is_ath9k_unloaded; |
394cf0a1 | 912 | |
313eb87f | 913 | u8 ath9k_parse_mpdudensity(u8 mpdudensity); |
394cf0a1 | 914 | irqreturn_t ath_isr(int irq, void *dev); |
eb93e891 | 915 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
5bb12791 | 916 | const struct ath_bus_ops *bus_ops); |
285f2dda | 917 | void ath9k_deinit_device(struct ath_softc *sc); |
285f2dda | 918 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
43c35284 | 919 | void ath9k_reload_chainmask_settings(struct ath_softc *sc); |
68a89116 | 920 | |
4801416c | 921 | bool ath9k_uses_beacons(int type); |
e93d083f SW |
922 | void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw); |
923 | int ath9k_spectral_scan_config(struct ieee80211_hw *hw, | |
924 | enum spectral_mode spectral_mode); | |
925 | ||
394cf0a1 | 926 | |
8e26a030 | 927 | #ifdef CONFIG_ATH9K_PCI |
394cf0a1 S |
928 | int ath_pci_init(void); |
929 | void ath_pci_exit(void); | |
930 | #else | |
931 | static inline int ath_pci_init(void) { return 0; }; | |
932 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 933 | #endif |
f1dc5600 | 934 | |
8e26a030 | 935 | #ifdef CONFIG_ATH9K_AHB |
394cf0a1 S |
936 | int ath_ahb_init(void); |
937 | void ath_ahb_exit(void); | |
938 | #else | |
939 | static inline int ath_ahb_init(void) { return 0; }; | |
940 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 941 | #endif |
394cf0a1 | 942 | |
0bc0798b GJ |
943 | void ath9k_ps_wakeup(struct ath_softc *sc); |
944 | void ath9k_ps_restore(struct ath_softc *sc); | |
8ca21f01 | 945 | |
ea066d5a MSS |
946 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); |
947 | ||
0fca65c1 S |
948 | void ath_start_rfkill_poll(struct ath_softc *sc); |
949 | extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
4801416c BG |
950 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, |
951 | struct ieee80211_vif *vif, | |
952 | struct ath9k_vif_iter_data *iter_data); | |
953 | ||
394cf0a1 | 954 | #endif /* ATH9K_H */ |