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ath9k: send powersave frame on channel switch
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ath9k.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
394cf0a1
S		 20#include <linux/etherdevice.h>
21#include <linux/device.h>
a6b7a407 22#include <linux/interrupt.h>
394cf0a1 23#include <linux/leds.h>
9f42c2b6 24#include <linux/completion.h>
394cf0a1 25
db86f07e 26#include "common.h"
9d83cd5c 27#include "debug.h"
7dc181c2 28#include "mci.h"
8e92d3f2 29#include "dfs.h"
f65c0825 30#include "spectral.h"
db86f07e 31
394cf0a1
S		 32struct ath_node;
33
7b6ef998
SM		 34extern struct ieee80211_ops ath9k_ops;
35extern int ath9k_modparam_nohwcrypt;
36extern int led_blink;
37extern bool is_ath9k_unloaded;
394cf0a1 38
394cf0a1
S		 39/*************************/
40/* Descriptor Management */
41/*************************/
42
7b6ef998
SM		 43#define ATH_TXSTATUS_RING_SIZE 512
44
45/* Macro to expand scalars to 64-bit objects */
46#define ito64(x) (sizeof(x) == 1) ? \
47 (((unsigned long long int)(x)) & (0xff)) : \
48 (sizeof(x) == 2) ? \
49 (((unsigned long long int)(x)) & 0xffff) : \
50 ((sizeof(x) == 4) ? \
51 (((unsigned long long int)(x)) & 0xffffffff) : \
52 (unsigned long long int)(x))
53
394cf0a1 54#define ATH_TXBUF_RESET(_bf) do { \
394cf0a1
S		 55 (_bf)->bf_lastbf = NULL; \
56 (_bf)->bf_next = NULL; \
57 memset(&((_bf)->bf_state), 0, \
58 sizeof(struct ath_buf_state)); \
59 } while (0)
60
c3d77696
MSS		 61#define DS2PHYS(_dd, _ds) \
62 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
63#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
64#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
65
394cf0a1 66struct ath_descdma {
5088c2f1 67 void *dd_desc;
17d7904d
S		 68 dma_addr_t dd_desc_paddr;
69 u32 dd_desc_len;
394cf0a1
S		 70};
71
72int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
73 struct list_head *head, const char *name,
4adfcded 74 int nbuf, int ndesc, bool is_tx);
394cf0a1
S		 75
76/***********/
77/* RX / TX */
78/***********/
79
7b6ef998
SM		 80#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
81
82/* increment with wrap-around */
83#define INCR(_l, _sz) do { \
84 (_l)++; \
85 (_l) &= ((_sz) - 1); \
86 } while (0)
87
394cf0a1 88#define ATH_RXBUF 512
394cf0a1 89#define ATH_TXBUF 512
84642d6b
FF		 90#define ATH_TXBUF_RESERVE 5
91#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
394cf0a1 92#define ATH_TXMAXTRY 13
7b6ef998 93#define ATH_MAX_SW_RETRIES 30
394cf0a1
S		 94
95#define TID_TO_WME_AC(_tid) \
bea843c7
SM		 96 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
97 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \
98 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \
99 IEEE80211_AC_VO)
394cf0a1 100
394cf0a1
S		 101#define ATH_AGGR_DELIM_SZ 4
102#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
103/* number of delimiters for encryption padding */
104#define ATH_AGGR_ENCRYPTDELIM 10
105/* minimum h/w qdepth to be sustained to maximize aggregation */
106#define ATH_AGGR_MIN_QDEPTH 2
2800e82b
FF		 107/* minimum h/w qdepth for non-aggregated traffic */
108#define ATH_NON_AGGR_MIN_QDEPTH 8
7b6ef998
SM		 109#define ATH_TX_COMPLETE_POLL_INT 1000
110#define ATH_TXFIFO_DEPTH 8
111#define ATH_TX_ERROR 0x01
394cf0a1 112
d463af4a
FF		 113/* Stop tx traffic 1ms before the GO goes away */
114#define ATH_P2P_PS_STOP_TIME 1000
115
394cf0a1
S		 116#define IEEE80211_SEQ_SEQ_SHIFT 4
117#define IEEE80211_SEQ_MAX 4096
394cf0a1
S		 118#define IEEE80211_WEP_IVLEN 3
119#define IEEE80211_WEP_KIDLEN 1
120#define IEEE80211_WEP_CRCLEN 4
121#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
122 (IEEE80211_WEP_IVLEN + \
123 IEEE80211_WEP_KIDLEN + \
124 IEEE80211_WEP_CRCLEN))
125
126/* return whether a bit at index _n in bitmap _bm is set
127 * _sz is the size of the bitmap */
128#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
129 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
130
131/* return block-ack bitmap index given sequence and starting sequence */
132#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
133
156369fa
FF		 134/* return the seqno for _start + _offset */
135#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
136
394cf0a1
S		 137/* returns delimiter padding required given the packet length */
138#define ATH_AGGR_GET_NDELIM(_len) \
39ec2997
VT		 139 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
140 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
394cf0a1
S		 141
142#define BAW_WITHIN(_start, _bawsz, _seqno) \
143 ((((_seqno) - (_start)) & 4095) < (_bawsz))
144
394cf0a1
S		 145#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
146
350e2dcb
SM		 147#define IS_HT_RATE(rate) (rate & 0x80)
148#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
149#define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf))
365d2ebc 150
9e495a26
SM		 151enum {
152 WLAN_RC_PHY_OFDM,
153 WLAN_RC_PHY_CCK,
154};
155
394cf0a1 156struct ath_txq {
60f2d1d5
BG		 157 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
158 u32 axq_qnum; /* ath9k hardware queue number */
fce041be 159 void *axq_link;
17d7904d 160 struct list_head axq_q;
394cf0a1 161 spinlock_t axq_lock;
17d7904d 162 u32 axq_depth;
4b3ba66a 163 u32 axq_ampdu_depth;
17d7904d 164 bool stopped;
164ace38 165 bool axq_tx_inprogress;
e5003249 166 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
e5003249
VT		 167 u8 txq_headidx;
168 u8 txq_tailidx;
066dae93 169 int pending_frames;
23de5dc9 170 struct sk_buff_head complete_q;
394cf0a1
S		 171};
172
93ef24b2 173struct ath_atx_ac {
066dae93 174 struct ath_txq *txq;
93ef24b2
S		 175 struct list_head list;
176 struct list_head tid_q;
5519541d 177 bool clear_ps_filter;
50676b81 178 bool sched;
93ef24b2
S		 179};
180
2d42efc4 181struct ath_frame_info {
56dc6336 182 struct ath_buf *bf;
2d42efc4 183 int framelen;
2d42efc4 184 enum ath9k_key_type keytype;
a75c0629 185 u8 keyix;
80b08a8d 186 u8 rtscts_rate;
8fed1408
FF		 187 u8 retries : 7;
188 u8 baw_tracked : 1;
2d42efc4
FF		 189};
190
1a04d59d
FF		 191struct ath_rxbuf {
192 struct list_head list;
193 struct sk_buff *bf_mpdu;
194 void *bf_desc;
195 dma_addr_t bf_daddr;
196 dma_addr_t bf_buf_addr;
197};
198
7b6ef998
SM		 199/**
200 * enum buffer_type - Buffer type flags
201 *
202 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
203 * @BUF_AGGR: Indicates whether the buffer can be aggregated
204 * (used in aggregation scheduling)
205 */
206enum buffer_type {
207 BUF_AMPDU = BIT(0),
208 BUF_AGGR = BIT(1),
209};
210
211#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
212#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
213
93ef24b2 214struct ath_buf_state {
93ef24b2 215 u8 bf_type;
9f42c2b6 216 u8 bfs_paprd;
399c6489 217 u8 ndelim;
50676b81 218 bool stale;
6a0ddaef 219 u16 seqno;
9cf04dcc 220 unsigned long bfs_paprd_timestamp;
93ef24b2
S		 221};
222
223struct ath_buf {
224 struct list_head list;
225 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
226 an aggregate) */
227 struct ath_buf *bf_next; /* next subframe in the aggregate */
228 struct sk_buff *bf_mpdu; /* enclosing frame structure */
229 void *bf_desc; /* virtual addr of desc */
230 dma_addr_t bf_daddr; /* physical addr of desc */
c1739eb3 231 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
79acac07 232 struct ieee80211_tx_rate rates[4];
93ef24b2 233 struct ath_buf_state bf_state;
93ef24b2
S		 234};
235
236struct ath_atx_tid {
237 struct list_head list;
56dc6336 238 struct sk_buff_head buf_q;
bb195ff6 239 struct sk_buff_head retry_q;
93ef24b2
S		 240 struct ath_node *an;
241 struct ath_atx_ac *ac;
81ee13ba 242 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
93ef24b2
S		 243 u16 seq_start;
244 u16 seq_next;
245 u16 baw_size;
50676b81 246 u8 tidno;
93ef24b2
S		 247 int baw_head; /* first un-acked tx buffer */
248 int baw_tail; /* next unused tx buffer slot */
50676b81
FF		 249
250 s8 bar_index;
08c96abd 251 bool sched;
08c96abd 252 bool active;
93ef24b2
S		 253};
254
255struct ath_node {
a145daf7 256 struct ath_softc *sc;
7f010c93 257 struct ieee80211_sta *sta; /* station struct we're part of */
7e1e3864 258 struct ieee80211_vif *vif; /* interface with which we're associated */
de7b7604 259 struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
bea843c7 260 struct ath_atx_ac ac[IEEE80211_NUM_ACS];
93ae2dd2 261
93ef24b2
S		 262 u16 maxampdu;
263 u8 mpdudensity;
50676b81 264 s8 ps_key;
5519541d
FF		 265
266 bool sleeping;
f89d1bc4 267 bool no_ps_filter;
350e2dcb
SM		 268
269#ifdef CONFIG_ATH9K_STATION_STATISTICS
270 struct ath_rx_rate_stats rx_rate_stats;
271#endif
4bbf4414 272 u8 key_idx[4];
93ef24b2
S		 273};
274
394cf0a1
S		 275struct ath_tx_control {
276 struct ath_txq *txq;
2d42efc4 277 struct ath_node *an;
36323f81 278 struct ieee80211_sta *sta;
befcf7e7
FF		 279 u8 paprd;
280 bool force_channel;
394cf0a1
S		 281};
282
394cf0a1 283
60f2d1d5
BG		 284/**
285 * @txq_map: Index is mac80211 queue number. This is
286 * not necessarily the same as the hardware queue number
287 * (axq_qnum).
288 */
394cf0a1
S		 289struct ath_tx {
290 u16 seq_no;
291 u32 txqsetup;
394cf0a1
S		 292 spinlock_t txbuflock;
293 struct list_head txbuf;
294 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
295 struct ath_descdma txdma;
bea843c7 296 struct ath_txq *txq_map[IEEE80211_NUM_ACS];
f2c7a793 297 struct ath_txq *uapsdq;
bea843c7
SM		 298 u32 txq_max_pending[IEEE80211_NUM_ACS];
299 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
394cf0a1
S		 300};
301
b5c80475
FF		 302struct ath_rx_edma {
303 struct sk_buff_head rx_fifo;
b5c80475
FF		 304 u32 rx_fifo_hwsize;
305};
306
394cf0a1
S		 307struct ath_rx {
308 u8 defant;
309 u8 rxotherant;
723e7113 310 bool discard_next;
394cf0a1 311 u32 *rxlink;
6995fb80 312 u32 num_pkts;
394cf0a1 313 unsigned int rxfilter;
394cf0a1
S		 314 struct list_head rxbuf;
315 struct ath_descdma rxdma;
b5c80475 316 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
0d95521e 317
1a04d59d 318 struct ath_rxbuf *buf_hold;
0d95521e 319 struct sk_buff *frag;
21fbbca3
CL		 320
321 u32 ampdu_ref;
394cf0a1
S		 322};
323
fbbcd146
FF		 324struct ath_chanctx {
325 struct cfg80211_chan_def chandef;
326 struct list_head vifs;
0453531e
FF		 327 struct list_head acq[IEEE80211_NUM_ACS];
328
bc7e1be7 329 u16 txpower;
fbbcd146 330 bool offchannel;
bff11766 331 bool stopped;
c083ce99 332 bool active;
fbbcd146
FF		 333};
334
335void ath_chanctx_init(struct ath_softc *sc);
bff11766
FF		 336void ath_chanctx_set_channel(struct ath_softc *sc, struct ath_chanctx *ctx,
337 struct cfg80211_chan_def *chandef);
338void ath_chanctx_switch(struct ath_softc *sc, struct ath_chanctx *ctx,
339 struct cfg80211_chan_def *chandef);
c083ce99
FF		 340void ath_chanctx_check_active(struct ath_softc *sc, struct ath_chanctx *ctx);
341
fbbcd146 342int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan);
394cf0a1
S		 343int ath_startrecv(struct ath_softc *sc);
344bool ath_stoprecv(struct ath_softc *sc);
394cf0a1
S		 345u32 ath_calcrxfilter(struct ath_softc *sc);
346int ath_rx_init(struct ath_softc *sc, int nbufs);
347void ath_rx_cleanup(struct ath_softc *sc);
b5c80475 348int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
394cf0a1 349struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
ef1b6cd9
SM		 350void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
351void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
352void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1 353void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
1381559b
FF		 354bool ath_drain_all_txq(struct ath_softc *sc);
355void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1
S		 356void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
357void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
358void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
0453531e 359void ath_txq_schedule_all(struct ath_softc *sc);
394cf0a1 360int ath_tx_init(struct ath_softc *sc, int nbufs);
394cf0a1
S		 361int ath_txq_update(struct ath_softc *sc, int qnum,
362 struct ath9k_tx_queue_info *q);
aa5955c3 363void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
c52f33d0 364int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
394cf0a1 365 struct ath_tx_control *txctl);
59505c02
FF		 366void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
367 struct sk_buff *skb);
394cf0a1 368void ath_tx_tasklet(struct ath_softc *sc);
e5003249 369void ath_tx_edma_tasklet(struct ath_softc *sc);
231c3a1f
FF		 370int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
371 u16 tid, u16 *ssn);
f83da965 372void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
394cf0a1
S		 373void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
374
5519541d 375void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
042ec453
JB		 376void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
377 struct ath_node *an);
86a22acf
FF		 378void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
379 struct ieee80211_sta *sta,
380 u16 tids, int nframes,
381 enum ieee80211_frame_release_type reason,
382 bool more_data);
5519541d 383
394cf0a1 384/********/
17d7904d 385/* VIFs */
394cf0a1 386/********/
f078f209 387
17d7904d 388struct ath_vif {
fbbcd146
FF		 389 struct list_head list;
390
d463af4a 391 struct ieee80211_vif *vif;
f89d1bc4 392 struct ath_node mcast_node;
394cf0a1 393 int av_bslot;
aa45fe96 394 bool primary_sta_vif;
4ed96f04 395 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
394cf0a1 396 struct ath_buf *av_bcbuf;
fbbcd146 397 struct ath_chanctx *chanctx;
d463af4a
FF		 398
399 /* P2P Client */
400 struct ieee80211_noa_data noa;
f078f209
LR		 401};
402
7b6ef998
SM		 403struct ath9k_vif_iter_data {
404 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
405 u8 mask[ETH_ALEN]; /* bssid mask */
406 bool has_hw_macaddr;
407
408 int naps; /* number of AP vifs */
409 int nmeshes; /* number of mesh vifs */
410 int nstations; /* number of station vifs */
411 int nwds; /* number of WDS vifs */
412 int nadhocs; /* number of adhoc vifs */
413};
414
415void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
416 struct ieee80211_vif *vif,
417 struct ath9k_vif_iter_data *iter_data);
418
394cf0a1
S		 419/*******************/
420/* Beacon Handling */
421/*******************/
f078f209 422
394cf0a1
S		 423/*
424 * Regardless of the number of beacons we stagger, (i.e. regardless of the
425 * number of BSSIDs) if a given beacon does not go out even after waiting this
426 * number of beacon intervals, the game's up.
427 */
c944daf4 428#define BSTUCK_THRESH 9
689e756f 429#define ATH_BCBUF 8
394cf0a1
S		 430#define ATH_DEFAULT_BINTVAL 100 /* TU */
431#define ATH_DEFAULT_BMISS_LIMIT 10
394cf0a1 432
7b6ef998
SM		 433#define TSF_TO_TU(_h,_l) \
434 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
435
394cf0a1
S		 436struct ath_beacon {
437 enum {
438 OK, /* no change needed */
439 UPDATE, /* update pending */
440 COMMIT /* beacon sent, commit change */
441 } updateslot; /* slot time update fsm */
442
443 u32 beaconq;
444 u32 bmisscnt;
2c3db3d5 445 struct ieee80211_vif *bslot[ATH_BCBUF];
394cf0a1
S		 446 int slottime;
447 int slotupdate;
394cf0a1
S		 448 struct ath_descdma bdma;
449 struct ath_txq *cabq;
450 struct list_head bbuf;
ba4903f9
FF		 451
452 bool tx_processed;
453 bool tx_last;
394cf0a1
S		 454};
455
fb6e252f 456void ath9k_beacon_tasklet(unsigned long data);
ef4ad633
SM		 457void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
458 u32 changed);
130ef6e9
SM		 459void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
460void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
ef4ad633 461void ath9k_set_beacon(struct ath_softc *sc);
4effc6fd
MK		 462bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif);
463void ath9k_csa_update(struct ath_softc *sc);
394cf0a1 464
ef1b6cd9
SM		 465/*******************/
466/* Link Monitoring */
467/*******************/
f078f209 468
20977d3e
S		 469#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
470#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
e36b27af
LR		 471#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
472#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
6044474e 473#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
20977d3e
S		 474#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
475#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
7b6ef998
SM		 476#define ATH_ANI_MAX_SKIP_COUNT 10
477#define ATH_PAPRD_TIMEOUT 100 /* msecs */
478#define ATH_PLL_WORK_INTERVAL 100
ca369eb4 479
bff11766 480void ath_chanctx_work(struct work_struct *work);
ef1b6cd9 481void ath_tx_complete_poll_work(struct work_struct *work);
236de514 482void ath_reset_work(struct work_struct *work);
415ec61b 483bool ath_hw_check(struct ath_softc *sc);
9eab61c2 484void ath_hw_pll_work(struct work_struct *work);
9f42c2b6 485void ath_paprd_calibrate(struct work_struct *work);
55624204 486void ath_ani_calibrate(unsigned long data);
da0d45f7
SM		 487void ath_start_ani(struct ath_softc *sc);
488void ath_stop_ani(struct ath_softc *sc);
489void ath_check_ani(struct ath_softc *sc);
ef1b6cd9
SM		 490int ath_update_survey_stats(struct ath_softc *sc);
491void ath_update_survey_nf(struct ath_softc *sc, int channel);
124b979b 492void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
bf3dac5a 493void ath_ps_full_sleep(unsigned long data);
d463af4a
FF		 494void ath9k_p2p_ps_timer(void *priv);
495void ath9k_update_p2p_ps(struct ath_softc *sc, struct ieee80211_vif *vif);
bff11766 496void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop);
55624204 497
0fca65c1
S		 498/**********/
499/* BTCOEX */
500/**********/
501
ac46ba43
SM		 502#define ATH_DUMP_BTCOEX(_s, _val) \
503 do { \
5e88ba62
ZK		 504 len += scnprintf(buf + len, size - len, \
505 "%20s : %10d\n", _s, (_val)); \
ac46ba43
SM		 506 } while (0)
507
e6930c4b
SM		 508enum bt_op_flags {
509 BT_OP_PRIORITY_DETECTED,
510 BT_OP_SCAN,
511};
512
2e20250a 513struct ath_btcoex {
2e20250a
LR		 514 spinlock_t btcoex_lock;
515 struct timer_list period_timer; /* Timer for BT period */
168c6f89 516 struct timer_list no_stomp_timer;
2e20250a
LR		 517 u32 bt_priority_cnt;
518 unsigned long bt_priority_time;
e6930c4b 519 unsigned long op_flags;
e08a6ace 520 int bt_stomp_type; /* Types of BT stomping */
168c6f89 521 u32 btcoex_no_stomp; /* in msec */
94ae77ea 522 u32 btcoex_period; /* in msec */
168c6f89 523 u32 btscan_no_stomp; /* in msec */
7dc181c2 524 u32 duty_cycle;
6995fb80 525 u32 bt_wait_time;
e82cb03f 526 int rssi_count;
7dc181c2 527 struct ath_mci_profile mci;
2884561a 528 u8 stomp_audio;
2e20250a
LR		 529};
530
4daa7760 531#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
5908120f
SM		 532int ath9k_init_btcoex(struct ath_softc *sc);
533void ath9k_deinit_btcoex(struct ath_softc *sc);
df198b17
SM		 534void ath9k_start_btcoex(struct ath_softc *sc);
535void ath9k_stop_btcoex(struct ath_softc *sc);
0fca65c1
S		 536void ath9k_btcoex_timer_resume(struct ath_softc *sc);
537void ath9k_btcoex_timer_pause(struct ath_softc *sc);
56ca0dba 538void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
c0ac53fa 539u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
08d4df41 540void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
ac46ba43 541int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
4daa7760
SM		 542#else
543static inline int ath9k_init_btcoex(struct ath_softc *sc)
544{
545 return 0;
546}
547static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
548{
549}
550static inline void ath9k_start_btcoex(struct ath_softc *sc)
551{
552}
553static inline void ath9k_stop_btcoex(struct ath_softc *sc)
554{
555}
556static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
557 u32 status)
558{
559}
560static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
561 u32 max_4ms_framelen)
562{
563 return 0;
564}
08d4df41
RM		 565static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
566{
567}
ac46ba43 568static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
4df50ca8
RM		 569{
570 return 0;
571}
4daa7760 572#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0fca65c1 573
394cf0a1
S		 574/********************/
575/* LED Control */
576/********************/
f078f209 577
08fc5c1b
VN		 578#define ATH_LED_PIN_DEF 1
579#define ATH_LED_PIN_9287 8
353e5019 580#define ATH_LED_PIN_9300 10
15178535 581#define ATH_LED_PIN_9485 6
1a68abb0 582#define ATH_LED_PIN_9462 4
f078f209 583
0cf55c21 584#ifdef CONFIG_MAC80211_LEDS
0fca65c1
S		 585void ath_init_leds(struct ath_softc *sc);
586void ath_deinit_leds(struct ath_softc *sc);
8f176a3a 587void ath_fill_led_pin(struct ath_softc *sc);
0cf55c21
FF		 588#else
589static inline void ath_init_leds(struct ath_softc *sc)
590{
591}
592
593static inline void ath_deinit_leds(struct ath_softc *sc)
8f176a3a
RM		 594{
595}
596static inline void ath_fill_led_pin(struct ath_softc *sc)
0cf55c21
FF		 597{
598}
599#endif
600
e60001e7
SM		 601/************************/
602/* Wake on Wireless LAN */
603/************************/
604
7b6ef998
SM		 605struct ath9k_wow_pattern {
606 u8 pattern_bytes[MAX_PATTERN_SIZE];
607 u8 mask_bytes[MAX_PATTERN_SIZE];
608 u32 pattern_len;
609};
610
e60001e7 611#ifdef CONFIG_ATH9K_WOW
babaa80a 612void ath9k_init_wow(struct ieee80211_hw *hw);
e60001e7
SM		 613int ath9k_suspend(struct ieee80211_hw *hw,
614 struct cfg80211_wowlan *wowlan);
615int ath9k_resume(struct ieee80211_hw *hw);
616void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
617#else
babaa80a
SM		 618static inline void ath9k_init_wow(struct ieee80211_hw *hw)
619{
620}
e60001e7
SM		 621static inline int ath9k_suspend(struct ieee80211_hw *hw,
622 struct cfg80211_wowlan *wowlan)
623{
624 return 0;
625}
626static inline int ath9k_resume(struct ieee80211_hw *hw)
627{
628 return 0;
629}
630static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
631{
632}
633#endif /* CONFIG_ATH9K_WOW */
634
8da07830 635/*******************************/
102885a5 636/* Antenna diversity/combining */
8da07830
SM		 637/*******************************/
638
102885a5
VT		 639#define ATH_ANT_RX_CURRENT_SHIFT 4
640#define ATH_ANT_RX_MAIN_SHIFT 2
641#define ATH_ANT_RX_MASK 0x3
642
643#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
644#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
645#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
646#define ATH_ANT_DIV_COMB_INIT_COUNT 95
647#define ATH_ANT_DIV_COMB_MAX_COUNT 100
648#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
649#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
3afa6b4f
SM		 650#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50
651#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50
102885a5 652
102885a5
VT		 653#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
654#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
655#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
656
102885a5
VT		 657struct ath_ant_comb {
658 u16 count;
659 u16 total_pkt_count;
660 bool scan;
661 bool scan_not_start;
662 int main_total_rssi;
663 int alt_total_rssi;
664 int alt_recv_cnt;
665 int main_recv_cnt;
666 int rssi_lna1;
667 int rssi_lna2;
668 int rssi_add;
669 int rssi_sub;
670 int rssi_first;
671 int rssi_second;
672 int rssi_third;
3afa6b4f
SM		 673 int ant_ratio;
674 int ant_ratio2;
102885a5
VT		 675 bool alt_good;
676 int quick_scan_cnt;
3fbaf4c5 677 enum ath9k_ant_div_comb_lna_conf main_conf;
102885a5
VT		 678 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
679 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
102885a5
VT		 680 bool first_ratio;
681 bool second_ratio;
682 unsigned long scan_start_time;
3afa6b4f
SM		 683
684 /*
685 * Card-specific config values.
686 */
687 int low_rssi_thresh;
688 int fast_div_bias;
102885a5
VT		 689};
690
8da07830 691void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
8da07830 692
394cf0a1
S		 693/********************/
694/* Main driver core */
695/********************/
f078f209 696
2d22c7dd
SM		 697#define ATH9K_PCI_CUS198 0x0001
698#define ATH9K_PCI_CUS230 0x0002
699#define ATH9K_PCI_CUS217 0x0004
700#define ATH9K_PCI_CUS252 0x0008
701#define ATH9K_PCI_WOW 0x0010
702#define ATH9K_PCI_BT_ANT_DIV 0x0020
703#define ATH9K_PCI_D3_L1_WAR 0x0040
704#define ATH9K_PCI_AR9565_1ANT 0x0080
705#define ATH9K_PCI_AR9565_2ANT 0x0100
706#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
4dd35640 707#define ATH9K_PCI_KILLER 0x0400
9b60b64b 708
394cf0a1
S		 709/*
710 * Default cache line size, in bytes.
711 * Used when PCI device not fully initialized by bootrom/BIOS
712*/
713#define DEFAULT_CACHELINE 32
394cf0a1 714#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
394cf0a1 715#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
071aa9a8 716#define MAX_GTT_CNT 5
394cf0a1 717
1b04b930
S		 718/* Powersave flags */
719#define PS_WAIT_FOR_BEACON BIT(0)
720#define PS_WAIT_FOR_CAB BIT(1)
721#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
722#define PS_WAIT_FOR_TX_ACK BIT(3)
723#define PS_BEACON_SYNC BIT(4)
424749c7 724#define PS_WAIT_FOR_ANI BIT(5)
394cf0a1 725
fbbcd146
FF		 726#define ATH9K_NUM_CHANCTX 2 /* supports 2 operating channels */
727
394cf0a1
S		 728struct ath_softc {
729 struct ieee80211_hw *hw;
730 struct device *dev;
c52f33d0 731
3430098a
FF		 732 struct survey_info *cur_survey;
733 struct survey_info survey[ATH9K_NUM_CHANNELS];
0e2dedf9 734
394cf0a1
S		 735 struct tasklet_struct intr_tq;
736 struct tasklet_struct bcon_tasklet;
cbe61d8a 737 struct ath_hw *sc_ah;
394cf0a1
S		 738 void __iomem *mem;
739 int irq;
2d6a5e95 740 spinlock_t sc_serial_rw;
04717ccd 741 spinlock_t sc_pm_lock;
4bdd1e97 742 spinlock_t sc_pcu_lock;
394cf0a1 743 struct mutex mutex;
9f42c2b6 744 struct work_struct paprd_work;
236de514 745 struct work_struct hw_reset_work;
bff11766 746 struct work_struct chanctx_work;
9f42c2b6 747 struct completion paprd_complete;
10e23181 748 wait_queue_head_t tx_wait;
394cf0a1 749
d463af4a
FF		 750 struct ath_gen_timer *p2p_ps_timer;
751 struct ath_vif *p2p_ps_vif;
752
9b60b64b 753 unsigned long driver_data;
cb8d61de 754
071aa9a8 755 u8 gtt_cnt;
17d7904d 756 u32 intrstatus;
1b04b930 757 u16 ps_flags; /* PS_* */
17d7904d 758 u16 curtxpow;
96148326 759 bool ps_enabled;
1dbfd9d4 760 bool ps_idle;
4801416c
BG		 761 short nbcnvifs;
762 short nvifs;
709ade9e 763 unsigned long ps_usecount;
394cf0a1 764
394cf0a1
S		 765 struct ath_rx rx;
766 struct ath_tx tx;
767 struct ath_beacon beacon;
394cf0a1 768
bff11766 769 struct cfg80211_chan_def cur_chandef;
fbbcd146
FF		 770 struct ath_chanctx chanctx[ATH9K_NUM_CHANCTX];
771 struct ath_chanctx *cur_chan;
bff11766
FF		 772 struct ath_chanctx *next_chan;
773 spinlock_t chan_lock;
fbbcd146 774
0cf55c21
FF		 775#ifdef CONFIG_MAC80211_LEDS
776 bool led_registered;
777 char led_name[32];
778 struct led_classdev led_cdev;
779#endif
394cf0a1 780
9ac58615 781 struct ath9k_hw_cal_data caldata;
9ac58615 782
a830df07 783#ifdef CONFIG_ATH9K_DEBUGFS
17d7904d 784 struct ath9k_debug debug;
394cf0a1 785#endif
6b96f93e 786 struct ath_beacon_config cur_beacon_conf;
164ace38 787 struct delayed_work tx_complete_work;
181fb18d 788 struct delayed_work hw_pll_work;
bf3dac5a 789 struct timer_list sleep_timer;
4daa7760
SM		 790
791#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2e20250a 792 struct ath_btcoex btcoex;
9e25365f 793 struct ath_mci_coex mci_coex;
3c7992e3 794 struct work_struct mci_work;
4daa7760 795#endif
5088c2f1
VT		 796
797 struct ath_descdma txsdma;
102885a5
VT		 798
799 struct ath_ant_comb ant_comb;
43c35284 800 u8 ant_tx, ant_rx;
8e92d3f2 801 struct dfs_pattern_detector *dfs_detector;
3f3c09f3 802 u64 dfs_prev_pulse_ts;
b11e640a 803 u32 wow_enabled;
e93d083f
SW		 804 /* relay(fs) channel for spectral scan */
805 struct rchan *rfs_chan_spec_scan;
806 enum spectral_mode spectral_mode;
04ccd4a1 807 struct ath_spec_scan spec_config;
01c78533 808
89f927af
LR		 809 struct ieee80211_vif *tx99_vif;
810 struct sk_buff *tx99_skb;
811 bool tx99_state;
812 s16 tx99_power;
813
e60001e7 814#ifdef CONFIG_ATH9K_WOW
01c78533
MSS		 815 atomic_t wow_got_bmiss_intr;
816 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
817 u32 wow_intr_before_sleep;
818#endif
394cf0a1
S		 819};
820
ef6b19e4
SM		 821/********/
822/* TX99 */
823/********/
824
825#ifdef CONFIG_ATH9K_TX99
826void ath9k_tx99_init_debug(struct ath_softc *sc);
89f927af
LR		 827int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
828 struct ath_tx_control *txctl);
ef6b19e4
SM		 829#else
830static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
831{
832}
833static inline int ath9k_tx99_send(struct ath_softc *sc,
834 struct sk_buff *skb,
835 struct ath_tx_control *txctl)
836{
837 return 0;
838}
839#endif /* CONFIG_ATH9K_TX99 */
89f927af 840
5bb12791 841static inline void ath_read_cachesize(struct ath_common *common, int *csz)
394cf0a1 842{
5bb12791 843 common->bus_ops->read_cachesize(common, csz);
394cf0a1
S		 844}
845
7b6ef998
SM		 846void ath9k_tasklet(unsigned long data);
847int ath_cabq_update(struct ath_softc *);
313eb87f 848u8 ath9k_parse_mpdudensity(u8 mpdudensity);
394cf0a1 849irqreturn_t ath_isr(int irq, void *dev);
ef6b19e4 850int ath_reset(struct ath_softc *sc);
e60001e7
SM		 851void ath_cancel_work(struct ath_softc *sc);
852void ath_restart_work(struct ath_softc *sc);
eb93e891 853int ath9k_init_device(u16 devid, struct ath_softc *sc,
5bb12791 854 const struct ath_bus_ops *bus_ops);
285f2dda 855void ath9k_deinit_device(struct ath_softc *sc);
43c35284 856void ath9k_reload_chainmask_settings(struct ath_softc *sc);
7b6ef998
SM		 857u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
858void ath_start_rfkill_poll(struct ath_softc *sc);
859void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
860void ath9k_ps_wakeup(struct ath_softc *sc);
861void ath9k_ps_restore(struct ath_softc *sc);
68a89116 862
8e26a030 863#ifdef CONFIG_ATH9K_PCI
394cf0a1
S		 864int ath_pci_init(void);
865void ath_pci_exit(void);
866#else
867static inline int ath_pci_init(void) { return 0; };
868static inline void ath_pci_exit(void) {};
f1dc5600 869#endif
f1dc5600 870
8e26a030 871#ifdef CONFIG_ATH9K_AHB
394cf0a1
S		 872int ath_ahb_init(void);
873void ath_ahb_exit(void);
874#else
875static inline int ath_ahb_init(void) { return 0; };
876static inline void ath_ahb_exit(void) {};
f078f209 877#endif
394cf0a1 878
394cf0a1 879#endif /* ATH9K_H */
Linux kernel - Deliverables
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