Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
a6b7a407 | 22 | #include <linux/interrupt.h> |
394cf0a1 | 23 | #include <linux/leds.h> |
9f42c2b6 | 24 | #include <linux/completion.h> |
394cf0a1 | 25 | |
db86f07e | 26 | #include "common.h" |
9d83cd5c | 27 | #include "debug.h" |
7dc181c2 | 28 | #include "mci.h" |
8e92d3f2 | 29 | #include "dfs.h" |
f65c0825 | 30 | #include "spectral.h" |
db86f07e | 31 | |
394cf0a1 S |
32 | struct ath_node; |
33 | ||
7b6ef998 SM |
34 | extern struct ieee80211_ops ath9k_ops; |
35 | extern int ath9k_modparam_nohwcrypt; | |
36 | extern int led_blink; | |
37 | extern bool is_ath9k_unloaded; | |
78b21949 | 38 | extern int ath9k_use_chanctx; |
394cf0a1 | 39 | |
394cf0a1 S |
40 | /*************************/ |
41 | /* Descriptor Management */ | |
42 | /*************************/ | |
43 | ||
7b6ef998 SM |
44 | #define ATH_TXSTATUS_RING_SIZE 512 |
45 | ||
46 | /* Macro to expand scalars to 64-bit objects */ | |
47 | #define ito64(x) (sizeof(x) == 1) ? \ | |
48 | (((unsigned long long int)(x)) & (0xff)) : \ | |
49 | (sizeof(x) == 2) ? \ | |
50 | (((unsigned long long int)(x)) & 0xffff) : \ | |
51 | ((sizeof(x) == 4) ? \ | |
52 | (((unsigned long long int)(x)) & 0xffffffff) : \ | |
53 | (unsigned long long int)(x)) | |
54 | ||
394cf0a1 | 55 | #define ATH_TXBUF_RESET(_bf) do { \ |
394cf0a1 S |
56 | (_bf)->bf_lastbf = NULL; \ |
57 | (_bf)->bf_next = NULL; \ | |
58 | memset(&((_bf)->bf_state), 0, \ | |
59 | sizeof(struct ath_buf_state)); \ | |
60 | } while (0) | |
61 | ||
c3d77696 MSS |
62 | #define DS2PHYS(_dd, _ds) \ |
63 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
64 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
65 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
66 | ||
394cf0a1 | 67 | struct ath_descdma { |
5088c2f1 | 68 | void *dd_desc; |
17d7904d S |
69 | dma_addr_t dd_desc_paddr; |
70 | u32 dd_desc_len; | |
394cf0a1 S |
71 | }; |
72 | ||
73 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
74 | struct list_head *head, const char *name, | |
4adfcded | 75 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
76 | |
77 | /***********/ | |
78 | /* RX / TX */ | |
79 | /***********/ | |
80 | ||
7b6ef998 SM |
81 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) |
82 | ||
83 | /* increment with wrap-around */ | |
84 | #define INCR(_l, _sz) do { \ | |
85 | (_l)++; \ | |
86 | (_l) &= ((_sz) - 1); \ | |
87 | } while (0) | |
88 | ||
394cf0a1 | 89 | #define ATH_RXBUF 512 |
394cf0a1 | 90 | #define ATH_TXBUF 512 |
84642d6b FF |
91 | #define ATH_TXBUF_RESERVE 5 |
92 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 93 | #define ATH_TXMAXTRY 13 |
7b6ef998 | 94 | #define ATH_MAX_SW_RETRIES 30 |
394cf0a1 S |
95 | |
96 | #define TID_TO_WME_AC(_tid) \ | |
bea843c7 SM |
97 | ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ |
98 | (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ | |
99 | (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ | |
100 | IEEE80211_AC_VO) | |
394cf0a1 | 101 | |
394cf0a1 S |
102 | #define ATH_AGGR_DELIM_SZ 4 |
103 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
104 | /* number of delimiters for encryption padding */ | |
105 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
106 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
107 | #define ATH_AGGR_MIN_QDEPTH 2 | |
2800e82b FF |
108 | /* minimum h/w qdepth for non-aggregated traffic */ |
109 | #define ATH_NON_AGGR_MIN_QDEPTH 8 | |
7b6ef998 SM |
110 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
111 | #define ATH_TXFIFO_DEPTH 8 | |
112 | #define ATH_TX_ERROR 0x01 | |
394cf0a1 | 113 | |
d463af4a FF |
114 | /* Stop tx traffic 1ms before the GO goes away */ |
115 | #define ATH_P2P_PS_STOP_TIME 1000 | |
116 | ||
394cf0a1 S |
117 | #define IEEE80211_SEQ_SEQ_SHIFT 4 |
118 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
119 | #define IEEE80211_WEP_IVLEN 3 |
120 | #define IEEE80211_WEP_KIDLEN 1 | |
121 | #define IEEE80211_WEP_CRCLEN 4 | |
122 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
123 | (IEEE80211_WEP_IVLEN + \ | |
124 | IEEE80211_WEP_KIDLEN + \ | |
125 | IEEE80211_WEP_CRCLEN)) | |
126 | ||
127 | /* return whether a bit at index _n in bitmap _bm is set | |
128 | * _sz is the size of the bitmap */ | |
129 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
130 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
131 | ||
132 | /* return block-ack bitmap index given sequence and starting sequence */ | |
133 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
134 | ||
156369fa FF |
135 | /* return the seqno for _start + _offset */ |
136 | #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) | |
137 | ||
394cf0a1 S |
138 | /* returns delimiter padding required given the packet length */ |
139 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
39ec2997 VT |
140 | (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ |
141 | DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) | |
394cf0a1 S |
142 | |
143 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
144 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
145 | ||
394cf0a1 S |
146 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
147 | ||
350e2dcb SM |
148 | #define IS_HT_RATE(rate) (rate & 0x80) |
149 | #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) | |
150 | #define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf)) | |
365d2ebc | 151 | |
9e495a26 SM |
152 | enum { |
153 | WLAN_RC_PHY_OFDM, | |
154 | WLAN_RC_PHY_CCK, | |
155 | }; | |
156 | ||
394cf0a1 | 157 | struct ath_txq { |
60f2d1d5 BG |
158 | int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ |
159 | u32 axq_qnum; /* ath9k hardware queue number */ | |
fce041be | 160 | void *axq_link; |
17d7904d | 161 | struct list_head axq_q; |
394cf0a1 | 162 | spinlock_t axq_lock; |
17d7904d | 163 | u32 axq_depth; |
4b3ba66a | 164 | u32 axq_ampdu_depth; |
17d7904d | 165 | bool stopped; |
164ace38 | 166 | bool axq_tx_inprogress; |
e5003249 | 167 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
e5003249 VT |
168 | u8 txq_headidx; |
169 | u8 txq_tailidx; | |
066dae93 | 170 | int pending_frames; |
23de5dc9 | 171 | struct sk_buff_head complete_q; |
394cf0a1 S |
172 | }; |
173 | ||
93ef24b2 | 174 | struct ath_atx_ac { |
066dae93 | 175 | struct ath_txq *txq; |
93ef24b2 S |
176 | struct list_head list; |
177 | struct list_head tid_q; | |
5519541d | 178 | bool clear_ps_filter; |
50676b81 | 179 | bool sched; |
93ef24b2 S |
180 | }; |
181 | ||
2d42efc4 | 182 | struct ath_frame_info { |
56dc6336 | 183 | struct ath_buf *bf; |
2d42efc4 | 184 | int framelen; |
2d42efc4 | 185 | enum ath9k_key_type keytype; |
a75c0629 | 186 | u8 keyix; |
80b08a8d | 187 | u8 rtscts_rate; |
8fed1408 FF |
188 | u8 retries : 7; |
189 | u8 baw_tracked : 1; | |
2d42efc4 FF |
190 | }; |
191 | ||
1a04d59d FF |
192 | struct ath_rxbuf { |
193 | struct list_head list; | |
194 | struct sk_buff *bf_mpdu; | |
195 | void *bf_desc; | |
196 | dma_addr_t bf_daddr; | |
197 | dma_addr_t bf_buf_addr; | |
198 | }; | |
199 | ||
7b6ef998 SM |
200 | /** |
201 | * enum buffer_type - Buffer type flags | |
202 | * | |
203 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
204 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
205 | * (used in aggregation scheduling) | |
206 | */ | |
207 | enum buffer_type { | |
208 | BUF_AMPDU = BIT(0), | |
209 | BUF_AGGR = BIT(1), | |
210 | }; | |
211 | ||
212 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
213 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
214 | ||
93ef24b2 | 215 | struct ath_buf_state { |
93ef24b2 | 216 | u8 bf_type; |
9f42c2b6 | 217 | u8 bfs_paprd; |
399c6489 | 218 | u8 ndelim; |
50676b81 | 219 | bool stale; |
6a0ddaef | 220 | u16 seqno; |
9cf04dcc | 221 | unsigned long bfs_paprd_timestamp; |
93ef24b2 S |
222 | }; |
223 | ||
224 | struct ath_buf { | |
225 | struct list_head list; | |
226 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
227 | an aggregate) */ | |
228 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
229 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
230 | void *bf_desc; /* virtual addr of desc */ | |
231 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
c1739eb3 | 232 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
79acac07 | 233 | struct ieee80211_tx_rate rates[4]; |
93ef24b2 | 234 | struct ath_buf_state bf_state; |
93ef24b2 S |
235 | }; |
236 | ||
237 | struct ath_atx_tid { | |
238 | struct list_head list; | |
56dc6336 | 239 | struct sk_buff_head buf_q; |
bb195ff6 | 240 | struct sk_buff_head retry_q; |
93ef24b2 S |
241 | struct ath_node *an; |
242 | struct ath_atx_ac *ac; | |
81ee13ba | 243 | unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; |
93ef24b2 S |
244 | u16 seq_start; |
245 | u16 seq_next; | |
246 | u16 baw_size; | |
50676b81 | 247 | u8 tidno; |
93ef24b2 S |
248 | int baw_head; /* first un-acked tx buffer */ |
249 | int baw_tail; /* next unused tx buffer slot */ | |
50676b81 FF |
250 | |
251 | s8 bar_index; | |
08c96abd | 252 | bool sched; |
08c96abd | 253 | bool active; |
93ef24b2 S |
254 | }; |
255 | ||
256 | struct ath_node { | |
a145daf7 | 257 | struct ath_softc *sc; |
7f010c93 | 258 | struct ieee80211_sta *sta; /* station struct we're part of */ |
7e1e3864 | 259 | struct ieee80211_vif *vif; /* interface with which we're associated */ |
de7b7604 | 260 | struct ath_atx_tid tid[IEEE80211_NUM_TIDS]; |
bea843c7 | 261 | struct ath_atx_ac ac[IEEE80211_NUM_ACS]; |
93ae2dd2 | 262 | |
93ef24b2 S |
263 | u16 maxampdu; |
264 | u8 mpdudensity; | |
50676b81 | 265 | s8 ps_key; |
5519541d FF |
266 | |
267 | bool sleeping; | |
f89d1bc4 | 268 | bool no_ps_filter; |
350e2dcb SM |
269 | |
270 | #ifdef CONFIG_ATH9K_STATION_STATISTICS | |
271 | struct ath_rx_rate_stats rx_rate_stats; | |
272 | #endif | |
4bbf4414 | 273 | u8 key_idx[4]; |
93ef24b2 S |
274 | }; |
275 | ||
394cf0a1 S |
276 | struct ath_tx_control { |
277 | struct ath_txq *txq; | |
2d42efc4 | 278 | struct ath_node *an; |
36323f81 | 279 | struct ieee80211_sta *sta; |
befcf7e7 FF |
280 | u8 paprd; |
281 | bool force_channel; | |
394cf0a1 S |
282 | }; |
283 | ||
394cf0a1 | 284 | |
60f2d1d5 BG |
285 | /** |
286 | * @txq_map: Index is mac80211 queue number. This is | |
287 | * not necessarily the same as the hardware queue number | |
288 | * (axq_qnum). | |
289 | */ | |
394cf0a1 S |
290 | struct ath_tx { |
291 | u16 seq_no; | |
292 | u32 txqsetup; | |
394cf0a1 S |
293 | spinlock_t txbuflock; |
294 | struct list_head txbuf; | |
295 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
296 | struct ath_descdma txdma; | |
bea843c7 | 297 | struct ath_txq *txq_map[IEEE80211_NUM_ACS]; |
f2c7a793 | 298 | struct ath_txq *uapsdq; |
bea843c7 SM |
299 | u32 txq_max_pending[IEEE80211_NUM_ACS]; |
300 | u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; | |
394cf0a1 S |
301 | }; |
302 | ||
b5c80475 FF |
303 | struct ath_rx_edma { |
304 | struct sk_buff_head rx_fifo; | |
b5c80475 FF |
305 | u32 rx_fifo_hwsize; |
306 | }; | |
307 | ||
394cf0a1 S |
308 | struct ath_rx { |
309 | u8 defant; | |
310 | u8 rxotherant; | |
723e7113 | 311 | bool discard_next; |
394cf0a1 | 312 | u32 *rxlink; |
6995fb80 | 313 | u32 num_pkts; |
394cf0a1 | 314 | unsigned int rxfilter; |
394cf0a1 S |
315 | struct list_head rxbuf; |
316 | struct ath_descdma rxdma; | |
b5c80475 | 317 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; |
0d95521e | 318 | |
1a04d59d | 319 | struct ath_rxbuf *buf_hold; |
0d95521e | 320 | struct sk_buff *frag; |
21fbbca3 CL |
321 | |
322 | u32 ampdu_ref; | |
394cf0a1 S |
323 | }; |
324 | ||
fbbcd146 FF |
325 | struct ath_chanctx { |
326 | struct cfg80211_chan_def chandef; | |
327 | struct list_head vifs; | |
0453531e FF |
328 | struct list_head acq[IEEE80211_NUM_ACS]; |
329 | ||
bc7e1be7 | 330 | u16 txpower; |
fbbcd146 | 331 | bool offchannel; |
bff11766 | 332 | bool stopped; |
c083ce99 | 333 | bool active; |
39305635 | 334 | bool assigned; |
fbbcd146 FF |
335 | }; |
336 | ||
78b21949 FF |
337 | enum ath_offchannel_state { |
338 | ATH_OFFCHANNEL_IDLE, | |
339 | ATH_OFFCHANNEL_PROBE_SEND, | |
340 | ATH_OFFCHANNEL_PROBE_WAIT, | |
341 | ATH_OFFCHANNEL_SUSPEND, | |
405393cf FF |
342 | ATH_OFFCHANNEL_ROC_START, |
343 | ATH_OFFCHANNEL_ROC_WAIT, | |
344 | ATH_OFFCHANNEL_ROC_DONE, | |
78b21949 FF |
345 | }; |
346 | ||
347 | struct ath_offchannel { | |
348 | struct ath_chanctx chan; | |
349 | struct timer_list timer; | |
350 | struct cfg80211_scan_request *scan_req; | |
351 | struct ieee80211_vif *scan_vif; | |
352 | int scan_idx; | |
353 | enum ath_offchannel_state state; | |
405393cf FF |
354 | struct ieee80211_channel *roc_chan; |
355 | struct ieee80211_vif *roc_vif; | |
356 | int roc_duration; | |
78b21949 | 357 | }; |
c4dc0d04 RM |
358 | #define ath_for_each_chanctx(_sc, _ctx) \ |
359 | for (ctx = &sc->chanctx[0]; \ | |
360 | ctx <= &sc->chanctx[ARRAY_SIZE(sc->chanctx) - 1]; \ | |
361 | ctx++) | |
78b21949 FF |
362 | |
363 | void ath9k_fill_chanctx_ops(void); | |
39305635 FF |
364 | static inline struct ath_chanctx * |
365 | ath_chanctx_get(struct ieee80211_chanctx_conf *ctx) | |
366 | { | |
367 | struct ath_chanctx **ptr = (void *) ctx->drv_priv; | |
368 | return *ptr; | |
369 | } | |
fbbcd146 | 370 | void ath_chanctx_init(struct ath_softc *sc); |
bff11766 FF |
371 | void ath_chanctx_set_channel(struct ath_softc *sc, struct ath_chanctx *ctx, |
372 | struct cfg80211_chan_def *chandef); | |
373 | void ath_chanctx_switch(struct ath_softc *sc, struct ath_chanctx *ctx, | |
374 | struct cfg80211_chan_def *chandef); | |
c083ce99 | 375 | void ath_chanctx_check_active(struct ath_softc *sc, struct ath_chanctx *ctx); |
78b21949 FF |
376 | void ath_offchannel_timer(unsigned long data); |
377 | void ath_offchannel_channel_change(struct ath_softc *sc); | |
378 | void ath_chanctx_offchan_switch(struct ath_softc *sc, | |
379 | struct ieee80211_channel *chan); | |
c4dc0d04 RM |
380 | struct ath_chanctx *ath_chanctx_get_oper_chan(struct ath_softc *sc, |
381 | bool active); | |
c083ce99 | 382 | |
fbbcd146 | 383 | int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan); |
394cf0a1 S |
384 | int ath_startrecv(struct ath_softc *sc); |
385 | bool ath_stoprecv(struct ath_softc *sc); | |
394cf0a1 S |
386 | u32 ath_calcrxfilter(struct ath_softc *sc); |
387 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
388 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 389 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 | 390 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
ef1b6cd9 SM |
391 | void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); |
392 | void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); | |
393 | void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); | |
394cf0a1 | 394 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); |
1381559b FF |
395 | bool ath_drain_all_txq(struct ath_softc *sc); |
396 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq); | |
394cf0a1 S |
397 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); |
398 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
399 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
0453531e | 400 | void ath_txq_schedule_all(struct ath_softc *sc); |
394cf0a1 | 401 | int ath_tx_init(struct ath_softc *sc, int nbufs); |
394cf0a1 S |
402 | int ath_txq_update(struct ath_softc *sc, int qnum, |
403 | struct ath9k_tx_queue_info *q); | |
aa5955c3 | 404 | void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); |
c52f33d0 | 405 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 | 406 | struct ath_tx_control *txctl); |
59505c02 FF |
407 | void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
408 | struct sk_buff *skb); | |
394cf0a1 | 409 | void ath_tx_tasklet(struct ath_softc *sc); |
e5003249 | 410 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
231c3a1f FF |
411 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
412 | u16 tid, u16 *ssn); | |
f83da965 | 413 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
394cf0a1 S |
414 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
415 | ||
5519541d | 416 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); |
042ec453 JB |
417 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
418 | struct ath_node *an); | |
86a22acf FF |
419 | void ath9k_release_buffered_frames(struct ieee80211_hw *hw, |
420 | struct ieee80211_sta *sta, | |
421 | u16 tids, int nframes, | |
422 | enum ieee80211_frame_release_type reason, | |
423 | bool more_data); | |
5519541d | 424 | |
394cf0a1 | 425 | /********/ |
17d7904d | 426 | /* VIFs */ |
394cf0a1 | 427 | /********/ |
f078f209 | 428 | |
17d7904d | 429 | struct ath_vif { |
fbbcd146 FF |
430 | struct list_head list; |
431 | ||
d463af4a | 432 | struct ieee80211_vif *vif; |
f89d1bc4 | 433 | struct ath_node mcast_node; |
394cf0a1 | 434 | int av_bslot; |
aa45fe96 | 435 | bool primary_sta_vif; |
4ed96f04 | 436 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 | 437 | struct ath_buf *av_bcbuf; |
fbbcd146 | 438 | struct ath_chanctx *chanctx; |
d463af4a FF |
439 | |
440 | /* P2P Client */ | |
441 | struct ieee80211_noa_data noa; | |
f078f209 LR |
442 | }; |
443 | ||
7b6ef998 SM |
444 | struct ath9k_vif_iter_data { |
445 | u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */ | |
446 | u8 mask[ETH_ALEN]; /* bssid mask */ | |
447 | bool has_hw_macaddr; | |
448 | ||
449 | int naps; /* number of AP vifs */ | |
450 | int nmeshes; /* number of mesh vifs */ | |
451 | int nstations; /* number of station vifs */ | |
452 | int nwds; /* number of WDS vifs */ | |
453 | int nadhocs; /* number of adhoc vifs */ | |
454 | }; | |
455 | ||
456 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
457 | struct ieee80211_vif *vif, | |
458 | struct ath9k_vif_iter_data *iter_data); | |
459 | ||
394cf0a1 S |
460 | /*******************/ |
461 | /* Beacon Handling */ | |
462 | /*******************/ | |
f078f209 | 463 | |
394cf0a1 S |
464 | /* |
465 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
466 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
467 | * number of beacon intervals, the game's up. | |
468 | */ | |
c944daf4 | 469 | #define BSTUCK_THRESH 9 |
689e756f | 470 | #define ATH_BCBUF 8 |
394cf0a1 S |
471 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
472 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
394cf0a1 | 473 | |
7b6ef998 SM |
474 | #define TSF_TO_TU(_h,_l) \ |
475 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
476 | ||
394cf0a1 S |
477 | struct ath_beacon { |
478 | enum { | |
479 | OK, /* no change needed */ | |
480 | UPDATE, /* update pending */ | |
481 | COMMIT /* beacon sent, commit change */ | |
482 | } updateslot; /* slot time update fsm */ | |
483 | ||
484 | u32 beaconq; | |
485 | u32 bmisscnt; | |
2c3db3d5 | 486 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
394cf0a1 S |
487 | int slottime; |
488 | int slotupdate; | |
394cf0a1 S |
489 | struct ath_descdma bdma; |
490 | struct ath_txq *cabq; | |
491 | struct list_head bbuf; | |
ba4903f9 FF |
492 | |
493 | bool tx_processed; | |
494 | bool tx_last; | |
394cf0a1 S |
495 | }; |
496 | ||
fb6e252f | 497 | void ath9k_beacon_tasklet(unsigned long data); |
ef4ad633 SM |
498 | void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, |
499 | u32 changed); | |
130ef6e9 SM |
500 | void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); |
501 | void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); | |
ef4ad633 | 502 | void ath9k_set_beacon(struct ath_softc *sc); |
4effc6fd MK |
503 | bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif); |
504 | void ath9k_csa_update(struct ath_softc *sc); | |
394cf0a1 | 505 | |
ef1b6cd9 SM |
506 | /*******************/ |
507 | /* Link Monitoring */ | |
508 | /*******************/ | |
f078f209 | 509 | |
20977d3e S |
510 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
511 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
512 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
513 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
6044474e | 514 | #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ |
20977d3e S |
515 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
516 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
7b6ef998 SM |
517 | #define ATH_ANI_MAX_SKIP_COUNT 10 |
518 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ | |
519 | #define ATH_PLL_WORK_INTERVAL 100 | |
ca369eb4 | 520 | |
bff11766 | 521 | void ath_chanctx_work(struct work_struct *work); |
ef1b6cd9 | 522 | void ath_tx_complete_poll_work(struct work_struct *work); |
236de514 | 523 | void ath_reset_work(struct work_struct *work); |
415ec61b | 524 | bool ath_hw_check(struct ath_softc *sc); |
9eab61c2 | 525 | void ath_hw_pll_work(struct work_struct *work); |
9f42c2b6 | 526 | void ath_paprd_calibrate(struct work_struct *work); |
55624204 | 527 | void ath_ani_calibrate(unsigned long data); |
da0d45f7 SM |
528 | void ath_start_ani(struct ath_softc *sc); |
529 | void ath_stop_ani(struct ath_softc *sc); | |
530 | void ath_check_ani(struct ath_softc *sc); | |
ef1b6cd9 SM |
531 | int ath_update_survey_stats(struct ath_softc *sc); |
532 | void ath_update_survey_nf(struct ath_softc *sc, int channel); | |
124b979b | 533 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); |
bf3dac5a | 534 | void ath_ps_full_sleep(unsigned long data); |
d463af4a FF |
535 | void ath9k_p2p_ps_timer(void *priv); |
536 | void ath9k_update_p2p_ps(struct ath_softc *sc, struct ieee80211_vif *vif); | |
bff11766 | 537 | void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop); |
55624204 | 538 | |
0fca65c1 S |
539 | /**********/ |
540 | /* BTCOEX */ | |
541 | /**********/ | |
542 | ||
ac46ba43 SM |
543 | #define ATH_DUMP_BTCOEX(_s, _val) \ |
544 | do { \ | |
5e88ba62 ZK |
545 | len += scnprintf(buf + len, size - len, \ |
546 | "%20s : %10d\n", _s, (_val)); \ | |
ac46ba43 SM |
547 | } while (0) |
548 | ||
e6930c4b SM |
549 | enum bt_op_flags { |
550 | BT_OP_PRIORITY_DETECTED, | |
551 | BT_OP_SCAN, | |
552 | }; | |
553 | ||
2e20250a | 554 | struct ath_btcoex { |
2e20250a LR |
555 | spinlock_t btcoex_lock; |
556 | struct timer_list period_timer; /* Timer for BT period */ | |
168c6f89 | 557 | struct timer_list no_stomp_timer; |
2e20250a LR |
558 | u32 bt_priority_cnt; |
559 | unsigned long bt_priority_time; | |
e6930c4b | 560 | unsigned long op_flags; |
e08a6ace | 561 | int bt_stomp_type; /* Types of BT stomping */ |
168c6f89 | 562 | u32 btcoex_no_stomp; /* in msec */ |
94ae77ea | 563 | u32 btcoex_period; /* in msec */ |
168c6f89 | 564 | u32 btscan_no_stomp; /* in msec */ |
7dc181c2 | 565 | u32 duty_cycle; |
6995fb80 | 566 | u32 bt_wait_time; |
e82cb03f | 567 | int rssi_count; |
7dc181c2 | 568 | struct ath_mci_profile mci; |
2884561a | 569 | u8 stomp_audio; |
2e20250a LR |
570 | }; |
571 | ||
4daa7760 | 572 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
5908120f SM |
573 | int ath9k_init_btcoex(struct ath_softc *sc); |
574 | void ath9k_deinit_btcoex(struct ath_softc *sc); | |
df198b17 SM |
575 | void ath9k_start_btcoex(struct ath_softc *sc); |
576 | void ath9k_stop_btcoex(struct ath_softc *sc); | |
0fca65c1 S |
577 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); |
578 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
56ca0dba | 579 | void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); |
c0ac53fa | 580 | u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); |
08d4df41 | 581 | void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); |
ac46ba43 | 582 | int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); |
4daa7760 SM |
583 | #else |
584 | static inline int ath9k_init_btcoex(struct ath_softc *sc) | |
585 | { | |
586 | return 0; | |
587 | } | |
588 | static inline void ath9k_deinit_btcoex(struct ath_softc *sc) | |
589 | { | |
590 | } | |
591 | static inline void ath9k_start_btcoex(struct ath_softc *sc) | |
592 | { | |
593 | } | |
594 | static inline void ath9k_stop_btcoex(struct ath_softc *sc) | |
595 | { | |
596 | } | |
597 | static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, | |
598 | u32 status) | |
599 | { | |
600 | } | |
601 | static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, | |
602 | u32 max_4ms_framelen) | |
603 | { | |
604 | return 0; | |
605 | } | |
08d4df41 RM |
606 | static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) |
607 | { | |
608 | } | |
ac46ba43 | 609 | static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) |
4df50ca8 RM |
610 | { |
611 | return 0; | |
612 | } | |
4daa7760 | 613 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |
0fca65c1 | 614 | |
394cf0a1 S |
615 | /********************/ |
616 | /* LED Control */ | |
617 | /********************/ | |
f078f209 | 618 | |
08fc5c1b VN |
619 | #define ATH_LED_PIN_DEF 1 |
620 | #define ATH_LED_PIN_9287 8 | |
353e5019 | 621 | #define ATH_LED_PIN_9300 10 |
15178535 | 622 | #define ATH_LED_PIN_9485 6 |
1a68abb0 | 623 | #define ATH_LED_PIN_9462 4 |
f078f209 | 624 | |
0cf55c21 | 625 | #ifdef CONFIG_MAC80211_LEDS |
0fca65c1 S |
626 | void ath_init_leds(struct ath_softc *sc); |
627 | void ath_deinit_leds(struct ath_softc *sc); | |
8f176a3a | 628 | void ath_fill_led_pin(struct ath_softc *sc); |
0cf55c21 FF |
629 | #else |
630 | static inline void ath_init_leds(struct ath_softc *sc) | |
631 | { | |
632 | } | |
633 | ||
634 | static inline void ath_deinit_leds(struct ath_softc *sc) | |
8f176a3a RM |
635 | { |
636 | } | |
637 | static inline void ath_fill_led_pin(struct ath_softc *sc) | |
0cf55c21 FF |
638 | { |
639 | } | |
640 | #endif | |
641 | ||
e60001e7 SM |
642 | /************************/ |
643 | /* Wake on Wireless LAN */ | |
644 | /************************/ | |
645 | ||
7b6ef998 SM |
646 | struct ath9k_wow_pattern { |
647 | u8 pattern_bytes[MAX_PATTERN_SIZE]; | |
648 | u8 mask_bytes[MAX_PATTERN_SIZE]; | |
649 | u32 pattern_len; | |
650 | }; | |
651 | ||
e60001e7 | 652 | #ifdef CONFIG_ATH9K_WOW |
babaa80a | 653 | void ath9k_init_wow(struct ieee80211_hw *hw); |
e60001e7 SM |
654 | int ath9k_suspend(struct ieee80211_hw *hw, |
655 | struct cfg80211_wowlan *wowlan); | |
656 | int ath9k_resume(struct ieee80211_hw *hw); | |
657 | void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled); | |
658 | #else | |
babaa80a SM |
659 | static inline void ath9k_init_wow(struct ieee80211_hw *hw) |
660 | { | |
661 | } | |
e60001e7 SM |
662 | static inline int ath9k_suspend(struct ieee80211_hw *hw, |
663 | struct cfg80211_wowlan *wowlan) | |
664 | { | |
665 | return 0; | |
666 | } | |
667 | static inline int ath9k_resume(struct ieee80211_hw *hw) | |
668 | { | |
669 | return 0; | |
670 | } | |
671 | static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) | |
672 | { | |
673 | } | |
674 | #endif /* CONFIG_ATH9K_WOW */ | |
675 | ||
8da07830 | 676 | /*******************************/ |
102885a5 | 677 | /* Antenna diversity/combining */ |
8da07830 SM |
678 | /*******************************/ |
679 | ||
102885a5 VT |
680 | #define ATH_ANT_RX_CURRENT_SHIFT 4 |
681 | #define ATH_ANT_RX_MAIN_SHIFT 2 | |
682 | #define ATH_ANT_RX_MASK 0x3 | |
683 | ||
684 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 | |
685 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 | |
686 | #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 | |
687 | #define ATH_ANT_DIV_COMB_INIT_COUNT 95 | |
688 | #define ATH_ANT_DIV_COMB_MAX_COUNT 100 | |
689 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 | |
690 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 | |
3afa6b4f SM |
691 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50 |
692 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50 | |
102885a5 | 693 | |
102885a5 VT |
694 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 |
695 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 | |
696 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 | |
697 | ||
102885a5 VT |
698 | struct ath_ant_comb { |
699 | u16 count; | |
700 | u16 total_pkt_count; | |
701 | bool scan; | |
702 | bool scan_not_start; | |
703 | int main_total_rssi; | |
704 | int alt_total_rssi; | |
705 | int alt_recv_cnt; | |
706 | int main_recv_cnt; | |
707 | int rssi_lna1; | |
708 | int rssi_lna2; | |
709 | int rssi_add; | |
710 | int rssi_sub; | |
711 | int rssi_first; | |
712 | int rssi_second; | |
713 | int rssi_third; | |
3afa6b4f SM |
714 | int ant_ratio; |
715 | int ant_ratio2; | |
102885a5 VT |
716 | bool alt_good; |
717 | int quick_scan_cnt; | |
3fbaf4c5 | 718 | enum ath9k_ant_div_comb_lna_conf main_conf; |
102885a5 VT |
719 | enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; |
720 | enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; | |
102885a5 VT |
721 | bool first_ratio; |
722 | bool second_ratio; | |
723 | unsigned long scan_start_time; | |
3afa6b4f SM |
724 | |
725 | /* | |
726 | * Card-specific config values. | |
727 | */ | |
728 | int low_rssi_thresh; | |
729 | int fast_div_bias; | |
102885a5 VT |
730 | }; |
731 | ||
8da07830 | 732 | void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); |
8da07830 | 733 | |
394cf0a1 S |
734 | /********************/ |
735 | /* Main driver core */ | |
736 | /********************/ | |
f078f209 | 737 | |
2d22c7dd SM |
738 | #define ATH9K_PCI_CUS198 0x0001 |
739 | #define ATH9K_PCI_CUS230 0x0002 | |
740 | #define ATH9K_PCI_CUS217 0x0004 | |
741 | #define ATH9K_PCI_CUS252 0x0008 | |
742 | #define ATH9K_PCI_WOW 0x0010 | |
743 | #define ATH9K_PCI_BT_ANT_DIV 0x0020 | |
744 | #define ATH9K_PCI_D3_L1_WAR 0x0040 | |
745 | #define ATH9K_PCI_AR9565_1ANT 0x0080 | |
746 | #define ATH9K_PCI_AR9565_2ANT 0x0100 | |
747 | #define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200 | |
4dd35640 | 748 | #define ATH9K_PCI_KILLER 0x0400 |
9b60b64b | 749 | |
394cf0a1 S |
750 | /* |
751 | * Default cache line size, in bytes. | |
752 | * Used when PCI device not fully initialized by bootrom/BIOS | |
753 | */ | |
754 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 | 755 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ |
394cf0a1 | 756 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
071aa9a8 | 757 | #define MAX_GTT_CNT 5 |
394cf0a1 | 758 | |
1b04b930 S |
759 | /* Powersave flags */ |
760 | #define PS_WAIT_FOR_BEACON BIT(0) | |
761 | #define PS_WAIT_FOR_CAB BIT(1) | |
762 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
763 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
764 | #define PS_BEACON_SYNC BIT(4) | |
424749c7 | 765 | #define PS_WAIT_FOR_ANI BIT(5) |
394cf0a1 | 766 | |
fbbcd146 FF |
767 | #define ATH9K_NUM_CHANCTX 2 /* supports 2 operating channels */ |
768 | ||
394cf0a1 S |
769 | struct ath_softc { |
770 | struct ieee80211_hw *hw; | |
771 | struct device *dev; | |
c52f33d0 | 772 | |
3430098a FF |
773 | struct survey_info *cur_survey; |
774 | struct survey_info survey[ATH9K_NUM_CHANNELS]; | |
0e2dedf9 | 775 | |
394cf0a1 S |
776 | struct tasklet_struct intr_tq; |
777 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 778 | struct ath_hw *sc_ah; |
394cf0a1 S |
779 | void __iomem *mem; |
780 | int irq; | |
2d6a5e95 | 781 | spinlock_t sc_serial_rw; |
04717ccd | 782 | spinlock_t sc_pm_lock; |
4bdd1e97 | 783 | spinlock_t sc_pcu_lock; |
394cf0a1 | 784 | struct mutex mutex; |
9f42c2b6 | 785 | struct work_struct paprd_work; |
236de514 | 786 | struct work_struct hw_reset_work; |
bff11766 | 787 | struct work_struct chanctx_work; |
9f42c2b6 | 788 | struct completion paprd_complete; |
10e23181 | 789 | wait_queue_head_t tx_wait; |
394cf0a1 | 790 | |
d463af4a FF |
791 | struct ath_gen_timer *p2p_ps_timer; |
792 | struct ath_vif *p2p_ps_vif; | |
793 | ||
9b60b64b | 794 | unsigned long driver_data; |
cb8d61de | 795 | |
071aa9a8 | 796 | u8 gtt_cnt; |
17d7904d | 797 | u32 intrstatus; |
1b04b930 | 798 | u16 ps_flags; /* PS_* */ |
17d7904d | 799 | u16 curtxpow; |
96148326 | 800 | bool ps_enabled; |
1dbfd9d4 | 801 | bool ps_idle; |
4801416c BG |
802 | short nbcnvifs; |
803 | short nvifs; | |
709ade9e | 804 | unsigned long ps_usecount; |
394cf0a1 | 805 | |
394cf0a1 S |
806 | struct ath_rx rx; |
807 | struct ath_tx tx; | |
808 | struct ath_beacon beacon; | |
394cf0a1 | 809 | |
bff11766 | 810 | struct cfg80211_chan_def cur_chandef; |
fbbcd146 FF |
811 | struct ath_chanctx chanctx[ATH9K_NUM_CHANCTX]; |
812 | struct ath_chanctx *cur_chan; | |
bff11766 FF |
813 | struct ath_chanctx *next_chan; |
814 | spinlock_t chan_lock; | |
78b21949 | 815 | struct ath_offchannel offchannel; |
fbbcd146 | 816 | |
0cf55c21 FF |
817 | #ifdef CONFIG_MAC80211_LEDS |
818 | bool led_registered; | |
819 | char led_name[32]; | |
820 | struct led_classdev led_cdev; | |
821 | #endif | |
394cf0a1 | 822 | |
9ac58615 | 823 | struct ath9k_hw_cal_data caldata; |
9ac58615 | 824 | |
a830df07 | 825 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 826 | struct ath9k_debug debug; |
394cf0a1 | 827 | #endif |
6b96f93e | 828 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 829 | struct delayed_work tx_complete_work; |
181fb18d | 830 | struct delayed_work hw_pll_work; |
bf3dac5a | 831 | struct timer_list sleep_timer; |
4daa7760 SM |
832 | |
833 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT | |
2e20250a | 834 | struct ath_btcoex btcoex; |
9e25365f | 835 | struct ath_mci_coex mci_coex; |
3c7992e3 | 836 | struct work_struct mci_work; |
4daa7760 | 837 | #endif |
5088c2f1 VT |
838 | |
839 | struct ath_descdma txsdma; | |
102885a5 VT |
840 | |
841 | struct ath_ant_comb ant_comb; | |
43c35284 | 842 | u8 ant_tx, ant_rx; |
8e92d3f2 | 843 | struct dfs_pattern_detector *dfs_detector; |
3f3c09f3 | 844 | u64 dfs_prev_pulse_ts; |
b11e640a | 845 | u32 wow_enabled; |
e93d083f SW |
846 | /* relay(fs) channel for spectral scan */ |
847 | struct rchan *rfs_chan_spec_scan; | |
848 | enum spectral_mode spectral_mode; | |
04ccd4a1 | 849 | struct ath_spec_scan spec_config; |
01c78533 | 850 | |
89f927af LR |
851 | struct ieee80211_vif *tx99_vif; |
852 | struct sk_buff *tx99_skb; | |
853 | bool tx99_state; | |
854 | s16 tx99_power; | |
855 | ||
e60001e7 | 856 | #ifdef CONFIG_ATH9K_WOW |
01c78533 MSS |
857 | atomic_t wow_got_bmiss_intr; |
858 | atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ | |
859 | u32 wow_intr_before_sleep; | |
860 | #endif | |
394cf0a1 S |
861 | }; |
862 | ||
ef6b19e4 SM |
863 | /********/ |
864 | /* TX99 */ | |
865 | /********/ | |
866 | ||
867 | #ifdef CONFIG_ATH9K_TX99 | |
868 | void ath9k_tx99_init_debug(struct ath_softc *sc); | |
89f927af LR |
869 | int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, |
870 | struct ath_tx_control *txctl); | |
ef6b19e4 SM |
871 | #else |
872 | static inline void ath9k_tx99_init_debug(struct ath_softc *sc) | |
873 | { | |
874 | } | |
875 | static inline int ath9k_tx99_send(struct ath_softc *sc, | |
876 | struct sk_buff *skb, | |
877 | struct ath_tx_control *txctl) | |
878 | { | |
879 | return 0; | |
880 | } | |
881 | #endif /* CONFIG_ATH9K_TX99 */ | |
89f927af | 882 | |
5bb12791 | 883 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 884 | { |
5bb12791 | 885 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
886 | } |
887 | ||
7b6ef998 SM |
888 | void ath9k_tasklet(unsigned long data); |
889 | int ath_cabq_update(struct ath_softc *); | |
313eb87f | 890 | u8 ath9k_parse_mpdudensity(u8 mpdudensity); |
394cf0a1 | 891 | irqreturn_t ath_isr(int irq, void *dev); |
ef6b19e4 | 892 | int ath_reset(struct ath_softc *sc); |
e60001e7 SM |
893 | void ath_cancel_work(struct ath_softc *sc); |
894 | void ath_restart_work(struct ath_softc *sc); | |
eb93e891 | 895 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
5bb12791 | 896 | const struct ath_bus_ops *bus_ops); |
285f2dda | 897 | void ath9k_deinit_device(struct ath_softc *sc); |
43c35284 | 898 | void ath9k_reload_chainmask_settings(struct ath_softc *sc); |
7b6ef998 SM |
899 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); |
900 | void ath_start_rfkill_poll(struct ath_softc *sc); | |
901 | void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
902 | void ath9k_ps_wakeup(struct ath_softc *sc); | |
903 | void ath9k_ps_restore(struct ath_softc *sc); | |
68a89116 | 904 | |
8e26a030 | 905 | #ifdef CONFIG_ATH9K_PCI |
394cf0a1 S |
906 | int ath_pci_init(void); |
907 | void ath_pci_exit(void); | |
908 | #else | |
909 | static inline int ath_pci_init(void) { return 0; }; | |
910 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 911 | #endif |
f1dc5600 | 912 | |
8e26a030 | 913 | #ifdef CONFIG_ATH9K_AHB |
394cf0a1 S |
914 | int ath_ahb_init(void); |
915 | void ath_ahb_exit(void); | |
916 | #else | |
917 | static inline int ath_ahb_init(void) { return 0; }; | |
918 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 919 | #endif |
394cf0a1 | 920 | |
394cf0a1 | 921 | #endif /* ATH9K_H */ |