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ath9k: Remove MAC_DEBUG
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ath9k.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
394cf0a1
S		 20#include <linux/etherdevice.h>
21#include <linux/device.h>
a6b7a407 22#include <linux/interrupt.h>
394cf0a1 23#include <linux/leds.h>
9f42c2b6 24#include <linux/completion.h>
394cf0a1 25
394cf0a1 26#include "debug.h"
db86f07e 27#include "common.h"
7dc181c2 28#include "mci.h"
8e92d3f2 29#include "dfs.h"
db86f07e
LR		 30
31/*
32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
33 * should rely on this file or its contents.
34 */
394cf0a1
S		 35
36struct ath_node;
37
38/* Macro to expand scalars to 64-bit objects */
39
13bda122 40#define ito64(x) (sizeof(x) == 1) ? \
394cf0a1 41 (((unsigned long long int)(x)) & (0xff)) : \
13bda122 42 (sizeof(x) == 2) ? \
394cf0a1 43 (((unsigned long long int)(x)) & 0xffff) : \
13bda122 44 ((sizeof(x) == 4) ? \
394cf0a1
S		 45 (((unsigned long long int)(x)) & 0xffffffff) : \
46 (unsigned long long int)(x))
47
48/* increment with wrap-around */
49#define INCR(_l, _sz) do { \
50 (_l)++; \
51 (_l) &= ((_sz) - 1); \
52 } while (0)
53
54/* decrement with wrap-around */
55#define DECR(_l, _sz) do { \
56 (_l)--; \
57 (_l) &= ((_sz) - 1); \
58 } while (0)
59
394cf0a1
S		 60#define TSF_TO_TU(_h,_l) \
61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
62
63#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
64
394cf0a1 65struct ath_config {
394cf0a1
S		 66 u16 txpowlimit;
67 u8 cabqReadytime;
394cf0a1
S		 68};
69
70/*************************/
71/* Descriptor Management */
72/*************************/
73
74#define ATH_TXBUF_RESET(_bf) do { \
a119cc49 75 (_bf)->bf_stale = false; \
394cf0a1
S		 76 (_bf)->bf_lastbf = NULL; \
77 (_bf)->bf_next = NULL; \
78 memset(&((_bf)->bf_state), 0, \
79 sizeof(struct ath_buf_state)); \
80 } while (0)
81
a119cc49
S		 82#define ATH_RXBUF_RESET(_bf) do { \
83 (_bf)->bf_stale = false; \
84 } while (0)
85
394cf0a1
S		 86/**
87 * enum buffer_type - Buffer type flags
88 *
394cf0a1
S		 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
90 * @BUF_AGGR: Indicates whether the buffer can be aggregated
91 * (used in aggregation scheduling)
394cf0a1
S		 92 */
93enum buffer_type {
436d0d98
MSS		 94 BUF_AMPDU = BIT(0),
95 BUF_AGGR = BIT(1),
394cf0a1
S		 96};
97
394cf0a1
S		 98#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
99#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
f078f209 100
016c2177 101#define ATH_TXSTATUS_RING_SIZE 512
5088c2f1 102
c3d77696
MSS		 103#define DS2PHYS(_dd, _ds) \
104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
105#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
106#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
107
394cf0a1 108struct ath_descdma {
5088c2f1 109 void *dd_desc;
17d7904d
S		 110 dma_addr_t dd_desc_paddr;
111 u32 dd_desc_len;
394cf0a1
S		 112};
113
114int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
115 struct list_head *head, const char *name,
4adfcded 116 int nbuf, int ndesc, bool is_tx);
394cf0a1
S		 117
118/***********/
119/* RX / TX */
120/***********/
121
394cf0a1 122#define ATH_RXBUF 512
394cf0a1 123#define ATH_TXBUF 512
84642d6b
FF		 124#define ATH_TXBUF_RESERVE 5
125#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
394cf0a1 126#define ATH_TXMAXTRY 13
394cf0a1
S		 127
128#define TID_TO_WME_AC(_tid) \
bea843c7
SM		 129 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
130 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \
131 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \
132 IEEE80211_AC_VO)
394cf0a1 133
394cf0a1
S		 134#define ATH_AGGR_DELIM_SZ 4
135#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
136/* number of delimiters for encryption padding */
137#define ATH_AGGR_ENCRYPTDELIM 10
138/* minimum h/w qdepth to be sustained to maximize aggregation */
139#define ATH_AGGR_MIN_QDEPTH 2
140#define ATH_AMPDU_SUBFRAME_DEFAULT 32
394cf0a1
S		 141
142#define IEEE80211_SEQ_SEQ_SHIFT 4
143#define IEEE80211_SEQ_MAX 4096
394cf0a1
S		 144#define IEEE80211_WEP_IVLEN 3
145#define IEEE80211_WEP_KIDLEN 1
146#define IEEE80211_WEP_CRCLEN 4
147#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
148 (IEEE80211_WEP_IVLEN + \
149 IEEE80211_WEP_KIDLEN + \
150 IEEE80211_WEP_CRCLEN))
151
152/* return whether a bit at index _n in bitmap _bm is set
153 * _sz is the size of the bitmap */
154#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
155 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
156
157/* return block-ack bitmap index given sequence and starting sequence */
158#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
159
156369fa
FF		 160/* return the seqno for _start + _offset */
161#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
162
394cf0a1
S		 163/* returns delimiter padding required given the packet length */
164#define ATH_AGGR_GET_NDELIM(_len) \
39ec2997
VT		 165 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
166 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
394cf0a1
S		 167
168#define BAW_WITHIN(_start, _bawsz, _seqno) \
169 ((((_seqno) - (_start)) & 4095) < (_bawsz))
170
394cf0a1
S		 171#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
172
365d2ebc
SM		 173#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
174
164ace38
SB		 175#define ATH_TX_COMPLETE_POLL_INT 1000
176
394cf0a1
S		 177enum ATH_AGGR_STATUS {
178 ATH_AGGR_DONE,
179 ATH_AGGR_BAW_CLOSED,
180 ATH_AGGR_LIMITED,
181};
182
e5003249 183#define ATH_TXFIFO_DEPTH 8
394cf0a1 184struct ath_txq {
60f2d1d5
BG		 185 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
186 u32 axq_qnum; /* ath9k hardware queue number */
fce041be 187 void *axq_link;
17d7904d 188 struct list_head axq_q;
394cf0a1 189 spinlock_t axq_lock;
17d7904d 190 u32 axq_depth;
4b3ba66a 191 u32 axq_ampdu_depth;
17d7904d 192 bool stopped;
164ace38 193 bool axq_tx_inprogress;
394cf0a1 194 struct list_head axq_acq;
e5003249 195 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
e5003249
VT		 196 u8 txq_headidx;
197 u8 txq_tailidx;
066dae93 198 int pending_frames;
23de5dc9 199 struct sk_buff_head complete_q;
394cf0a1
S		 200};
201
93ef24b2 202struct ath_atx_ac {
066dae93 203 struct ath_txq *txq;
93ef24b2 204 int sched;
93ef24b2
S		 205 struct list_head list;
206 struct list_head tid_q;
5519541d 207 bool clear_ps_filter;
93ef24b2
S		 208};
209
2d42efc4 210struct ath_frame_info {
56dc6336 211 struct ath_buf *bf;
2d42efc4 212 int framelen;
2d42efc4 213 enum ath9k_key_type keytype;
a75c0629 214 u8 keyix;
2d42efc4 215 u8 retries;
80b08a8d 216 u8 rtscts_rate;
2d42efc4
FF		 217};
218
93ef24b2 219struct ath_buf_state {
93ef24b2 220 u8 bf_type;
9f42c2b6 221 u8 bfs_paprd;
399c6489 222 u8 ndelim;
6a0ddaef 223 u16 seqno;
9cf04dcc 224 unsigned long bfs_paprd_timestamp;
93ef24b2
S		 225};
226
227struct ath_buf {
228 struct list_head list;
229 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
230 an aggregate) */
231 struct ath_buf *bf_next; /* next subframe in the aggregate */
232 struct sk_buff *bf_mpdu; /* enclosing frame structure */
233 void *bf_desc; /* virtual addr of desc */
234 dma_addr_t bf_daddr; /* physical addr of desc */
c1739eb3 235 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
93ef24b2 236 bool bf_stale;
79acac07 237 struct ieee80211_tx_rate rates[4];
93ef24b2 238 struct ath_buf_state bf_state;
93ef24b2
S		 239};
240
241struct ath_atx_tid {
242 struct list_head list;
56dc6336 243 struct sk_buff_head buf_q;
93ef24b2
S		 244 struct ath_node *an;
245 struct ath_atx_ac *ac;
81ee13ba 246 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
f9437543 247 int bar_index;
93ef24b2
S		 248 u16 seq_start;
249 u16 seq_next;
250 u16 baw_size;
251 int tidno;
252 int baw_head; /* first un-acked tx buffer */
253 int baw_tail; /* next unused tx buffer slot */
254 int sched;
255 int paused;
256 u8 state;
257};
258
259struct ath_node {
a145daf7 260 struct ath_softc *sc;
7f010c93 261 struct ieee80211_sta *sta; /* station struct we're part of */
7e1e3864 262 struct ieee80211_vif *vif; /* interface with which we're associated */
de7b7604 263 struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
bea843c7 264 struct ath_atx_ac ac[IEEE80211_NUM_ACS];
93ae2dd2
FF		 265 int ps_key;
266
93ef24b2
S		 267 u16 maxampdu;
268 u8 mpdudensity;
5519541d
FF		 269
270 bool sleeping;
a145daf7
SM		 271
272#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
273 struct dentry *node_stat;
274#endif
93ef24b2
S		 275};
276
394cf0a1
S		 277#define AGGR_CLEANUP BIT(1)
278#define AGGR_ADDBA_COMPLETE BIT(2)
279#define AGGR_ADDBA_PROGRESS BIT(3)
280
394cf0a1
S		 281struct ath_tx_control {
282 struct ath_txq *txq;
2d42efc4 283 struct ath_node *an;
9f42c2b6 284 u8 paprd;
36323f81 285 struct ieee80211_sta *sta;
394cf0a1
S		 286};
287
394cf0a1 288#define ATH_TX_ERROR 0x01
394cf0a1 289
60f2d1d5
BG		 290/**
291 * @txq_map: Index is mac80211 queue number. This is
292 * not necessarily the same as the hardware queue number
293 * (axq_qnum).
294 */
394cf0a1
S		 295struct ath_tx {
296 u16 seq_no;
297 u32 txqsetup;
394cf0a1
S		 298 spinlock_t txbuflock;
299 struct list_head txbuf;
300 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
301 struct ath_descdma txdma;
bea843c7
SM		 302 struct ath_txq *txq_map[IEEE80211_NUM_ACS];
303 u32 txq_max_pending[IEEE80211_NUM_ACS];
304 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
394cf0a1
S		 305};
306
b5c80475
FF		 307struct ath_rx_edma {
308 struct sk_buff_head rx_fifo;
b5c80475
FF		 309 u32 rx_fifo_hwsize;
310};
311
394cf0a1
S		 312struct ath_rx {
313 u8 defant;
314 u8 rxotherant;
723e7113 315 bool discard_next;
394cf0a1 316 u32 *rxlink;
6995fb80 317 u32 num_pkts;
394cf0a1 318 unsigned int rxfilter;
394cf0a1
S		 319 struct list_head rxbuf;
320 struct ath_descdma rxdma;
b5c80475 321 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
0d95521e
FF		 322
323 struct sk_buff *frag;
21fbbca3
CL		 324
325 u32 ampdu_ref;
394cf0a1
S		 326};
327
328int ath_startrecv(struct ath_softc *sc);
329bool ath_stoprecv(struct ath_softc *sc);
394cf0a1
S		 330u32 ath_calcrxfilter(struct ath_softc *sc);
331int ath_rx_init(struct ath_softc *sc, int nbufs);
332void ath_rx_cleanup(struct ath_softc *sc);
b5c80475 333int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
394cf0a1 334struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
ef1b6cd9
SM		 335void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
336void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
337void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1 338void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
1381559b
FF		 339bool ath_drain_all_txq(struct ath_softc *sc);
340void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1
S		 341void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
342void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
343void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
344int ath_tx_init(struct ath_softc *sc, int nbufs);
394cf0a1
S		 345int ath_txq_update(struct ath_softc *sc, int qnum,
346 struct ath9k_tx_queue_info *q);
aa5955c3 347void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
c52f33d0 348int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
394cf0a1
S		 349 struct ath_tx_control *txctl);
350void ath_tx_tasklet(struct ath_softc *sc);
e5003249 351void ath_tx_edma_tasklet(struct ath_softc *sc);
231c3a1f
FF		 352int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
353 u16 tid, u16 *ssn);
f83da965 354void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
394cf0a1
S		 355void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
356
5519541d 357void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
042ec453
JB		 358void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
359 struct ath_node *an);
5519541d 360
394cf0a1 361/********/
17d7904d 362/* VIFs */
394cf0a1 363/********/
f078f209 364
17d7904d 365struct ath_vif {
394cf0a1 366 int av_bslot;
aa45fe96 367 bool primary_sta_vif;
4ed96f04 368 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
394cf0a1 369 struct ath_buf *av_bcbuf;
f078f209
LR		 370};
371
394cf0a1
S		 372/*******************/
373/* Beacon Handling */
374/*******************/
f078f209 375
394cf0a1
S		 376/*
377 * Regardless of the number of beacons we stagger, (i.e. regardless of the
378 * number of BSSIDs) if a given beacon does not go out even after waiting this
379 * number of beacon intervals, the game's up.
380 */
c944daf4 381#define BSTUCK_THRESH 9
689e756f 382#define ATH_BCBUF 8
394cf0a1
S		 383#define ATH_DEFAULT_BINTVAL 100 /* TU */
384#define ATH_DEFAULT_BMISS_LIMIT 10
385#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
386
387struct ath_beacon_config {
9814f6b3 388 int beacon_interval;
394cf0a1
S		 389 u16 listen_interval;
390 u16 dtim_period;
391 u16 bmiss_timeout;
392 u8 dtim_count;
ef4ad633 393 bool enable_beacon;
1a6404a1 394 bool ibss_creator;
394cf0a1
S		 395};
396
397struct ath_beacon {
398 enum {
399 OK, /* no change needed */
400 UPDATE, /* update pending */
401 COMMIT /* beacon sent, commit change */
402 } updateslot; /* slot time update fsm */
403
404 u32 beaconq;
405 u32 bmisscnt;
dd347f2f 406 u32 bc_tstamp;
2c3db3d5 407 struct ieee80211_vif *bslot[ATH_BCBUF];
394cf0a1
S		 408 int slottime;
409 int slotupdate;
410 struct ath9k_tx_queue_info beacon_qi;
411 struct ath_descdma bdma;
412 struct ath_txq *cabq;
413 struct list_head bbuf;
ba4903f9
FF		 414
415 bool tx_processed;
416 bool tx_last;
394cf0a1
S		 417};
418
fb6e252f 419void ath9k_beacon_tasklet(unsigned long data);
ef4ad633
SM		 420bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
421void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
422 u32 changed);
130ef6e9
SM		 423void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
424void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
2f8e82e8 425void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
ef4ad633 426void ath9k_set_beacon(struct ath_softc *sc);
394cf0a1 427
ef1b6cd9
SM		 428/*******************/
429/* Link Monitoring */
430/*******************/
f078f209 431
20977d3e
S		 432#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
433#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
e36b27af
LR		 434#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
435#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
6044474e 436#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
20977d3e
S		 437#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
438#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
424749c7 439#define ATH_ANI_MAX_SKIP_COUNT 10
f078f209 440
ca369eb4 441#define ATH_PAPRD_TIMEOUT 100 /* msecs */
af68abad 442#define ATH_PLL_WORK_INTERVAL 100
ca369eb4 443
ef1b6cd9 444void ath_tx_complete_poll_work(struct work_struct *work);
236de514 445void ath_reset_work(struct work_struct *work);
347809fc 446void ath_hw_check(struct work_struct *work);
9eab61c2 447void ath_hw_pll_work(struct work_struct *work);
01e18918
RM		 448void ath_rx_poll(unsigned long data);
449void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
9f42c2b6 450void ath_paprd_calibrate(struct work_struct *work);
55624204 451void ath_ani_calibrate(unsigned long data);
da0d45f7
SM		 452void ath_start_ani(struct ath_softc *sc);
453void ath_stop_ani(struct ath_softc *sc);
454void ath_check_ani(struct ath_softc *sc);
ef1b6cd9
SM		 455int ath_update_survey_stats(struct ath_softc *sc);
456void ath_update_survey_nf(struct ath_softc *sc, int channel);
124b979b 457void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
55624204 458
0fca65c1
S		 459/**********/
460/* BTCOEX */
461/**********/
462
ac46ba43
SM		 463#define ATH_DUMP_BTCOEX(_s, _val) \
464 do { \
465 len += snprintf(buf + len, size - len, \
466 "%20s : %10d\n", _s, (_val)); \
467 } while (0)
468
e6930c4b
SM		 469enum bt_op_flags {
470 BT_OP_PRIORITY_DETECTED,
471 BT_OP_SCAN,
472};
473
2e20250a
LR		 474struct ath_btcoex {
475 bool hw_timer_enabled;
476 spinlock_t btcoex_lock;
477 struct timer_list period_timer; /* Timer for BT period */
478 u32 bt_priority_cnt;
479 unsigned long bt_priority_time;
e6930c4b 480 unsigned long op_flags;
e08a6ace 481 int bt_stomp_type; /* Types of BT stomping */
2e20250a 482 u32 btcoex_no_stomp; /* in usec */
94ae77ea 483 u32 btcoex_period; /* in msec */
58da1318 484 u32 btscan_no_stomp; /* in usec */
7dc181c2 485 u32 duty_cycle;
6995fb80 486 u32 bt_wait_time;
e82cb03f 487 int rssi_count;
75d7839f 488 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
7dc181c2 489 struct ath_mci_profile mci;
2884561a 490 u8 stomp_audio;
2e20250a
LR		 491};
492
4daa7760 493#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
5908120f
SM		 494int ath9k_init_btcoex(struct ath_softc *sc);
495void ath9k_deinit_btcoex(struct ath_softc *sc);
df198b17
SM		 496void ath9k_start_btcoex(struct ath_softc *sc);
497void ath9k_stop_btcoex(struct ath_softc *sc);
0fca65c1
S		 498void ath9k_btcoex_timer_resume(struct ath_softc *sc);
499void ath9k_btcoex_timer_pause(struct ath_softc *sc);
56ca0dba 500void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
c0ac53fa 501u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
08d4df41 502void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
ac46ba43 503int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
4daa7760
SM		 504#else
505static inline int ath9k_init_btcoex(struct ath_softc *sc)
506{
507 return 0;
508}
509static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
510{
511}
512static inline void ath9k_start_btcoex(struct ath_softc *sc)
513{
514}
515static inline void ath9k_stop_btcoex(struct ath_softc *sc)
516{
517}
518static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
519 u32 status)
520{
521}
522static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
523 u32 max_4ms_framelen)
524{
525 return 0;
526}
08d4df41
RM		 527static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
528{
529}
ac46ba43 530static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
4df50ca8
RM		 531{
532 return 0;
533}
4daa7760 534#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0fca65c1 535
01c78533
MSS		 536struct ath9k_wow_pattern {
537 u8 pattern_bytes[MAX_PATTERN_SIZE];
538 u8 mask_bytes[MAX_PATTERN_SIZE];
539 u32 pattern_len;
540};
541
394cf0a1
S		 542/********************/
543/* LED Control */
544/********************/
f078f209 545
08fc5c1b
VN		 546#define ATH_LED_PIN_DEF 1
547#define ATH_LED_PIN_9287 8
353e5019 548#define ATH_LED_PIN_9300 10
15178535 549#define ATH_LED_PIN_9485 6
1a68abb0 550#define ATH_LED_PIN_9462 4
f078f209 551
0cf55c21 552#ifdef CONFIG_MAC80211_LEDS
0fca65c1
S		 553void ath_init_leds(struct ath_softc *sc);
554void ath_deinit_leds(struct ath_softc *sc);
8f176a3a 555void ath_fill_led_pin(struct ath_softc *sc);
0cf55c21
FF		 556#else
557static inline void ath_init_leds(struct ath_softc *sc)
558{
559}
560
561static inline void ath_deinit_leds(struct ath_softc *sc)
8f176a3a
RM		 562{
563}
564static inline void ath_fill_led_pin(struct ath_softc *sc)
0cf55c21
FF		 565{
566}
567#endif
568
8da07830 569/*******************************/
102885a5 570/* Antenna diversity/combining */
8da07830
SM		 571/*******************************/
572
102885a5
VT		 573#define ATH_ANT_RX_CURRENT_SHIFT 4
574#define ATH_ANT_RX_MAIN_SHIFT 2
575#define ATH_ANT_RX_MASK 0x3
576
577#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
578#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
579#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
580#define ATH_ANT_DIV_COMB_INIT_COUNT 95
581#define ATH_ANT_DIV_COMB_MAX_COUNT 100
582#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
583#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
584
102885a5
VT		 585#define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
586#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
587#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
588#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
589
590enum ath9k_ant_div_comb_lna_conf {
591 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
592 ATH_ANT_DIV_COMB_LNA2,
593 ATH_ANT_DIV_COMB_LNA1,
594 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
595};
596
597struct ath_ant_comb {
598 u16 count;
599 u16 total_pkt_count;
600 bool scan;
601 bool scan_not_start;
602 int main_total_rssi;
603 int alt_total_rssi;
604 int alt_recv_cnt;
605 int main_recv_cnt;
606 int rssi_lna1;
607 int rssi_lna2;
608 int rssi_add;
609 int rssi_sub;
610 int rssi_first;
611 int rssi_second;
612 int rssi_third;
613 bool alt_good;
614 int quick_scan_cnt;
615 int main_conf;
616 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
617 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
102885a5
VT		 618 bool first_ratio;
619 bool second_ratio;
620 unsigned long scan_start_time;
621};
622
8da07830
SM		 623void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
624void ath_ant_comb_update(struct ath_softc *sc);
625
394cf0a1
S		 626/********************/
627/* Main driver core */
628/********************/
f078f209 629
394cf0a1
S		 630/*
631 * Default cache line size, in bytes.
632 * Used when PCI device not fully initialized by bootrom/BIOS
633*/
634#define DEFAULT_CACHELINE 32
394cf0a1
S		 635#define ATH_REGCLASSIDS_MAX 10
636#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
da647626 637#define ATH_MAX_SW_RETRIES 30
394cf0a1 638#define ATH_CHAN_MAX 255
f1dc5600 639
394cf0a1 640#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
394cf0a1
S		 641#define ATH_RATE_DUMMY_MARKER 0
642
781b14a3
SM		 643enum sc_op_flags {
644 SC_OP_INVALID,
645 SC_OP_BEACONS,
781b14a3
SM		 646 SC_OP_ANI_RUN,
647 SC_OP_PRIM_STA_VIF,
b74713d0 648 SC_OP_HW_RESET,
781b14a3 649};
1b04b930
S		 650
651/* Powersave flags */
652#define PS_WAIT_FOR_BEACON BIT(0)
653#define PS_WAIT_FOR_CAB BIT(1)
654#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
655#define PS_WAIT_FOR_TX_ACK BIT(3)
656#define PS_BEACON_SYNC BIT(4)
424749c7 657#define PS_WAIT_FOR_ANI BIT(5)
394cf0a1 658
545750d3 659struct ath_rate_table;
bce048d7 660
4801416c 661struct ath9k_vif_iter_data {
ab11bb28 662 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
4801416c 663 u8 mask[ETH_ALEN]; /* bssid mask */
ab11bb28
FF		 664 bool has_hw_macaddr;
665
4801416c
BG		 666 int naps; /* number of AP vifs */
667 int nmeshes; /* number of mesh vifs */
668 int nstations; /* number of station vifs */
e707549a 669 int nwds; /* number of WDS vifs */
4801416c 670 int nadhocs; /* number of adhoc vifs */
4801416c
BG		 671};
672
e93d083f
SW		 673/* enum spectral_mode:
674 *
675 * @SPECTRAL_DISABLED: spectral mode is disabled
676 * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
677 * something else.
678 * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
679 * is performed manually.
680 * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
681 * during a channel scan.
682 */
683enum spectral_mode {
684 SPECTRAL_DISABLED = 0,
685 SPECTRAL_BACKGROUND,
686 SPECTRAL_MANUAL,
687 SPECTRAL_CHANSCAN,
688};
689
394cf0a1
S		 690struct ath_softc {
691 struct ieee80211_hw *hw;
692 struct device *dev;
c52f33d0 693
3430098a
FF		 694 struct survey_info *cur_survey;
695 struct survey_info survey[ATH9K_NUM_CHANNELS];
0e2dedf9 696
394cf0a1
S		 697 struct tasklet_struct intr_tq;
698 struct tasklet_struct bcon_tasklet;
cbe61d8a 699 struct ath_hw *sc_ah;
394cf0a1
S		 700 void __iomem *mem;
701 int irq;
2d6a5e95 702 spinlock_t sc_serial_rw;
04717ccd 703 spinlock_t sc_pm_lock;
4bdd1e97 704 spinlock_t sc_pcu_lock;
394cf0a1 705 struct mutex mutex;
9f42c2b6 706 struct work_struct paprd_work;
347809fc 707 struct work_struct hw_check_work;
236de514 708 struct work_struct hw_reset_work;
9f42c2b6 709 struct completion paprd_complete;
394cf0a1 710
cb8d61de 711 unsigned int hw_busy_count;
781b14a3 712 unsigned long sc_flags;
cb8d61de 713
17d7904d 714 u32 intrstatus;
1b04b930 715 u16 ps_flags; /* PS_* */
17d7904d 716 u16 curtxpow;
96148326 717 bool ps_enabled;
1dbfd9d4 718 bool ps_idle;
4801416c
BG		 719 short nbcnvifs;
720 short nvifs;
709ade9e 721 unsigned long ps_usecount;
394cf0a1 722
17d7904d 723 struct ath_config config;
394cf0a1
S		 724 struct ath_rx rx;
725 struct ath_tx tx;
726 struct ath_beacon beacon;
394cf0a1
S		 727 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
728
0cf55c21
FF		 729#ifdef CONFIG_MAC80211_LEDS
730 bool led_registered;
731 char led_name[32];
732 struct led_classdev led_cdev;
733#endif
394cf0a1 734
9ac58615
FF		 735 struct ath9k_hw_cal_data caldata;
736 int last_rssi;
737
a830df07 738#ifdef CONFIG_ATH9K_DEBUGFS
17d7904d 739 struct ath9k_debug debug;
394cf0a1 740#endif
6b96f93e 741 struct ath_beacon_config cur_beacon_conf;
164ace38 742 struct delayed_work tx_complete_work;
181fb18d 743 struct delayed_work hw_pll_work;
01e18918 744 struct timer_list rx_poll_timer;
4daa7760
SM		 745
746#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2e20250a 747 struct ath_btcoex btcoex;
9e25365f 748 struct ath_mci_coex mci_coex;
3c7992e3 749 struct work_struct mci_work;
4daa7760 750#endif
5088c2f1
VT		 751
752 struct ath_descdma txsdma;
102885a5
VT		 753
754 struct ath_ant_comb ant_comb;
43c35284 755 u8 ant_tx, ant_rx;
8e92d3f2 756 struct dfs_pattern_detector *dfs_detector;
b11e640a 757 u32 wow_enabled;
e93d083f
SW		 758 /* relay(fs) channel for spectral scan */
759 struct rchan *rfs_chan_spec_scan;
760 enum spectral_mode spectral_mode;
04ccd4a1 761 struct ath_spec_scan spec_config;
e93d083f 762 int scanning;
01c78533
MSS		 763
764#ifdef CONFIG_PM_SLEEP
765 atomic_t wow_got_bmiss_intr;
766 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
767 u32 wow_intr_before_sleep;
768#endif
394cf0a1
S		 769};
770
e93d083f
SW		 771#define SPECTRAL_SCAN_BITMASK 0x10
772/* Radar info packet format, used for DFS and spectral formats. */
773struct ath_radar_info {
774 u8 pulse_length_pri;
775 u8 pulse_length_ext;
776 u8 pulse_bw_info;
777} __packed;
778
779/* The HT20 spectral data has 4 bytes of additional information at it's end.
780 *
781 * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
782 * [7:0]: all bins max_magnitude[9:2]
783 * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
784 * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
785 */
786struct ath_ht20_mag_info {
787 u8 all_bins[3];
788 u8 max_exp;
789} __packed;
790
791#define SPECTRAL_HT20_NUM_BINS 56
792
793/* WARNING: don't actually use this struct! MAC may vary the amount of
794 * data by -1/+2. This struct is for reference only.
795 */
796struct ath_ht20_fft_packet {
797 u8 data[SPECTRAL_HT20_NUM_BINS];
798 struct ath_ht20_mag_info mag_info;
799 struct ath_radar_info radar_info;
800} __packed;
801
802#define SPECTRAL_HT20_TOTAL_DATA_LEN (sizeof(struct ath_ht20_fft_packet))
803
804/* Dynamic 20/40 mode:
805 *
806 * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
807 * [7:0]: lower bins max_magnitude[9:2]
808 * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
809 * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
810 * [7:0]: upper bins max_magnitude[9:2]
811 * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
812 * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
813 */
814struct ath_ht20_40_mag_info {
815 u8 lower_bins[3];
816 u8 upper_bins[3];
817 u8 max_exp;
818} __packed;
819
820#define SPECTRAL_HT20_40_NUM_BINS 128
821
822/* WARNING: don't actually use this struct! MAC may vary the amount of
823 * data. This struct is for reference only.
824 */
825struct ath_ht20_40_fft_packet {
826 u8 data[SPECTRAL_HT20_40_NUM_BINS];
827 struct ath_ht20_40_mag_info mag_info;
828 struct ath_radar_info radar_info;
829} __packed;
830
831
832#define SPECTRAL_HT20_40_TOTAL_DATA_LEN (sizeof(struct ath_ht20_40_fft_packet))
833
834/* grabs the max magnitude from the all/upper/lower bins */
835static inline u16 spectral_max_magnitude(u8 *bins)
836{
837 return (bins[0] & 0xc0) >> 6 |
838 (bins[1] & 0xff) << 2 |
839 (bins[2] & 0x03) << 10;
840}
841
842/* return the max magnitude from the all/upper/lower bins */
843static inline u8 spectral_max_index(u8 *bins)
844{
845 s8 m = (bins[2] & 0xfc) >> 2;
846
847 /* TODO: this still doesn't always report the right values ... */
848 if (m > 32)
849 m |= 0xe0;
850 else
851 m &= ~0xe0;
852
853 return m + 29;
854}
855
856/* return the bitmap weight from the all/upper/lower bins */
857static inline u8 spectral_bitmap_weight(u8 *bins)
858{
859 return bins[0] & 0x3f;
860}
861
862/* FFT sample format given to userspace via debugfs.
863 *
864 * Please keep the type/length at the front position and change
865 * other fields after adding another sample type
866 *
867 * TODO: this might need rework when switching to nl80211-based
868 * interface.
869 */
870enum ath_fft_sample_type {
4ab0b0aa 871 ATH_FFT_SAMPLE_HT20 = 1,
e93d083f
SW		 872};
873
874struct fft_sample_tlv {
875 u8 type; /* see ath_fft_sample */
12824374 876 __be16 length;
e93d083f
SW		 877 /* type dependent data follows */
878} __packed;
879
880struct fft_sample_ht20 {
881 struct fft_sample_tlv tlv;
882
4ab0b0aa 883 u8 max_exp;
e93d083f 884
12824374 885 __be16 freq;
e93d083f
SW		 886 s8 rssi;
887 s8 noise;
888
12824374 889 __be16 max_magnitude;
e93d083f
SW		 890 u8 max_index;
891 u8 bitmap_weight;
892
12824374 893 __be64 tsf;
e93d083f 894
4ab0b0aa 895 u8 data[SPECTRAL_HT20_NUM_BINS];
e93d083f
SW		 896} __packed;
897
55624204 898void ath9k_tasklet(unsigned long data);
394cf0a1
S		 899int ath_cabq_update(struct ath_softc *);
900
5bb12791 901static inline void ath_read_cachesize(struct ath_common *common, int *csz)
394cf0a1 902{
5bb12791 903 common->bus_ops->read_cachesize(common, csz);
394cf0a1
S		 904}
905
394cf0a1 906extern struct ieee80211_ops ath9k_ops;
3e6109c5 907extern int ath9k_modparam_nohwcrypt;
9a75c2ff 908extern int led_blink;
d584747b 909extern bool is_ath9k_unloaded;
394cf0a1 910
313eb87f 911u8 ath9k_parse_mpdudensity(u8 mpdudensity);
394cf0a1 912irqreturn_t ath_isr(int irq, void *dev);
eb93e891 913int ath9k_init_device(u16 devid, struct ath_softc *sc,
5bb12791 914 const struct ath_bus_ops *bus_ops);
285f2dda 915void ath9k_deinit_device(struct ath_softc *sc);
285f2dda 916void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
43c35284 917void ath9k_reload_chainmask_settings(struct ath_softc *sc);
68a89116 918
4801416c 919bool ath9k_uses_beacons(int type);
e93d083f
SW		 920void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
921int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
922 enum spectral_mode spectral_mode);
923
394cf0a1 924
8e26a030 925#ifdef CONFIG_ATH9K_PCI
394cf0a1
S		 926int ath_pci_init(void);
927void ath_pci_exit(void);
928#else
929static inline int ath_pci_init(void) { return 0; };
930static inline void ath_pci_exit(void) {};
f1dc5600 931#endif
f1dc5600 932
8e26a030 933#ifdef CONFIG_ATH9K_AHB
394cf0a1
S		 934int ath_ahb_init(void);
935void ath_ahb_exit(void);
936#else
937static inline int ath_ahb_init(void) { return 0; };
938static inline void ath_ahb_exit(void) {};
f078f209 939#endif
394cf0a1 940
0bc0798b
GJ		 941void ath9k_ps_wakeup(struct ath_softc *sc);
942void ath9k_ps_restore(struct ath_softc *sc);
8ca21f01 943
ea066d5a
MSS		 944u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
945
0fca65c1
S		 946void ath_start_rfkill_poll(struct ath_softc *sc);
947extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
4801416c
BG		 948void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
949 struct ieee80211_vif *vif,
950 struct ath9k_vif_iter_data *iter_data);
951
394cf0a1 952#endif /* ATH9K_H */
Linux kernel - Deliverables
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