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ath9k: adjust WLAN and BT concurrent transmission
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ath9k.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
394cf0a1
S		 20#include <linux/etherdevice.h>
21#include <linux/device.h>
a6b7a407 22#include <linux/interrupt.h>
394cf0a1 23#include <linux/leds.h>
9f42c2b6 24#include <linux/completion.h>
394cf0a1 25
394cf0a1 26#include "debug.h"
db86f07e 27#include "common.h"
7dc181c2 28#include "mci.h"
8e92d3f2 29#include "dfs.h"
db86f07e
LR		 30
31/*
32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
33 * should rely on this file or its contents.
34 */
394cf0a1
S		 35
36struct ath_node;
37
38/* Macro to expand scalars to 64-bit objects */
39
13bda122 40#define ito64(x) (sizeof(x) == 1) ? \
394cf0a1 41 (((unsigned long long int)(x)) & (0xff)) : \
13bda122 42 (sizeof(x) == 2) ? \
394cf0a1 43 (((unsigned long long int)(x)) & 0xffff) : \
13bda122 44 ((sizeof(x) == 4) ? \
394cf0a1
S		 45 (((unsigned long long int)(x)) & 0xffffffff) : \
46 (unsigned long long int)(x))
47
48/* increment with wrap-around */
49#define INCR(_l, _sz) do { \
50 (_l)++; \
51 (_l) &= ((_sz) - 1); \
52 } while (0)
53
54/* decrement with wrap-around */
55#define DECR(_l, _sz) do { \
56 (_l)--; \
57 (_l) &= ((_sz) - 1); \
58 } while (0)
59
394cf0a1
S		 60#define TSF_TO_TU(_h,_l) \
61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
62
63#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
64
394cf0a1 65struct ath_config {
394cf0a1
S		 66 u16 txpowlimit;
67 u8 cabqReadytime;
394cf0a1
S		 68};
69
70/*************************/
71/* Descriptor Management */
72/*************************/
73
74#define ATH_TXBUF_RESET(_bf) do { \
a119cc49 75 (_bf)->bf_stale = false; \
394cf0a1
S		 76 (_bf)->bf_lastbf = NULL; \
77 (_bf)->bf_next = NULL; \
78 memset(&((_bf)->bf_state), 0, \
79 sizeof(struct ath_buf_state)); \
80 } while (0)
81
a119cc49
S		 82#define ATH_RXBUF_RESET(_bf) do { \
83 (_bf)->bf_stale = false; \
84 } while (0)
85
394cf0a1
S		 86/**
87 * enum buffer_type - Buffer type flags
88 *
394cf0a1
S		 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
90 * @BUF_AGGR: Indicates whether the buffer can be aggregated
91 * (used in aggregation scheduling)
394cf0a1
S		 92 */
93enum buffer_type {
436d0d98
MSS		 94 BUF_AMPDU = BIT(0),
95 BUF_AGGR = BIT(1),
394cf0a1
S		 96};
97
394cf0a1
S		 98#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
99#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
f078f209 100
016c2177 101#define ATH_TXSTATUS_RING_SIZE 512
5088c2f1 102
c3d77696
MSS		 103#define DS2PHYS(_dd, _ds) \
104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
105#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
106#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
107
394cf0a1 108struct ath_descdma {
5088c2f1 109 void *dd_desc;
17d7904d
S		 110 dma_addr_t dd_desc_paddr;
111 u32 dd_desc_len;
112 struct ath_buf *dd_bufptr;
394cf0a1
S		 113};
114
115int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
116 struct list_head *head, const char *name,
4adfcded 117 int nbuf, int ndesc, bool is_tx);
394cf0a1
S		 118void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
119 struct list_head *head);
120
121/***********/
122/* RX / TX */
123/***********/
124
394cf0a1 125#define ATH_RXBUF 512
394cf0a1 126#define ATH_TXBUF 512
84642d6b
FF		 127#define ATH_TXBUF_RESERVE 5
128#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
394cf0a1 129#define ATH_TXMAXTRY 13
394cf0a1
S		 130
131#define TID_TO_WME_AC(_tid) \
132 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
133 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
134 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
135 WME_AC_VO)
136
394cf0a1
S		 137#define ATH_AGGR_DELIM_SZ 4
138#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
139/* number of delimiters for encryption padding */
140#define ATH_AGGR_ENCRYPTDELIM 10
141/* minimum h/w qdepth to be sustained to maximize aggregation */
142#define ATH_AGGR_MIN_QDEPTH 2
143#define ATH_AMPDU_SUBFRAME_DEFAULT 32
394cf0a1
S		 144
145#define IEEE80211_SEQ_SEQ_SHIFT 4
146#define IEEE80211_SEQ_MAX 4096
394cf0a1
S		 147#define IEEE80211_WEP_IVLEN 3
148#define IEEE80211_WEP_KIDLEN 1
149#define IEEE80211_WEP_CRCLEN 4
150#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
151 (IEEE80211_WEP_IVLEN + \
152 IEEE80211_WEP_KIDLEN + \
153 IEEE80211_WEP_CRCLEN))
154
155/* return whether a bit at index _n in bitmap _bm is set
156 * _sz is the size of the bitmap */
157#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
158 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
159
160/* return block-ack bitmap index given sequence and starting sequence */
161#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
162
156369fa
FF		 163/* return the seqno for _start + _offset */
164#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
165
394cf0a1
S		 166/* returns delimiter padding required given the packet length */
167#define ATH_AGGR_GET_NDELIM(_len) \
39ec2997
VT		 168 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
169 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
394cf0a1
S		 170
171#define BAW_WITHIN(_start, _bawsz, _seqno) \
172 ((((_seqno) - (_start)) & 4095) < (_bawsz))
173
394cf0a1
S		 174#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
175
365d2ebc
SM		 176#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
177
164ace38
SB		 178#define ATH_TX_COMPLETE_POLL_INT 1000
179
394cf0a1
S		 180enum ATH_AGGR_STATUS {
181 ATH_AGGR_DONE,
182 ATH_AGGR_BAW_CLOSED,
183 ATH_AGGR_LIMITED,
184};
185
e5003249 186#define ATH_TXFIFO_DEPTH 8
394cf0a1 187struct ath_txq {
60f2d1d5
BG		 188 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
189 u32 axq_qnum; /* ath9k hardware queue number */
fce041be 190 void *axq_link;
17d7904d 191 struct list_head axq_q;
394cf0a1 192 spinlock_t axq_lock;
17d7904d 193 u32 axq_depth;
4b3ba66a 194 u32 axq_ampdu_depth;
17d7904d 195 bool stopped;
164ace38 196 bool axq_tx_inprogress;
394cf0a1 197 struct list_head axq_acq;
e5003249 198 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
e5003249
VT		 199 u8 txq_headidx;
200 u8 txq_tailidx;
066dae93 201 int pending_frames;
23de5dc9 202 struct sk_buff_head complete_q;
394cf0a1
S		 203};
204
93ef24b2 205struct ath_atx_ac {
066dae93 206 struct ath_txq *txq;
93ef24b2 207 int sched;
93ef24b2
S		 208 struct list_head list;
209 struct list_head tid_q;
5519541d 210 bool clear_ps_filter;
93ef24b2
S		 211};
212
2d42efc4 213struct ath_frame_info {
56dc6336 214 struct ath_buf *bf;
2d42efc4 215 int framelen;
2d42efc4 216 enum ath9k_key_type keytype;
a75c0629 217 u8 keyix;
2d42efc4 218 u8 retries;
80b08a8d 219 u8 rtscts_rate;
2d42efc4
FF		 220};
221
93ef24b2 222struct ath_buf_state {
93ef24b2 223 u8 bf_type;
9f42c2b6 224 u8 bfs_paprd;
399c6489 225 u8 ndelim;
6a0ddaef 226 u16 seqno;
9cf04dcc 227 unsigned long bfs_paprd_timestamp;
93ef24b2
S		 228};
229
230struct ath_buf {
231 struct list_head list;
232 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
233 an aggregate) */
234 struct ath_buf *bf_next; /* next subframe in the aggregate */
235 struct sk_buff *bf_mpdu; /* enclosing frame structure */
236 void *bf_desc; /* virtual addr of desc */
237 dma_addr_t bf_daddr; /* physical addr of desc */
c1739eb3 238 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
93ef24b2 239 bool bf_stale;
93ef24b2 240 struct ath_buf_state bf_state;
93ef24b2
S		 241};
242
243struct ath_atx_tid {
244 struct list_head list;
56dc6336 245 struct sk_buff_head buf_q;
93ef24b2
S		 246 struct ath_node *an;
247 struct ath_atx_ac *ac;
81ee13ba 248 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
f9437543 249 int bar_index;
93ef24b2
S		 250 u16 seq_start;
251 u16 seq_next;
252 u16 baw_size;
253 int tidno;
254 int baw_head; /* first un-acked tx buffer */
255 int baw_tail; /* next unused tx buffer slot */
256 int sched;
257 int paused;
258 u8 state;
259};
260
261struct ath_node {
7f010c93
BG		 262#ifdef CONFIG_ATH9K_DEBUGFS
263 struct list_head list; /* for sc->nodes */
156369fa 264#endif
7f010c93 265 struct ieee80211_sta *sta; /* station struct we're part of */
7e1e3864 266 struct ieee80211_vif *vif; /* interface with which we're associated */
93ef24b2
S		 267 struct ath_atx_tid tid[WME_NUM_TID];
268 struct ath_atx_ac ac[WME_NUM_AC];
93ae2dd2
FF		 269 int ps_key;
270
93ef24b2
S		 271 u16 maxampdu;
272 u8 mpdudensity;
5519541d
FF		 273
274 bool sleeping;
93ef24b2
S		 275};
276
394cf0a1
S		 277#define AGGR_CLEANUP BIT(1)
278#define AGGR_ADDBA_COMPLETE BIT(2)
279#define AGGR_ADDBA_PROGRESS BIT(3)
280
394cf0a1
S		 281struct ath_tx_control {
282 struct ath_txq *txq;
2d42efc4 283 struct ath_node *an;
9f42c2b6 284 u8 paprd;
36323f81 285 struct ieee80211_sta *sta;
394cf0a1
S		 286};
287
394cf0a1 288#define ATH_TX_ERROR 0x01
394cf0a1 289
60f2d1d5
BG		 290/**
291 * @txq_map: Index is mac80211 queue number. This is
292 * not necessarily the same as the hardware queue number
293 * (axq_qnum).
294 */
394cf0a1
S		 295struct ath_tx {
296 u16 seq_no;
297 u32 txqsetup;
394cf0a1
S		 298 spinlock_t txbuflock;
299 struct list_head txbuf;
300 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
301 struct ath_descdma txdma;
066dae93 302 struct ath_txq *txq_map[WME_NUM_AC];
7702e788 303 u32 txq_max_pending[WME_NUM_AC];
aa5955c3 304 u16 max_aggr_framelen[WME_NUM_AC][4][32];
394cf0a1
S		 305};
306
b5c80475
FF		 307struct ath_rx_edma {
308 struct sk_buff_head rx_fifo;
b5c80475
FF		 309 u32 rx_fifo_hwsize;
310};
311
394cf0a1
S		 312struct ath_rx {
313 u8 defant;
314 u8 rxotherant;
315 u32 *rxlink;
6995fb80 316 u32 num_pkts;
394cf0a1 317 unsigned int rxfilter;
394cf0a1
S		 318 spinlock_t rxbuflock;
319 struct list_head rxbuf;
320 struct ath_descdma rxdma;
b5c80475
FF		 321 struct ath_buf *rx_bufptr;
322 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
0d95521e
FF		 323
324 struct sk_buff *frag;
394cf0a1
S		 325};
326
327int ath_startrecv(struct ath_softc *sc);
328bool ath_stoprecv(struct ath_softc *sc);
329void ath_flushrecv(struct ath_softc *sc);
330u32 ath_calcrxfilter(struct ath_softc *sc);
331int ath_rx_init(struct ath_softc *sc, int nbufs);
332void ath_rx_cleanup(struct ath_softc *sc);
b5c80475 333int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
394cf0a1 334struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
ef1b6cd9
SM		 335void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
336void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
337void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
394cf0a1 338void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
080e1a25 339bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
394cf0a1
S		 340void ath_draintxq(struct ath_softc *sc,
341 struct ath_txq *txq, bool retry_tx);
342void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
343void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
344void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
345int ath_tx_init(struct ath_softc *sc, int nbufs);
797fe5cb 346void ath_tx_cleanup(struct ath_softc *sc);
394cf0a1
S		 347int ath_txq_update(struct ath_softc *sc, int qnum,
348 struct ath9k_tx_queue_info *q);
aa5955c3 349void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
c52f33d0 350int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
394cf0a1
S		 351 struct ath_tx_control *txctl);
352void ath_tx_tasklet(struct ath_softc *sc);
e5003249 353void ath_tx_edma_tasklet(struct ath_softc *sc);
231c3a1f
FF		 354int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
355 u16 tid, u16 *ssn);
f83da965 356void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
394cf0a1
S		 357void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
358
5519541d 359void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
042ec453
JB		 360void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
361 struct ath_node *an);
5519541d 362
394cf0a1 363/********/
17d7904d 364/* VIFs */
394cf0a1 365/********/
f078f209 366
17d7904d 367struct ath_vif {
394cf0a1 368 int av_bslot;
aa45fe96 369 bool primary_sta_vif;
4ed96f04 370 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
394cf0a1 371 struct ath_buf *av_bcbuf;
f078f209
LR		 372};
373
394cf0a1
S		 374/*******************/
375/* Beacon Handling */
376/*******************/
f078f209 377
394cf0a1
S		 378/*
379 * Regardless of the number of beacons we stagger, (i.e. regardless of the
380 * number of BSSIDs) if a given beacon does not go out even after waiting this
381 * number of beacon intervals, the game's up.
382 */
c944daf4 383#define BSTUCK_THRESH 9
689e756f 384#define ATH_BCBUF 8
394cf0a1
S		 385#define ATH_DEFAULT_BINTVAL 100 /* TU */
386#define ATH_DEFAULT_BMISS_LIMIT 10
387#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
388
389struct ath_beacon_config {
9814f6b3 390 int beacon_interval;
394cf0a1
S		 391 u16 listen_interval;
392 u16 dtim_period;
393 u16 bmiss_timeout;
394 u8 dtim_count;
ef4ad633 395 bool enable_beacon;
394cf0a1
S		 396};
397
398struct ath_beacon {
399 enum {
400 OK, /* no change needed */
401 UPDATE, /* update pending */
402 COMMIT /* beacon sent, commit change */
403 } updateslot; /* slot time update fsm */
404
405 u32 beaconq;
406 u32 bmisscnt;
dd347f2f 407 u32 bc_tstamp;
2c3db3d5 408 struct ieee80211_vif *bslot[ATH_BCBUF];
394cf0a1
S		 409 int slottime;
410 int slotupdate;
411 struct ath9k_tx_queue_info beacon_qi;
412 struct ath_descdma bdma;
413 struct ath_txq *cabq;
414 struct list_head bbuf;
ba4903f9
FF		 415
416 bool tx_processed;
417 bool tx_last;
394cf0a1
S		 418};
419
fb6e252f 420void ath9k_beacon_tasklet(unsigned long data);
ef4ad633
SM		 421bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
422void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
423 u32 changed);
130ef6e9
SM		 424void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
425void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
2f8e82e8 426void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
ef4ad633 427void ath9k_set_beacon(struct ath_softc *sc);
394cf0a1 428
ef1b6cd9
SM		 429/*******************/
430/* Link Monitoring */
431/*******************/
f078f209 432
20977d3e
S		 433#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
434#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
e36b27af
LR		 435#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
436#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
6044474e 437#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
20977d3e
S		 438#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
439#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
424749c7 440#define ATH_ANI_MAX_SKIP_COUNT 10
f078f209 441
ca369eb4 442#define ATH_PAPRD_TIMEOUT 100 /* msecs */
af68abad 443#define ATH_PLL_WORK_INTERVAL 100
ca369eb4 444
ef1b6cd9 445void ath_tx_complete_poll_work(struct work_struct *work);
236de514 446void ath_reset_work(struct work_struct *work);
347809fc 447void ath_hw_check(struct work_struct *work);
9eab61c2 448void ath_hw_pll_work(struct work_struct *work);
01e18918
RM		 449void ath_rx_poll(unsigned long data);
450void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
9f42c2b6 451void ath_paprd_calibrate(struct work_struct *work);
55624204 452void ath_ani_calibrate(unsigned long data);
da0d45f7
SM		 453void ath_start_ani(struct ath_softc *sc);
454void ath_stop_ani(struct ath_softc *sc);
455void ath_check_ani(struct ath_softc *sc);
ef1b6cd9
SM		 456int ath_update_survey_stats(struct ath_softc *sc);
457void ath_update_survey_nf(struct ath_softc *sc, int channel);
124b979b 458void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
55624204 459
0fca65c1
S		 460/**********/
461/* BTCOEX */
462/**********/
463
e6930c4b
SM		 464enum bt_op_flags {
465 BT_OP_PRIORITY_DETECTED,
466 BT_OP_SCAN,
467};
468
2e20250a
LR		 469struct ath_btcoex {
470 bool hw_timer_enabled;
471 spinlock_t btcoex_lock;
472 struct timer_list period_timer; /* Timer for BT period */
473 u32 bt_priority_cnt;
474 unsigned long bt_priority_time;
e6930c4b 475 unsigned long op_flags;
e08a6ace 476 int bt_stomp_type; /* Types of BT stomping */
2e20250a 477 u32 btcoex_no_stomp; /* in usec */
94ae77ea 478 u32 btcoex_period; /* in msec */
58da1318 479 u32 btscan_no_stomp; /* in usec */
7dc181c2 480 u32 duty_cycle;
6995fb80 481 u32 bt_wait_time;
e82cb03f 482 int rssi_count;
75d7839f 483 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
7dc181c2 484 struct ath_mci_profile mci;
2e20250a
LR		 485};
486
4daa7760 487#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
5908120f
SM		 488int ath9k_init_btcoex(struct ath_softc *sc);
489void ath9k_deinit_btcoex(struct ath_softc *sc);
df198b17
SM		 490void ath9k_start_btcoex(struct ath_softc *sc);
491void ath9k_stop_btcoex(struct ath_softc *sc);
0fca65c1
S		 492void ath9k_btcoex_timer_resume(struct ath_softc *sc);
493void ath9k_btcoex_timer_pause(struct ath_softc *sc);
56ca0dba 494void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
c0ac53fa 495u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
08d4df41 496void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
4daa7760
SM		 497#else
498static inline int ath9k_init_btcoex(struct ath_softc *sc)
499{
500 return 0;
501}
502static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
503{
504}
505static inline void ath9k_start_btcoex(struct ath_softc *sc)
506{
507}
508static inline void ath9k_stop_btcoex(struct ath_softc *sc)
509{
510}
511static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
512 u32 status)
513{
514}
515static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
516 u32 max_4ms_framelen)
517{
518 return 0;
519}
08d4df41
RM		 520static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
521{
522}
4daa7760 523#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0fca65c1 524
01c78533
MSS		 525struct ath9k_wow_pattern {
526 u8 pattern_bytes[MAX_PATTERN_SIZE];
527 u8 mask_bytes[MAX_PATTERN_SIZE];
528 u32 pattern_len;
529};
530
394cf0a1
S		 531/********************/
532/* LED Control */
533/********************/
f078f209 534
08fc5c1b
VN		 535#define ATH_LED_PIN_DEF 1
536#define ATH_LED_PIN_9287 8
353e5019 537#define ATH_LED_PIN_9300 10
15178535 538#define ATH_LED_PIN_9485 6
1a68abb0 539#define ATH_LED_PIN_9462 4
f078f209 540
0cf55c21 541#ifdef CONFIG_MAC80211_LEDS
0fca65c1
S		 542void ath_init_leds(struct ath_softc *sc);
543void ath_deinit_leds(struct ath_softc *sc);
8f176a3a 544void ath_fill_led_pin(struct ath_softc *sc);
0cf55c21
FF		 545#else
546static inline void ath_init_leds(struct ath_softc *sc)
547{
548}
549
550static inline void ath_deinit_leds(struct ath_softc *sc)
8f176a3a
RM		 551{
552}
553static inline void ath_fill_led_pin(struct ath_softc *sc)
0cf55c21
FF		 554{
555}
556#endif
557
8da07830 558/*******************************/
102885a5 559/* Antenna diversity/combining */
8da07830
SM		 560/*******************************/
561
102885a5
VT		 562#define ATH_ANT_RX_CURRENT_SHIFT 4
563#define ATH_ANT_RX_MAIN_SHIFT 2
564#define ATH_ANT_RX_MASK 0x3
565
566#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
567#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
568#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
569#define ATH_ANT_DIV_COMB_INIT_COUNT 95
570#define ATH_ANT_DIV_COMB_MAX_COUNT 100
571#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
572#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
573
102885a5
VT		 574#define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
575#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
576#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
577#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
578
579enum ath9k_ant_div_comb_lna_conf {
580 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
581 ATH_ANT_DIV_COMB_LNA2,
582 ATH_ANT_DIV_COMB_LNA1,
583 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
584};
585
586struct ath_ant_comb {
587 u16 count;
588 u16 total_pkt_count;
589 bool scan;
590 bool scan_not_start;
591 int main_total_rssi;
592 int alt_total_rssi;
593 int alt_recv_cnt;
594 int main_recv_cnt;
595 int rssi_lna1;
596 int rssi_lna2;
597 int rssi_add;
598 int rssi_sub;
599 int rssi_first;
600 int rssi_second;
601 int rssi_third;
602 bool alt_good;
603 int quick_scan_cnt;
604 int main_conf;
605 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
606 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
102885a5
VT		 607 bool first_ratio;
608 bool second_ratio;
609 unsigned long scan_start_time;
610};
611
8da07830
SM		 612void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
613void ath_ant_comb_update(struct ath_softc *sc);
614
394cf0a1
S		 615/********************/
616/* Main driver core */
617/********************/
f078f209 618
394cf0a1
S		 619/*
620 * Default cache line size, in bytes.
621 * Used when PCI device not fully initialized by bootrom/BIOS
622*/
623#define DEFAULT_CACHELINE 32
394cf0a1
S		 624#define ATH_REGCLASSIDS_MAX 10
625#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
da647626 626#define ATH_MAX_SW_RETRIES 30
394cf0a1 627#define ATH_CHAN_MAX 255
f1dc5600 628
394cf0a1 629#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
394cf0a1
S		 630#define ATH_RATE_DUMMY_MARKER 0
631
781b14a3
SM		 632enum sc_op_flags {
633 SC_OP_INVALID,
634 SC_OP_BEACONS,
635 SC_OP_RXFLUSH,
781b14a3
SM		 636 SC_OP_ANI_RUN,
637 SC_OP_PRIM_STA_VIF,
b74713d0 638 SC_OP_HW_RESET,
781b14a3 639};
1b04b930
S		 640
641/* Powersave flags */
642#define PS_WAIT_FOR_BEACON BIT(0)
643#define PS_WAIT_FOR_CAB BIT(1)
644#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
645#define PS_WAIT_FOR_TX_ACK BIT(3)
646#define PS_BEACON_SYNC BIT(4)
424749c7 647#define PS_WAIT_FOR_ANI BIT(5)
394cf0a1 648
545750d3 649struct ath_rate_table;
bce048d7 650
4801416c
BG		 651struct ath9k_vif_iter_data {
652 const u8 *hw_macaddr; /* phy's hardware address, set
653 * before starting iteration for
654 * valid bssid mask.
655 */
656 u8 mask[ETH_ALEN]; /* bssid mask */
657 int naps; /* number of AP vifs */
658 int nmeshes; /* number of mesh vifs */
659 int nstations; /* number of station vifs */
e707549a 660 int nwds; /* number of WDS vifs */
4801416c 661 int nadhocs; /* number of adhoc vifs */
4801416c
BG		 662};
663
394cf0a1
S		 664struct ath_softc {
665 struct ieee80211_hw *hw;
666 struct device *dev;
c52f33d0 667
3430098a
FF		 668 struct survey_info *cur_survey;
669 struct survey_info survey[ATH9K_NUM_CHANNELS];
0e2dedf9 670
394cf0a1
S		 671 struct tasklet_struct intr_tq;
672 struct tasklet_struct bcon_tasklet;
cbe61d8a 673 struct ath_hw *sc_ah;
394cf0a1
S		 674 void __iomem *mem;
675 int irq;
2d6a5e95 676 spinlock_t sc_serial_rw;
04717ccd 677 spinlock_t sc_pm_lock;
4bdd1e97 678 spinlock_t sc_pcu_lock;
394cf0a1 679 struct mutex mutex;
9f42c2b6 680 struct work_struct paprd_work;
347809fc 681 struct work_struct hw_check_work;
236de514 682 struct work_struct hw_reset_work;
9f42c2b6 683 struct completion paprd_complete;
394cf0a1 684
cb8d61de 685 unsigned int hw_busy_count;
781b14a3 686 unsigned long sc_flags;
cb8d61de 687
17d7904d 688 u32 intrstatus;
1b04b930 689 u16 ps_flags; /* PS_* */
17d7904d 690 u16 curtxpow;
96148326 691 bool ps_enabled;
1dbfd9d4 692 bool ps_idle;
4801416c
BG		 693 short nbcnvifs;
694 short nvifs;
709ade9e 695 unsigned long ps_usecount;
394cf0a1 696
17d7904d 697 struct ath_config config;
394cf0a1
S		 698 struct ath_rx rx;
699 struct ath_tx tx;
700 struct ath_beacon beacon;
394cf0a1
S		 701 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
702
0cf55c21
FF		 703#ifdef CONFIG_MAC80211_LEDS
704 bool led_registered;
705 char led_name[32];
706 struct led_classdev led_cdev;
707#endif
394cf0a1 708
9ac58615
FF		 709 struct ath9k_hw_cal_data caldata;
710 int last_rssi;
711
a830df07 712#ifdef CONFIG_ATH9K_DEBUGFS
17d7904d 713 struct ath9k_debug debug;
7f010c93
BG		 714 spinlock_t nodes_lock;
715 struct list_head nodes; /* basically, stations */
60f2d1d5 716 unsigned int tx_complete_poll_work_seen;
394cf0a1 717#endif
6b96f93e 718 struct ath_beacon_config cur_beacon_conf;
164ace38 719 struct delayed_work tx_complete_work;
181fb18d 720 struct delayed_work hw_pll_work;
01e18918 721 struct timer_list rx_poll_timer;
4daa7760
SM		 722
723#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2e20250a 724 struct ath_btcoex btcoex;
9e25365f 725 struct ath_mci_coex mci_coex;
3c7992e3 726 struct work_struct mci_work;
4daa7760 727#endif
5088c2f1
VT		 728
729 struct ath_descdma txsdma;
102885a5
VT		 730
731 struct ath_ant_comb ant_comb;
43c35284 732 u8 ant_tx, ant_rx;
8e92d3f2 733 struct dfs_pattern_detector *dfs_detector;
b11e640a 734 u32 wow_enabled;
01c78533
MSS		 735
736#ifdef CONFIG_PM_SLEEP
737 atomic_t wow_got_bmiss_intr;
738 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
739 u32 wow_intr_before_sleep;
740#endif
394cf0a1
S		 741};
742
55624204 743void ath9k_tasklet(unsigned long data);
394cf0a1
S		 744int ath_cabq_update(struct ath_softc *);
745
5bb12791 746static inline void ath_read_cachesize(struct ath_common *common, int *csz)
394cf0a1 747{
5bb12791 748 common->bus_ops->read_cachesize(common, csz);
394cf0a1
S		 749}
750
394cf0a1 751extern struct ieee80211_ops ath9k_ops;
3e6109c5 752extern int ath9k_modparam_nohwcrypt;
9a75c2ff 753extern int led_blink;
d584747b 754extern bool is_ath9k_unloaded;
394cf0a1 755
313eb87f 756u8 ath9k_parse_mpdudensity(u8 mpdudensity);
394cf0a1 757irqreturn_t ath_isr(int irq, void *dev);
eb93e891 758int ath9k_init_device(u16 devid, struct ath_softc *sc,
5bb12791 759 const struct ath_bus_ops *bus_ops);
285f2dda 760void ath9k_deinit_device(struct ath_softc *sc);
285f2dda 761void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
43c35284 762void ath9k_reload_chainmask_settings(struct ath_softc *sc);
68a89116 763
4801416c 764bool ath9k_uses_beacons(int type);
394cf0a1 765
8e26a030 766#ifdef CONFIG_ATH9K_PCI
394cf0a1
S		 767int ath_pci_init(void);
768void ath_pci_exit(void);
769#else
770static inline int ath_pci_init(void) { return 0; };
771static inline void ath_pci_exit(void) {};
f1dc5600 772#endif
f1dc5600 773
8e26a030 774#ifdef CONFIG_ATH9K_AHB
394cf0a1
S		 775int ath_ahb_init(void);
776void ath_ahb_exit(void);
777#else
778static inline int ath_ahb_init(void) { return 0; };
779static inline void ath_ahb_exit(void) {};
f078f209 780#endif
394cf0a1 781
0bc0798b
GJ		 782void ath9k_ps_wakeup(struct ath_softc *sc);
783void ath9k_ps_restore(struct ath_softc *sc);
8ca21f01 784
ea066d5a
MSS		 785u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
786
0fca65c1
S		 787void ath_start_rfkill_poll(struct ath_softc *sc);
788extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
4801416c
BG		 789void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
790 struct ieee80211_vif *vif,
791 struct ath9k_vif_iter_data *iter_data);
792
394cf0a1 793#endif /* ATH9K_H */
Linux kernel - Deliverables
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