[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / btcoex.c

/*
 * Copyright (c) 2009-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/export.h>
#include "hw.h"

enum ath_bt_mode {
	ATH_BT_COEX_MODE_LEGACY,        /* legacy rx_clear mode */
	ATH_BT_COEX_MODE_UNSLOTTED,     /* untimed/unslotted mode */
	ATH_BT_COEX_MODE_SLOTTED,       /* slotted mode */
	ATH_BT_COEX_MODE_DISABLED,      /* coexistence disabled */
};

struct ath_btcoex_config {
	u8 bt_time_extend;
	bool bt_txstate_extend;
	bool bt_txframe_extend;
	enum ath_bt_mode bt_mode; /* coexistence mode */
	bool bt_quiet_collision;
	bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
	u8 bt_priority_time;
	u8 bt_first_slot_time;
	bool bt_hold_rx_clear;
};

static const u32 ar9003_wlan_weights[ATH_BTCOEX_STOMP_MAX]
				    [AR9300_NUM_WLAN_WEIGHTS] = {
	{ 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0 }, /* STOMP_ALL */
	{ 0x88888880, 0x88888880, 0x88888880, 0x88888880 }, /* STOMP_LOW */
	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */
};

static const u32 mci_wlan_weights[ATH_BTCOEX_STOMP_MAX]
				 [AR9300_NUM_WLAN_WEIGHTS] = {
	{ 0x01017d01, 0x41414101, 0x41414101, 0x41414141 }, /* STOMP_ALL */
	{ 0x01017d01, 0x3b3b3b01, 0x3b3b3b01, 0x3b3b3b3b }, /* STOMP_LOW */
	{ 0x01017d01, 0x01010101, 0x01010101, 0x01010101 }, /* STOMP_NONE */
	{ 0x01017d01, 0x013b0101, 0x3b3b0101, 0x3b3b013b }, /* STOMP_LOW_FTP */
	{ 0xffffff01, 0xffffffff, 0xffffff01, 0xffffffff }, /* STOMP_AUDIO */
};

void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	const struct ath_btcoex_config ath_bt_config = {
		.bt_time_extend = 0,
		.bt_txstate_extend = true,
		.bt_txframe_extend = true,
		.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
		.bt_quiet_collision = true,
		.bt_rxclear_polarity = true,
		.bt_priority_time = 2,
		.bt_first_slot_time = 5,
		.bt_hold_rx_clear = true,
	};
	bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;

	if (AR_SREV_9300_20_OR_LATER(ah))
		rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;

	btcoex_hw->bt_coex_mode =
		(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
		SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
		SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
		SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
		SM(ath_bt_config.bt_mode, AR_BT_MODE) |
		SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
		SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
		SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
		SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
		SM(qnum, AR_BT_QCU_THRESH);

	btcoex_hw->bt_coex_mode2 =
		SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
		SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
		AR_BT_DISABLE_BT_ANT;
}
EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);

void ath9k_hw_btcoex_init_scheme(struct ath_hw *ah)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/*
	 * Check if BTCOEX is globally disabled.
	 */
	if (!common->btcoex_enabled) {
		btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
		return;
	}

	if (AR_SREV_9300_20_OR_LATER(ah)) {
		btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
		btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
	} else if (AR_SREV_9280_20_OR_LATER(ah)) {
		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;

		if (AR_SREV_9285(ah)) {
			btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
			btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9285;
		} else {
			btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
		}
	}
}
EXPORT_SYMBOL(ath9k_hw_btcoex_init_scheme);

void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* connect bt_active to baseband */
	REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
		     AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));

	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);

	/* Set input mux for bt_active to gpio pin */
	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
		      AR_GPIO_INPUT_MUX1_BT_ACTIVE,
		      btcoex_hw->btactive_gpio);

	/* Configure the desired gpio port for input */
	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
}
EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);

void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* btcoex 3-wire */
	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
			(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
			 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));

	/* Set input mux for bt_prority_async and
	 *                  bt_active_async to GPIO pins */
	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
			AR_GPIO_INPUT_MUX1_BT_ACTIVE,
			btcoex_hw->btactive_gpio);

	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
			AR_GPIO_INPUT_MUX1_BT_PRIORITY,
			btcoex_hw->btpriority_gpio);

	/* Configure the desired GPIO ports for input */

	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
}
EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);

void ath9k_hw_btcoex_init_mci(struct ath_hw *ah)
{
	ah->btcoex_hw.mci.ready = false;
	ah->btcoex_hw.mci.bt_state = 0;
	ah->btcoex_hw.mci.bt_ver_major = 3;
	ah->btcoex_hw.mci.bt_ver_minor = 0;
	ah->btcoex_hw.mci.bt_version_known = false;
	ah->btcoex_hw.mci.update_2g5g = true;
	ah->btcoex_hw.mci.is_2g = true;
	ah->btcoex_hw.mci.wlan_channels_update = false;
	ah->btcoex_hw.mci.wlan_channels[0] = 0x00000000;
	ah->btcoex_hw.mci.wlan_channels[1] = 0xffffffff;
	ah->btcoex_hw.mci.wlan_channels[2] = 0xffffffff;
	ah->btcoex_hw.mci.wlan_channels[3] = 0x7fffffff;
	ah->btcoex_hw.mci.query_bt = true;
	ah->btcoex_hw.mci.unhalt_bt_gpm = true;
	ah->btcoex_hw.mci.halted_bt_gpm = false;
	ah->btcoex_hw.mci.need_flush_btinfo = false;
	ah->btcoex_hw.mci.wlan_cal_seq = 0;
	ah->btcoex_hw.mci.wlan_cal_done = 0;
	ah->btcoex_hw.mci.config = (AR_SREV_9462(ah)) ? 0x2201 : 0xa4c1;
}
EXPORT_SYMBOL(ath9k_hw_btcoex_init_mci);

static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	/* Configure the desired GPIO port for TX_FRAME output */
	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
			    AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
}

/*
 * For AR9002, bt_weight/wlan_weight are used.
 * For AR9003 and above, stomp_type is used.
 */
void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
				u32 bt_weight,
				u32 wlan_weight,
				enum ath_stomp_type stomp_type)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	u8 txprio_shift[] = { 24, 16, 16, 0 }; /* tx priority weight */
	bool concur_tx = (mci_hw->concur_tx && btcoex_hw->tx_prio[stomp_type]);
	const u32 *weight = ar9003_wlan_weights[stomp_type];
	int i;

	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		btcoex_hw->bt_coex_weights =
			SM(bt_weight, AR_BTCOEX_BT_WGHT) |
			SM(wlan_weight, AR_BTCOEX_WL_WGHT);
		return;
	}

	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
		enum ath_stomp_type stype =
			((stomp_type == ATH_BTCOEX_STOMP_LOW) &&
			 btcoex_hw->mci.stomp_ftp) ?
			ATH_BTCOEX_STOMP_LOW_FTP : stomp_type;
		weight = mci_wlan_weights[stype];
	}

	for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
		btcoex_hw->bt_weight[i] = AR9300_BT_WGHT;
		btcoex_hw->wlan_weight[i] = weight[i];
		if (concur_tx && i) {
			btcoex_hw->wlan_weight[i] &=
				~(0xff << txprio_shift[i-1]);
			btcoex_hw->wlan_weight[i] |=
				(btcoex_hw->tx_prio[stomp_type] <<
				 txprio_shift[i-1]);
		}
	}
	/* Last WLAN weight has to be adjusted wrt tx priority */
	if (concur_tx) {
		btcoex_hw->wlan_weight[i-1] &= ~(0xff << txprio_shift[i-1]);
		btcoex_hw->wlan_weight[i-1] |= (btcoex_hw->tx_prio[stomp_type]
						      << txprio_shift[i-1]);
	}

}
EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);


static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
	u32  val;
	int i;

	/*
	 * Program coex mode and weight registers to
	 * enable coex 3-wire
	 */
	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode);
	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);


	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]);
		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]);
		for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i),
				  btcoex->bt_weight[i]);
	} else
		REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights);


	if (AR_SREV_9271(ah)) {
		val = REG_READ(ah, 0x50040);
		val &= 0xFFFFFEFF;
		REG_WRITE(ah, 0x50040, val);
	}

	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);

	ath9k_hw_cfg_output(ah, btcoex->wlanactive_gpio,
			    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
}

static void ath9k_hw_btcoex_enable_mci(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
	int i;

	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
		REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
			  btcoex->wlan_weight[i]);

	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	btcoex->enabled = true;
}

void ath9k_hw_btcoex_enable(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	switch (ath9k_hw_get_btcoex_scheme(ah)) {
	case ATH_BTCOEX_CFG_NONE:
		return;
	case ATH_BTCOEX_CFG_2WIRE:
		ath9k_hw_btcoex_enable_2wire(ah);
		break;
	case ATH_BTCOEX_CFG_3WIRE:
		if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
			ath9k_hw_btcoex_enable_mci(ah);
			return;
		}
		ath9k_hw_btcoex_enable_3wire(ah);
		break;
	}

	REG_RMW(ah, AR_GPIO_PDPU,
		(0x2 << (btcoex_hw->btactive_gpio * 2)),
		(0x3 << (btcoex_hw->btactive_gpio * 2)));

	ah->btcoex_hw.enabled = true;
}
EXPORT_SYMBOL(ath9k_hw_btcoex_enable);

void ath9k_hw_btcoex_disable(struct ath_hw *ah)
{
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	int i;

	btcoex_hw->enabled = false;
	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
		ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
		for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
			REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
				  btcoex_hw->wlan_weight[i]);
		return;
	}
	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);

	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
			AR_GPIO_OUTPUT_MUX_AS_OUTPUT);

	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
		REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
		REG_WRITE(ah, AR_BT_COEX_MODE2, 0);

		if (AR_SREV_9300_20_OR_LATER(ah)) {
			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
			for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
				REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0);
		} else
			REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);

	}
}
EXPORT_SYMBOL(ath9k_hw_btcoex_disable);

/*
 * Configures appropriate weight based on stomp type.
 */
void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
			      enum ath_stomp_type stomp_type)
{
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		ath9k_hw_btcoex_set_weight(ah, 0, 0, stomp_type);
		return;
	}

	switch (stomp_type) {
	case ATH_BTCOEX_STOMP_ALL:
		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
					   AR_STOMP_ALL_WLAN_WGHT, 0);
		break;
	case ATH_BTCOEX_STOMP_LOW:
		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
					   AR_STOMP_LOW_WLAN_WGHT, 0);
		break;
	case ATH_BTCOEX_STOMP_NONE:
		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
					   AR_STOMP_NONE_WLAN_WGHT, 0);
		break;
	default:
		ath_dbg(ath9k_hw_common(ah), BTCOEX, "Invalid Stomptype\n");
		break;
	}
}
EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);

void ath9k_hw_btcoex_set_concur_txprio(struct ath_hw *ah, u8 *stomp_txprio)
{
	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
	int i;

	for (i = 0; i < ATH_BTCOEX_STOMP_MAX; i++)
		btcoex->tx_prio[i] = stomp_txprio[i];
}
EXPORT_SYMBOL(ath9k_hw_btcoex_set_concur_txprio);
Commit	Line	Data
17d50d1d	1	/*
5b68138e	2	* Copyright (c) 2009-2011 Atheros Communications Inc.
17d50d1d VT	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
ee40fa06	17	#include <linux/export.h>
cfe8cba9	18	#include "hw.h"
17d50d1d	19
8b4fc5ba LR	20	enum ath_bt_mode {
	21	ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
	22	ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
	23	ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
32b1076d	24	ATH_BT_COEX_MODE_DISABLED, /* coexistence disabled */
8b4fc5ba LR	25	};
	26
	27	struct ath_btcoex_config {
	28	u8 bt_time_extend;
	29	bool bt_txstate_extend;
	30	bool bt_txframe_extend;
	31	enum ath_bt_mode bt_mode; /* coexistence mode */
	32	bool bt_quiet_collision;
	33	bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
	34	u8 bt_priority_time;
	35	u8 bt_first_slot_time;
	36	bool bt_hold_rx_clear;
	37	};
1773912b	38
54f10b05 RM	39	static const u32 ar9003_wlan_weights[ATH_BTCOEX_STOMP_MAX]
	40	[AR9300_NUM_WLAN_WEIGHTS] = {
	41	{ 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0 }, /* STOMP_ALL */
	42	{ 0x88888880, 0x88888880, 0x88888880, 0x88888880 }, /* STOMP_LOW */
	43	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */
	44	};
1773912b	45
5160b46f SM	46	static const u32 mci_wlan_weights[ATH_BTCOEX_STOMP_MAX]
5160b46f SM	47	[AR9300_NUM_WLAN_WEIGHTS] = {
8227bf45 RM	48	{ 0x01017d01, 0x41414101, 0x41414101, 0x41414141 }, /* STOMP_ALL */
	49	{ 0x01017d01, 0x3b3b3b01, 0x3b3b3b01, 0x3b3b3b3b }, /* STOMP_LOW */
	50	{ 0x01017d01, 0x01010101, 0x01010101, 0x01010101 }, /* STOMP_NONE */
	51	{ 0x01017d01, 0x013b0101, 0x3b3b0101, 0x3b3b013b }, /* STOMP_LOW_FTP */
2884561a	52	{ 0xffffff01, 0xffffffff, 0xffffff01, 0xffffffff }, /* STOMP_AUDIO */
8227bf45 RM	53	};
8227bf45 RM	54
766ec4a9	55	void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
af03abec	56	{
766ec4a9	57	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
8b4fc5ba LR	58	const struct ath_btcoex_config ath_bt_config = {
	59	.bt_time_extend = 0,
	60	.bt_txstate_extend = true,
	61	.bt_txframe_extend = true,
	62	.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
	63	.bt_quiet_collision = true,
	64	.bt_rxclear_polarity = true,
	65	.bt_priority_time = 2,
	66	.bt_first_slot_time = 5,
	67	.bt_hold_rx_clear = true,
	68	};
a6ef530f VN	69	bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
	70
	71	if (AR_SREV_9300_20_OR_LATER(ah))
	72	rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;
1773912b	73
766ec4a9 LR	74	btcoex_hw->bt_coex_mode =
766ec4a9 LR	75	(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) \|
1773912b VT	76	SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) \|
	77	SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) \|
	78	SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) \|
	79	SM(ath_bt_config.bt_mode, AR_BT_MODE) \|
	80	SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) \|
a6ef530f	81	SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) \|
1773912b VT	82	SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) \|
	83	SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) \|
	84	SM(qnum, AR_BT_QCU_THRESH);
	85
766ec4a9	86	btcoex_hw->bt_coex_mode2 =
1773912b VT	87	SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) \|
	88	SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) \|
	89	AR_BT_DISABLE_BT_ANT;
1773912b	90	}
7322fd19	91	EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
1773912b	92
d68475de SM	93	void ath9k_hw_btcoex_init_scheme(struct ath_hw *ah)
	94	{
	95	struct ath_common *common = ath9k_hw_common(ah);
	96	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
	97
	98	/*
	99	* Check if BTCOEX is globally disabled.
	100	*/
	101	if (!common->btcoex_enabled) {
	102	btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
	103	return;
	104	}
	105
0466e254	106	if (AR_SREV_9300_20_OR_LATER(ah)) {
d68475de SM	107	btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
	108	btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
	109	btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
	110	btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
	111	} else if (AR_SREV_9280_20_OR_LATER(ah)) {
	112	btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
	113	btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
	114
	115	if (AR_SREV_9285(ah)) {
	116	btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
	117	btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9285;
	118	} else {
	119	btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
	120	}
	121	}
	122	}
	123	EXPORT_SYMBOL(ath9k_hw_btcoex_init_scheme);
	124
75d7839f	125	void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
17d50d1d	126	{
766ec4a9	127	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1773912b	128
7a2f0f58 LR	129	/* connect bt_active to baseband */
	130	REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
	131	(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF \|
	132	AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
1773912b	133
7a2f0f58 LR	134	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
7a2f0f58 LR	135	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
1773912b	136
7a2f0f58 LR	137	/* Set input mux for bt_active to gpio pin */
	138	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
	139	AR_GPIO_INPUT_MUX1_BT_ACTIVE,
766ec4a9	140	btcoex_hw->btactive_gpio);
f14462c6	141
7a2f0f58	142	/* Configure the desired gpio port for input */
766ec4a9	143	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
7a2f0f58	144	}
7322fd19	145	EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
7a2f0f58	146
75d7839f	147	void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
7a2f0f58	148	{
766ec4a9	149	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
17d50d1d	150
7a2f0f58 LR	151	/* btcoex 3-wire */
	152	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
	153	(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB \|
	154	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
17d50d1d	155
7a2f0f58 LR	156	/* Set input mux for bt_prority_async and
	157	* bt_active_async to GPIO pins */
	158	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
	159	AR_GPIO_INPUT_MUX1_BT_ACTIVE,
766ec4a9	160	btcoex_hw->btactive_gpio);
17d50d1d	161
7a2f0f58 LR	162	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
7a2f0f58 LR	163	AR_GPIO_INPUT_MUX1_BT_PRIORITY,
766ec4a9	164	btcoex_hw->btpriority_gpio);
1773912b	165
7a2f0f58 LR	166	/* Configure the desired GPIO ports for input */
7a2f0f58 LR	167
766ec4a9 LR	168	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
766ec4a9 LR	169	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
7a2f0f58	170	}
7322fd19	171	EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
7a2f0f58	172
d3c83ac1 SM	173	void ath9k_hw_btcoex_init_mci(struct ath_hw *ah)
	174	{
	175	ah->btcoex_hw.mci.ready = false;
	176	ah->btcoex_hw.mci.bt_state = 0;
	177	ah->btcoex_hw.mci.bt_ver_major = 3;
	178	ah->btcoex_hw.mci.bt_ver_minor = 0;
	179	ah->btcoex_hw.mci.bt_version_known = false;
	180	ah->btcoex_hw.mci.update_2g5g = true;
	181	ah->btcoex_hw.mci.is_2g = true;
	182	ah->btcoex_hw.mci.wlan_channels_update = false;
	183	ah->btcoex_hw.mci.wlan_channels[0] = 0x00000000;
	184	ah->btcoex_hw.mci.wlan_channels[1] = 0xffffffff;
	185	ah->btcoex_hw.mci.wlan_channels[2] = 0xffffffff;
	186	ah->btcoex_hw.mci.wlan_channels[3] = 0x7fffffff;
	187	ah->btcoex_hw.mci.query_bt = true;
	188	ah->btcoex_hw.mci.unhalt_bt_gpm = true;
	189	ah->btcoex_hw.mci.halted_bt_gpm = false;
	190	ah->btcoex_hw.mci.need_flush_btinfo = false;
	191	ah->btcoex_hw.mci.wlan_cal_seq = 0;
	192	ah->btcoex_hw.mci.wlan_cal_done = 0;
3c5c9d04	193	ah->btcoex_hw.mci.config = (AR_SREV_9462(ah)) ? 0x2201 : 0xa4c1;
d3c83ac1 SM	194	}
	195	EXPORT_SYMBOL(ath9k_hw_btcoex_init_mci);
	196
bc74bf8f LR	197	static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
bc74bf8f LR	198	{
766ec4a9	199	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
bc74bf8f LR	200
bc74bf8f LR	201	/* Configure the desired GPIO port for TX_FRAME output */
766ec4a9	202	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
bc74bf8f LR	203	AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
	204	}
	205
5160b46f SM	206	/*
	207	* For AR9002, bt_weight/wlan_weight are used.
	208	* For AR9003 and above, stomp_type is used.
	209	*/
5e197292 LR	210	void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
5e197292 LR	211	u32 bt_weight,
5160b46f SM	212	u32 wlan_weight,
5160b46f SM	213	enum ath_stomp_type stomp_type)
5e197292 LR	214	{
5e197292 LR	215	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
db60428b RM	216	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	217	u8 txprio_shift[] = { 24, 16, 16, 0 }; /* tx priority weight */
	218	bool concur_tx = (mci_hw->concur_tx && btcoex_hw->tx_prio[stomp_type]);
	219	const u32 *weight = ar9003_wlan_weights[stomp_type];
	220	int i;
5e197292	221
db60428b	222	if (!AR_SREV_9300_20_OR_LATER(ah)) {
5160b46f SM	223	btcoex_hw->bt_coex_weights =
	224	SM(bt_weight, AR_BTCOEX_BT_WGHT) \|
	225	SM(wlan_weight, AR_BTCOEX_WL_WGHT);
db60428b RM	226	return;
	227	}
	228
	229	if (AR_SREV_9462(ah) \|\| AR_SREV_9565(ah)) {
	230	enum ath_stomp_type stype =
	231	((stomp_type == ATH_BTCOEX_STOMP_LOW) &&
	232	btcoex_hw->mci.stomp_ftp) ?
	233	ATH_BTCOEX_STOMP_LOW_FTP : stomp_type;
	234	weight = mci_wlan_weights[stype];
5160b46f	235	}
db60428b RM	236
	237	for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
	238	btcoex_hw->bt_weight[i] = AR9300_BT_WGHT;
	239	btcoex_hw->wlan_weight[i] = weight[i];
	240	if (concur_tx && i) {
	241	btcoex_hw->wlan_weight[i] &=
	242	~(0xff << txprio_shift[i-1]);
	243	btcoex_hw->wlan_weight[i] \|=
	244	(btcoex_hw->tx_prio[stomp_type] <<
	245	txprio_shift[i-1]);
	246	}
	247	}
	248	/* Last WLAN weight has to be adjusted wrt tx priority */
	249	if (concur_tx) {
	250	btcoex_hw->wlan_weight[i-1] &= ~(0xff << txprio_shift[i-1]);
	251	btcoex_hw->wlan_weight[i-1] \|= (btcoex_hw->tx_prio[stomp_type]
	252	<< txprio_shift[i-1]);
	253	}
	254
5e197292	255	}
7322fd19	256	EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
5e197292	257
a6ef530f	258
bc74bf8f LR	259	static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
bc74bf8f LR	260	{
54f10b05	261	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
21cb9879	262	u32 val;
54f10b05	263	int i;
bc74bf8f LR	264
	265	/*
	266	* Program coex mode and weight registers to
	267	* enable coex 3-wire
	268	*/
54f10b05 RM	269	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode);
54f10b05 RM	270	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
bc74bf8f	271
a6ef530f VN	272
a6ef530f VN	273	if (AR_SREV_9300_20_OR_LATER(ah)) {
54f10b05 RM	274	REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]);
	275	REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]);
	276	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
	277	REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i),
	278	btcoex->bt_weight[i]);
a6ef530f	279	} else
54f10b05	280	REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights);
a6ef530f VN	281
	282
	283
21cb9879 VN	284	if (AR_SREV_9271(ah)) {
	285	val = REG_READ(ah, 0x50040);
	286	val &= 0xFFFFFEFF;
	287	REG_WRITE(ah, 0x50040, val);
	288	}
	289
bc74bf8f LR	290	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	291	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
	292
54f10b05	293	ath9k_hw_cfg_output(ah, btcoex->wlanactive_gpio,
bc74bf8f LR	294	AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
	295	}
	296
8227bf45 RM	297	static void ath9k_hw_btcoex_enable_mci(struct ath_hw *ah)
	298	{
	299	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
	300	int i;
	301
	302	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
	303	REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
	304	btcoex->wlan_weight[i]);
	305
	306	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
	307	btcoex->enabled = true;
	308	}
	309
17d50d1d VT	310	void ath9k_hw_btcoex_enable(struct ath_hw *ah)
17d50d1d VT	311	{
766ec4a9	312	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
f14462c6	313
8a309305	314	switch (ath9k_hw_get_btcoex_scheme(ah)) {
bc74bf8f	315	case ATH_BTCOEX_CFG_NONE:
8a309305	316	return;
bc74bf8f LR	317	case ATH_BTCOEX_CFG_2WIRE:
	318	ath9k_hw_btcoex_enable_2wire(ah);
	319	break;
	320	case ATH_BTCOEX_CFG_3WIRE:
6a73f507	321	if (AR_SREV_9462(ah) \|\| AR_SREV_9565(ah)) {
0466e254 RM	322	ath9k_hw_btcoex_enable_mci(ah);
	323	return;
	324	}
bc74bf8f LR	325	ath9k_hw_btcoex_enable_3wire(ah);
bc74bf8f LR	326	break;
1773912b VT	327	}
	328
	329	REG_RMW(ah, AR_GPIO_PDPU,
766ec4a9 LR	330	(0x2 << (btcoex_hw->btactive_gpio * 2)),
766ec4a9 LR	331	(0x3 << (btcoex_hw->btactive_gpio * 2)));
17d50d1d	332
766ec4a9	333	ah->btcoex_hw.enabled = true;
17d50d1d	334	}
7322fd19	335	EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
17d50d1d VT	336
	337	void ath9k_hw_btcoex_disable(struct ath_hw *ah)
	338	{
766ec4a9	339	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
54f10b05	340	int i;
f14462c6	341
8227bf45	342	btcoex_hw->enabled = false;
6a73f507	343	if (AR_SREV_9462(ah) \|\| AR_SREV_9565(ah)) {
8227bf45 RM	344	ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
	345	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
	346	REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
	347	btcoex_hw->wlan_weight[i]);
0466e254	348	return;
8227bf45	349	}
766ec4a9	350	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
17d50d1d	351
766ec4a9	352	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
17d50d1d VT	353	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
17d50d1d VT	354
766ec4a9	355	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
1773912b	356	REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET \| AR_BT_MODE);
1773912b	357	REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
a6ef530f VN	358
	359	if (AR_SREV_9300_20_OR_LATER(ah)) {
	360	REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
	361	REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
54f10b05 RM	362	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
54f10b05 RM	363	REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0);
a6ef530f VN	364	} else
	365	REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
	366
1773912b	367	}
17d50d1d	368	}
7322fd19	369	EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
978f78bf	370
978f78bf VN	371	/*
	372	* Configures appropriate weight based on stomp type.
	373	*/
	374	void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
	375	enum ath_stomp_type stomp_type)
	376	{
	377	if (AR_SREV_9300_20_OR_LATER(ah)) {
5160b46f	378	ath9k_hw_btcoex_set_weight(ah, 0, 0, stomp_type);
978f78bf VN	379	return;
	380	}
	381
	382	switch (stomp_type) {
	383	case ATH_BTCOEX_STOMP_ALL:
	384	ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
5160b46f	385	AR_STOMP_ALL_WLAN_WGHT, 0);
978f78bf VN	386	break;
	387	case ATH_BTCOEX_STOMP_LOW:
	388	ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
5160b46f	389	AR_STOMP_LOW_WLAN_WGHT, 0);
978f78bf VN	390	break;
	391	case ATH_BTCOEX_STOMP_NONE:
	392	ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
5160b46f	393	AR_STOMP_NONE_WLAN_WGHT, 0);
978f78bf VN	394	break;
978f78bf VN	395	default:
d2182b69	396	ath_dbg(ath9k_hw_common(ah), BTCOEX, "Invalid Stomptype\n");
978f78bf VN	397	break;
978f78bf VN	398	}
978f78bf VN	399	}
978f78bf VN	400	EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);
db60428b RM	401
	402	void ath9k_hw_btcoex_set_concur_txprio(struct ath_hw ah, u8 stomp_txprio)
	403	{
	404	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
	405	int i;
	406
	407	for (i = 0; i < ATH_BTCOEX_STOMP_MAX; i++)
	408	btcoex->tx_prio[i] = stomp_txprio[i];
	409	}
	410	EXPORT_SYMBOL(ath9k_hw_btcoex_set_concur_txprio);