Commit | Line | Data |
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394cf0a1 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
394cf0a1 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef DEBUG_H | |
18 | #define DEBUG_H | |
19 | ||
4d6b228d | 20 | #include "hw.h" |
545750d3 | 21 | #include "rc.h" |
29942bc1 | 22 | #include "dfs_debug.h" |
4d6b228d | 23 | |
fec247c0 S |
24 | struct ath_txq; |
25 | struct ath_buf; | |
26 | ||
a830df07 | 27 | #ifdef CONFIG_ATH9K_DEBUGFS |
fec247c0 | 28 | #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ |
030d6294 | 29 | #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++ |
fec247c0 S |
30 | #else |
31 | #define TX_STAT_INC(q, c) do { } while (0) | |
030d6294 | 32 | #define RESET_STAT_INC(sc, type) do { } while (0) |
fec247c0 S |
33 | #endif |
34 | ||
a830df07 | 35 | #ifdef CONFIG_ATH9K_DEBUGFS |
394cf0a1 S |
36 | |
37 | /** | |
38 | * struct ath_interrupt_stats - Contains statistics about interrupts | |
39 | * @total: Total no. of interrupts generated so far | |
40 | * @rxok: RX with no errors | |
a9616f41 LR |
41 | * @rxlp: RX with low priority RX |
42 | * @rxhp: RX with high priority, uapsd only | |
394cf0a1 S |
43 | * @rxeol: RX with no more RXDESC available |
44 | * @rxorn: RX FIFO overrun | |
45 | * @txok: TX completed at the requested rate | |
46 | * @txurn: TX FIFO underrun | |
47 | * @mib: MIB regs reaching its threshold | |
48 | * @rxphyerr: RX with phy errors | |
49 | * @rx_keycache_miss: RX with key cache misses | |
50 | * @swba: Software Beacon Alert | |
51 | * @bmiss: Beacon Miss | |
52 | * @bnr: Beacon Not Ready | |
53 | * @cst: Carrier Sense TImeout | |
54 | * @gtt: Global TX Timeout | |
55 | * @tim: RX beacon TIM occurrence | |
56 | * @cabend: RX End of CAB traffic | |
57 | * @dtimsync: DTIM sync lossage | |
58 | * @dtim: RX Beacon with DTIM | |
08578b8f | 59 | * @bb_watchdog: Baseband watchdog |
6dde1aab MSS |
60 | * @tsfoor: TSF out of range, indicates that the corrected TSF received |
61 | * from a beacon differs from the PCU's internal TSF by more than a | |
62 | * (programmable) threshold | |
394cf0a1 S |
63 | */ |
64 | struct ath_interrupt_stats { | |
65 | u32 total; | |
66 | u32 rxok; | |
a9616f41 LR |
67 | u32 rxlp; |
68 | u32 rxhp; | |
394cf0a1 S |
69 | u32 rxeol; |
70 | u32 rxorn; | |
71 | u32 txok; | |
72 | u32 txeol; | |
73 | u32 txurn; | |
74 | u32 mib; | |
75 | u32 rxphyerr; | |
76 | u32 rx_keycache_miss; | |
77 | u32 swba; | |
78 | u32 bmiss; | |
79 | u32 bnr; | |
80 | u32 cst; | |
81 | u32 gtt; | |
82 | u32 tim; | |
83 | u32 cabend; | |
84 | u32 dtimsync; | |
85 | u32 dtim; | |
08578b8f | 86 | u32 bb_watchdog; |
6dde1aab | 87 | u32 tsfoor; |
394cf0a1 S |
88 | }; |
89 | ||
fec247c0 S |
90 | /** |
91 | * struct ath_tx_stats - Statistics about TX | |
99c15bf5 BG |
92 | * @tx_pkts_all: No. of total frames transmitted, including ones that |
93 | may have had errors. | |
94 | * @tx_bytes_all: No. of total bytes transmitted, including ones that | |
95 | may have had errors. | |
fec247c0 S |
96 | * @queued: Total MPDUs (non-aggr) queued |
97 | * @completed: Total MPDUs (non-aggr) completed | |
98 | * @a_aggr: Total no. of aggregates queued | |
bda8adda BG |
99 | * @a_queued_hw: Total AMPDUs queued to hardware |
100 | * @a_queued_sw: Total AMPDUs queued to software queues | |
fec247c0 S |
101 | * @a_completed: Total AMPDUs completed |
102 | * @a_retries: No. of AMPDUs retried (SW) | |
103 | * @a_xretries: No. of AMPDUs dropped due to xretries | |
104 | * @fifo_underrun: FIFO underrun occurrences | |
105 | Valid only for: | |
106 | - non-aggregate condition. | |
107 | - first packet of aggregate. | |
108 | * @xtxop: No. of frames filtered because of TXOP limit | |
109 | * @timer_exp: Transmit timer expiry | |
110 | * @desc_cfg_err: Descriptor configuration errors | |
111 | * @data_urn: TX data underrun errors | |
112 | * @delim_urn: TX delimiter underrun errors | |
2dac4fb9 BG |
113 | * @puttxbuf: Number of times hardware was given txbuf to write. |
114 | * @txstart: Number of times hardware was told to start tx. | |
115 | * @txprocdesc: Number of times tx descriptor was processed | |
a5a0bca1 | 116 | * @txfailed: Out-of-memory or other errors in xmit path. |
fec247c0 S |
117 | */ |
118 | struct ath_tx_stats { | |
99c15bf5 BG |
119 | u32 tx_pkts_all; |
120 | u32 tx_bytes_all; | |
fec247c0 S |
121 | u32 queued; |
122 | u32 completed; | |
5a6f78af | 123 | u32 xretries; |
fec247c0 | 124 | u32 a_aggr; |
bda8adda BG |
125 | u32 a_queued_hw; |
126 | u32 a_queued_sw; | |
fec247c0 S |
127 | u32 a_completed; |
128 | u32 a_retries; | |
129 | u32 a_xretries; | |
130 | u32 fifo_underrun; | |
131 | u32 xtxop; | |
132 | u32 timer_exp; | |
133 | u32 desc_cfg_err; | |
134 | u32 data_underrun; | |
135 | u32 delim_underrun; | |
2dac4fb9 BG |
136 | u32 puttxbuf; |
137 | u32 txstart; | |
138 | u32 txprocdesc; | |
a5a0bca1 | 139 | u32 txfailed; |
fec247c0 S |
140 | }; |
141 | ||
15072189 BG |
142 | #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++) |
143 | ||
1395d3f0 S |
144 | /** |
145 | * struct ath_rx_stats - RX Statistics | |
99c15bf5 BG |
146 | * @rx_pkts_all: No. of total frames received, including ones that |
147 | may have had errors. | |
148 | * @rx_bytes_all: No. of total bytes received, including ones that | |
149 | may have had errors. | |
1395d3f0 S |
150 | * @crc_err: No. of frames with incorrect CRC value |
151 | * @decrypt_crc_err: No. of frames whose CRC check failed after | |
152 | decryption process completed | |
153 | * @phy_err: No. of frames whose reception failed because the PHY | |
154 | encountered an error | |
155 | * @mic_err: No. of frames with incorrect TKIP MIC verification failure | |
156 | * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections | |
157 | * @post_delim_crc_err: Post-Frame delimiter CRC error detections | |
158 | * @decrypt_busy_err: Decryption interruptions counter | |
159 | * @phy_err_stats: Individual PHY error statistics | |
15072189 BG |
160 | * @rx_len_err: No. of frames discarded due to bad length. |
161 | * @rx_oom_err: No. of frames dropped due to OOM issues. | |
162 | * @rx_rate_err: No. of frames dropped due to rate errors. | |
163 | * @rx_too_many_frags_err: Frames dropped due to too-many-frags received. | |
164 | * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH. | |
165 | * @rx_beacons: No. of beacons received. | |
166 | * @rx_frags: No. of rx-fragements received. | |
1395d3f0 S |
167 | */ |
168 | struct ath_rx_stats { | |
99c15bf5 BG |
169 | u32 rx_pkts_all; |
170 | u32 rx_bytes_all; | |
1395d3f0 S |
171 | u32 crc_err; |
172 | u32 decrypt_crc_err; | |
173 | u32 phy_err; | |
174 | u32 mic_err; | |
175 | u32 pre_delim_crc_err; | |
176 | u32 post_delim_crc_err; | |
177 | u32 decrypt_busy_err; | |
178 | u32 phy_err_stats[ATH9K_PHYERR_MAX]; | |
15072189 BG |
179 | u32 rx_len_err; |
180 | u32 rx_oom_err; | |
181 | u32 rx_rate_err; | |
182 | u32 rx_too_many_frags_err; | |
183 | u32 rx_drop_rxflush; | |
184 | u32 rx_beacons; | |
185 | u32 rx_frags; | |
1395d3f0 S |
186 | }; |
187 | ||
030d6294 FF |
188 | enum ath_reset_type { |
189 | RESET_TYPE_BB_HANG, | |
190 | RESET_TYPE_BB_WATCHDOG, | |
191 | RESET_TYPE_FATAL_INT, | |
192 | RESET_TYPE_TX_ERROR, | |
193 | RESET_TYPE_TX_HANG, | |
194 | RESET_TYPE_PLL_HANG, | |
01e18918 | 195 | RESET_TYPE_MAC_HANG, |
030d6294 FF |
196 | __RESET_TYPE_MAX |
197 | }; | |
198 | ||
394cf0a1 S |
199 | struct ath_stats { |
200 | struct ath_interrupt_stats istats; | |
fec247c0 | 201 | struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; |
1395d3f0 | 202 | struct ath_rx_stats rxstats; |
29942bc1 | 203 | struct ath_dfs_stats dfs_stats; |
030d6294 | 204 | u32 reset[__RESET_TYPE_MAX]; |
394cf0a1 S |
205 | }; |
206 | ||
cf3af748 RM |
207 | #define ATH_DBG_MAX_SAMPLES 10 |
208 | struct ath_dbg_bb_mac_samp { | |
209 | u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS]; | |
210 | u32 pcu_obs, pcu_cr, noise; | |
211 | struct { | |
212 | u64 jiffies; | |
213 | int8_t rssi_ctl0; | |
214 | int8_t rssi_ctl1; | |
215 | int8_t rssi_ctl2; | |
216 | int8_t rssi_ext0; | |
217 | int8_t rssi_ext1; | |
218 | int8_t rssi_ext2; | |
219 | int8_t rssi; | |
220 | bool isok; | |
221 | u8 rts_fail_cnt; | |
222 | u8 data_fail_cnt; | |
223 | u8 rateindex; | |
224 | u8 qid; | |
225 | u8 tid; | |
12932180 MSS |
226 | u32 ba_low; |
227 | u32 ba_high; | |
cf3af748 RM |
228 | } ts[ATH_DBG_MAX_SAMPLES]; |
229 | struct { | |
230 | u64 jiffies; | |
231 | int8_t rssi_ctl0; | |
232 | int8_t rssi_ctl1; | |
233 | int8_t rssi_ctl2; | |
234 | int8_t rssi_ext0; | |
235 | int8_t rssi_ext1; | |
236 | int8_t rssi_ext2; | |
237 | int8_t rssi; | |
238 | bool is_mybeacon; | |
239 | u8 antenna; | |
240 | u8 rate; | |
241 | } rs[ATH_DBG_MAX_SAMPLES]; | |
242 | struct ath_cycle_counters cc; | |
243 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; | |
244 | }; | |
245 | ||
394cf0a1 | 246 | struct ath9k_debug { |
394cf0a1 | 247 | struct dentry *debugfs_phy; |
9bff0bc4 | 248 | u32 regidx; |
394cf0a1 | 249 | struct ath_stats stats; |
5baec742 | 250 | #ifdef CONFIG_ATH9K_MAC_DEBUG |
cf3af748 RM |
251 | spinlock_t samp_lock; |
252 | struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES]; | |
253 | u8 sampidx; | |
254 | u8 tsidx; | |
255 | u8 rsidx; | |
5baec742 | 256 | #endif |
394cf0a1 S |
257 | }; |
258 | ||
4d6b228d | 259 | int ath9k_init_debug(struct ath_hw *ah); |
4d6b228d | 260 | |
394cf0a1 | 261 | void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); |
066dae93 | 262 | void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, |
55797b1a FF |
263 | struct ath_tx_status *ts, struct ath_txq *txq, |
264 | unsigned int flags); | |
8e6f5aa2 | 265 | void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); |
394cf0a1 S |
266 | |
267 | #else | |
268 | ||
15072189 BG |
269 | #define RX_STAT_INC(c) /* NOP */ |
270 | ||
4d6b228d | 271 | static inline int ath9k_init_debug(struct ath_hw *ah) |
394cf0a1 S |
272 | { |
273 | return 0; | |
274 | } | |
275 | ||
394cf0a1 S |
276 | static inline void ath_debug_stat_interrupt(struct ath_softc *sc, |
277 | enum ath9k_int status) | |
278 | { | |
279 | } | |
280 | ||
fec247c0 | 281 | static inline void ath_debug_stat_tx(struct ath_softc *sc, |
32ffb1f4 | 282 | struct ath_buf *bf, |
3bf63e59 | 283 | struct ath_tx_status *ts, |
55797b1a FF |
284 | struct ath_txq *txq, |
285 | unsigned int flags) | |
fec247c0 S |
286 | { |
287 | } | |
288 | ||
1395d3f0 | 289 | static inline void ath_debug_stat_rx(struct ath_softc *sc, |
32ffb1f4 | 290 | struct ath_rx_status *rs) |
1395d3f0 S |
291 | { |
292 | } | |
293 | ||
a830df07 | 294 | #endif /* CONFIG_ATH9K_DEBUGFS */ |
394cf0a1 | 295 | |
5baec742 FF |
296 | #ifdef CONFIG_ATH9K_MAC_DEBUG |
297 | ||
298 | void ath9k_debug_samp_bb_mac(struct ath_softc *sc); | |
299 | ||
300 | #else | |
301 | ||
302 | static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc) | |
303 | { | |
304 | } | |
305 | ||
306 | #endif | |
307 | ||
308 | ||
394cf0a1 | 309 | #endif /* DEBUG_H */ |