[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / debug.h

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef DEBUG_H
#define DEBUG_H

#include "hw.h"
#include "rc.h"

struct ath_txq;
struct ath_buf;

#ifdef CONFIG_ATH9K_DEBUGFS
#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
#else
#define TX_STAT_INC(q, c) do { } while (0)
#endif

#ifdef CONFIG_ATH9K_DEBUGFS

/**
 * struct ath_interrupt_stats - Contains statistics about interrupts
 * @total: Total no. of interrupts generated so far
 * @rxok: RX with no errors
 * @rxlp: RX with low priority RX
 * @rxhp: RX with high priority, uapsd only
 * @rxeol: RX with no more RXDESC available
 * @rxorn: RX FIFO overrun
 * @txok: TX completed at the requested rate
 * @txurn: TX FIFO underrun
 * @mib: MIB regs reaching its threshold
 * @rxphyerr: RX with phy errors
 * @rx_keycache_miss: RX with key cache misses
 * @swba: Software Beacon Alert
 * @bmiss: Beacon Miss
 * @bnr: Beacon Not Ready
 * @cst: Carrier Sense TImeout
 * @gtt: Global TX Timeout
 * @tim: RX beacon TIM occurrence
 * @cabend: RX End of CAB traffic
 * @dtimsync: DTIM sync lossage
 * @dtim: RX Beacon with DTIM
 * @bb_watchdog: Baseband watchdog
 * @tsfoor: TSF out of range, indicates that the corrected TSF received
 * from a beacon differs from the PCU's internal TSF by more than a
 * (programmable) threshold
 */
struct ath_interrupt_stats {
	u32 total;
	u32 rxok;
	u32 rxlp;
	u32 rxhp;
	u32 rxeol;
	u32 rxorn;
	u32 txok;
	u32 txeol;
	u32 txurn;
	u32 mib;
	u32 rxphyerr;
	u32 rx_keycache_miss;
	u32 swba;
	u32 bmiss;
	u32 bnr;
	u32 cst;
	u32 gtt;
	u32 tim;
	u32 cabend;
	u32 dtimsync;
	u32 dtim;
	u32 bb_watchdog;
	u32 tsfoor;
};

/**
 * struct ath_tx_stats - Statistics about TX
 * @tx_pkts_all:  No. of total frames transmitted, including ones that
	may have had errors.
 * @tx_bytes_all:  No. of total bytes transmitted, including ones that
	may have had errors.
 * @queued: Total MPDUs (non-aggr) queued
 * @completed: Total MPDUs (non-aggr) completed
 * @a_aggr: Total no. of aggregates queued
 * @a_queued_hw: Total AMPDUs queued to hardware
 * @a_queued_sw: Total AMPDUs queued to software queues
 * @a_completed: Total AMPDUs completed
 * @a_retries: No. of AMPDUs retried (SW)
 * @a_xretries: No. of AMPDUs dropped due to xretries
 * @fifo_underrun: FIFO underrun occurrences
	Valid only for:
		- non-aggregate condition.
		- first packet of aggregate.
 * @xtxop: No. of frames filtered because of TXOP limit
 * @timer_exp: Transmit timer expiry
 * @desc_cfg_err: Descriptor configuration errors
 * @data_urn: TX data underrun errors
 * @delim_urn: TX delimiter underrun errors
 * @puttxbuf: Number of times hardware was given txbuf to write.
 * @txstart:  Number of times hardware was told to start tx.
 * @txprocdesc:  Number of times tx descriptor was processed
 */
struct ath_tx_stats {
	u32 tx_pkts_all;
	u32 tx_bytes_all;
	u32 queued;
	u32 completed;
	u32 xretries;
	u32 a_aggr;
	u32 a_queued_hw;
	u32 a_queued_sw;
	u32 a_completed;
	u32 a_retries;
	u32 a_xretries;
	u32 fifo_underrun;
	u32 xtxop;
	u32 timer_exp;
	u32 desc_cfg_err;
	u32 data_underrun;
	u32 delim_underrun;
	u32 puttxbuf;
	u32 txstart;
	u32 txprocdesc;
};

/**
 * struct ath_rx_stats - RX Statistics
 * @rx_pkts_all:  No. of total frames received, including ones that
	may have had errors.
 * @rx_bytes_all:  No. of total bytes received, including ones that
	may have had errors.
 * @crc_err: No. of frames with incorrect CRC value
 * @decrypt_crc_err: No. of frames whose CRC check failed after
	decryption process completed
 * @phy_err: No. of frames whose reception failed because the PHY
	encountered an error
 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 * @decrypt_busy_err: Decryption interruptions counter
 * @phy_err_stats: Individual PHY error statistics
 */
struct ath_rx_stats {
	u32 rx_pkts_all;
	u32 rx_bytes_all;
	u32 crc_err;
	u32 decrypt_crc_err;
	u32 phy_err;
	u32 mic_err;
	u32 pre_delim_crc_err;
	u32 post_delim_crc_err;
	u32 decrypt_busy_err;
	u32 phy_err_stats[ATH9K_PHYERR_MAX];
	int8_t rs_rssi_ctl0;
	int8_t rs_rssi_ctl1;
	int8_t rs_rssi_ctl2;
	int8_t rs_rssi_ext0;
	int8_t rs_rssi_ext1;
	int8_t rs_rssi_ext2;
	u8 rs_antenna;
};

struct ath_stats {
	struct ath_interrupt_stats istats;
	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
	struct ath_rx_stats rxstats;
};

#define ATH_DBG_MAX_SAMPLES	10
struct ath_dbg_bb_mac_samp {
	u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
	u32 pcu_obs, pcu_cr, noise;
	struct {
		u64 jiffies;
		int8_t rssi_ctl0;
		int8_t rssi_ctl1;
		int8_t rssi_ctl2;
		int8_t rssi_ext0;
		int8_t rssi_ext1;
		int8_t rssi_ext2;
		int8_t rssi;
		bool isok;
		u8 rts_fail_cnt;
		u8 data_fail_cnt;
		u8 rateindex;
		u8 qid;
		u8 tid;
	} ts[ATH_DBG_MAX_SAMPLES];
	struct {
		u64 jiffies;
		int8_t rssi_ctl0;
		int8_t rssi_ctl1;
		int8_t rssi_ctl2;
		int8_t rssi_ext0;
		int8_t rssi_ext1;
		int8_t rssi_ext2;
		int8_t rssi;
		bool is_mybeacon;
		u8 antenna;
		u8 rate;
	} rs[ATH_DBG_MAX_SAMPLES];
	struct ath_cycle_counters cc;
	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
};

struct ath9k_debug {
	struct dentry *debugfs_phy;
	u32 regidx;
	struct ath_stats stats;
	spinlock_t samp_lock;
	struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
	u8 sampidx;
	u8 tsidx;
	u8 rsidx;
};

int ath9k_init_debug(struct ath_hw *ah);

void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
		       struct ath_tx_status *ts, struct ath_txq *txq);
void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);

#else

static inline int ath9k_init_debug(struct ath_hw *ah)
{
	return 0;
}

static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
{
}

static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
					    enum ath9k_int status)
{
}

static inline void ath_debug_stat_tx(struct ath_softc *sc,
				     struct ath_buf *bf,
				     struct ath_tx_status *ts,
				     struct ath_txq *txq)
{
}

static inline void ath_debug_stat_rx(struct ath_softc *sc,
				     struct ath_rx_status *rs)
{
}

#endif /* CONFIG_ATH9K_DEBUGFS */

#endif /* DEBUG_H */
Commit	Line	Data
394cf0a1	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
394cf0a1 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef DEBUG_H
	18	#define DEBUG_H
	19
4d6b228d	20	#include "hw.h"
545750d3	21	#include "rc.h"
4d6b228d	22
fec247c0 S	23	struct ath_txq;
	24	struct ath_buf;
	25
a830df07	26	#ifdef CONFIG_ATH9K_DEBUGFS
fec247c0 S	27	#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
	28	#else
	29	#define TX_STAT_INC(q, c) do { } while (0)
	30	#endif
	31
a830df07	32	#ifdef CONFIG_ATH9K_DEBUGFS
394cf0a1 S	33
	34	/**
	35	* struct ath_interrupt_stats - Contains statistics about interrupts
	36	* @total: Total no. of interrupts generated so far
	37	* @rxok: RX with no errors
a9616f41 LR	38	* @rxlp: RX with low priority RX
a9616f41 LR	39	* @rxhp: RX with high priority, uapsd only
394cf0a1 S	40	* @rxeol: RX with no more RXDESC available
	41	* @rxorn: RX FIFO overrun
	42	* @txok: TX completed at the requested rate
	43	* @txurn: TX FIFO underrun
	44	* @mib: MIB regs reaching its threshold
	45	* @rxphyerr: RX with phy errors
	46	* @rx_keycache_miss: RX with key cache misses
	47	* @swba: Software Beacon Alert
	48	* @bmiss: Beacon Miss
	49	* @bnr: Beacon Not Ready
	50	* @cst: Carrier Sense TImeout
	51	* @gtt: Global TX Timeout
	52	* @tim: RX beacon TIM occurrence
	53	* @cabend: RX End of CAB traffic
	54	* @dtimsync: DTIM sync lossage
	55	* @dtim: RX Beacon with DTIM
08578b8f	56	* @bb_watchdog: Baseband watchdog
6dde1aab MSS	57	* @tsfoor: TSF out of range, indicates that the corrected TSF received
	58	* from a beacon differs from the PCU's internal TSF by more than a
	59	* (programmable) threshold
394cf0a1 S	60	*/
	61	struct ath_interrupt_stats {
	62	u32 total;
	63	u32 rxok;
a9616f41 LR	64	u32 rxlp;
a9616f41 LR	65	u32 rxhp;
394cf0a1 S	66	u32 rxeol;
	67	u32 rxorn;
	68	u32 txok;
	69	u32 txeol;
	70	u32 txurn;
	71	u32 mib;
	72	u32 rxphyerr;
	73	u32 rx_keycache_miss;
	74	u32 swba;
	75	u32 bmiss;
	76	u32 bnr;
	77	u32 cst;
	78	u32 gtt;
	79	u32 tim;
	80	u32 cabend;
	81	u32 dtimsync;
	82	u32 dtim;
08578b8f	83	u32 bb_watchdog;
6dde1aab	84	u32 tsfoor;
394cf0a1 S	85	};
394cf0a1 S	86
fec247c0 S	87	/**
fec247c0 S	88	* struct ath_tx_stats - Statistics about TX
99c15bf5 BG	89	* @tx_pkts_all: No. of total frames transmitted, including ones that
	90	may have had errors.
	91	* @tx_bytes_all: No. of total bytes transmitted, including ones that
	92	may have had errors.
fec247c0 S	93	* @queued: Total MPDUs (non-aggr) queued
	94	* @completed: Total MPDUs (non-aggr) completed
	95	* @a_aggr: Total no. of aggregates queued
bda8adda BG	96	* @a_queued_hw: Total AMPDUs queued to hardware
bda8adda BG	97	* @a_queued_sw: Total AMPDUs queued to software queues
fec247c0 S	98	* @a_completed: Total AMPDUs completed
	99	* @a_retries: No. of AMPDUs retried (SW)
	100	* @a_xretries: No. of AMPDUs dropped due to xretries
	101	* @fifo_underrun: FIFO underrun occurrences
	102	Valid only for:
	103	- non-aggregate condition.
	104	- first packet of aggregate.
	105	* @xtxop: No. of frames filtered because of TXOP limit
	106	* @timer_exp: Transmit timer expiry
	107	* @desc_cfg_err: Descriptor configuration errors
	108	* @data_urn: TX data underrun errors
	109	* @delim_urn: TX delimiter underrun errors
2dac4fb9 BG	110	* @puttxbuf: Number of times hardware was given txbuf to write.
	111	* @txstart: Number of times hardware was told to start tx.
	112	* @txprocdesc: Number of times tx descriptor was processed
fec247c0 S	113	*/
fec247c0 S	114	struct ath_tx_stats {
99c15bf5 BG	115	u32 tx_pkts_all;
99c15bf5 BG	116	u32 tx_bytes_all;
fec247c0 S	117	u32 queued;
fec247c0 S	118	u32 completed;
5a6f78af	119	u32 xretries;
fec247c0	120	u32 a_aggr;
bda8adda BG	121	u32 a_queued_hw;
bda8adda BG	122	u32 a_queued_sw;
fec247c0 S	123	u32 a_completed;
	124	u32 a_retries;
	125	u32 a_xretries;
	126	u32 fifo_underrun;
	127	u32 xtxop;
	128	u32 timer_exp;
	129	u32 desc_cfg_err;
	130	u32 data_underrun;
	131	u32 delim_underrun;
2dac4fb9 BG	132	u32 puttxbuf;
	133	u32 txstart;
	134	u32 txprocdesc;
fec247c0 S	135	};
fec247c0 S	136
1395d3f0 S	137	/**
1395d3f0 S	138	* struct ath_rx_stats - RX Statistics
99c15bf5 BG	139	* @rx_pkts_all: No. of total frames received, including ones that
	140	may have had errors.
	141	* @rx_bytes_all: No. of total bytes received, including ones that
	142	may have had errors.
1395d3f0 S	143	* @crc_err: No. of frames with incorrect CRC value
	144	* @decrypt_crc_err: No. of frames whose CRC check failed after
	145	decryption process completed
	146	* @phy_err: No. of frames whose reception failed because the PHY
	147	encountered an error
	148	* @mic_err: No. of frames with incorrect TKIP MIC verification failure
	149	* @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
	150	* @post_delim_crc_err: Post-Frame delimiter CRC error detections
	151	* @decrypt_busy_err: Decryption interruptions counter
	152	* @phy_err_stats: Individual PHY error statistics
	153	*/
	154	struct ath_rx_stats {
99c15bf5 BG	155	u32 rx_pkts_all;
99c15bf5 BG	156	u32 rx_bytes_all;
1395d3f0 S	157	u32 crc_err;
	158	u32 decrypt_crc_err;
	159	u32 phy_err;
	160	u32 mic_err;
	161	u32 pre_delim_crc_err;
	162	u32 post_delim_crc_err;
	163	u32 decrypt_busy_err;
	164	u32 phy_err_stats[ATH9K_PHYERR_MAX];
7d755414 SB	165	int8_t rs_rssi_ctl0;
	166	int8_t rs_rssi_ctl1;
	167	int8_t rs_rssi_ctl2;
	168	int8_t rs_rssi_ext0;
	169	int8_t rs_rssi_ext1;
	170	int8_t rs_rssi_ext2;
	171	u8 rs_antenna;
1395d3f0 S	172	};
1395d3f0 S	173
394cf0a1 S	174	struct ath_stats {
394cf0a1 S	175	struct ath_interrupt_stats istats;
fec247c0	176	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
1395d3f0	177	struct ath_rx_stats rxstats;
394cf0a1 S	178	};
394cf0a1 S	179
cf3af748 RM	180	#define ATH_DBG_MAX_SAMPLES 10
	181	struct ath_dbg_bb_mac_samp {
	182	u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
	183	u32 pcu_obs, pcu_cr, noise;
	184	struct {
	185	u64 jiffies;
	186	int8_t rssi_ctl0;
	187	int8_t rssi_ctl1;
	188	int8_t rssi_ctl2;
	189	int8_t rssi_ext0;
	190	int8_t rssi_ext1;
	191	int8_t rssi_ext2;
	192	int8_t rssi;
	193	bool isok;
	194	u8 rts_fail_cnt;
	195	u8 data_fail_cnt;
	196	u8 rateindex;
	197	u8 qid;
	198	u8 tid;
	199	} ts[ATH_DBG_MAX_SAMPLES];
	200	struct {
	201	u64 jiffies;
	202	int8_t rssi_ctl0;
	203	int8_t rssi_ctl1;
	204	int8_t rssi_ctl2;
	205	int8_t rssi_ext0;
	206	int8_t rssi_ext1;
	207	int8_t rssi_ext2;
	208	int8_t rssi;
	209	bool is_mybeacon;
	210	u8 antenna;
	211	u8 rate;
	212	} rs[ATH_DBG_MAX_SAMPLES];
	213	struct ath_cycle_counters cc;
	214	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
	215	};
	216
394cf0a1	217	struct ath9k_debug {
394cf0a1	218	struct dentry *debugfs_phy;
9bff0bc4	219	u32 regidx;
394cf0a1	220	struct ath_stats stats;
cf3af748 RM	221	spinlock_t samp_lock;
	222	struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
	223	u8 sampidx;
	224	u8 tsidx;
	225	u8 rsidx;
394cf0a1 S	226	};
394cf0a1 S	227
4d6b228d	228	int ath9k_init_debug(struct ath_hw *ah);
4d6b228d	229
cf3af748	230	void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
394cf0a1	231	void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
066dae93	232	void ath_debug_stat_tx(struct ath_softc sc, struct ath_buf bf,
5bec3e5a	233	struct ath_tx_status ts, struct ath_txq txq);
8e6f5aa2	234	void ath_debug_stat_rx(struct ath_softc sc, struct ath_rx_status rs);
394cf0a1 S	235
	236	#else
	237
4d6b228d	238	static inline int ath9k_init_debug(struct ath_hw *ah)
394cf0a1 S	239	{
	240	return 0;
	241	}
	242
cf3af748 RM	243	static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
	244	{
	245	}
	246
394cf0a1 S	247	static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
	248	enum ath9k_int status)
	249	{
	250	}
	251
fec247c0	252	static inline void ath_debug_stat_tx(struct ath_softc *sc,
32ffb1f4	253	struct ath_buf *bf,
3bf63e59 FF	254	struct ath_tx_status *ts,
3bf63e59 FF	255	struct ath_txq *txq)
fec247c0 S	256	{
	257	}
	258
1395d3f0	259	static inline void ath_debug_stat_rx(struct ath_softc *sc,
32ffb1f4	260	struct ath_rx_status *rs)
1395d3f0 S	261	{
	262	}
	263
a830df07	264	#endif /* CONFIG_ATH9K_DEBUGFS */
394cf0a1 S	265
394cf0a1 S	266	#endif /* DEBUG_H */