[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / debug.h

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef DEBUG_H
#define DEBUG_H

#include "hw.h"
#include "rc.h"
#include "dfs_debug.h"

struct ath_txq;
struct ath_buf;
struct fft_sample_tlv;

#ifdef CONFIG_ATH9K_DEBUGFS
#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
#define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
#define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_config_cnt[c]++;
#else
#define TX_STAT_INC(q, c) do { } while (0)
#define RESET_STAT_INC(sc, type) do { } while (0)
#define ANT_STAT_INC(i, c) do { } while (0)
#define ANT_LNA_INC(i, c) do { } while (0)
#endif

enum ath_reset_type {
	RESET_TYPE_BB_HANG,
	RESET_TYPE_BB_WATCHDOG,
	RESET_TYPE_FATAL_INT,
	RESET_TYPE_TX_ERROR,
	RESET_TYPE_TX_HANG,
	RESET_TYPE_PLL_HANG,
	RESET_TYPE_MAC_HANG,
	RESET_TYPE_BEACON_STUCK,
	RESET_TYPE_MCI,
	__RESET_TYPE_MAX
};

#ifdef CONFIG_ATH9K_DEBUGFS

/**
 * struct ath_interrupt_stats - Contains statistics about interrupts
 * @total: Total no. of interrupts generated so far
 * @rxok: RX with no errors
 * @rxlp: RX with low priority RX
 * @rxhp: RX with high priority, uapsd only
 * @rxeol: RX with no more RXDESC available
 * @rxorn: RX FIFO overrun
 * @txok: TX completed at the requested rate
 * @txurn: TX FIFO underrun
 * @mib: MIB regs reaching its threshold
 * @rxphyerr: RX with phy errors
 * @rx_keycache_miss: RX with key cache misses
 * @swba: Software Beacon Alert
 * @bmiss: Beacon Miss
 * @bnr: Beacon Not Ready
 * @cst: Carrier Sense TImeout
 * @gtt: Global TX Timeout
 * @tim: RX beacon TIM occurrence
 * @cabend: RX End of CAB traffic
 * @dtimsync: DTIM sync lossage
 * @dtim: RX Beacon with DTIM
 * @bb_watchdog: Baseband watchdog
 * @tsfoor: TSF out of range, indicates that the corrected TSF received
 * from a beacon differs from the PCU's internal TSF by more than a
 * (programmable) threshold
 * @local_timeout: Internal bus timeout.
 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
 * @gen_timer: Generic hardware timer interrupt
 */
struct ath_interrupt_stats {
	u32 total;
	u32 rxok;
	u32 rxlp;
	u32 rxhp;
	u32 rxeol;
	u32 rxorn;
	u32 txok;
	u32 txeol;
	u32 txurn;
	u32 mib;
	u32 rxphyerr;
	u32 rx_keycache_miss;
	u32 swba;
	u32 bmiss;
	u32 bnr;
	u32 cst;
	u32 gtt;
	u32 tim;
	u32 cabend;
	u32 dtimsync;
	u32 dtim;
	u32 bb_watchdog;
	u32 tsfoor;
	u32 mci;
	u32 gen_timer;

	/* Sync-cause stats */
	u32 sync_cause_all;
	u32 sync_rtc_irq;
	u32 sync_mac_irq;
	u32 eeprom_illegal_access;
	u32 apb_timeout;
	u32 pci_mode_conflict;
	u32 host1_fatal;
	u32 host1_perr;
	u32 trcv_fifo_perr;
	u32 radm_cpl_ep;
	u32 radm_cpl_dllp_abort;
	u32 radm_cpl_tlp_abort;
	u32 radm_cpl_ecrc_err;
	u32 radm_cpl_timeout;
	u32 local_timeout;
	u32 pm_access;
	u32 mac_awake;
	u32 mac_asleep;
	u32 mac_sleep_access;
};


/**
 * struct ath_tx_stats - Statistics about TX
 * @tx_pkts_all:  No. of total frames transmitted, including ones that
	may have had errors.
 * @tx_bytes_all:  No. of total bytes transmitted, including ones that
	may have had errors.
 * @queued: Total MPDUs (non-aggr) queued
 * @completed: Total MPDUs (non-aggr) completed
 * @a_aggr: Total no. of aggregates queued
 * @a_queued_hw: Total AMPDUs queued to hardware
 * @a_queued_sw: Total AMPDUs queued to software queues
 * @a_completed: Total AMPDUs completed
 * @a_retries: No. of AMPDUs retried (SW)
 * @a_xretries: No. of AMPDUs dropped due to xretries
 * @txerr_filtered: No. of frames with TXERR_FILT flag set.
 * @fifo_underrun: FIFO underrun occurrences
	Valid only for:
		- non-aggregate condition.
		- first packet of aggregate.
 * @xtxop: No. of frames filtered because of TXOP limit
 * @timer_exp: Transmit timer expiry
 * @desc_cfg_err: Descriptor configuration errors
 * @data_urn: TX data underrun errors
 * @delim_urn: TX delimiter underrun errors
 * @puttxbuf: Number of times hardware was given txbuf to write.
 * @txstart:  Number of times hardware was told to start tx.
 * @txprocdesc:  Number of times tx descriptor was processed
 * @txfailed:  Out-of-memory or other errors in xmit path.
 */
struct ath_tx_stats {
	u32 tx_pkts_all;
	u32 tx_bytes_all;
	u32 queued;
	u32 completed;
	u32 xretries;
	u32 a_aggr;
	u32 a_queued_hw;
	u32 a_queued_sw;
	u32 a_completed;
	u32 a_retries;
	u32 a_xretries;
	u32 txerr_filtered;
	u32 fifo_underrun;
	u32 xtxop;
	u32 timer_exp;
	u32 desc_cfg_err;
	u32 data_underrun;
	u32 delim_underrun;
	u32 puttxbuf;
	u32 txstart;
	u32 txprocdesc;
	u32 txfailed;
};

/*
 * Various utility macros to print TX/Queue counters.
 */
#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
#define TXSTATS sc->debug.stats.txstats
#define PR(str, elem)							\
	do {								\
		len += snprintf(buf + len, size - len,			\
				"%s%13u%11u%10u%10u\n", str,		\
				TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,	\
				TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,	\
				TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,	\
				TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
	} while(0)

#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)

/**
 * struct ath_rx_stats - RX Statistics
 * @rx_pkts_all:  No. of total frames received, including ones that
	may have had errors.
 * @rx_bytes_all:  No. of total bytes received, including ones that
	may have had errors.
 * @crc_err: No. of frames with incorrect CRC value
 * @decrypt_crc_err: No. of frames whose CRC check failed after
	decryption process completed
 * @phy_err: No. of frames whose reception failed because the PHY
	encountered an error
 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 * @decrypt_busy_err: Decryption interruptions counter
 * @phy_err_stats: Individual PHY error statistics
 * @rx_len_err:  No. of frames discarded due to bad length.
 * @rx_oom_err:  No. of frames dropped due to OOM issues.
 * @rx_rate_err:  No. of frames dropped due to rate errors.
 * @rx_too_many_frags_err:  Frames dropped due to too-many-frags received.
 * @rx_beacons:  No. of beacons received.
 * @rx_frags:  No. of rx-fragements received.
 * @rx_spectral: No of spectral packets received.
 */
struct ath_rx_stats {
	u32 rx_pkts_all;
	u32 rx_bytes_all;
	u32 crc_err;
	u32 decrypt_crc_err;
	u32 phy_err;
	u32 mic_err;
	u32 pre_delim_crc_err;
	u32 post_delim_crc_err;
	u32 decrypt_busy_err;
	u32 phy_err_stats[ATH9K_PHYERR_MAX];
	u32 rx_len_err;
	u32 rx_oom_err;
	u32 rx_rate_err;
	u32 rx_too_many_frags_err;
	u32 rx_beacons;
	u32 rx_frags;
	u32 rx_spectral;
};

#define ANT_MAIN 0
#define ANT_ALT  1

struct ath_antenna_stats {
	u32 recv_cnt;
	u32 lna_config_cnt[4];
};

struct ath_stats {
	struct ath_interrupt_stats istats;
	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
	struct ath_rx_stats rxstats;
	struct ath_dfs_stats dfs_stats;
	struct ath_antenna_stats ant_stats[2];
	u32 reset[__RESET_TYPE_MAX];
};

struct ath9k_debug {
	struct dentry *debugfs_phy;
	u32 regidx;
	struct ath_stats stats;
};

int ath9k_init_debug(struct ath_hw *ah);
void ath9k_deinit_debug(struct ath_softc *sc);

void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
		       struct ath_tx_status *ts, struct ath_txq *txq,
		       unsigned int flags);
void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
			    struct ieee80211_vif *vif, int sset);
void ath9k_get_et_stats(struct ieee80211_hw *hw,
			struct ieee80211_vif *vif,
			struct ethtool_stats *stats, u64 *data);
void ath9k_get_et_strings(struct ieee80211_hw *hw,
			  struct ieee80211_vif *vif,
			  u32 sset, u8 *data);
void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
			   struct ieee80211_vif *vif,
			   struct ieee80211_sta *sta,
			   struct dentry *dir);
void ath9k_sta_remove_debugfs(struct ieee80211_hw *hw,
			      struct ieee80211_vif *vif,
			      struct ieee80211_sta *sta,
			      struct dentry *dir);

void ath_debug_send_fft_sample(struct ath_softc *sc,
			       struct fft_sample_tlv *fft_sample);

#else

#define RX_STAT_INC(c) /* NOP */

static inline int ath9k_init_debug(struct ath_hw *ah)
{
	return 0;
}

static inline void ath9k_deinit_debug(struct ath_softc *sc)
{
}

static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
					    enum ath9k_int status)
{
}

static inline void ath_debug_stat_tx(struct ath_softc *sc,
				     struct ath_buf *bf,
				     struct ath_tx_status *ts,
				     struct ath_txq *txq,
				     unsigned int flags)
{
}

static inline void ath_debug_stat_rx(struct ath_softc *sc,
				     struct ath_rx_status *rs)
{
}

#endif /* CONFIG_ATH9K_DEBUGFS */

#endif /* DEBUG_H */
Commit	Line	Data
394cf0a1	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
394cf0a1 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef DEBUG_H
	18	#define DEBUG_H
	19
4d6b228d	20	#include "hw.h"
545750d3	21	#include "rc.h"
29942bc1	22	#include "dfs_debug.h"
4d6b228d	23
fec247c0 S	24	struct ath_txq;
fec247c0 S	25	struct ath_buf;
e93d083f	26	struct fft_sample_tlv;
fec247c0	27
a830df07	28	#ifdef CONFIG_ATH9K_DEBUGFS
fec247c0	29	#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
030d6294	30	#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
3fbaf4c5 SM	31	#define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
3fbaf4c5 SM	32	#define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_config_cnt[c]++;
fec247c0 S	33	#else
fec247c0 S	34	#define TX_STAT_INC(q, c) do { } while (0)
030d6294	35	#define RESET_STAT_INC(sc, type) do { } while (0)
3fbaf4c5 SM	36	#define ANT_STAT_INC(i, c) do { } while (0)
3fbaf4c5 SM	37	#define ANT_LNA_INC(i, c) do { } while (0)
fec247c0 S	38	#endif
fec247c0 S	39
124b979b RM	40	enum ath_reset_type {
	41	RESET_TYPE_BB_HANG,
	42	RESET_TYPE_BB_WATCHDOG,
	43	RESET_TYPE_FATAL_INT,
	44	RESET_TYPE_TX_ERROR,
	45	RESET_TYPE_TX_HANG,
	46	RESET_TYPE_PLL_HANG,
	47	RESET_TYPE_MAC_HANG,
	48	RESET_TYPE_BEACON_STUCK,
b88083bf	49	RESET_TYPE_MCI,
124b979b RM	50	__RESET_TYPE_MAX
	51	};
	52
a830df07	53	#ifdef CONFIG_ATH9K_DEBUGFS
394cf0a1 S	54
	55	/**
	56	* struct ath_interrupt_stats - Contains statistics about interrupts
	57	* @total: Total no. of interrupts generated so far
	58	* @rxok: RX with no errors
a9616f41 LR	59	* @rxlp: RX with low priority RX
a9616f41 LR	60	* @rxhp: RX with high priority, uapsd only
394cf0a1 S	61	* @rxeol: RX with no more RXDESC available
	62	* @rxorn: RX FIFO overrun
	63	* @txok: TX completed at the requested rate
	64	* @txurn: TX FIFO underrun
	65	* @mib: MIB regs reaching its threshold
	66	* @rxphyerr: RX with phy errors
	67	* @rx_keycache_miss: RX with key cache misses
	68	* @swba: Software Beacon Alert
	69	* @bmiss: Beacon Miss
	70	* @bnr: Beacon Not Ready
	71	* @cst: Carrier Sense TImeout
	72	* @gtt: Global TX Timeout
	73	* @tim: RX beacon TIM occurrence
	74	* @cabend: RX End of CAB traffic
	75	* @dtimsync: DTIM sync lossage
	76	* @dtim: RX Beacon with DTIM
08578b8f	77	* @bb_watchdog: Baseband watchdog
6dde1aab MSS	78	* @tsfoor: TSF out of range, indicates that the corrected TSF received
	79	* from a beacon differs from the PCU's internal TSF by more than a
	80	* (programmable) threshold
462e58f2	81	* @local_timeout: Internal bus timeout.
c9e6e980 MSS	82	* @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
c9e6e980 MSS	83	* @gen_timer: Generic hardware timer interrupt
394cf0a1 S	84	*/
	85	struct ath_interrupt_stats {
	86	u32 total;
	87	u32 rxok;
a9616f41 LR	88	u32 rxlp;
a9616f41 LR	89	u32 rxhp;
394cf0a1 S	90	u32 rxeol;
	91	u32 rxorn;
	92	u32 txok;
	93	u32 txeol;
	94	u32 txurn;
	95	u32 mib;
	96	u32 rxphyerr;
	97	u32 rx_keycache_miss;
	98	u32 swba;
	99	u32 bmiss;
	100	u32 bnr;
	101	u32 cst;
	102	u32 gtt;
	103	u32 tim;
	104	u32 cabend;
	105	u32 dtimsync;
	106	u32 dtim;
08578b8f	107	u32 bb_watchdog;
6dde1aab	108	u32 tsfoor;
97ba515a	109	u32 mci;
c9e6e980	110	u32 gen_timer;
462e58f2 BG	111
	112	/* Sync-cause stats */
	113	u32 sync_cause_all;
	114	u32 sync_rtc_irq;
	115	u32 sync_mac_irq;
	116	u32 eeprom_illegal_access;
	117	u32 apb_timeout;
	118	u32 pci_mode_conflict;
	119	u32 host1_fatal;
	120	u32 host1_perr;
	121	u32 trcv_fifo_perr;
	122	u32 radm_cpl_ep;
	123	u32 radm_cpl_dllp_abort;
	124	u32 radm_cpl_tlp_abort;
	125	u32 radm_cpl_ecrc_err;
	126	u32 radm_cpl_timeout;
	127	u32 local_timeout;
	128	u32 pm_access;
	129	u32 mac_awake;
	130	u32 mac_asleep;
	131	u32 mac_sleep_access;
394cf0a1 S	132	};
394cf0a1 S	133
462e58f2	134
fec247c0 S	135	/**
fec247c0 S	136	* struct ath_tx_stats - Statistics about TX
99c15bf5 BG	137	* @tx_pkts_all: No. of total frames transmitted, including ones that
	138	may have had errors.
	139	* @tx_bytes_all: No. of total bytes transmitted, including ones that
	140	may have had errors.
fec247c0 S	141	* @queued: Total MPDUs (non-aggr) queued
	142	* @completed: Total MPDUs (non-aggr) completed
	143	* @a_aggr: Total no. of aggregates queued
bda8adda BG	144	* @a_queued_hw: Total AMPDUs queued to hardware
bda8adda BG	145	* @a_queued_sw: Total AMPDUs queued to software queues
fec247c0 S	146	* @a_completed: Total AMPDUs completed
	147	* @a_retries: No. of AMPDUs retried (SW)
	148	* @a_xretries: No. of AMPDUs dropped due to xretries
4d900389	149	* @txerr_filtered: No. of frames with TXERR_FILT flag set.
fec247c0 S	150	* @fifo_underrun: FIFO underrun occurrences
	151	Valid only for:
	152	- non-aggregate condition.
	153	- first packet of aggregate.
	154	* @xtxop: No. of frames filtered because of TXOP limit
	155	* @timer_exp: Transmit timer expiry
	156	* @desc_cfg_err: Descriptor configuration errors
	157	* @data_urn: TX data underrun errors
	158	* @delim_urn: TX delimiter underrun errors
2dac4fb9 BG	159	* @puttxbuf: Number of times hardware was given txbuf to write.
	160	* @txstart: Number of times hardware was told to start tx.
	161	* @txprocdesc: Number of times tx descriptor was processed
a5a0bca1	162	* @txfailed: Out-of-memory or other errors in xmit path.
fec247c0 S	163	*/
fec247c0 S	164	struct ath_tx_stats {
99c15bf5 BG	165	u32 tx_pkts_all;
99c15bf5 BG	166	u32 tx_bytes_all;
fec247c0 S	167	u32 queued;
fec247c0 S	168	u32 completed;
5a6f78af	169	u32 xretries;
fec247c0	170	u32 a_aggr;
bda8adda BG	171	u32 a_queued_hw;
bda8adda BG	172	u32 a_queued_sw;
fec247c0 S	173	u32 a_completed;
	174	u32 a_retries;
	175	u32 a_xretries;
4d900389	176	u32 txerr_filtered;
fec247c0 S	177	u32 fifo_underrun;
	178	u32 xtxop;
	179	u32 timer_exp;
	180	u32 desc_cfg_err;
	181	u32 data_underrun;
	182	u32 delim_underrun;
2dac4fb9 BG	183	u32 puttxbuf;
	184	u32 txstart;
	185	u32 txprocdesc;
a5a0bca1	186	u32 txfailed;
fec247c0 S	187	};
fec247c0 S	188
78ef731c SM	189	/*
	190	* Various utility macros to print TX/Queue counters.
	191	*/
	192	#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
	193	#define TXSTATS sc->debug.stats.txstats
	194	#define PR(str, elem) \
	195	do { \
	196	len += snprintf(buf + len, size - len, \
	197	"%s%13u%11u%10u%10u\n", str, \
	198	TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem, \
	199	TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem, \
	200	TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem, \
	201	TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
	202	} while(0)
	203
15072189 BG	204	#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
15072189 BG	205
1395d3f0 S	206	/**
1395d3f0 S	207	* struct ath_rx_stats - RX Statistics
99c15bf5 BG	208	* @rx_pkts_all: No. of total frames received, including ones that
	209	may have had errors.
	210	* @rx_bytes_all: No. of total bytes received, including ones that
	211	may have had errors.
1395d3f0 S	212	* @crc_err: No. of frames with incorrect CRC value
	213	* @decrypt_crc_err: No. of frames whose CRC check failed after
	214	decryption process completed
	215	* @phy_err: No. of frames whose reception failed because the PHY
	216	encountered an error
	217	* @mic_err: No. of frames with incorrect TKIP MIC verification failure
	218	* @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
	219	* @post_delim_crc_err: Post-Frame delimiter CRC error detections
	220	* @decrypt_busy_err: Decryption interruptions counter
	221	* @phy_err_stats: Individual PHY error statistics
15072189 BG	222	* @rx_len_err: No. of frames discarded due to bad length.
	223	* @rx_oom_err: No. of frames dropped due to OOM issues.
	224	* @rx_rate_err: No. of frames dropped due to rate errors.
	225	* @rx_too_many_frags_err: Frames dropped due to too-many-frags received.
15072189 BG	226	* @rx_beacons: No. of beacons received.
15072189 BG	227	* @rx_frags: No. of rx-fragements received.
9b99e665	228	* @rx_spectral: No of spectral packets received.
1395d3f0 S	229	*/
1395d3f0 S	230	struct ath_rx_stats {
99c15bf5 BG	231	u32 rx_pkts_all;
99c15bf5 BG	232	u32 rx_bytes_all;
1395d3f0 S	233	u32 crc_err;
	234	u32 decrypt_crc_err;
	235	u32 phy_err;
	236	u32 mic_err;
	237	u32 pre_delim_crc_err;
	238	u32 post_delim_crc_err;
	239	u32 decrypt_busy_err;
	240	u32 phy_err_stats[ATH9K_PHYERR_MAX];
15072189 BG	241	u32 rx_len_err;
	242	u32 rx_oom_err;
	243	u32 rx_rate_err;
	244	u32 rx_too_many_frags_err;
15072189 BG	245	u32 rx_beacons;
15072189 BG	246	u32 rx_frags;
9b99e665	247	u32 rx_spectral;
1395d3f0 S	248	};
1395d3f0 S	249
3fbaf4c5 SM	250	#define ANT_MAIN 0
	251	#define ANT_ALT 1
	252
	253	struct ath_antenna_stats {
	254	u32 recv_cnt;
	255	u32 lna_config_cnt[4];
	256	};
	257
394cf0a1 S	258	struct ath_stats {
394cf0a1 S	259	struct ath_interrupt_stats istats;
4f7dc951	260	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
1395d3f0	261	struct ath_rx_stats rxstats;
29942bc1	262	struct ath_dfs_stats dfs_stats;
3fbaf4c5	263	struct ath_antenna_stats ant_stats[2];
030d6294	264	u32 reset[__RESET_TYPE_MAX];
394cf0a1 S	265	};
	266
	267	struct ath9k_debug {
394cf0a1	268	struct dentry *debugfs_phy;
9bff0bc4	269	u32 regidx;
394cf0a1 S	270	struct ath_stats stats;
	271	};
	272
4d6b228d	273	int ath9k_init_debug(struct ath_hw *ah);
af690092	274	void ath9k_deinit_debug(struct ath_softc *sc);
4d6b228d	275
394cf0a1	276	void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
066dae93	277	void ath_debug_stat_tx(struct ath_softc sc, struct ath_buf bf,
55797b1a FF	278	struct ath_tx_status ts, struct ath_txq txq,
55797b1a FF	279	unsigned int flags);
8e6f5aa2	280	void ath_debug_stat_rx(struct ath_softc sc, struct ath_rx_status rs);
c175db87 SM	281	int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
	282	struct ieee80211_vif *vif, int sset);
	283	void ath9k_get_et_stats(struct ieee80211_hw *hw,
	284	struct ieee80211_vif *vif,
	285	struct ethtool_stats stats, u64 data);
	286	void ath9k_get_et_strings(struct ieee80211_hw *hw,
	287	struct ieee80211_vif *vif,
	288	u32 sset, u8 *data);
a145daf7 SM	289	void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
	290	struct ieee80211_vif *vif,
	291	struct ieee80211_sta *sta,
	292	struct dentry *dir);
	293	void ath9k_sta_remove_debugfs(struct ieee80211_hw *hw,
	294	struct ieee80211_vif *vif,
	295	struct ieee80211_sta *sta,
	296	struct dentry *dir);
e93d083f SW	297
	298	void ath_debug_send_fft_sample(struct ath_softc *sc,
	299	struct fft_sample_tlv *fft_sample);
	300
394cf0a1 S	301	#else
394cf0a1 S	302
15072189 BG	303	#define RX_STAT_INC(c) /* NOP */
15072189 BG	304
4d6b228d	305	static inline int ath9k_init_debug(struct ath_hw *ah)
394cf0a1 S	306	{
	307	return 0;
	308	}
	309
af690092 SM	310	static inline void ath9k_deinit_debug(struct ath_softc *sc)
	311	{
	312	}
	313
394cf0a1 S	314	static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
	315	enum ath9k_int status)
	316	{
	317	}
	318
fec247c0	319	static inline void ath_debug_stat_tx(struct ath_softc *sc,
32ffb1f4	320	struct ath_buf *bf,
3bf63e59	321	struct ath_tx_status *ts,
55797b1a FF	322	struct ath_txq *txq,
55797b1a FF	323	unsigned int flags)
fec247c0 S	324	{
	325	}
	326
1395d3f0	327	static inline void ath_debug_stat_rx(struct ath_softc *sc,
32ffb1f4	328	struct ath_rx_status *rs)
1395d3f0 S	329	{
	330	}
	331
a830df07	332	#endif /* CONFIG_ATH9K_DEBUGFS */
394cf0a1 S	333
394cf0a1 S	334	#endif /* DEBUG_H */