[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / debug.h

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef DEBUG_H
#define DEBUG_H

#include "hw.h"
#include "dfs_debug.h"

struct ath_txq;
struct ath_buf;
struct fft_sample_tlv;

#ifdef CONFIG_ATH9K_DEBUGFS
#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
#define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
#define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++;
#else
#define TX_STAT_INC(q, c) do { } while (0)
#define RX_STAT_INC(c)
#define RESET_STAT_INC(sc, type) do { } while (0)
#define ANT_STAT_INC(i, c) do { } while (0)
#define ANT_LNA_INC(i, c) do { } while (0)
#endif

enum ath_reset_type {
	RESET_TYPE_BB_HANG,
	RESET_TYPE_BB_WATCHDOG,
	RESET_TYPE_FATAL_INT,
	RESET_TYPE_TX_ERROR,
	RESET_TYPE_TX_GTT,
	RESET_TYPE_TX_HANG,
	RESET_TYPE_PLL_HANG,
	RESET_TYPE_MAC_HANG,
	RESET_TYPE_BEACON_STUCK,
	RESET_TYPE_MCI,
	__RESET_TYPE_MAX
};

#ifdef CONFIG_ATH9K_DEBUGFS

/**
 * struct ath_interrupt_stats - Contains statistics about interrupts
 * @total: Total no. of interrupts generated so far
 * @rxok: RX with no errors
 * @rxlp: RX with low priority RX
 * @rxhp: RX with high priority, uapsd only
 * @rxeol: RX with no more RXDESC available
 * @rxorn: RX FIFO overrun
 * @txok: TX completed at the requested rate
 * @txurn: TX FIFO underrun
 * @mib: MIB regs reaching its threshold
 * @rxphyerr: RX with phy errors
 * @rx_keycache_miss: RX with key cache misses
 * @swba: Software Beacon Alert
 * @bmiss: Beacon Miss
 * @bnr: Beacon Not Ready
 * @cst: Carrier Sense TImeout
 * @gtt: Global TX Timeout
 * @tim: RX beacon TIM occurrence
 * @cabend: RX End of CAB traffic
 * @dtimsync: DTIM sync lossage
 * @dtim: RX Beacon with DTIM
 * @bb_watchdog: Baseband watchdog
 * @tsfoor: TSF out of range, indicates that the corrected TSF received
 * from a beacon differs from the PCU's internal TSF by more than a
 * (programmable) threshold
 * @local_timeout: Internal bus timeout.
 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
 * @gen_timer: Generic hardware timer interrupt
 */
struct ath_interrupt_stats {
	u32 total;
	u32 rxok;
	u32 rxlp;
	u32 rxhp;
	u32 rxeol;
	u32 rxorn;
	u32 txok;
	u32 txeol;
	u32 txurn;
	u32 mib;
	u32 rxphyerr;
	u32 rx_keycache_miss;
	u32 swba;
	u32 bmiss;
	u32 bnr;
	u32 cst;
	u32 gtt;
	u32 tim;
	u32 cabend;
	u32 dtimsync;
	u32 dtim;
	u32 bb_watchdog;
	u32 tsfoor;
	u32 mci;
	u32 gen_timer;

	/* Sync-cause stats */
	u32 sync_cause_all;
	u32 sync_rtc_irq;
	u32 sync_mac_irq;
	u32 eeprom_illegal_access;
	u32 apb_timeout;
	u32 pci_mode_conflict;
	u32 host1_fatal;
	u32 host1_perr;
	u32 trcv_fifo_perr;
	u32 radm_cpl_ep;
	u32 radm_cpl_dllp_abort;
	u32 radm_cpl_tlp_abort;
	u32 radm_cpl_ecrc_err;
	u32 radm_cpl_timeout;
	u32 local_timeout;
	u32 pm_access;
	u32 mac_awake;
	u32 mac_asleep;
	u32 mac_sleep_access;
};


/**
 * struct ath_tx_stats - Statistics about TX
 * @tx_pkts_all:  No. of total frames transmitted, including ones that
	may have had errors.
 * @tx_bytes_all:  No. of total bytes transmitted, including ones that
	may have had errors.
 * @queued: Total MPDUs (non-aggr) queued
 * @completed: Total MPDUs (non-aggr) completed
 * @a_aggr: Total no. of aggregates queued
 * @a_queued_hw: Total AMPDUs queued to hardware
 * @a_queued_sw: Total AMPDUs queued to software queues
 * @a_completed: Total AMPDUs completed
 * @a_retries: No. of AMPDUs retried (SW)
 * @a_xretries: No. of AMPDUs dropped due to xretries
 * @txerr_filtered: No. of frames with TXERR_FILT flag set.
 * @fifo_underrun: FIFO underrun occurrences
	Valid only for:
		- non-aggregate condition.
		- first packet of aggregate.
 * @xtxop: No. of frames filtered because of TXOP limit
 * @timer_exp: Transmit timer expiry
 * @desc_cfg_err: Descriptor configuration errors
 * @data_urn: TX data underrun errors
 * @delim_urn: TX delimiter underrun errors
 * @puttxbuf: Number of times hardware was given txbuf to write.
 * @txstart:  Number of times hardware was told to start tx.
 * @txprocdesc:  Number of times tx descriptor was processed
 * @txfailed:  Out-of-memory or other errors in xmit path.
 */
struct ath_tx_stats {
	u32 tx_pkts_all;
	u32 tx_bytes_all;
	u32 queued;
	u32 completed;
	u32 xretries;
	u32 a_aggr;
	u32 a_queued_hw;
	u32 a_queued_sw;
	u32 a_completed;
	u32 a_retries;
	u32 a_xretries;
	u32 txerr_filtered;
	u32 fifo_underrun;
	u32 xtxop;
	u32 timer_exp;
	u32 desc_cfg_err;
	u32 data_underrun;
	u32 delim_underrun;
	u32 puttxbuf;
	u32 txstart;
	u32 txprocdesc;
	u32 txfailed;
};

/*
 * Various utility macros to print TX/Queue counters.
 */
#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
#define TXSTATS sc->debug.stats.txstats
#define PR(str, elem)							\
	do {								\
		len += scnprintf(buf + len, size - len,			\
				 "%s%13u%11u%10u%10u\n", str,		\
				 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
				 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
				 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
				 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
	} while(0)

struct ath_rx_rate_stats {
	struct {
		u32 ht20_cnt;
		u32 ht40_cnt;
		u32 sgi_cnt;
		u32 lgi_cnt;
	} ht_stats[24];

	struct {
		u32 ofdm_cnt;
	} ofdm_stats[8];

	struct {
		u32 cck_lp_cnt;
		u32 cck_sp_cnt;
	} cck_stats[4];
};

/**
 * struct ath_rx_stats - RX Statistics
 * @rx_pkts_all:  No. of total frames received, including ones that
	may have had errors.
 * @rx_bytes_all:  No. of total bytes received, including ones that
	may have had errors.
 * @crc_err: No. of frames with incorrect CRC value
 * @decrypt_crc_err: No. of frames whose CRC check failed after
	decryption process completed
 * @phy_err: No. of frames whose reception failed because the PHY
	encountered an error
 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 * @decrypt_busy_err: Decryption interruptions counter
 * @phy_err_stats: Individual PHY error statistics
 * @rx_len_err:  No. of frames discarded due to bad length.
 * @rx_oom_err:  No. of frames dropped due to OOM issues.
 * @rx_rate_err:  No. of frames dropped due to rate errors.
 * @rx_too_many_frags_err:  Frames dropped due to too-many-frags received.
 * @rx_beacons:  No. of beacons received.
 * @rx_frags:  No. of rx-fragements received.
 * @rx_spectral: No of spectral packets received.
 */
struct ath_rx_stats {
	u32 rx_pkts_all;
	u32 rx_bytes_all;
	u32 crc_err;
	u32 decrypt_crc_err;
	u32 phy_err;
	u32 mic_err;
	u32 pre_delim_crc_err;
	u32 post_delim_crc_err;
	u32 decrypt_busy_err;
	u32 phy_err_stats[ATH9K_PHYERR_MAX];
	u32 rx_len_err;
	u32 rx_oom_err;
	u32 rx_rate_err;
	u32 rx_too_many_frags_err;
	u32 rx_beacons;
	u32 rx_frags;
	u32 rx_spectral;
};

#define ANT_MAIN 0
#define ANT_ALT  1

struct ath_antenna_stats {
	u32 recv_cnt;
	u32 rssi_avg;
	u32 lna_recv_cnt[4];
	u32 lna_attempt_cnt[4];
};

struct ath_stats {
	struct ath_interrupt_stats istats;
	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
	struct ath_rx_stats rxstats;
	struct ath_dfs_stats dfs_stats;
	struct ath_antenna_stats ant_stats[2];
	u32 reset[__RESET_TYPE_MAX];
};

struct ath9k_debug {
	struct dentry *debugfs_phy;
	u32 regidx;
	struct ath_stats stats;
};

int ath9k_init_debug(struct ath_hw *ah);
void ath9k_deinit_debug(struct ath_softc *sc);

void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
		       struct ath_tx_status *ts, struct ath_txq *txq,
		       unsigned int flags);
void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
			    struct ieee80211_vif *vif, int sset);
void ath9k_get_et_stats(struct ieee80211_hw *hw,
			struct ieee80211_vif *vif,
			struct ethtool_stats *stats, u64 *data);
void ath9k_get_et_strings(struct ieee80211_hw *hw,
			  struct ieee80211_vif *vif,
			  u32 sset, u8 *data);
void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
			   struct ieee80211_vif *vif,
			   struct ieee80211_sta *sta,
			   struct dentry *dir);
void ath9k_debug_stat_ant(struct ath_softc *sc,
			  struct ath_hw_antcomb_conf *div_ant_conf,
			  int main_rssi_avg, int alt_rssi_avg);
void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);

#else

static inline int ath9k_init_debug(struct ath_hw *ah)
{
	return 0;
}

static inline void ath9k_deinit_debug(struct ath_softc *sc)
{
}
static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
					    enum ath9k_int status)
{
}
static inline void ath_debug_stat_tx(struct ath_softc *sc,
				     struct ath_buf *bf,
				     struct ath_tx_status *ts,
				     struct ath_txq *txq,
				     unsigned int flags)
{
}
static inline void ath_debug_stat_rx(struct ath_softc *sc,
				     struct ath_rx_status *rs)
{
}
static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
					struct ath_hw_antcomb_conf *div_ant_conf,
					int main_rssi_avg, int alt_rssi_avg)
{

}

static inline void
ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
{
}

#endif /* CONFIG_ATH9K_DEBUGFS */

#ifdef CONFIG_ATH9K_STATION_STATISTICS
void ath_debug_rate_stats(struct ath_softc *sc,
			  struct ath_rx_status *rs,
			  struct sk_buff *skb);
#else
static inline void ath_debug_rate_stats(struct ath_softc *sc,
					struct ath_rx_status *rs,
					struct sk_buff *skb)
{
}
#endif /* CONFIG_ATH9K_STATION_STATISTICS */

#endif /* DEBUG_H */
Commit	Line	Data
394cf0a1	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
394cf0a1 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef DEBUG_H
	18	#define DEBUG_H
	19
4d6b228d	20	#include "hw.h"
29942bc1	21	#include "dfs_debug.h"
4d6b228d	22
fec247c0 S	23	struct ath_txq;
fec247c0 S	24	struct ath_buf;
e93d083f	25	struct fft_sample_tlv;
fec247c0	26
a830df07	27	#ifdef CONFIG_ATH9K_DEBUGFS
fec247c0	28	#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
350e2dcb	29	#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
030d6294	30	#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
3fbaf4c5	31	#define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
e3d52914	32	#define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++;
fec247c0 S	33	#else
fec247c0 S	34	#define TX_STAT_INC(q, c) do { } while (0)
350e2dcb	35	#define RX_STAT_INC(c)
030d6294	36	#define RESET_STAT_INC(sc, type) do { } while (0)
3fbaf4c5 SM	37	#define ANT_STAT_INC(i, c) do { } while (0)
3fbaf4c5 SM	38	#define ANT_LNA_INC(i, c) do { } while (0)
fec247c0 S	39	#endif
fec247c0 S	40
124b979b RM	41	enum ath_reset_type {
	42	RESET_TYPE_BB_HANG,
	43	RESET_TYPE_BB_WATCHDOG,
	44	RESET_TYPE_FATAL_INT,
	45	RESET_TYPE_TX_ERROR,
071aa9a8	46	RESET_TYPE_TX_GTT,
124b979b RM	47	RESET_TYPE_TX_HANG,
	48	RESET_TYPE_PLL_HANG,
	49	RESET_TYPE_MAC_HANG,
	50	RESET_TYPE_BEACON_STUCK,
b88083bf	51	RESET_TYPE_MCI,
124b979b RM	52	__RESET_TYPE_MAX
	53	};
	54
a830df07	55	#ifdef CONFIG_ATH9K_DEBUGFS
394cf0a1 S	56
	57	/**
	58	* struct ath_interrupt_stats - Contains statistics about interrupts
	59	* @total: Total no. of interrupts generated so far
	60	* @rxok: RX with no errors
a9616f41 LR	61	* @rxlp: RX with low priority RX
a9616f41 LR	62	* @rxhp: RX with high priority, uapsd only
394cf0a1 S	63	* @rxeol: RX with no more RXDESC available
	64	* @rxorn: RX FIFO overrun
	65	* @txok: TX completed at the requested rate
	66	* @txurn: TX FIFO underrun
	67	* @mib: MIB regs reaching its threshold
	68	* @rxphyerr: RX with phy errors
	69	* @rx_keycache_miss: RX with key cache misses
	70	* @swba: Software Beacon Alert
	71	* @bmiss: Beacon Miss
	72	* @bnr: Beacon Not Ready
	73	* @cst: Carrier Sense TImeout
	74	* @gtt: Global TX Timeout
	75	* @tim: RX beacon TIM occurrence
	76	* @cabend: RX End of CAB traffic
	77	* @dtimsync: DTIM sync lossage
	78	* @dtim: RX Beacon with DTIM
08578b8f	79	* @bb_watchdog: Baseband watchdog
6dde1aab MSS	80	* @tsfoor: TSF out of range, indicates that the corrected TSF received
	81	* from a beacon differs from the PCU's internal TSF by more than a
	82	* (programmable) threshold
462e58f2	83	* @local_timeout: Internal bus timeout.
c9e6e980 MSS	84	* @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
c9e6e980 MSS	85	* @gen_timer: Generic hardware timer interrupt
394cf0a1 S	86	*/
	87	struct ath_interrupt_stats {
	88	u32 total;
	89	u32 rxok;
a9616f41 LR	90	u32 rxlp;
a9616f41 LR	91	u32 rxhp;
394cf0a1 S	92	u32 rxeol;
	93	u32 rxorn;
	94	u32 txok;
	95	u32 txeol;
	96	u32 txurn;
	97	u32 mib;
	98	u32 rxphyerr;
	99	u32 rx_keycache_miss;
	100	u32 swba;
	101	u32 bmiss;
	102	u32 bnr;
	103	u32 cst;
	104	u32 gtt;
	105	u32 tim;
	106	u32 cabend;
	107	u32 dtimsync;
	108	u32 dtim;
08578b8f	109	u32 bb_watchdog;
6dde1aab	110	u32 tsfoor;
97ba515a	111	u32 mci;
c9e6e980	112	u32 gen_timer;
462e58f2 BG	113
	114	/* Sync-cause stats */
	115	u32 sync_cause_all;
	116	u32 sync_rtc_irq;
	117	u32 sync_mac_irq;
	118	u32 eeprom_illegal_access;
	119	u32 apb_timeout;
	120	u32 pci_mode_conflict;
	121	u32 host1_fatal;
	122	u32 host1_perr;
	123	u32 trcv_fifo_perr;
	124	u32 radm_cpl_ep;
	125	u32 radm_cpl_dllp_abort;
	126	u32 radm_cpl_tlp_abort;
	127	u32 radm_cpl_ecrc_err;
	128	u32 radm_cpl_timeout;
	129	u32 local_timeout;
	130	u32 pm_access;
	131	u32 mac_awake;
	132	u32 mac_asleep;
	133	u32 mac_sleep_access;
394cf0a1 S	134	};
394cf0a1 S	135
462e58f2	136
fec247c0 S	137	/**
fec247c0 S	138	* struct ath_tx_stats - Statistics about TX
99c15bf5 BG	139	* @tx_pkts_all: No. of total frames transmitted, including ones that
	140	may have had errors.
	141	* @tx_bytes_all: No. of total bytes transmitted, including ones that
	142	may have had errors.
fec247c0 S	143	* @queued: Total MPDUs (non-aggr) queued
	144	* @completed: Total MPDUs (non-aggr) completed
	145	* @a_aggr: Total no. of aggregates queued
bda8adda BG	146	* @a_queued_hw: Total AMPDUs queued to hardware
bda8adda BG	147	* @a_queued_sw: Total AMPDUs queued to software queues
fec247c0 S	148	* @a_completed: Total AMPDUs completed
	149	* @a_retries: No. of AMPDUs retried (SW)
	150	* @a_xretries: No. of AMPDUs dropped due to xretries
4d900389	151	* @txerr_filtered: No. of frames with TXERR_FILT flag set.
fec247c0 S	152	* @fifo_underrun: FIFO underrun occurrences
	153	Valid only for:
	154	- non-aggregate condition.
	155	- first packet of aggregate.
	156	* @xtxop: No. of frames filtered because of TXOP limit
	157	* @timer_exp: Transmit timer expiry
	158	* @desc_cfg_err: Descriptor configuration errors
	159	* @data_urn: TX data underrun errors
	160	* @delim_urn: TX delimiter underrun errors
2dac4fb9 BG	161	* @puttxbuf: Number of times hardware was given txbuf to write.
	162	* @txstart: Number of times hardware was told to start tx.
	163	* @txprocdesc: Number of times tx descriptor was processed
a5a0bca1	164	* @txfailed: Out-of-memory or other errors in xmit path.
fec247c0 S	165	*/
fec247c0 S	166	struct ath_tx_stats {
99c15bf5 BG	167	u32 tx_pkts_all;
99c15bf5 BG	168	u32 tx_bytes_all;
fec247c0 S	169	u32 queued;
fec247c0 S	170	u32 completed;
5a6f78af	171	u32 xretries;
fec247c0	172	u32 a_aggr;
bda8adda BG	173	u32 a_queued_hw;
bda8adda BG	174	u32 a_queued_sw;
fec247c0 S	175	u32 a_completed;
	176	u32 a_retries;
	177	u32 a_xretries;
4d900389	178	u32 txerr_filtered;
fec247c0 S	179	u32 fifo_underrun;
	180	u32 xtxop;
	181	u32 timer_exp;
	182	u32 desc_cfg_err;
	183	u32 data_underrun;
	184	u32 delim_underrun;
2dac4fb9 BG	185	u32 puttxbuf;
	186	u32 txstart;
	187	u32 txprocdesc;
a5a0bca1	188	u32 txfailed;
fec247c0 S	189	};
fec247c0 S	190
78ef731c SM	191	/*
	192	* Various utility macros to print TX/Queue counters.
	193	*/
	194	#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
	195	#define TXSTATS sc->debug.stats.txstats
	196	#define PR(str, elem) \
	197	do { \
5e88ba62 ZK	198	len += scnprintf(buf + len, size - len, \
	199	"%s%13u%11u%10u%10u\n", str, \
	200	TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
	201	TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
	202	TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
	203	TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
78ef731c SM	204	} while(0)
78ef731c SM	205
350e2dcb SM	206	struct ath_rx_rate_stats {
	207	struct {
	208	u32 ht20_cnt;
	209	u32 ht40_cnt;
	210	u32 sgi_cnt;
	211	u32 lgi_cnt;
	212	} ht_stats[24];
	213
	214	struct {
	215	u32 ofdm_cnt;
	216	} ofdm_stats[8];
	217
	218	struct {
	219	u32 cck_lp_cnt;
	220	u32 cck_sp_cnt;
	221	} cck_stats[4];
	222	};
15072189	223
1395d3f0 S	224	/**
1395d3f0 S	225	* struct ath_rx_stats - RX Statistics
99c15bf5 BG	226	* @rx_pkts_all: No. of total frames received, including ones that
	227	may have had errors.
	228	* @rx_bytes_all: No. of total bytes received, including ones that
	229	may have had errors.
1395d3f0 S	230	* @crc_err: No. of frames with incorrect CRC value
	231	* @decrypt_crc_err: No. of frames whose CRC check failed after
	232	decryption process completed
	233	* @phy_err: No. of frames whose reception failed because the PHY
	234	encountered an error
	235	* @mic_err: No. of frames with incorrect TKIP MIC verification failure
	236	* @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
	237	* @post_delim_crc_err: Post-Frame delimiter CRC error detections
	238	* @decrypt_busy_err: Decryption interruptions counter
	239	* @phy_err_stats: Individual PHY error statistics
15072189 BG	240	* @rx_len_err: No. of frames discarded due to bad length.
	241	* @rx_oom_err: No. of frames dropped due to OOM issues.
	242	* @rx_rate_err: No. of frames dropped due to rate errors.
	243	* @rx_too_many_frags_err: Frames dropped due to too-many-frags received.
15072189 BG	244	* @rx_beacons: No. of beacons received.
15072189 BG	245	* @rx_frags: No. of rx-fragements received.
9b99e665	246	* @rx_spectral: No of spectral packets received.
1395d3f0 S	247	*/
1395d3f0 S	248	struct ath_rx_stats {
99c15bf5 BG	249	u32 rx_pkts_all;
99c15bf5 BG	250	u32 rx_bytes_all;
1395d3f0 S	251	u32 crc_err;
	252	u32 decrypt_crc_err;
	253	u32 phy_err;
	254	u32 mic_err;
	255	u32 pre_delim_crc_err;
	256	u32 post_delim_crc_err;
	257	u32 decrypt_busy_err;
	258	u32 phy_err_stats[ATH9K_PHYERR_MAX];
15072189 BG	259	u32 rx_len_err;
	260	u32 rx_oom_err;
	261	u32 rx_rate_err;
	262	u32 rx_too_many_frags_err;
15072189 BG	263	u32 rx_beacons;
15072189 BG	264	u32 rx_frags;
9b99e665	265	u32 rx_spectral;
1395d3f0 S	266	};
1395d3f0 S	267
3fbaf4c5 SM	268	#define ANT_MAIN 0
	269	#define ANT_ALT 1
	270
	271	struct ath_antenna_stats {
	272	u32 recv_cnt;
e3d52914 SM	273	u32 rssi_avg;
	274	u32 lna_recv_cnt[4];
	275	u32 lna_attempt_cnt[4];
3fbaf4c5 SM	276	};
3fbaf4c5 SM	277
394cf0a1 S	278	struct ath_stats {
394cf0a1 S	279	struct ath_interrupt_stats istats;
4f7dc951	280	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
1395d3f0	281	struct ath_rx_stats rxstats;
29942bc1	282	struct ath_dfs_stats dfs_stats;
3fbaf4c5	283	struct ath_antenna_stats ant_stats[2];
030d6294	284	u32 reset[__RESET_TYPE_MAX];
394cf0a1 S	285	};
	286
	287	struct ath9k_debug {
394cf0a1	288	struct dentry *debugfs_phy;
9bff0bc4	289	u32 regidx;
394cf0a1 S	290	struct ath_stats stats;
	291	};
	292
4d6b228d	293	int ath9k_init_debug(struct ath_hw *ah);
af690092	294	void ath9k_deinit_debug(struct ath_softc *sc);
4d6b228d	295
394cf0a1	296	void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
066dae93	297	void ath_debug_stat_tx(struct ath_softc sc, struct ath_buf bf,
55797b1a FF	298	struct ath_tx_status ts, struct ath_txq txq,
55797b1a FF	299	unsigned int flags);
8e6f5aa2	300	void ath_debug_stat_rx(struct ath_softc sc, struct ath_rx_status rs);
c175db87 SM	301	int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
	302	struct ieee80211_vif *vif, int sset);
	303	void ath9k_get_et_stats(struct ieee80211_hw *hw,
	304	struct ieee80211_vif *vif,
	305	struct ethtool_stats stats, u64 data);
	306	void ath9k_get_et_strings(struct ieee80211_hw *hw,
	307	struct ieee80211_vif *vif,
	308	u32 sset, u8 *data);
a145daf7 SM	309	void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
	310	struct ieee80211_vif *vif,
	311	struct ieee80211_sta *sta,
	312	struct dentry *dir);
e3d52914 SM	313	void ath9k_debug_stat_ant(struct ath_softc *sc,
	314	struct ath_hw_antcomb_conf *div_ant_conf,
	315	int main_rssi_avg, int alt_rssi_avg);
6a4d05dc FF	316	void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
6a4d05dc FF	317
394cf0a1 S	318	#else
394cf0a1 S	319
4d6b228d	320	static inline int ath9k_init_debug(struct ath_hw *ah)
394cf0a1 S	321	{
	322	return 0;
	323	}
	324
af690092 SM	325	static inline void ath9k_deinit_debug(struct ath_softc *sc)
	326	{
	327	}
394cf0a1 S	328	static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
	329	enum ath9k_int status)
	330	{
	331	}
fec247c0	332	static inline void ath_debug_stat_tx(struct ath_softc *sc,
32ffb1f4	333	struct ath_buf *bf,
3bf63e59	334	struct ath_tx_status *ts,
55797b1a FF	335	struct ath_txq *txq,
55797b1a FF	336	unsigned int flags)
fec247c0 S	337	{
fec247c0 S	338	}
1395d3f0	339	static inline void ath_debug_stat_rx(struct ath_softc *sc,
32ffb1f4	340	struct ath_rx_status *rs)
1395d3f0	341	{
e3d52914 SM	342	}
	343	static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
	344	struct ath_hw_antcomb_conf *div_ant_conf,
	345	int main_rssi_avg, int alt_rssi_avg)
	346	{
	347
1395d3f0 S	348	}
1395d3f0 S	349
6a4d05dc FF	350	static inline void
	351	ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
	352	{
	353	}
	354
a830df07	355	#endif /* CONFIG_ATH9K_DEBUGFS */
394cf0a1	356
350e2dcb SM	357	#ifdef CONFIG_ATH9K_STATION_STATISTICS
	358	void ath_debug_rate_stats(struct ath_softc *sc,
	359	struct ath_rx_status *rs,
	360	struct sk_buff *skb);
	361	#else
	362	static inline void ath_debug_rate_stats(struct ath_softc *sc,
	363	struct ath_rx_status *rs,
	364	struct sk_buff *skb)
	365	{
	366	}
	367	#endif /* CONFIG_ATH9K_STATION_STATISTICS */
	368
394cf0a1	369	#endif /* DEBUG_H */