[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / debug.h

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef DEBUG_H
#define DEBUG_H

#include "hw.h"
#include "rc.h"
#include "dfs_debug.h"

struct ath_txq;
struct ath_buf;

#ifdef CONFIG_ATH9K_DEBUGFS
#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
#else
#define TX_STAT_INC(q, c) do { } while (0)
#define RESET_STAT_INC(sc, type) do { } while (0)
#endif

enum ath_reset_type {
	RESET_TYPE_BB_HANG,
	RESET_TYPE_BB_WATCHDOG,
	RESET_TYPE_FATAL_INT,
	RESET_TYPE_TX_ERROR,
	RESET_TYPE_TX_HANG,
	RESET_TYPE_PLL_HANG,
	RESET_TYPE_MAC_HANG,
	RESET_TYPE_BEACON_STUCK,
	RESET_TYPE_MCI,
	__RESET_TYPE_MAX
};

#ifdef CONFIG_ATH9K_DEBUGFS

/**
 * struct ath_interrupt_stats - Contains statistics about interrupts
 * @total: Total no. of interrupts generated so far
 * @rxok: RX with no errors
 * @rxlp: RX with low priority RX
 * @rxhp: RX with high priority, uapsd only
 * @rxeol: RX with no more RXDESC available
 * @rxorn: RX FIFO overrun
 * @txok: TX completed at the requested rate
 * @txurn: TX FIFO underrun
 * @mib: MIB regs reaching its threshold
 * @rxphyerr: RX with phy errors
 * @rx_keycache_miss: RX with key cache misses
 * @swba: Software Beacon Alert
 * @bmiss: Beacon Miss
 * @bnr: Beacon Not Ready
 * @cst: Carrier Sense TImeout
 * @gtt: Global TX Timeout
 * @tim: RX beacon TIM occurrence
 * @cabend: RX End of CAB traffic
 * @dtimsync: DTIM sync lossage
 * @dtim: RX Beacon with DTIM
 * @bb_watchdog: Baseband watchdog
 * @tsfoor: TSF out of range, indicates that the corrected TSF received
 * from a beacon differs from the PCU's internal TSF by more than a
 * (programmable) threshold
 * @local_timeout: Internal bus timeout.
 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
 * @gen_timer: Generic hardware timer interrupt
 */
struct ath_interrupt_stats {
	u32 total;
	u32 rxok;
	u32 rxlp;
	u32 rxhp;
	u32 rxeol;
	u32 rxorn;
	u32 txok;
	u32 txeol;
	u32 txurn;
	u32 mib;
	u32 rxphyerr;
	u32 rx_keycache_miss;
	u32 swba;
	u32 bmiss;
	u32 bnr;
	u32 cst;
	u32 gtt;
	u32 tim;
	u32 cabend;
	u32 dtimsync;
	u32 dtim;
	u32 bb_watchdog;
	u32 tsfoor;
	u32 mci;
	u32 gen_timer;

	/* Sync-cause stats */
	u32 sync_cause_all;
	u32 sync_rtc_irq;
	u32 sync_mac_irq;
	u32 eeprom_illegal_access;
	u32 apb_timeout;
	u32 pci_mode_conflict;
	u32 host1_fatal;
	u32 host1_perr;
	u32 trcv_fifo_perr;
	u32 radm_cpl_ep;
	u32 radm_cpl_dllp_abort;
	u32 radm_cpl_tlp_abort;
	u32 radm_cpl_ecrc_err;
	u32 radm_cpl_timeout;
	u32 local_timeout;
	u32 pm_access;
	u32 mac_awake;
	u32 mac_asleep;
	u32 mac_sleep_access;
};


/**
 * struct ath_tx_stats - Statistics about TX
 * @tx_pkts_all:  No. of total frames transmitted, including ones that
	may have had errors.
 * @tx_bytes_all:  No. of total bytes transmitted, including ones that
	may have had errors.
 * @queued: Total MPDUs (non-aggr) queued
 * @completed: Total MPDUs (non-aggr) completed
 * @a_aggr: Total no. of aggregates queued
 * @a_queued_hw: Total AMPDUs queued to hardware
 * @a_queued_sw: Total AMPDUs queued to software queues
 * @a_completed: Total AMPDUs completed
 * @a_retries: No. of AMPDUs retried (SW)
 * @a_xretries: No. of AMPDUs dropped due to xretries
 * @fifo_underrun: FIFO underrun occurrences
	Valid only for:
		- non-aggregate condition.
		- first packet of aggregate.
 * @xtxop: No. of frames filtered because of TXOP limit
 * @timer_exp: Transmit timer expiry
 * @desc_cfg_err: Descriptor configuration errors
 * @data_urn: TX data underrun errors
 * @delim_urn: TX delimiter underrun errors
 * @puttxbuf: Number of times hardware was given txbuf to write.
 * @txstart:  Number of times hardware was told to start tx.
 * @txprocdesc:  Number of times tx descriptor was processed
 * @txfailed:  Out-of-memory or other errors in xmit path.
 */
struct ath_tx_stats {
	u32 tx_pkts_all;
	u32 tx_bytes_all;
	u32 queued;
	u32 completed;
	u32 xretries;
	u32 a_aggr;
	u32 a_queued_hw;
	u32 a_queued_sw;
	u32 a_completed;
	u32 a_retries;
	u32 a_xretries;
	u32 fifo_underrun;
	u32 xtxop;
	u32 timer_exp;
	u32 desc_cfg_err;
	u32 data_underrun;
	u32 delim_underrun;
	u32 puttxbuf;
	u32 txstart;
	u32 txprocdesc;
	u32 txfailed;
};

#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)

/**
 * struct ath_rx_stats - RX Statistics
 * @rx_pkts_all:  No. of total frames received, including ones that
	may have had errors.
 * @rx_bytes_all:  No. of total bytes received, including ones that
	may have had errors.
 * @crc_err: No. of frames with incorrect CRC value
 * @decrypt_crc_err: No. of frames whose CRC check failed after
	decryption process completed
 * @phy_err: No. of frames whose reception failed because the PHY
	encountered an error
 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 * @decrypt_busy_err: Decryption interruptions counter
 * @phy_err_stats: Individual PHY error statistics
 * @rx_len_err:  No. of frames discarded due to bad length.
 * @rx_oom_err:  No. of frames dropped due to OOM issues.
 * @rx_rate_err:  No. of frames dropped due to rate errors.
 * @rx_too_many_frags_err:  Frames dropped due to too-many-frags received.
 * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
 * @rx_beacons:  No. of beacons received.
 * @rx_frags:  No. of rx-fragements received.
 */
struct ath_rx_stats {
	u32 rx_pkts_all;
	u32 rx_bytes_all;
	u32 crc_err;
	u32 decrypt_crc_err;
	u32 phy_err;
	u32 mic_err;
	u32 pre_delim_crc_err;
	u32 post_delim_crc_err;
	u32 decrypt_busy_err;
	u32 phy_err_stats[ATH9K_PHYERR_MAX];
	u32 rx_len_err;
	u32 rx_oom_err;
	u32 rx_rate_err;
	u32 rx_too_many_frags_err;
	u32 rx_drop_rxflush;
	u32 rx_beacons;
	u32 rx_frags;
};

struct ath_stats {
	struct ath_interrupt_stats istats;
	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
	struct ath_rx_stats rxstats;
	struct ath_dfs_stats dfs_stats;
	u32 reset[__RESET_TYPE_MAX];
};

#define ATH_DBG_MAX_SAMPLES	10
struct ath_dbg_bb_mac_samp {
	u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
	u32 pcu_obs, pcu_cr, noise;
	struct {
		u64 jiffies;
		int8_t rssi_ctl0;
		int8_t rssi_ctl1;
		int8_t rssi_ctl2;
		int8_t rssi_ext0;
		int8_t rssi_ext1;
		int8_t rssi_ext2;
		int8_t rssi;
		bool isok;
		u8 rts_fail_cnt;
		u8 data_fail_cnt;
		u8 rateindex;
		u8 qid;
		u8 tid;
		u32 ba_low;
		u32 ba_high;
	} ts[ATH_DBG_MAX_SAMPLES];
	struct {
		u64 jiffies;
		int8_t rssi_ctl0;
		int8_t rssi_ctl1;
		int8_t rssi_ctl2;
		int8_t rssi_ext0;
		int8_t rssi_ext1;
		int8_t rssi_ext2;
		int8_t rssi;
		bool is_mybeacon;
		u8 antenna;
		u8 rate;
	} rs[ATH_DBG_MAX_SAMPLES];
	struct ath_cycle_counters cc;
	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
};

struct ath9k_debug {
	struct dentry *debugfs_phy;
	u32 regidx;
	struct ath_stats stats;
#ifdef CONFIG_ATH9K_MAC_DEBUG
	spinlock_t samp_lock;
	struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
	u8 sampidx;
	u8 tsidx;
	u8 rsidx;
#endif
};

int ath9k_init_debug(struct ath_hw *ah);

void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
		       struct ath_tx_status *ts, struct ath_txq *txq,
		       unsigned int flags);
void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);

#else

#define RX_STAT_INC(c) /* NOP */

static inline int ath9k_init_debug(struct ath_hw *ah)
{
	return 0;
}

static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
					    enum ath9k_int status)
{
}

static inline void ath_debug_stat_tx(struct ath_softc *sc,
				     struct ath_buf *bf,
				     struct ath_tx_status *ts,
				     struct ath_txq *txq,
				     unsigned int flags)
{
}

static inline void ath_debug_stat_rx(struct ath_softc *sc,
				     struct ath_rx_status *rs)
{
}

#endif /* CONFIG_ATH9K_DEBUGFS */

#ifdef CONFIG_ATH9K_MAC_DEBUG

void ath9k_debug_samp_bb_mac(struct ath_softc *sc);

#else

static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
{
}

#endif


#endif /* DEBUG_H */
Commit	Line	Data
394cf0a1	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
394cf0a1 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef DEBUG_H
	18	#define DEBUG_H
	19
4d6b228d	20	#include "hw.h"
545750d3	21	#include "rc.h"
29942bc1	22	#include "dfs_debug.h"
4d6b228d	23
fec247c0 S	24	struct ath_txq;
	25	struct ath_buf;
	26
a830df07	27	#ifdef CONFIG_ATH9K_DEBUGFS
fec247c0	28	#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
030d6294	29	#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
fec247c0 S	30	#else
fec247c0 S	31	#define TX_STAT_INC(q, c) do { } while (0)
030d6294	32	#define RESET_STAT_INC(sc, type) do { } while (0)
fec247c0 S	33	#endif
fec247c0 S	34
124b979b RM	35	enum ath_reset_type {
	36	RESET_TYPE_BB_HANG,
	37	RESET_TYPE_BB_WATCHDOG,
	38	RESET_TYPE_FATAL_INT,
	39	RESET_TYPE_TX_ERROR,
	40	RESET_TYPE_TX_HANG,
	41	RESET_TYPE_PLL_HANG,
	42	RESET_TYPE_MAC_HANG,
	43	RESET_TYPE_BEACON_STUCK,
b88083bf	44	RESET_TYPE_MCI,
124b979b RM	45	__RESET_TYPE_MAX
	46	};
	47
a830df07	48	#ifdef CONFIG_ATH9K_DEBUGFS
394cf0a1 S	49
	50	/**
	51	* struct ath_interrupt_stats - Contains statistics about interrupts
	52	* @total: Total no. of interrupts generated so far
	53	* @rxok: RX with no errors
a9616f41 LR	54	* @rxlp: RX with low priority RX
a9616f41 LR	55	* @rxhp: RX with high priority, uapsd only
394cf0a1 S	56	* @rxeol: RX with no more RXDESC available
	57	* @rxorn: RX FIFO overrun
	58	* @txok: TX completed at the requested rate
	59	* @txurn: TX FIFO underrun
	60	* @mib: MIB regs reaching its threshold
	61	* @rxphyerr: RX with phy errors
	62	* @rx_keycache_miss: RX with key cache misses
	63	* @swba: Software Beacon Alert
	64	* @bmiss: Beacon Miss
	65	* @bnr: Beacon Not Ready
	66	* @cst: Carrier Sense TImeout
	67	* @gtt: Global TX Timeout
	68	* @tim: RX beacon TIM occurrence
	69	* @cabend: RX End of CAB traffic
	70	* @dtimsync: DTIM sync lossage
	71	* @dtim: RX Beacon with DTIM
08578b8f	72	* @bb_watchdog: Baseband watchdog
6dde1aab MSS	73	* @tsfoor: TSF out of range, indicates that the corrected TSF received
	74	* from a beacon differs from the PCU's internal TSF by more than a
	75	* (programmable) threshold
462e58f2	76	* @local_timeout: Internal bus timeout.
c9e6e980 MSS	77	* @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
c9e6e980 MSS	78	* @gen_timer: Generic hardware timer interrupt
394cf0a1 S	79	*/
	80	struct ath_interrupt_stats {
	81	u32 total;
	82	u32 rxok;
a9616f41 LR	83	u32 rxlp;
a9616f41 LR	84	u32 rxhp;
394cf0a1 S	85	u32 rxeol;
	86	u32 rxorn;
	87	u32 txok;
	88	u32 txeol;
	89	u32 txurn;
	90	u32 mib;
	91	u32 rxphyerr;
	92	u32 rx_keycache_miss;
	93	u32 swba;
	94	u32 bmiss;
	95	u32 bnr;
	96	u32 cst;
	97	u32 gtt;
	98	u32 tim;
	99	u32 cabend;
	100	u32 dtimsync;
	101	u32 dtim;
08578b8f	102	u32 bb_watchdog;
6dde1aab	103	u32 tsfoor;
97ba515a	104	u32 mci;
c9e6e980	105	u32 gen_timer;
462e58f2 BG	106
	107	/* Sync-cause stats */
	108	u32 sync_cause_all;
	109	u32 sync_rtc_irq;
	110	u32 sync_mac_irq;
	111	u32 eeprom_illegal_access;
	112	u32 apb_timeout;
	113	u32 pci_mode_conflict;
	114	u32 host1_fatal;
	115	u32 host1_perr;
	116	u32 trcv_fifo_perr;
	117	u32 radm_cpl_ep;
	118	u32 radm_cpl_dllp_abort;
	119	u32 radm_cpl_tlp_abort;
	120	u32 radm_cpl_ecrc_err;
	121	u32 radm_cpl_timeout;
	122	u32 local_timeout;
	123	u32 pm_access;
	124	u32 mac_awake;
	125	u32 mac_asleep;
	126	u32 mac_sleep_access;
394cf0a1 S	127	};
394cf0a1 S	128
462e58f2	129
fec247c0 S	130	/**
fec247c0 S	131	* struct ath_tx_stats - Statistics about TX
99c15bf5 BG	132	* @tx_pkts_all: No. of total frames transmitted, including ones that
	133	may have had errors.
	134	* @tx_bytes_all: No. of total bytes transmitted, including ones that
	135	may have had errors.
fec247c0 S	136	* @queued: Total MPDUs (non-aggr) queued
	137	* @completed: Total MPDUs (non-aggr) completed
	138	* @a_aggr: Total no. of aggregates queued
bda8adda BG	139	* @a_queued_hw: Total AMPDUs queued to hardware
bda8adda BG	140	* @a_queued_sw: Total AMPDUs queued to software queues
fec247c0 S	141	* @a_completed: Total AMPDUs completed
	142	* @a_retries: No. of AMPDUs retried (SW)
	143	* @a_xretries: No. of AMPDUs dropped due to xretries
	144	* @fifo_underrun: FIFO underrun occurrences
	145	Valid only for:
	146	- non-aggregate condition.
	147	- first packet of aggregate.
	148	* @xtxop: No. of frames filtered because of TXOP limit
	149	* @timer_exp: Transmit timer expiry
	150	* @desc_cfg_err: Descriptor configuration errors
	151	* @data_urn: TX data underrun errors
	152	* @delim_urn: TX delimiter underrun errors
2dac4fb9 BG	153	* @puttxbuf: Number of times hardware was given txbuf to write.
	154	* @txstart: Number of times hardware was told to start tx.
	155	* @txprocdesc: Number of times tx descriptor was processed
a5a0bca1	156	* @txfailed: Out-of-memory or other errors in xmit path.
fec247c0 S	157	*/
fec247c0 S	158	struct ath_tx_stats {
99c15bf5 BG	159	u32 tx_pkts_all;
99c15bf5 BG	160	u32 tx_bytes_all;
fec247c0 S	161	u32 queued;
fec247c0 S	162	u32 completed;
5a6f78af	163	u32 xretries;
fec247c0	164	u32 a_aggr;
bda8adda BG	165	u32 a_queued_hw;
bda8adda BG	166	u32 a_queued_sw;
fec247c0 S	167	u32 a_completed;
	168	u32 a_retries;
	169	u32 a_xretries;
	170	u32 fifo_underrun;
	171	u32 xtxop;
	172	u32 timer_exp;
	173	u32 desc_cfg_err;
	174	u32 data_underrun;
	175	u32 delim_underrun;
2dac4fb9 BG	176	u32 puttxbuf;
	177	u32 txstart;
	178	u32 txprocdesc;
a5a0bca1	179	u32 txfailed;
fec247c0 S	180	};
fec247c0 S	181
15072189 BG	182	#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
15072189 BG	183
1395d3f0 S	184	/**
1395d3f0 S	185	* struct ath_rx_stats - RX Statistics
99c15bf5 BG	186	* @rx_pkts_all: No. of total frames received, including ones that
	187	may have had errors.
	188	* @rx_bytes_all: No. of total bytes received, including ones that
	189	may have had errors.
1395d3f0 S	190	* @crc_err: No. of frames with incorrect CRC value
	191	* @decrypt_crc_err: No. of frames whose CRC check failed after
	192	decryption process completed
	193	* @phy_err: No. of frames whose reception failed because the PHY
	194	encountered an error
	195	* @mic_err: No. of frames with incorrect TKIP MIC verification failure
	196	* @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
	197	* @post_delim_crc_err: Post-Frame delimiter CRC error detections
	198	* @decrypt_busy_err: Decryption interruptions counter
	199	* @phy_err_stats: Individual PHY error statistics
15072189 BG	200	* @rx_len_err: No. of frames discarded due to bad length.
	201	* @rx_oom_err: No. of frames dropped due to OOM issues.
	202	* @rx_rate_err: No. of frames dropped due to rate errors.
	203	* @rx_too_many_frags_err: Frames dropped due to too-many-frags received.
	204	* @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
	205	* @rx_beacons: No. of beacons received.
	206	* @rx_frags: No. of rx-fragements received.
1395d3f0 S	207	*/
1395d3f0 S	208	struct ath_rx_stats {
99c15bf5 BG	209	u32 rx_pkts_all;
99c15bf5 BG	210	u32 rx_bytes_all;
1395d3f0 S	211	u32 crc_err;
	212	u32 decrypt_crc_err;
	213	u32 phy_err;
	214	u32 mic_err;
	215	u32 pre_delim_crc_err;
	216	u32 post_delim_crc_err;
	217	u32 decrypt_busy_err;
	218	u32 phy_err_stats[ATH9K_PHYERR_MAX];
15072189 BG	219	u32 rx_len_err;
	220	u32 rx_oom_err;
	221	u32 rx_rate_err;
	222	u32 rx_too_many_frags_err;
	223	u32 rx_drop_rxflush;
	224	u32 rx_beacons;
	225	u32 rx_frags;
1395d3f0 S	226	};
1395d3f0 S	227
394cf0a1 S	228	struct ath_stats {
394cf0a1 S	229	struct ath_interrupt_stats istats;
fec247c0	230	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
1395d3f0	231	struct ath_rx_stats rxstats;
29942bc1	232	struct ath_dfs_stats dfs_stats;
030d6294	233	u32 reset[__RESET_TYPE_MAX];
394cf0a1 S	234	};
394cf0a1 S	235
cf3af748 RM	236	#define ATH_DBG_MAX_SAMPLES 10
	237	struct ath_dbg_bb_mac_samp {
	238	u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
	239	u32 pcu_obs, pcu_cr, noise;
	240	struct {
	241	u64 jiffies;
	242	int8_t rssi_ctl0;
	243	int8_t rssi_ctl1;
	244	int8_t rssi_ctl2;
	245	int8_t rssi_ext0;
	246	int8_t rssi_ext1;
	247	int8_t rssi_ext2;
	248	int8_t rssi;
	249	bool isok;
	250	u8 rts_fail_cnt;
	251	u8 data_fail_cnt;
	252	u8 rateindex;
	253	u8 qid;
	254	u8 tid;
12932180 MSS	255	u32 ba_low;
12932180 MSS	256	u32 ba_high;
cf3af748 RM	257	} ts[ATH_DBG_MAX_SAMPLES];
	258	struct {
	259	u64 jiffies;
	260	int8_t rssi_ctl0;
	261	int8_t rssi_ctl1;
	262	int8_t rssi_ctl2;
	263	int8_t rssi_ext0;
	264	int8_t rssi_ext1;
	265	int8_t rssi_ext2;
	266	int8_t rssi;
	267	bool is_mybeacon;
	268	u8 antenna;
	269	u8 rate;
	270	} rs[ATH_DBG_MAX_SAMPLES];
	271	struct ath_cycle_counters cc;
	272	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
	273	};
	274
394cf0a1	275	struct ath9k_debug {
394cf0a1	276	struct dentry *debugfs_phy;
9bff0bc4	277	u32 regidx;
394cf0a1	278	struct ath_stats stats;
5baec742	279	#ifdef CONFIG_ATH9K_MAC_DEBUG
cf3af748 RM	280	spinlock_t samp_lock;
	281	struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
	282	u8 sampidx;
	283	u8 tsidx;
	284	u8 rsidx;
5baec742	285	#endif
394cf0a1 S	286	};
394cf0a1 S	287
4d6b228d	288	int ath9k_init_debug(struct ath_hw *ah);
4d6b228d	289
394cf0a1	290	void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
066dae93	291	void ath_debug_stat_tx(struct ath_softc sc, struct ath_buf bf,
55797b1a FF	292	struct ath_tx_status ts, struct ath_txq txq,
55797b1a FF	293	unsigned int flags);
8e6f5aa2	294	void ath_debug_stat_rx(struct ath_softc sc, struct ath_rx_status rs);
394cf0a1 S	295
	296	#else
	297
15072189 BG	298	#define RX_STAT_INC(c) /* NOP */
15072189 BG	299
4d6b228d	300	static inline int ath9k_init_debug(struct ath_hw *ah)
394cf0a1 S	301	{
	302	return 0;
	303	}
	304
394cf0a1 S	305	static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
	306	enum ath9k_int status)
	307	{
	308	}
	309
fec247c0	310	static inline void ath_debug_stat_tx(struct ath_softc *sc,
32ffb1f4	311	struct ath_buf *bf,
3bf63e59	312	struct ath_tx_status *ts,
55797b1a FF	313	struct ath_txq *txq,
55797b1a FF	314	unsigned int flags)
fec247c0 S	315	{
	316	}
	317
1395d3f0	318	static inline void ath_debug_stat_rx(struct ath_softc *sc,
32ffb1f4	319	struct ath_rx_status *rs)
1395d3f0 S	320	{
	321	}
	322
a830df07	323	#endif /* CONFIG_ATH9K_DEBUGFS */
394cf0a1	324
5baec742 FF	325	#ifdef CONFIG_ATH9K_MAC_DEBUG
	326
	327	void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
	328
	329	#else
	330
	331	static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
	332	{
	333	}
	334
	335	#endif
	336
	337
394cf0a1	338	#endif /* DEBUG_H */