Commit | Line | Data |
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b5aec950 S |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
c46917bb | 17 | #include "hw.h" |
8fe65368 | 18 | #include "ar9002_phy.h" |
b5aec950 S |
19 | |
20 | static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) | |
21 | { | |
22 | return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF); | |
23 | } | |
24 | ||
25 | static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) | |
26 | { | |
27 | return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF); | |
28 | } | |
29 | ||
b5aec950 | 30 | #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) |
04cf53f4 SM |
31 | |
32 | static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) | |
33 | { | |
c46917bb | 34 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 | 35 | u16 *eep_data = (u16 *)&ah->eeprom.map4k; |
04cf53f4 | 36 | int addr, eep_start_loc = 64; |
b5aec950 S |
37 | |
38 | for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { | |
5bb12791 | 39 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { |
226afe68 JP |
40 | ath_dbg(common, ATH_DBG_EEPROM, |
41 | "Unable to read eeprom region\n"); | |
b5aec950 S |
42 | return false; |
43 | } | |
44 | eep_data++; | |
45 | } | |
46 | ||
47 | return true; | |
b5aec950 S |
48 | } |
49 | ||
04cf53f4 SM |
50 | static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah) |
51 | { | |
52 | u16 *eep_data = (u16 *)&ah->eeprom.map4k; | |
53 | ||
54 | ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K); | |
55 | ||
56 | return true; | |
57 | } | |
58 | ||
59 | static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) | |
60 | { | |
61 | struct ath_common *common = ath9k_hw_common(ah); | |
62 | ||
63 | if (!ath9k_hw_use_flash(ah)) { | |
64 | ath_dbg(common, ATH_DBG_EEPROM, | |
65 | "Reading from EEPROM, not flash\n"); | |
66 | } | |
67 | ||
68 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
69 | return __ath9k_hw_usb_4k_fill_eeprom(ah); | |
70 | else | |
71 | return __ath9k_hw_4k_fill_eeprom(ah); | |
72 | } | |
73 | ||
74 | #undef SIZE_EEPROM_4K | |
75 | ||
b5aec950 S |
76 | static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) |
77 | { | |
78 | #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) | |
c46917bb | 79 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
80 | struct ar5416_eeprom_4k *eep = |
81 | (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; | |
82 | u16 *eepdata, temp, magic, magic2; | |
83 | u32 sum = 0, el; | |
84 | bool need_swap = false; | |
85 | int i, addr; | |
86 | ||
87 | ||
88 | if (!ath9k_hw_use_flash(ah)) { | |
5bb12791 | 89 | if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, |
b5aec950 | 90 | &magic)) { |
3800276a | 91 | ath_err(common, "Reading Magic # failed\n"); |
b5aec950 S |
92 | return false; |
93 | } | |
94 | ||
226afe68 JP |
95 | ath_dbg(common, ATH_DBG_EEPROM, |
96 | "Read Magic = 0x%04X\n", magic); | |
b5aec950 S |
97 | |
98 | if (magic != AR5416_EEPROM_MAGIC) { | |
99 | magic2 = swab16(magic); | |
100 | ||
101 | if (magic2 == AR5416_EEPROM_MAGIC) { | |
102 | need_swap = true; | |
103 | eepdata = (u16 *) (&ah->eeprom); | |
104 | ||
105 | for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { | |
106 | temp = swab16(*eepdata); | |
107 | *eepdata = temp; | |
108 | eepdata++; | |
109 | } | |
110 | } else { | |
3800276a | 111 | ath_err(common, |
226afe68 | 112 | "Invalid EEPROM Magic. Endianness mismatch.\n"); |
b5aec950 S |
113 | return -EINVAL; |
114 | } | |
115 | } | |
116 | } | |
117 | ||
226afe68 JP |
118 | ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", |
119 | need_swap ? "True" : "False"); | |
b5aec950 S |
120 | |
121 | if (need_swap) | |
122 | el = swab16(ah->eeprom.map4k.baseEepHeader.length); | |
123 | else | |
124 | el = ah->eeprom.map4k.baseEepHeader.length; | |
125 | ||
126 | if (el > sizeof(struct ar5416_eeprom_4k)) | |
127 | el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); | |
128 | else | |
129 | el = el / sizeof(u16); | |
130 | ||
131 | eepdata = (u16 *)(&ah->eeprom); | |
132 | ||
133 | for (i = 0; i < el; i++) | |
134 | sum ^= *eepdata++; | |
135 | ||
136 | if (need_swap) { | |
137 | u32 integer; | |
138 | u16 word; | |
139 | ||
226afe68 JP |
140 | ath_dbg(common, ATH_DBG_EEPROM, |
141 | "EEPROM Endianness is not native.. Changing\n"); | |
b5aec950 S |
142 | |
143 | word = swab16(eep->baseEepHeader.length); | |
144 | eep->baseEepHeader.length = word; | |
145 | ||
146 | word = swab16(eep->baseEepHeader.checksum); | |
147 | eep->baseEepHeader.checksum = word; | |
148 | ||
149 | word = swab16(eep->baseEepHeader.version); | |
150 | eep->baseEepHeader.version = word; | |
151 | ||
152 | word = swab16(eep->baseEepHeader.regDmn[0]); | |
153 | eep->baseEepHeader.regDmn[0] = word; | |
154 | ||
155 | word = swab16(eep->baseEepHeader.regDmn[1]); | |
156 | eep->baseEepHeader.regDmn[1] = word; | |
157 | ||
158 | word = swab16(eep->baseEepHeader.rfSilent); | |
159 | eep->baseEepHeader.rfSilent = word; | |
160 | ||
161 | word = swab16(eep->baseEepHeader.blueToothOptions); | |
162 | eep->baseEepHeader.blueToothOptions = word; | |
163 | ||
164 | word = swab16(eep->baseEepHeader.deviceCap); | |
165 | eep->baseEepHeader.deviceCap = word; | |
166 | ||
167 | integer = swab32(eep->modalHeader.antCtrlCommon); | |
168 | eep->modalHeader.antCtrlCommon = integer; | |
169 | ||
170 | for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { | |
171 | integer = swab32(eep->modalHeader.antCtrlChain[i]); | |
172 | eep->modalHeader.antCtrlChain[i] = integer; | |
173 | } | |
174 | ||
4ddfcd7d | 175 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
b5aec950 S |
176 | word = swab16(eep->modalHeader.spurChans[i].spurChan); |
177 | eep->modalHeader.spurChans[i].spurChan = word; | |
178 | } | |
179 | } | |
180 | ||
181 | if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || | |
182 | ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { | |
3800276a JP |
183 | ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", |
184 | sum, ah->eep_ops->get_eeprom_ver(ah)); | |
b5aec950 S |
185 | return -EINVAL; |
186 | } | |
187 | ||
188 | return 0; | |
189 | #undef EEPROM_4K_SIZE | |
190 | } | |
191 | ||
192 | static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, | |
193 | enum eeprom_param param) | |
194 | { | |
195 | struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; | |
196 | struct modal_eep_4k_header *pModal = &eep->modalHeader; | |
197 | struct base_eep_header_4k *pBase = &eep->baseEepHeader; | |
970bf9d4 GJ |
198 | u16 ver_minor; |
199 | ||
200 | ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK; | |
b5aec950 S |
201 | |
202 | switch (param) { | |
203 | case EEP_NFTHRESH_2: | |
204 | return pModal->noiseFloorThreshCh[0]; | |
49101676 | 205 | case EEP_MAC_LSW: |
b5aec950 | 206 | return pBase->macAddr[0] << 8 | pBase->macAddr[1]; |
49101676 | 207 | case EEP_MAC_MID: |
b5aec950 | 208 | return pBase->macAddr[2] << 8 | pBase->macAddr[3]; |
49101676 | 209 | case EEP_MAC_MSW: |
b5aec950 S |
210 | return pBase->macAddr[4] << 8 | pBase->macAddr[5]; |
211 | case EEP_REG_0: | |
212 | return pBase->regDmn[0]; | |
213 | case EEP_REG_1: | |
214 | return pBase->regDmn[1]; | |
215 | case EEP_OP_CAP: | |
216 | return pBase->deviceCap; | |
217 | case EEP_OP_MODE: | |
218 | return pBase->opCapFlags; | |
219 | case EEP_RF_SILENT: | |
220 | return pBase->rfSilent; | |
221 | case EEP_OB_2: | |
7f63845f | 222 | return pModal->ob_0; |
b5aec950 | 223 | case EEP_DB_2: |
7f63845f | 224 | return pModal->db1_1; |
b5aec950 | 225 | case EEP_MINOR_REV: |
970bf9d4 | 226 | return ver_minor; |
b5aec950 S |
227 | case EEP_TX_MASK: |
228 | return pBase->txMask; | |
229 | case EEP_RX_MASK: | |
230 | return pBase->rxMask; | |
231 | case EEP_FRAC_N_5G: | |
232 | return 0; | |
e41f0bfc SB |
233 | case EEP_PWR_TABLE_OFFSET: |
234 | return AR5416_PWR_TABLE_OFFSET_DB; | |
754dc536 VT |
235 | case EEP_MODAL_VER: |
236 | return pModal->version; | |
237 | case EEP_ANT_DIV_CTL1: | |
238 | return pModal->antdiv_ctl1; | |
970bf9d4 GJ |
239 | case EEP_TXGAIN_TYPE: |
240 | if (ver_minor >= AR5416_EEP_MINOR_VER_19) | |
241 | return pBase->txGainType; | |
242 | else | |
243 | return AR5416_EEP_TXGAIN_ORIGINAL; | |
b5aec950 S |
244 | default: |
245 | return 0; | |
246 | } | |
247 | } | |
248 | ||
b5aec950 S |
249 | static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, |
250 | struct ath9k_channel *chan, | |
251 | int16_t *pTxPowerIndexOffset) | |
252 | { | |
c46917bb | 253 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
254 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; |
255 | struct cal_data_per_freq_4k *pRawDataset; | |
256 | u8 *pCalBChans = NULL; | |
257 | u16 pdGainOverlap_t2; | |
258 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; | |
4ddfcd7d | 259 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; |
b5aec950 | 260 | u16 numPiers, i, j; |
b5aec950 S |
261 | u16 numXpdGain, xpdMask; |
262 | u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 }; | |
263 | u32 reg32, regOffset, regChainOffset; | |
264 | ||
265 | xpdMask = pEepData->modalHeader.xpdGain; | |
266 | ||
267 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
268 | AR5416_EEP_MINOR_VER_2) { | |
269 | pdGainOverlap_t2 = | |
270 | pEepData->modalHeader.pdGainOverlap; | |
271 | } else { | |
272 | pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), | |
273 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); | |
274 | } | |
275 | ||
276 | pCalBChans = pEepData->calFreqPier2G; | |
277 | numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS; | |
278 | ||
279 | numXpdGain = 0; | |
280 | ||
4ddfcd7d FF |
281 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { |
282 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { | |
b5aec950 S |
283 | if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS) |
284 | break; | |
285 | xpdGainValues[numXpdGain] = | |
4ddfcd7d | 286 | (u16)(AR5416_PD_GAINS_IN_MASK - i); |
b5aec950 S |
287 | numXpdGain++; |
288 | } | |
289 | } | |
290 | ||
291 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, | |
292 | (numXpdGain - 1) & 0x3); | |
293 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, | |
294 | xpdGainValues[0]); | |
295 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, | |
296 | xpdGainValues[1]); | |
297 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0); | |
298 | ||
299 | for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { | |
300 | if (AR_SREV_5416_20_OR_LATER(ah) && | |
301 | (ah->rxchainmask == 5 || ah->txchainmask == 5) && | |
302 | (i != 0)) { | |
303 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | |
304 | } else | |
305 | regChainOffset = i * 0x1000; | |
306 | ||
307 | if (pEepData->baseEepHeader.txMask & (1 << i)) { | |
308 | pRawDataset = pEepData->calPierData2G[i]; | |
309 | ||
115277a3 | 310 | ath9k_hw_get_gain_boundaries_pdadcs(ah, chan, |
b5aec950 S |
311 | pRawDataset, pCalBChans, |
312 | numPiers, pdGainOverlap_t2, | |
6eb90d46 | 313 | gainBoundaries, |
b5aec950 S |
314 | pdadcValues, numXpdGain); |
315 | ||
7d0d0df0 S |
316 | ENABLE_REGWRITE_BUFFER(ah); |
317 | ||
b5aec950 S |
318 | if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { |
319 | REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, | |
320 | SM(pdGainOverlap_t2, | |
321 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | |
322 | | SM(gainBoundaries[0], | |
323 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | |
324 | | SM(gainBoundaries[1], | |
325 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | |
326 | | SM(gainBoundaries[2], | |
327 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | |
328 | | SM(gainBoundaries[3], | |
329 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); | |
330 | } | |
331 | ||
332 | regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; | |
333 | for (j = 0; j < 32; j++) { | |
334 | reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | | |
335 | ((pdadcValues[4 * j + 1] & 0xFF) << 8) | | |
336 | ((pdadcValues[4 * j + 2] & 0xFF) << 16)| | |
337 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); | |
338 | REG_WRITE(ah, regOffset, reg32); | |
339 | ||
226afe68 JP |
340 | ath_dbg(common, ATH_DBG_EEPROM, |
341 | "PDADC (%d,%4x): %4.4x %8.8x\n", | |
342 | i, regChainOffset, regOffset, | |
343 | reg32); | |
344 | ath_dbg(common, ATH_DBG_EEPROM, | |
345 | "PDADC: Chain %d | " | |
346 | "PDADC %3d Value %3d | " | |
347 | "PDADC %3d Value %3d | " | |
348 | "PDADC %3d Value %3d | " | |
349 | "PDADC %3d Value %3d |\n", | |
350 | i, 4 * j, pdadcValues[4 * j], | |
351 | 4 * j + 1, pdadcValues[4 * j + 1], | |
352 | 4 * j + 2, pdadcValues[4 * j + 2], | |
353 | 4 * j + 3, pdadcValues[4 * j + 3]); | |
b5aec950 S |
354 | |
355 | regOffset += 4; | |
356 | } | |
7d0d0df0 S |
357 | |
358 | REGWRITE_BUFFER_FLUSH(ah); | |
b5aec950 S |
359 | } |
360 | } | |
361 | ||
362 | *pTxPowerIndexOffset = 0; | |
363 | } | |
364 | ||
365 | static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, | |
366 | struct ath9k_channel *chan, | |
367 | int16_t *ratesArray, | |
368 | u16 cfgCtl, | |
369 | u16 AntennaReduction, | |
370 | u16 twiceMaxRegulatoryPower, | |
371 | u16 powerLimit) | |
372 | { | |
180d674b S |
373 | #define CMP_TEST_GRP \ |
374 | (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \ | |
375 | pEepData->ctlIndex[i]) \ | |
376 | || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ | |
377 | ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) | |
b5aec950 | 378 | |
608b88cb | 379 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
b5aec950 S |
380 | int i; |
381 | int16_t twiceLargestAntenna; | |
180d674b | 382 | u16 twiceMinEdgePower; |
4ddfcd7d | 383 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
180d674b | 384 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; |
07b2fa5a JP |
385 | u16 numCtlModes; |
386 | const u16 *pCtlMode; | |
387 | u16 ctlMode, freq; | |
180d674b | 388 | struct chan_centers centers; |
b5aec950 | 389 | struct cal_ctl_data_4k *rep; |
180d674b S |
390 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; |
391 | static const u16 tpScaleReductionTable[5] = | |
4ddfcd7d | 392 | { 0, 3, 6, 9, MAX_RATE_POWER }; |
b5aec950 S |
393 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { |
394 | 0, { 0, 0, 0, 0} | |
395 | }; | |
396 | struct cal_target_power_leg targetPowerOfdmExt = { | |
397 | 0, { 0, 0, 0, 0} }, targetPowerCckExt = { | |
398 | 0, { 0, 0, 0, 0 } | |
399 | }; | |
400 | struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { | |
401 | 0, {0, 0, 0, 0} | |
402 | }; | |
07b2fa5a JP |
403 | static const u16 ctlModesFor11g[] = { |
404 | CTL_11B, CTL_11G, CTL_2GHT20, | |
405 | CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 | |
406 | }; | |
b5aec950 S |
407 | |
408 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
409 | ||
410 | twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; | |
b5aec950 S |
411 | twiceLargestAntenna = (int16_t)min(AntennaReduction - |
412 | twiceLargestAntenna, 0); | |
413 | ||
414 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; | |
608b88cb | 415 | if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) { |
b5aec950 | 416 | maxRegAllowedPower -= |
608b88cb | 417 | (tpScaleReductionTable[(regulatory->tp_scale)] * 2); |
b5aec950 S |
418 | } |
419 | ||
420 | scaledPower = min(powerLimit, maxRegAllowedPower); | |
421 | scaledPower = max((u16)0, scaledPower); | |
422 | ||
423 | numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; | |
424 | pCtlMode = ctlModesFor11g; | |
425 | ||
426 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
427 | pEepData->calTargetPowerCck, | |
428 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
429 | &targetPowerCck, 4, false); | |
430 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
431 | pEepData->calTargetPower2G, | |
432 | AR5416_NUM_2G_20_TARGET_POWERS, | |
433 | &targetPowerOfdm, 4, false); | |
434 | ath9k_hw_get_target_powers(ah, chan, | |
435 | pEepData->calTargetPower2GHT20, | |
436 | AR5416_NUM_2G_20_TARGET_POWERS, | |
437 | &targetPowerHt20, 8, false); | |
438 | ||
439 | if (IS_CHAN_HT40(chan)) { | |
440 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
441 | ath9k_hw_get_target_powers(ah, chan, | |
442 | pEepData->calTargetPower2GHT40, | |
443 | AR5416_NUM_2G_40_TARGET_POWERS, | |
444 | &targetPowerHt40, 8, true); | |
445 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
446 | pEepData->calTargetPowerCck, | |
447 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
448 | &targetPowerCckExt, 4, true); | |
449 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
450 | pEepData->calTargetPower2G, | |
451 | AR5416_NUM_2G_20_TARGET_POWERS, | |
452 | &targetPowerOfdmExt, 4, true); | |
453 | } | |
454 | ||
455 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
456 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
457 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
180d674b | 458 | |
b5aec950 S |
459 | if (isHt40CtlMode) |
460 | freq = centers.synth_center; | |
461 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
462 | freq = centers.ext_center; | |
463 | else | |
464 | freq = centers.ctl_center; | |
465 | ||
466 | if (ah->eep_ops->get_eeprom_ver(ah) == 14 && | |
467 | ah->eep_ops->get_eeprom_rev(ah) <= 2) | |
4ddfcd7d | 468 | twiceMaxEdgePower = MAX_RATE_POWER; |
b5aec950 S |
469 | |
470 | for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && | |
180d674b S |
471 | pEepData->ctlIndex[i]; i++) { |
472 | ||
473 | if (CMP_TEST_GRP) { | |
b5aec950 S |
474 | rep = &(pEepData->ctlData[i]); |
475 | ||
180d674b S |
476 | twiceMinEdgePower = ath9k_hw_get_max_edge_power( |
477 | freq, | |
478 | rep->ctlEdges[ | |
479 | ar5416_get_ntxchains(ah->txchainmask) - 1], | |
480 | IS_CHAN_2GHZ(chan), | |
481 | AR5416_EEP4K_NUM_BAND_EDGES); | |
b5aec950 S |
482 | |
483 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { | |
484 | twiceMaxEdgePower = | |
485 | min(twiceMaxEdgePower, | |
486 | twiceMinEdgePower); | |
487 | } else { | |
488 | twiceMaxEdgePower = twiceMinEdgePower; | |
489 | break; | |
490 | } | |
491 | } | |
492 | } | |
493 | ||
494 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); | |
495 | ||
496 | switch (pCtlMode[ctlMode]) { | |
497 | case CTL_11B: | |
180d674b | 498 | for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { |
b5aec950 S |
499 | targetPowerCck.tPow2x[i] = |
500 | min((u16)targetPowerCck.tPow2x[i], | |
501 | minCtlPower); | |
502 | } | |
503 | break; | |
504 | case CTL_11G: | |
180d674b | 505 | for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { |
b5aec950 S |
506 | targetPowerOfdm.tPow2x[i] = |
507 | min((u16)targetPowerOfdm.tPow2x[i], | |
508 | minCtlPower); | |
509 | } | |
510 | break; | |
511 | case CTL_2GHT20: | |
180d674b | 512 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { |
b5aec950 S |
513 | targetPowerHt20.tPow2x[i] = |
514 | min((u16)targetPowerHt20.tPow2x[i], | |
515 | minCtlPower); | |
516 | } | |
517 | break; | |
518 | case CTL_11B_EXT: | |
180d674b S |
519 | targetPowerCckExt.tPow2x[0] = |
520 | min((u16)targetPowerCckExt.tPow2x[0], | |
521 | minCtlPower); | |
b5aec950 S |
522 | break; |
523 | case CTL_11G_EXT: | |
180d674b S |
524 | targetPowerOfdmExt.tPow2x[0] = |
525 | min((u16)targetPowerOfdmExt.tPow2x[0], | |
526 | minCtlPower); | |
b5aec950 S |
527 | break; |
528 | case CTL_2GHT40: | |
180d674b | 529 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { |
b5aec950 S |
530 | targetPowerHt40.tPow2x[i] = |
531 | min((u16)targetPowerHt40.tPow2x[i], | |
532 | minCtlPower); | |
533 | } | |
534 | break; | |
535 | default: | |
536 | break; | |
537 | } | |
538 | } | |
539 | ||
180d674b S |
540 | ratesArray[rate6mb] = |
541 | ratesArray[rate9mb] = | |
542 | ratesArray[rate12mb] = | |
543 | ratesArray[rate18mb] = | |
544 | ratesArray[rate24mb] = | |
545 | targetPowerOfdm.tPow2x[0]; | |
546 | ||
b5aec950 S |
547 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; |
548 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; | |
549 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; | |
550 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; | |
551 | ||
552 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) | |
553 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; | |
554 | ||
555 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; | |
556 | ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; | |
557 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; | |
558 | ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; | |
559 | ||
560 | if (IS_CHAN_HT40(chan)) { | |
561 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
562 | ratesArray[rateHt40_0 + i] = | |
563 | targetPowerHt40.tPow2x[i]; | |
564 | } | |
565 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; | |
566 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; | |
567 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; | |
568 | ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; | |
569 | } | |
180d674b S |
570 | |
571 | #undef CMP_TEST_GRP | |
b5aec950 S |
572 | } |
573 | ||
574 | static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, | |
bf466fb6 S |
575 | struct ath9k_channel *chan, |
576 | u16 cfgCtl, | |
577 | u8 twiceAntennaReduction, | |
578 | u8 twiceMaxRegulatoryPower, | |
de40f316 | 579 | u8 powerLimit, bool test) |
b5aec950 | 580 | { |
608b88cb | 581 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
b5aec950 S |
582 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; |
583 | struct modal_eep_4k_header *pModal = &pEepData->modalHeader; | |
584 | int16_t ratesArray[Ar5416RateSize]; | |
585 | int16_t txPowerIndexOffset = 0; | |
586 | u8 ht40PowerIncForPdadc = 2; | |
587 | int i; | |
588 | ||
589 | memset(ratesArray, 0, sizeof(ratesArray)); | |
590 | ||
591 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
592 | AR5416_EEP_MINOR_VER_2) { | |
593 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; | |
594 | } | |
595 | ||
596 | ath9k_hw_set_4k_power_per_rate_table(ah, chan, | |
bf466fb6 S |
597 | &ratesArray[0], cfgCtl, |
598 | twiceAntennaReduction, | |
599 | twiceMaxRegulatoryPower, | |
600 | powerLimit); | |
b5aec950 S |
601 | |
602 | ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset); | |
603 | ||
de40f316 | 604 | regulatory->max_power_level = 0; |
b5aec950 S |
605 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
606 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | |
4ddfcd7d FF |
607 | if (ratesArray[i] > MAX_RATE_POWER) |
608 | ratesArray[i] = MAX_RATE_POWER; | |
de40f316 FF |
609 | |
610 | if (ratesArray[i] > regulatory->max_power_level) | |
611 | regulatory->max_power_level = ratesArray[i]; | |
b5aec950 S |
612 | } |
613 | ||
de40f316 FF |
614 | if (test) |
615 | return; | |
bf466fb6 S |
616 | |
617 | /* Update regulatory */ | |
bf466fb6 S |
618 | i = rate6mb; |
619 | if (IS_CHAN_HT40(chan)) | |
620 | i = rateHt40_0; | |
621 | else if (IS_CHAN_HT20(chan)) | |
622 | i = rateHt20_0; | |
623 | ||
608b88cb | 624 | regulatory->max_power_level = ratesArray[i]; |
bf466fb6 | 625 | |
7a37081e | 626 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
b5aec950 | 627 | for (i = 0; i < Ar5416RateSize; i++) |
e41f0bfc | 628 | ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; |
b5aec950 S |
629 | } |
630 | ||
7d0d0df0 S |
631 | ENABLE_REGWRITE_BUFFER(ah); |
632 | ||
bf466fb6 | 633 | /* OFDM power per rate */ |
b5aec950 S |
634 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, |
635 | ATH9K_POW_SM(ratesArray[rate18mb], 24) | |
636 | | ATH9K_POW_SM(ratesArray[rate12mb], 16) | |
637 | | ATH9K_POW_SM(ratesArray[rate9mb], 8) | |
638 | | ATH9K_POW_SM(ratesArray[rate6mb], 0)); | |
639 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, | |
640 | ATH9K_POW_SM(ratesArray[rate54mb], 24) | |
641 | | ATH9K_POW_SM(ratesArray[rate48mb], 16) | |
642 | | ATH9K_POW_SM(ratesArray[rate36mb], 8) | |
643 | | ATH9K_POW_SM(ratesArray[rate24mb], 0)); | |
644 | ||
bf466fb6 S |
645 | /* CCK power per rate */ |
646 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | |
647 | ATH9K_POW_SM(ratesArray[rate2s], 24) | |
648 | | ATH9K_POW_SM(ratesArray[rate2l], 16) | |
649 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | |
650 | | ATH9K_POW_SM(ratesArray[rate1l], 0)); | |
651 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | |
652 | ATH9K_POW_SM(ratesArray[rate11s], 24) | |
653 | | ATH9K_POW_SM(ratesArray[rate11l], 16) | |
654 | | ATH9K_POW_SM(ratesArray[rate5_5s], 8) | |
655 | | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); | |
656 | ||
657 | /* HT20 power per rate */ | |
b5aec950 S |
658 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, |
659 | ATH9K_POW_SM(ratesArray[rateHt20_3], 24) | |
660 | | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | |
661 | | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) | |
662 | | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); | |
663 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, | |
664 | ATH9K_POW_SM(ratesArray[rateHt20_7], 24) | |
665 | | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) | |
666 | | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | |
667 | | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); | |
668 | ||
bf466fb6 | 669 | /* HT40 power per rate */ |
b5aec950 S |
670 | if (IS_CHAN_HT40(chan)) { |
671 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | |
672 | ATH9K_POW_SM(ratesArray[rateHt40_3] + | |
673 | ht40PowerIncForPdadc, 24) | |
674 | | ATH9K_POW_SM(ratesArray[rateHt40_2] + | |
675 | ht40PowerIncForPdadc, 16) | |
676 | | ATH9K_POW_SM(ratesArray[rateHt40_1] + | |
677 | ht40PowerIncForPdadc, 8) | |
678 | | ATH9K_POW_SM(ratesArray[rateHt40_0] + | |
679 | ht40PowerIncForPdadc, 0)); | |
680 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | |
681 | ATH9K_POW_SM(ratesArray[rateHt40_7] + | |
682 | ht40PowerIncForPdadc, 24) | |
683 | | ATH9K_POW_SM(ratesArray[rateHt40_6] + | |
684 | ht40PowerIncForPdadc, 16) | |
685 | | ATH9K_POW_SM(ratesArray[rateHt40_5] + | |
686 | ht40PowerIncForPdadc, 8) | |
687 | | ATH9K_POW_SM(ratesArray[rateHt40_4] + | |
688 | ht40PowerIncForPdadc, 0)); | |
b5aec950 S |
689 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, |
690 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | |
691 | | ATH9K_POW_SM(ratesArray[rateExtCck], 16) | |
692 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | |
693 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); | |
694 | } | |
7d0d0df0 S |
695 | |
696 | REGWRITE_BUFFER_FLUSH(ah); | |
b5aec950 S |
697 | } |
698 | ||
699 | static void ath9k_hw_4k_set_addac(struct ath_hw *ah, | |
700 | struct ath9k_channel *chan) | |
701 | { | |
702 | struct modal_eep_4k_header *pModal; | |
703 | struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; | |
704 | u8 biaslevel; | |
705 | ||
706 | if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) | |
707 | return; | |
708 | ||
709 | if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) | |
710 | return; | |
711 | ||
712 | pModal = &eep->modalHeader; | |
713 | ||
714 | if (pModal->xpaBiasLvl != 0xff) { | |
715 | biaslevel = pModal->xpaBiasLvl; | |
716 | INI_RA(&ah->iniAddac, 7, 1) = | |
717 | (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; | |
718 | } | |
719 | } | |
720 | ||
721 | static void ath9k_hw_4k_set_gain(struct ath_hw *ah, | |
722 | struct modal_eep_4k_header *pModal, | |
723 | struct ar5416_eeprom_4k *eep, | |
a37414a2 | 724 | u8 txRxAttenLocal) |
b5aec950 | 725 | { |
a37414a2 | 726 | REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, |
b5aec950 S |
727 | pModal->antCtrlChain[0]); |
728 | ||
a37414a2 S |
729 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), |
730 | (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & | |
b5aec950 S |
731 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | |
732 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | | |
733 | SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | | |
734 | SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); | |
735 | ||
736 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
737 | AR5416_EEP_MINOR_VER_3) { | |
738 | txRxAttenLocal = pModal->txRxAttenCh[0]; | |
739 | ||
a37414a2 | 740 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, |
b5aec950 | 741 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); |
a37414a2 | 742 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, |
b5aec950 | 743 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); |
a37414a2 | 744 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, |
b5aec950 S |
745 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, |
746 | pModal->xatten2Margin[0]); | |
a37414a2 | 747 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, |
b5aec950 S |
748 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); |
749 | ||
750 | /* Set the block 1 value to block 0 value */ | |
751 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, | |
752 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, | |
753 | pModal->bswMargin[0]); | |
754 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, | |
755 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); | |
756 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, | |
757 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, | |
758 | pModal->xatten2Margin[0]); | |
759 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, | |
760 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, | |
761 | pModal->xatten2Db[0]); | |
762 | } | |
763 | ||
a37414a2 | 764 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN, |
b5aec950 | 765 | AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); |
a37414a2 | 766 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN, |
b5aec950 S |
767 | AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); |
768 | ||
769 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, | |
770 | AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); | |
771 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, | |
772 | AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); | |
b5aec950 S |
773 | } |
774 | ||
775 | /* | |
776 | * Read EEPROM header info and program the device for correct operation | |
777 | * given the channel value. | |
778 | */ | |
779 | static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, | |
780 | struct ath9k_channel *chan) | |
781 | { | |
782 | struct modal_eep_4k_header *pModal; | |
783 | struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; | |
784 | u8 txRxAttenLocal; | |
785 | u8 ob[5], db1[5], db2[5]; | |
786 | u8 ant_div_control1, ant_div_control2; | |
787 | u32 regVal; | |
788 | ||
789 | pModal = &eep->modalHeader; | |
790 | txRxAttenLocal = 23; | |
791 | ||
df3c8b2b | 792 | REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); |
b5aec950 S |
793 | |
794 | /* Single chain for 4K EEPROM*/ | |
a37414a2 | 795 | ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal); |
b5aec950 S |
796 | |
797 | /* Initialize Ant Diversity settings from EEPROM */ | |
798 | if (pModal->version >= 3) { | |
7f63845f S |
799 | ant_div_control1 = pModal->antdiv_ctl1; |
800 | ant_div_control2 = pModal->antdiv_ctl2; | |
801 | ||
802 | regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); | |
803 | regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); | |
804 | ||
805 | regVal |= SM(ant_div_control1, | |
806 | AR_PHY_9285_ANT_DIV_CTL); | |
807 | regVal |= SM(ant_div_control2, | |
808 | AR_PHY_9285_ANT_DIV_ALT_LNACONF); | |
809 | regVal |= SM((ant_div_control2 >> 2), | |
810 | AR_PHY_9285_ANT_DIV_MAIN_LNACONF); | |
811 | regVal |= SM((ant_div_control1 >> 1), | |
812 | AR_PHY_9285_ANT_DIV_ALT_GAINTB); | |
813 | regVal |= SM((ant_div_control1 >> 2), | |
814 | AR_PHY_9285_ANT_DIV_MAIN_GAINTB); | |
815 | ||
816 | ||
817 | REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); | |
818 | regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); | |
819 | regVal = REG_READ(ah, AR_PHY_CCK_DETECT); | |
820 | regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); | |
821 | regVal |= SM((ant_div_control1 >> 3), | |
822 | AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); | |
823 | ||
824 | REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); | |
825 | regVal = REG_READ(ah, AR_PHY_CCK_DETECT); | |
b5aec950 S |
826 | } |
827 | ||
828 | if (pModal->version >= 2) { | |
7f63845f S |
829 | ob[0] = pModal->ob_0; |
830 | ob[1] = pModal->ob_1; | |
831 | ob[2] = pModal->ob_2; | |
832 | ob[3] = pModal->ob_3; | |
833 | ob[4] = pModal->ob_4; | |
834 | ||
835 | db1[0] = pModal->db1_0; | |
836 | db1[1] = pModal->db1_1; | |
837 | db1[2] = pModal->db1_2; | |
838 | db1[3] = pModal->db1_3; | |
839 | db1[4] = pModal->db1_4; | |
840 | ||
841 | db2[0] = pModal->db2_0; | |
842 | db2[1] = pModal->db2_1; | |
843 | db2[2] = pModal->db2_2; | |
844 | db2[3] = pModal->db2_3; | |
845 | db2[4] = pModal->db2_4; | |
b5aec950 | 846 | } else if (pModal->version == 1) { |
7f63845f S |
847 | ob[0] = pModal->ob_0; |
848 | ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; | |
849 | db1[0] = pModal->db1_0; | |
850 | db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; | |
851 | db2[0] = pModal->db2_0; | |
852 | db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; | |
b5aec950 S |
853 | } else { |
854 | int i; | |
7f63845f | 855 | |
b5aec950 | 856 | for (i = 0; i < 5; i++) { |
7f63845f S |
857 | ob[i] = pModal->ob_0; |
858 | db1[i] = pModal->db1_0; | |
859 | db2[i] = pModal->db1_0; | |
b5aec950 S |
860 | } |
861 | } | |
862 | ||
863 | if (AR_SREV_9271(ah)) { | |
864 | ath9k_hw_analog_shift_rmw(ah, | |
865 | AR9285_AN_RF2G3, | |
866 | AR9271_AN_RF2G3_OB_cck, | |
867 | AR9271_AN_RF2G3_OB_cck_S, | |
868 | ob[0]); | |
869 | ath9k_hw_analog_shift_rmw(ah, | |
870 | AR9285_AN_RF2G3, | |
871 | AR9271_AN_RF2G3_OB_psk, | |
872 | AR9271_AN_RF2G3_OB_psk_S, | |
873 | ob[1]); | |
874 | ath9k_hw_analog_shift_rmw(ah, | |
875 | AR9285_AN_RF2G3, | |
876 | AR9271_AN_RF2G3_OB_qam, | |
877 | AR9271_AN_RF2G3_OB_qam_S, | |
878 | ob[2]); | |
879 | ath9k_hw_analog_shift_rmw(ah, | |
880 | AR9285_AN_RF2G3, | |
881 | AR9271_AN_RF2G3_DB_1, | |
882 | AR9271_AN_RF2G3_DB_1_S, | |
883 | db1[0]); | |
884 | ath9k_hw_analog_shift_rmw(ah, | |
885 | AR9285_AN_RF2G4, | |
886 | AR9271_AN_RF2G4_DB_2, | |
887 | AR9271_AN_RF2G4_DB_2_S, | |
888 | db2[0]); | |
889 | } else { | |
890 | ath9k_hw_analog_shift_rmw(ah, | |
891 | AR9285_AN_RF2G3, | |
892 | AR9285_AN_RF2G3_OB_0, | |
893 | AR9285_AN_RF2G3_OB_0_S, | |
894 | ob[0]); | |
895 | ath9k_hw_analog_shift_rmw(ah, | |
896 | AR9285_AN_RF2G3, | |
897 | AR9285_AN_RF2G3_OB_1, | |
898 | AR9285_AN_RF2G3_OB_1_S, | |
899 | ob[1]); | |
900 | ath9k_hw_analog_shift_rmw(ah, | |
901 | AR9285_AN_RF2G3, | |
902 | AR9285_AN_RF2G3_OB_2, | |
903 | AR9285_AN_RF2G3_OB_2_S, | |
904 | ob[2]); | |
905 | ath9k_hw_analog_shift_rmw(ah, | |
906 | AR9285_AN_RF2G3, | |
907 | AR9285_AN_RF2G3_OB_3, | |
908 | AR9285_AN_RF2G3_OB_3_S, | |
909 | ob[3]); | |
910 | ath9k_hw_analog_shift_rmw(ah, | |
911 | AR9285_AN_RF2G3, | |
912 | AR9285_AN_RF2G3_OB_4, | |
913 | AR9285_AN_RF2G3_OB_4_S, | |
914 | ob[4]); | |
915 | ||
916 | ath9k_hw_analog_shift_rmw(ah, | |
917 | AR9285_AN_RF2G3, | |
918 | AR9285_AN_RF2G3_DB1_0, | |
919 | AR9285_AN_RF2G3_DB1_0_S, | |
920 | db1[0]); | |
921 | ath9k_hw_analog_shift_rmw(ah, | |
922 | AR9285_AN_RF2G3, | |
923 | AR9285_AN_RF2G3_DB1_1, | |
924 | AR9285_AN_RF2G3_DB1_1_S, | |
925 | db1[1]); | |
926 | ath9k_hw_analog_shift_rmw(ah, | |
927 | AR9285_AN_RF2G3, | |
928 | AR9285_AN_RF2G3_DB1_2, | |
929 | AR9285_AN_RF2G3_DB1_2_S, | |
930 | db1[2]); | |
931 | ath9k_hw_analog_shift_rmw(ah, | |
932 | AR9285_AN_RF2G4, | |
933 | AR9285_AN_RF2G4_DB1_3, | |
934 | AR9285_AN_RF2G4_DB1_3_S, | |
935 | db1[3]); | |
936 | ath9k_hw_analog_shift_rmw(ah, | |
937 | AR9285_AN_RF2G4, | |
938 | AR9285_AN_RF2G4_DB1_4, | |
939 | AR9285_AN_RF2G4_DB1_4_S, db1[4]); | |
940 | ||
941 | ath9k_hw_analog_shift_rmw(ah, | |
942 | AR9285_AN_RF2G4, | |
943 | AR9285_AN_RF2G4_DB2_0, | |
944 | AR9285_AN_RF2G4_DB2_0_S, | |
945 | db2[0]); | |
946 | ath9k_hw_analog_shift_rmw(ah, | |
947 | AR9285_AN_RF2G4, | |
948 | AR9285_AN_RF2G4_DB2_1, | |
949 | AR9285_AN_RF2G4_DB2_1_S, | |
950 | db2[1]); | |
951 | ath9k_hw_analog_shift_rmw(ah, | |
952 | AR9285_AN_RF2G4, | |
953 | AR9285_AN_RF2G4_DB2_2, | |
954 | AR9285_AN_RF2G4_DB2_2_S, | |
955 | db2[2]); | |
956 | ath9k_hw_analog_shift_rmw(ah, | |
957 | AR9285_AN_RF2G4, | |
958 | AR9285_AN_RF2G4_DB2_3, | |
959 | AR9285_AN_RF2G4_DB2_3_S, | |
960 | db2[3]); | |
961 | ath9k_hw_analog_shift_rmw(ah, | |
962 | AR9285_AN_RF2G4, | |
963 | AR9285_AN_RF2G4_DB2_4, | |
964 | AR9285_AN_RF2G4_DB2_4_S, | |
965 | db2[4]); | |
966 | } | |
967 | ||
968 | ||
b5aec950 S |
969 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, |
970 | pModal->switchSettling); | |
971 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, | |
972 | pModal->adcDesiredSize); | |
973 | ||
974 | REG_WRITE(ah, AR_PHY_RF_CTL4, | |
975 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | | |
976 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | | |
977 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | | |
978 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); | |
979 | ||
980 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | |
981 | pModal->txEndToRxOn); | |
0cab6559 LR |
982 | |
983 | if (AR_SREV_9271_10(ah)) | |
984 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | |
985 | pModal->txEndToRxOn); | |
b5aec950 S |
986 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, |
987 | pModal->thresh62); | |
988 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, | |
989 | pModal->thresh62); | |
990 | ||
991 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
992 | AR5416_EEP_MINOR_VER_2) { | |
993 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, | |
994 | pModal->txFrameToDataStart); | |
995 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, | |
996 | pModal->txFrameToPaOn); | |
997 | } | |
998 | ||
999 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1000 | AR5416_EEP_MINOR_VER_3) { | |
1001 | if (IS_CHAN_HT40(chan)) | |
1002 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | |
1003 | AR_PHY_SETTLING_SWITCH, | |
1004 | pModal->swSettleHt40); | |
1005 | } | |
1006 | } | |
1007 | ||
b5aec950 S |
1008 | static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) |
1009 | { | |
1010 | #define EEP_MAP4K_SPURCHAN \ | |
1011 | (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) | |
c46917bb | 1012 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
1013 | |
1014 | u16 spur_val = AR_NO_SPUR; | |
1015 | ||
226afe68 JP |
1016 | ath_dbg(common, ATH_DBG_ANI, |
1017 | "Getting spur idx:%d is2Ghz:%d val:%x\n", | |
1018 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | |
b5aec950 S |
1019 | |
1020 | switch (ah->config.spurmode) { | |
1021 | case SPUR_DISABLE: | |
1022 | break; | |
1023 | case SPUR_ENABLE_IOCTL: | |
1024 | spur_val = ah->config.spurchans[i][is2GHz]; | |
226afe68 JP |
1025 | ath_dbg(common, ATH_DBG_ANI, |
1026 | "Getting spur val from new loc. %d\n", spur_val); | |
b5aec950 S |
1027 | break; |
1028 | case SPUR_ENABLE_EEPROM: | |
1029 | spur_val = EEP_MAP4K_SPURCHAN; | |
1030 | break; | |
1031 | } | |
1032 | ||
1033 | return spur_val; | |
1034 | ||
1035 | #undef EEP_MAP4K_SPURCHAN | |
1036 | } | |
1037 | ||
1038 | const struct eeprom_ops eep_4k_ops = { | |
1039 | .check_eeprom = ath9k_hw_4k_check_eeprom, | |
1040 | .get_eeprom = ath9k_hw_4k_get_eeprom, | |
1041 | .fill_eeprom = ath9k_hw_4k_fill_eeprom, | |
1042 | .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver, | |
1043 | .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev, | |
b5aec950 S |
1044 | .set_board_values = ath9k_hw_4k_set_board_values, |
1045 | .set_addac = ath9k_hw_4k_set_addac, | |
1046 | .set_txpower = ath9k_hw_4k_set_txpower, | |
1047 | .get_spur_channel = ath9k_hw_4k_get_spur_channel | |
1048 | }; |