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ath9k_hw: make ath9k_hw_set_interrupts use ah->imask by default
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / eeprom_4k.c
CommitLineData
b5aec950 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
b5aec950
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
78fa99ab 17#include <asm/unaligned.h>
c46917bb 18#include "hw.h"
8fe65368 19#include "ar9002_phy.h"
b5aec950
S		 20
21static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
22{
23 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
24}
25
26static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
27{
28 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
29}
30
b5aec950 31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
04cf53f4
SM		 32
33static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
34{
c46917bb 35 struct ath_common *common = ath9k_hw_common(ah);
b5aec950 36 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
04cf53f4 37 int addr, eep_start_loc = 64;
b5aec950
S		 38
39 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
5bb12791 40 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
226afe68
JP		 41 ath_dbg(common, ATH_DBG_EEPROM,
42 "Unable to read eeprom region\n");
b5aec950
S		 43 return false;
44 }
45 eep_data++;
46 }
47
48 return true;
b5aec950
S		 49}
50
04cf53f4
SM		 51static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
52{
53 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
54
55 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
56
57 return true;
58}
59
60static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
61{
62 struct ath_common *common = ath9k_hw_common(ah);
63
64 if (!ath9k_hw_use_flash(ah)) {
65 ath_dbg(common, ATH_DBG_EEPROM,
66 "Reading from EEPROM, not flash\n");
67 }
68
69 if (common->bus_ops->ath_bus_type == ATH_USB)
70 return __ath9k_hw_usb_4k_fill_eeprom(ah);
71 else
72 return __ath9k_hw_4k_fill_eeprom(ah);
73}
74
4f011a2e
RM		 75#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
76static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size,
77 struct modal_eep_4k_header *modal_hdr)
78{
79 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
80 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
81 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
82 PR_EEP("Switch Settle", modal_hdr->switchSettling);
83 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
84 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
85 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
86 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
87 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
88 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
89 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
90 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
91 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
92 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
93 PR_EEP("xpdGain", modal_hdr->xpdGain);
94 PR_EEP("External PD", modal_hdr->xpd);
95 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
96 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
97 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
98 PR_EEP("O/D Bias Version", modal_hdr->version);
99 PR_EEP("CCK OutputBias", modal_hdr->ob_0);
100 PR_EEP("BPSK OutputBias", modal_hdr->ob_1);
101 PR_EEP("QPSK OutputBias", modal_hdr->ob_2);
102 PR_EEP("16QAM OutputBias", modal_hdr->ob_3);
103 PR_EEP("64QAM OutputBias", modal_hdr->ob_4);
104 PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0);
105 PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1);
106 PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2);
107 PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3);
108 PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4);
109 PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0);
110 PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1);
111 PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2);
112 PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3);
113 PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4);
114 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
115 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
116 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
117 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
118 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
119 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
120 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
121 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
122 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
123 PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1);
124 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2);
125 PR_EEP("TX Diversity", modal_hdr->tx_diversity);
126
127 return len;
128}
129
130static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
131 u8 *buf, u32 len, u32 size)
132{
133 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
134 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
135
136 if (!dump_base_hdr) {
137 len += snprintf(buf + len, size - len,
138 "%20s :\n", "2GHz modal Header");
139 len += ath9k_dump_4k_modal_eeprom(buf, len, size,
140 &eep->modalHeader);
141 goto out;
142 }
143
144 PR_EEP("Major Version", pBase->version >> 12);
145 PR_EEP("Minor Version", pBase->version & 0xFFF);
146 PR_EEP("Checksum", pBase->checksum);
147 PR_EEP("Length", pBase->length);
148 PR_EEP("RegDomain1", pBase->regDmn[0]);
149 PR_EEP("RegDomain2", pBase->regDmn[1]);
150 PR_EEP("TX Mask", pBase->txMask);
151 PR_EEP("RX Mask", pBase->rxMask);
152 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
153 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
154 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
155 AR5416_OPFLAGS_N_2G_HT20));
156 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
157 AR5416_OPFLAGS_N_2G_HT40));
158 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
159 AR5416_OPFLAGS_N_5G_HT20));
160 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
161 AR5416_OPFLAGS_N_5G_HT40));
162 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
163 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
164 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
165 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
166 PR_EEP("TX Gain type", pBase->txGainType);
167
168 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
169 pBase->macAddr);
170
171out:
172 if (len > size)
173 len = size;
174
175 return len;
176}
177#else
178static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
179 u8 *buf, u32 len, u32 size)
180{
181 return 0;
182}
183#endif
184
185
04cf53f4
SM		 186#undef SIZE_EEPROM_4K
187
b5aec950
S		 188static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
189{
190#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
c46917bb 191 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 192 struct ar5416_eeprom_4k *eep =
193 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
194 u16 *eepdata, temp, magic, magic2;
195 u32 sum = 0, el;
196 bool need_swap = false;
197 int i, addr;
198
199
200 if (!ath9k_hw_use_flash(ah)) {
5bb12791 201 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
b5aec950 202 &magic)) {
3800276a 203 ath_err(common, "Reading Magic # failed\n");
b5aec950
S		 204 return false;
205 }
206
226afe68
JP		 207 ath_dbg(common, ATH_DBG_EEPROM,
208 "Read Magic = 0x%04X\n", magic);
b5aec950
S		 209
210 if (magic != AR5416_EEPROM_MAGIC) {
211 magic2 = swab16(magic);
212
213 if (magic2 == AR5416_EEPROM_MAGIC) {
214 need_swap = true;
215 eepdata = (u16 *) (&ah->eeprom);
216
217 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
218 temp = swab16(*eepdata);
219 *eepdata = temp;
220 eepdata++;
221 }
222 } else {
3800276a 223 ath_err(common,
226afe68 224 "Invalid EEPROM Magic. Endianness mismatch.\n");
b5aec950
S		 225 return -EINVAL;
226 }
227 }
228 }
229
226afe68
JP		 230 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
231 need_swap ? "True" : "False");
b5aec950
S		 232
233 if (need_swap)
234 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
235 else
236 el = ah->eeprom.map4k.baseEepHeader.length;
237
238 if (el > sizeof(struct ar5416_eeprom_4k))
239 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
240 else
241 el = el / sizeof(u16);
242
243 eepdata = (u16 *)(&ah->eeprom);
244
245 for (i = 0; i < el; i++)
246 sum ^= *eepdata++;
247
248 if (need_swap) {
249 u32 integer;
250 u16 word;
251
226afe68
JP		 252 ath_dbg(common, ATH_DBG_EEPROM,
253 "EEPROM Endianness is not native.. Changing\n");
b5aec950
S		 254
255 word = swab16(eep->baseEepHeader.length);
256 eep->baseEepHeader.length = word;
257
258 word = swab16(eep->baseEepHeader.checksum);
259 eep->baseEepHeader.checksum = word;
260
261 word = swab16(eep->baseEepHeader.version);
262 eep->baseEepHeader.version = word;
263
264 word = swab16(eep->baseEepHeader.regDmn[0]);
265 eep->baseEepHeader.regDmn[0] = word;
266
267 word = swab16(eep->baseEepHeader.regDmn[1]);
268 eep->baseEepHeader.regDmn[1] = word;
269
270 word = swab16(eep->baseEepHeader.rfSilent);
271 eep->baseEepHeader.rfSilent = word;
272
273 word = swab16(eep->baseEepHeader.blueToothOptions);
274 eep->baseEepHeader.blueToothOptions = word;
275
276 word = swab16(eep->baseEepHeader.deviceCap);
277 eep->baseEepHeader.deviceCap = word;
278
279 integer = swab32(eep->modalHeader.antCtrlCommon);
280 eep->modalHeader.antCtrlCommon = integer;
281
282 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
283 integer = swab32(eep->modalHeader.antCtrlChain[i]);
284 eep->modalHeader.antCtrlChain[i] = integer;
285 }
286
4ddfcd7d 287 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
b5aec950
S		 288 word = swab16(eep->modalHeader.spurChans[i].spurChan);
289 eep->modalHeader.spurChans[i].spurChan = word;
290 }
291 }
292
293 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
294 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
3800276a
JP		 295 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
296 sum, ah->eep_ops->get_eeprom_ver(ah));
b5aec950
S		 297 return -EINVAL;
298 }
299
300 return 0;
301#undef EEPROM_4K_SIZE
302}
303
304static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
305 enum eeprom_param param)
306{
307 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
308 struct modal_eep_4k_header *pModal = &eep->modalHeader;
309 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
970bf9d4
GJ		 310 u16 ver_minor;
311
312 ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
b5aec950
S		 313
314 switch (param) {
315 case EEP_NFTHRESH_2:
316 return pModal->noiseFloorThreshCh[0];
49101676 317 case EEP_MAC_LSW:
78fa99ab 318 return get_unaligned_be16(pBase->macAddr);
49101676 319 case EEP_MAC_MID:
78fa99ab 320 return get_unaligned_be16(pBase->macAddr + 2);
49101676 321 case EEP_MAC_MSW:
78fa99ab 322 return get_unaligned_be16(pBase->macAddr + 4);
b5aec950
S		 323 case EEP_REG_0:
324 return pBase->regDmn[0];
325 case EEP_REG_1:
326 return pBase->regDmn[1];
327 case EEP_OP_CAP:
328 return pBase->deviceCap;
329 case EEP_OP_MODE:
330 return pBase->opCapFlags;
331 case EEP_RF_SILENT:
332 return pBase->rfSilent;
333 case EEP_OB_2:
7f63845f 334 return pModal->ob_0;
b5aec950 335 case EEP_DB_2:
7f63845f 336 return pModal->db1_1;
b5aec950 337 case EEP_MINOR_REV:
970bf9d4 338 return ver_minor;
b5aec950
S		 339 case EEP_TX_MASK:
340 return pBase->txMask;
341 case EEP_RX_MASK:
342 return pBase->rxMask;
343 case EEP_FRAC_N_5G:
344 return 0;
e41f0bfc
SB		 345 case EEP_PWR_TABLE_OFFSET:
346 return AR5416_PWR_TABLE_OFFSET_DB;
754dc536
VT		 347 case EEP_MODAL_VER:
348 return pModal->version;
349 case EEP_ANT_DIV_CTL1:
350 return pModal->antdiv_ctl1;
970bf9d4 351 case EEP_TXGAIN_TYPE:
f3d4505d 352 return pBase->txGainType;
b5aec950
S		 353 default:
354 return 0;
355 }
356}
357
b5aec950 358static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
e832bf10 359 struct ath9k_channel *chan)
b5aec950 360{
c46917bb 361 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 362 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
363 struct cal_data_per_freq_4k *pRawDataset;
364 u8 *pCalBChans = NULL;
365 u16 pdGainOverlap_t2;
366 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
4ddfcd7d 367 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
b5aec950 368 u16 numPiers, i, j;
b5aec950
S		 369 u16 numXpdGain, xpdMask;
370 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
371 u32 reg32, regOffset, regChainOffset;
372
373 xpdMask = pEepData->modalHeader.xpdGain;
374
375 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
376 AR5416_EEP_MINOR_VER_2) {
377 pdGainOverlap_t2 =
378 pEepData->modalHeader.pdGainOverlap;
379 } else {
380 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
381 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
382 }
383
384 pCalBChans = pEepData->calFreqPier2G;
385 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
386
387 numXpdGain = 0;
388
4ddfcd7d
FF		 389 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
390 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
b5aec950
S		 391 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
392 break;
393 xpdGainValues[numXpdGain] =
4ddfcd7d 394 (u16)(AR5416_PD_GAINS_IN_MASK - i);
b5aec950
S		 395 numXpdGain++;
396 }
397 }
398
399 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
400 (numXpdGain - 1) & 0x3);
401 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
402 xpdGainValues[0]);
403 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
404 xpdGainValues[1]);
405 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
406
407 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
1b8714f7 408 regChainOffset = i * 0x1000;
b5aec950
S		 409
410 if (pEepData->baseEepHeader.txMask & (1 << i)) {
411 pRawDataset = pEepData->calPierData2G[i];
412
115277a3 413 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
b5aec950
S		 414 pRawDataset, pCalBChans,
415 numPiers, pdGainOverlap_t2,
6eb90d46 416 gainBoundaries,
b5aec950
S		 417 pdadcValues, numXpdGain);
418
7d0d0df0
S		 419 ENABLE_REGWRITE_BUFFER(ah);
420
1b8714f7
FF		 421 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
422 SM(pdGainOverlap_t2,
423 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
424 | SM(gainBoundaries[0],
425 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
426 | SM(gainBoundaries[1],
427 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
428 | SM(gainBoundaries[2],
429 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
430 | SM(gainBoundaries[3],
431 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
b5aec950
S		 432
433 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
434 for (j = 0; j < 32; j++) {
78fa99ab 435 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
b5aec950
S		 436 REG_WRITE(ah, regOffset, reg32);
437
226afe68
JP		 438 ath_dbg(common, ATH_DBG_EEPROM,
439 "PDADC (%d,%4x): %4.4x %8.8x\n",
440 i, regChainOffset, regOffset,
441 reg32);
442 ath_dbg(common, ATH_DBG_EEPROM,
443 "PDADC: Chain %d | "
444 "PDADC %3d Value %3d | "
445 "PDADC %3d Value %3d | "
446 "PDADC %3d Value %3d | "
447 "PDADC %3d Value %3d |\n",
448 i, 4 * j, pdadcValues[4 * j],
449 4 * j + 1, pdadcValues[4 * j + 1],
450 4 * j + 2, pdadcValues[4 * j + 2],
451 4 * j + 3, pdadcValues[4 * j + 3]);
b5aec950
S		 452
453 regOffset += 4;
454 }
7d0d0df0
S		 455
456 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 457 }
458 }
b5aec950
S		 459}
460
461static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
462 struct ath9k_channel *chan,
463 int16_t *ratesArray,
464 u16 cfgCtl,
465 u16 AntennaReduction,
466 u16 twiceMaxRegulatoryPower,
467 u16 powerLimit)
468{
180d674b
S		 469#define CMP_TEST_GRP \
470 (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
471 pEepData->ctlIndex[i]) \
472 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
473 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
b5aec950 474
608b88cb 475 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 476 int i;
477 int16_t twiceLargestAntenna;
180d674b 478 u16 twiceMinEdgePower;
4ddfcd7d 479 u16 twiceMaxEdgePower = MAX_RATE_POWER;
180d674b 480 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
07b2fa5a
JP		 481 u16 numCtlModes;
482 const u16 *pCtlMode;
483 u16 ctlMode, freq;
180d674b 484 struct chan_centers centers;
b5aec950 485 struct cal_ctl_data_4k *rep;
180d674b
S		 486 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
487 static const u16 tpScaleReductionTable[5] =
4ddfcd7d 488 { 0, 3, 6, 9, MAX_RATE_POWER };
b5aec950
S		 489 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
490 0, { 0, 0, 0, 0}
491 };
492 struct cal_target_power_leg targetPowerOfdmExt = {
493 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
494 0, { 0, 0, 0, 0 }
495 };
496 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
497 0, {0, 0, 0, 0}
498 };
07b2fa5a
JP		 499 static const u16 ctlModesFor11g[] = {
500 CTL_11B, CTL_11G, CTL_2GHT20,
501 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
502 };
b5aec950
S		 503
504 ath9k_hw_get_channel_centers(ah, chan, &centers);
505
506 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
b5aec950
S		 507 twiceLargestAntenna = (int16_t)min(AntennaReduction -
508 twiceLargestAntenna, 0);
509
510 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
608b88cb 511 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
b5aec950 512 maxRegAllowedPower -=
608b88cb 513 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
b5aec950
S		 514 }
515
516 scaledPower = min(powerLimit, maxRegAllowedPower);
517 scaledPower = max((u16)0, scaledPower);
518
519 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
520 pCtlMode = ctlModesFor11g;
521
522 ath9k_hw_get_legacy_target_powers(ah, chan,
523 pEepData->calTargetPowerCck,
524 AR5416_NUM_2G_CCK_TARGET_POWERS,
525 &targetPowerCck, 4, false);
526 ath9k_hw_get_legacy_target_powers(ah, chan,
527 pEepData->calTargetPower2G,
528 AR5416_NUM_2G_20_TARGET_POWERS,
529 &targetPowerOfdm, 4, false);
530 ath9k_hw_get_target_powers(ah, chan,
531 pEepData->calTargetPower2GHT20,
532 AR5416_NUM_2G_20_TARGET_POWERS,
533 &targetPowerHt20, 8, false);
534
535 if (IS_CHAN_HT40(chan)) {
536 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
537 ath9k_hw_get_target_powers(ah, chan,
538 pEepData->calTargetPower2GHT40,
539 AR5416_NUM_2G_40_TARGET_POWERS,
540 &targetPowerHt40, 8, true);
541 ath9k_hw_get_legacy_target_powers(ah, chan,
542 pEepData->calTargetPowerCck,
543 AR5416_NUM_2G_CCK_TARGET_POWERS,
544 &targetPowerCckExt, 4, true);
545 ath9k_hw_get_legacy_target_powers(ah, chan,
546 pEepData->calTargetPower2G,
547 AR5416_NUM_2G_20_TARGET_POWERS,
548 &targetPowerOfdmExt, 4, true);
549 }
550
551 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
552 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
553 (pCtlMode[ctlMode] == CTL_2GHT40);
180d674b 554
b5aec950
S		 555 if (isHt40CtlMode)
556 freq = centers.synth_center;
557 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
558 freq = centers.ext_center;
559 else
560 freq = centers.ctl_center;
561
562 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
563 ah->eep_ops->get_eeprom_rev(ah) <= 2)
4ddfcd7d 564 twiceMaxEdgePower = MAX_RATE_POWER;
b5aec950
S		 565
566 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
180d674b
S		 567 pEepData->ctlIndex[i]; i++) {
568
569 if (CMP_TEST_GRP) {
b5aec950
S		 570 rep = &(pEepData->ctlData[i]);
571
180d674b
S		 572 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
573 freq,
574 rep->ctlEdges[
575 ar5416_get_ntxchains(ah->txchainmask) - 1],
576 IS_CHAN_2GHZ(chan),
577 AR5416_EEP4K_NUM_BAND_EDGES);
b5aec950
S		 578
579 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
580 twiceMaxEdgePower =
581 min(twiceMaxEdgePower,
582 twiceMinEdgePower);
583 } else {
584 twiceMaxEdgePower = twiceMinEdgePower;
585 break;
586 }
587 }
588 }
589
590 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
591
592 switch (pCtlMode[ctlMode]) {
593 case CTL_11B:
180d674b 594 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
b5aec950
S		 595 targetPowerCck.tPow2x[i] =
596 min((u16)targetPowerCck.tPow2x[i],
597 minCtlPower);
598 }
599 break;
600 case CTL_11G:
180d674b 601 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
b5aec950
S		 602 targetPowerOfdm.tPow2x[i] =
603 min((u16)targetPowerOfdm.tPow2x[i],
604 minCtlPower);
605 }
606 break;
607 case CTL_2GHT20:
180d674b 608 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
b5aec950
S		 609 targetPowerHt20.tPow2x[i] =
610 min((u16)targetPowerHt20.tPow2x[i],
611 minCtlPower);
612 }
613 break;
614 case CTL_11B_EXT:
180d674b
S		 615 targetPowerCckExt.tPow2x[0] =
616 min((u16)targetPowerCckExt.tPow2x[0],
617 minCtlPower);
b5aec950
S		 618 break;
619 case CTL_11G_EXT:
180d674b
S		 620 targetPowerOfdmExt.tPow2x[0] =
621 min((u16)targetPowerOfdmExt.tPow2x[0],
622 minCtlPower);
b5aec950
S		 623 break;
624 case CTL_2GHT40:
180d674b 625 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
b5aec950
S		 626 targetPowerHt40.tPow2x[i] =
627 min((u16)targetPowerHt40.tPow2x[i],
628 minCtlPower);
629 }
630 break;
631 default:
632 break;
633 }
634 }
635
180d674b
S		 636 ratesArray[rate6mb] =
637 ratesArray[rate9mb] =
638 ratesArray[rate12mb] =
639 ratesArray[rate18mb] =
640 ratesArray[rate24mb] =
641 targetPowerOfdm.tPow2x[0];
642
b5aec950
S		 643 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
644 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
645 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
646 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
647
648 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
649 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
650
651 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
652 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
653 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
654 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
655
656 if (IS_CHAN_HT40(chan)) {
657 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
658 ratesArray[rateHt40_0 + i] =
659 targetPowerHt40.tPow2x[i];
660 }
661 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
662 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
663 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
664 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
665 }
180d674b
S		 666
667#undef CMP_TEST_GRP
b5aec950
S		 668}
669
670static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
bf466fb6
S		 671 struct ath9k_channel *chan,
672 u16 cfgCtl,
673 u8 twiceAntennaReduction,
674 u8 twiceMaxRegulatoryPower,
de40f316 675 u8 powerLimit, bool test)
b5aec950 676{
608b88cb 677 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 678 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
679 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
680 int16_t ratesArray[Ar5416RateSize];
b5aec950
S		 681 u8 ht40PowerIncForPdadc = 2;
682 int i;
683
684 memset(ratesArray, 0, sizeof(ratesArray));
685
686 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
687 AR5416_EEP_MINOR_VER_2) {
688 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
689 }
690
691 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
bf466fb6
S		 692 &ratesArray[0], cfgCtl,
693 twiceAntennaReduction,
694 twiceMaxRegulatoryPower,
695 powerLimit);
b5aec950 696
e832bf10 697 ath9k_hw_set_4k_power_cal_table(ah, chan);
b5aec950 698
de40f316 699 regulatory->max_power_level = 0;
b5aec950 700 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4ddfcd7d
FF		 701 if (ratesArray[i] > MAX_RATE_POWER)
702 ratesArray[i] = MAX_RATE_POWER;
de40f316
FF		 703
704 if (ratesArray[i] > regulatory->max_power_level)
705 regulatory->max_power_level = ratesArray[i];
b5aec950
S		 706 }
707
de40f316
FF		 708 if (test)
709 return;
bf466fb6 710
1b8714f7
FF		 711 for (i = 0; i < Ar5416RateSize; i++)
712 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
b5aec950 713
7d0d0df0
S		 714 ENABLE_REGWRITE_BUFFER(ah);
715
bf466fb6 716 /* OFDM power per rate */
b5aec950
S		 717 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
718 ATH9K_POW_SM(ratesArray[rate18mb], 24)
719 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
720 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
721 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
722 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
723 ATH9K_POW_SM(ratesArray[rate54mb], 24)
724 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
725 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
726 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
727
bf466fb6
S		 728 /* CCK power per rate */
729 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
730 ATH9K_POW_SM(ratesArray[rate2s], 24)
731 | ATH9K_POW_SM(ratesArray[rate2l], 16)
732 | ATH9K_POW_SM(ratesArray[rateXr], 8)
733 | ATH9K_POW_SM(ratesArray[rate1l], 0));
734 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
735 ATH9K_POW_SM(ratesArray[rate11s], 24)
736 | ATH9K_POW_SM(ratesArray[rate11l], 16)
737 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
738 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
739
740 /* HT20 power per rate */
b5aec950
S		 741 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
742 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
743 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
744 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
745 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
746 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
747 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
748 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
749 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
750 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
751
bf466fb6 752 /* HT40 power per rate */
b5aec950
S		 753 if (IS_CHAN_HT40(chan)) {
754 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
755 ATH9K_POW_SM(ratesArray[rateHt40_3] +
756 ht40PowerIncForPdadc, 24)
757 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
758 ht40PowerIncForPdadc, 16)
759 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
760 ht40PowerIncForPdadc, 8)
761 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
762 ht40PowerIncForPdadc, 0));
763 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
764 ATH9K_POW_SM(ratesArray[rateHt40_7] +
765 ht40PowerIncForPdadc, 24)
766 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
767 ht40PowerIncForPdadc, 16)
768 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
769 ht40PowerIncForPdadc, 8)
770 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
771 ht40PowerIncForPdadc, 0));
b5aec950
S		 772 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
773 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
774 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
775 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
776 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
777 }
7d0d0df0
S		 778
779 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 780}
781
b5aec950
S		 782static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
783 struct modal_eep_4k_header *pModal,
784 struct ar5416_eeprom_4k *eep,
a37414a2 785 u8 txRxAttenLocal)
b5aec950 786{
a37414a2 787 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
b5aec950
S		 788 pModal->antCtrlChain[0]);
789
a37414a2
S		 790 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
791 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
b5aec950
S		 792 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
793 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
794 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
795 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
796
797 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
798 AR5416_EEP_MINOR_VER_3) {
799 txRxAttenLocal = pModal->txRxAttenCh[0];
800
a37414a2 801 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950 802 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
a37414a2 803 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950 804 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
a37414a2 805 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950
S		 806 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
807 pModal->xatten2Margin[0]);
a37414a2 808 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950
S		 809 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
810
811 /* Set the block 1 value to block 0 value */
812 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
813 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
814 pModal->bswMargin[0]);
815 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
816 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
817 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
818 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
819 pModal->xatten2Margin[0]);
820 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
821 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
822 pModal->xatten2Db[0]);
823 }
824
a37414a2 825 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
b5aec950 826 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
a37414a2 827 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
b5aec950
S		 828 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
829
830 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
831 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
832 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
833 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
b5aec950
S		 834}
835
836/*
837 * Read EEPROM header info and program the device for correct operation
838 * given the channel value.
839 */
840static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
841 struct ath9k_channel *chan)
842{
843 struct modal_eep_4k_header *pModal;
844 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
d88525e8 845 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
b5aec950
S		 846 u8 txRxAttenLocal;
847 u8 ob[5], db1[5], db2[5];
848 u8 ant_div_control1, ant_div_control2;
1b8714f7 849 u8 bb_desired_scale;
b5aec950
S		 850 u32 regVal;
851
852 pModal = &eep->modalHeader;
853 txRxAttenLocal = 23;
854
df3c8b2b 855 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
b5aec950
S		 856
857 /* Single chain for 4K EEPROM*/
a37414a2 858 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
b5aec950
S		 859
860 /* Initialize Ant Diversity settings from EEPROM */
861 if (pModal->version >= 3) {
7f63845f
S		 862 ant_div_control1 = pModal->antdiv_ctl1;
863 ant_div_control2 = pModal->antdiv_ctl2;
864
865 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
866 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
867
868 regVal |= SM(ant_div_control1,
869 AR_PHY_9285_ANT_DIV_CTL);
870 regVal |= SM(ant_div_control2,
871 AR_PHY_9285_ANT_DIV_ALT_LNACONF);
872 regVal |= SM((ant_div_control2 >> 2),
873 AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
874 regVal |= SM((ant_div_control1 >> 1),
875 AR_PHY_9285_ANT_DIV_ALT_GAINTB);
876 regVal |= SM((ant_div_control1 >> 2),
877 AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
878
879
880 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
881 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
882 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
883 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
884 regVal |= SM((ant_div_control1 >> 3),
885 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
886
887 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
888 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
b5aec950
S		 889 }
890
891 if (pModal->version >= 2) {
7f63845f
S		 892 ob[0] = pModal->ob_0;
893 ob[1] = pModal->ob_1;
894 ob[2] = pModal->ob_2;
895 ob[3] = pModal->ob_3;
896 ob[4] = pModal->ob_4;
897
898 db1[0] = pModal->db1_0;
899 db1[1] = pModal->db1_1;
900 db1[2] = pModal->db1_2;
901 db1[3] = pModal->db1_3;
902 db1[4] = pModal->db1_4;
903
904 db2[0] = pModal->db2_0;
905 db2[1] = pModal->db2_1;
906 db2[2] = pModal->db2_2;
907 db2[3] = pModal->db2_3;
908 db2[4] = pModal->db2_4;
b5aec950 909 } else if (pModal->version == 1) {
7f63845f
S		 910 ob[0] = pModal->ob_0;
911 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
912 db1[0] = pModal->db1_0;
913 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
914 db2[0] = pModal->db2_0;
915 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
b5aec950
S		 916 } else {
917 int i;
7f63845f 918
b5aec950 919 for (i = 0; i < 5; i++) {
7f63845f
S		 920 ob[i] = pModal->ob_0;
921 db1[i] = pModal->db1_0;
922 db2[i] = pModal->db1_0;
b5aec950
S		 923 }
924 }
925
926 if (AR_SREV_9271(ah)) {
927 ath9k_hw_analog_shift_rmw(ah,
928 AR9285_AN_RF2G3,
929 AR9271_AN_RF2G3_OB_cck,
930 AR9271_AN_RF2G3_OB_cck_S,
931 ob[0]);
932 ath9k_hw_analog_shift_rmw(ah,
933 AR9285_AN_RF2G3,
934 AR9271_AN_RF2G3_OB_psk,
935 AR9271_AN_RF2G3_OB_psk_S,
936 ob[1]);
937 ath9k_hw_analog_shift_rmw(ah,
938 AR9285_AN_RF2G3,
939 AR9271_AN_RF2G3_OB_qam,
940 AR9271_AN_RF2G3_OB_qam_S,
941 ob[2]);
942 ath9k_hw_analog_shift_rmw(ah,
943 AR9285_AN_RF2G3,
944 AR9271_AN_RF2G3_DB_1,
945 AR9271_AN_RF2G3_DB_1_S,
946 db1[0]);
947 ath9k_hw_analog_shift_rmw(ah,
948 AR9285_AN_RF2G4,
949 AR9271_AN_RF2G4_DB_2,
950 AR9271_AN_RF2G4_DB_2_S,
951 db2[0]);
952 } else {
953 ath9k_hw_analog_shift_rmw(ah,
954 AR9285_AN_RF2G3,
955 AR9285_AN_RF2G3_OB_0,
956 AR9285_AN_RF2G3_OB_0_S,
957 ob[0]);
958 ath9k_hw_analog_shift_rmw(ah,
959 AR9285_AN_RF2G3,
960 AR9285_AN_RF2G3_OB_1,
961 AR9285_AN_RF2G3_OB_1_S,
962 ob[1]);
963 ath9k_hw_analog_shift_rmw(ah,
964 AR9285_AN_RF2G3,
965 AR9285_AN_RF2G3_OB_2,
966 AR9285_AN_RF2G3_OB_2_S,
967 ob[2]);
968 ath9k_hw_analog_shift_rmw(ah,
969 AR9285_AN_RF2G3,
970 AR9285_AN_RF2G3_OB_3,
971 AR9285_AN_RF2G3_OB_3_S,
972 ob[3]);
973 ath9k_hw_analog_shift_rmw(ah,
974 AR9285_AN_RF2G3,
975 AR9285_AN_RF2G3_OB_4,
976 AR9285_AN_RF2G3_OB_4_S,
977 ob[4]);
978
979 ath9k_hw_analog_shift_rmw(ah,
980 AR9285_AN_RF2G3,
981 AR9285_AN_RF2G3_DB1_0,
982 AR9285_AN_RF2G3_DB1_0_S,
983 db1[0]);
984 ath9k_hw_analog_shift_rmw(ah,
985 AR9285_AN_RF2G3,
986 AR9285_AN_RF2G3_DB1_1,
987 AR9285_AN_RF2G3_DB1_1_S,
988 db1[1]);
989 ath9k_hw_analog_shift_rmw(ah,
990 AR9285_AN_RF2G3,
991 AR9285_AN_RF2G3_DB1_2,
992 AR9285_AN_RF2G3_DB1_2_S,
993 db1[2]);
994 ath9k_hw_analog_shift_rmw(ah,
995 AR9285_AN_RF2G4,
996 AR9285_AN_RF2G4_DB1_3,
997 AR9285_AN_RF2G4_DB1_3_S,
998 db1[3]);
999 ath9k_hw_analog_shift_rmw(ah,
1000 AR9285_AN_RF2G4,
1001 AR9285_AN_RF2G4_DB1_4,
1002 AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1003
1004 ath9k_hw_analog_shift_rmw(ah,
1005 AR9285_AN_RF2G4,
1006 AR9285_AN_RF2G4_DB2_0,
1007 AR9285_AN_RF2G4_DB2_0_S,
1008 db2[0]);
1009 ath9k_hw_analog_shift_rmw(ah,
1010 AR9285_AN_RF2G4,
1011 AR9285_AN_RF2G4_DB2_1,
1012 AR9285_AN_RF2G4_DB2_1_S,
1013 db2[1]);
1014 ath9k_hw_analog_shift_rmw(ah,
1015 AR9285_AN_RF2G4,
1016 AR9285_AN_RF2G4_DB2_2,
1017 AR9285_AN_RF2G4_DB2_2_S,
1018 db2[2]);
1019 ath9k_hw_analog_shift_rmw(ah,
1020 AR9285_AN_RF2G4,
1021 AR9285_AN_RF2G4_DB2_3,
1022 AR9285_AN_RF2G4_DB2_3_S,
1023 db2[3]);
1024 ath9k_hw_analog_shift_rmw(ah,
1025 AR9285_AN_RF2G4,
1026 AR9285_AN_RF2G4_DB2_4,
1027 AR9285_AN_RF2G4_DB2_4_S,
1028 db2[4]);
1029 }
1030
1031
b5aec950
S		 1032 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1033 pModal->switchSettling);
1034 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1035 pModal->adcDesiredSize);
1036
1037 REG_WRITE(ah, AR_PHY_RF_CTL4,
1038 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1039 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1040 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1041 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1042
1043 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1044 pModal->txEndToRxOn);
0cab6559
LR		 1045
1046 if (AR_SREV_9271_10(ah))
1047 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1048 pModal->txEndToRxOn);
b5aec950
S		 1049 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1050 pModal->thresh62);
1051 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1052 pModal->thresh62);
1053
1054 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1055 AR5416_EEP_MINOR_VER_2) {
1056 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1057 pModal->txFrameToDataStart);
1058 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1059 pModal->txFrameToPaOn);
1060 }
1061
1062 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1063 AR5416_EEP_MINOR_VER_3) {
1064 if (IS_CHAN_HT40(chan))
1065 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1066 AR_PHY_SETTLING_SWITCH,
1067 pModal->swSettleHt40);
1068 }
1b8714f7
FF		 1069
1070 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
1071 EEP_4K_BB_DESIRED_SCALE_MASK);
1072 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
1073 u32 pwrctrl, mask, clr;
1074
1075 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
1076 pwrctrl = mask * bb_desired_scale;
1077 clr = mask * 0x1f;
1078 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1079 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1080 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1081
1082 mask = BIT(0)|BIT(5)|BIT(15);
1083 pwrctrl = mask * bb_desired_scale;
1084 clr = mask * 0x1f;
1085 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1086
1087 mask = BIT(0)|BIT(5);
1088 pwrctrl = mask * bb_desired_scale;
1089 clr = mask * 0x1f;
1090 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1091 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
d88525e8 1092 }
b5aec950
S		 1093}
1094
b5aec950
S		 1095static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1096{
1097#define EEP_MAP4K_SPURCHAN \
1098 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
c46917bb 1099 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 1100
1101 u16 spur_val = AR_NO_SPUR;
1102
226afe68
JP		 1103 ath_dbg(common, ATH_DBG_ANI,
1104 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1105 i, is2GHz, ah->config.spurchans[i][is2GHz]);
b5aec950
S		 1106
1107 switch (ah->config.spurmode) {
1108 case SPUR_DISABLE:
1109 break;
1110 case SPUR_ENABLE_IOCTL:
1111 spur_val = ah->config.spurchans[i][is2GHz];
226afe68
JP		 1112 ath_dbg(common, ATH_DBG_ANI,
1113 "Getting spur val from new loc. %d\n", spur_val);
b5aec950
S		 1114 break;
1115 case SPUR_ENABLE_EEPROM:
1116 spur_val = EEP_MAP4K_SPURCHAN;
1117 break;
1118 }
1119
1120 return spur_val;
1121
1122#undef EEP_MAP4K_SPURCHAN
1123}
1124
1125const struct eeprom_ops eep_4k_ops = {
1126 .check_eeprom = ath9k_hw_4k_check_eeprom,
1127 .get_eeprom = ath9k_hw_4k_get_eeprom,
1128 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
4f011a2e 1129 .dump_eeprom = ath9k_hw_4k_dump_eeprom,
b5aec950
S		 1130 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1131 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
b5aec950 1132 .set_board_values = ath9k_hw_4k_set_board_values,
b5aec950
S		 1133 .set_txpower = ath9k_hw_4k_set_txpower,
1134 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1135};
Linux kernel - Deliverables
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