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cfg80211: Return beacon loss count in station
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / eeprom_4k.c
CommitLineData
b5aec950 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
b5aec950
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
78fa99ab 17#include <asm/unaligned.h>
c46917bb 18#include "hw.h"
8fe65368 19#include "ar9002_phy.h"
b5aec950
S		 20
21static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
22{
23 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
24}
25
26static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
27{
28 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
29}
30
b5aec950 31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
04cf53f4
SM		 32
33static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
34{
c46917bb 35 struct ath_common *common = ath9k_hw_common(ah);
b5aec950 36 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
04cf53f4 37 int addr, eep_start_loc = 64;
b5aec950
S		 38
39 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
5bb12791 40 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
226afe68
JP		 41 ath_dbg(common, ATH_DBG_EEPROM,
42 "Unable to read eeprom region\n");
b5aec950
S		 43 return false;
44 }
45 eep_data++;
46 }
47
48 return true;
b5aec950
S		 49}
50
04cf53f4
SM		 51static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
52{
53 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
54
55 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
56
57 return true;
58}
59
60static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
61{
62 struct ath_common *common = ath9k_hw_common(ah);
63
64 if (!ath9k_hw_use_flash(ah)) {
65 ath_dbg(common, ATH_DBG_EEPROM,
66 "Reading from EEPROM, not flash\n");
67 }
68
69 if (common->bus_ops->ath_bus_type == ATH_USB)
70 return __ath9k_hw_usb_4k_fill_eeprom(ah);
71 else
72 return __ath9k_hw_4k_fill_eeprom(ah);
73}
74
4f011a2e
RM		 75#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
76static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size,
77 struct modal_eep_4k_header *modal_hdr)
78{
79 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
80 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
81 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
82 PR_EEP("Switch Settle", modal_hdr->switchSettling);
83 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
84 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
85 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
86 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
87 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
88 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
89 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
90 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
91 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
92 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
93 PR_EEP("xpdGain", modal_hdr->xpdGain);
94 PR_EEP("External PD", modal_hdr->xpd);
95 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
96 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
97 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
98 PR_EEP("O/D Bias Version", modal_hdr->version);
99 PR_EEP("CCK OutputBias", modal_hdr->ob_0);
100 PR_EEP("BPSK OutputBias", modal_hdr->ob_1);
101 PR_EEP("QPSK OutputBias", modal_hdr->ob_2);
102 PR_EEP("16QAM OutputBias", modal_hdr->ob_3);
103 PR_EEP("64QAM OutputBias", modal_hdr->ob_4);
104 PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0);
105 PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1);
106 PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2);
107 PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3);
108 PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4);
109 PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0);
110 PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1);
111 PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2);
112 PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3);
113 PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4);
114 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
115 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
116 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
117 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
118 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
119 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
120 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
121 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
122 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
123 PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1);
124 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2);
125 PR_EEP("TX Diversity", modal_hdr->tx_diversity);
126
127 return len;
128}
129
130static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
131 u8 *buf, u32 len, u32 size)
132{
133 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
134 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
135
136 if (!dump_base_hdr) {
137 len += snprintf(buf + len, size - len,
138 "%20s :\n", "2GHz modal Header");
139 len += ath9k_dump_4k_modal_eeprom(buf, len, size,
140 &eep->modalHeader);
141 goto out;
142 }
143
144 PR_EEP("Major Version", pBase->version >> 12);
145 PR_EEP("Minor Version", pBase->version & 0xFFF);
146 PR_EEP("Checksum", pBase->checksum);
147 PR_EEP("Length", pBase->length);
148 PR_EEP("RegDomain1", pBase->regDmn[0]);
149 PR_EEP("RegDomain2", pBase->regDmn[1]);
150 PR_EEP("TX Mask", pBase->txMask);
151 PR_EEP("RX Mask", pBase->rxMask);
152 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
153 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
154 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
155 AR5416_OPFLAGS_N_2G_HT20));
156 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
157 AR5416_OPFLAGS_N_2G_HT40));
158 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
159 AR5416_OPFLAGS_N_5G_HT20));
160 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
161 AR5416_OPFLAGS_N_5G_HT40));
162 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
163 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
164 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
165 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
166 PR_EEP("TX Gain type", pBase->txGainType);
167
168 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
169 pBase->macAddr);
170
171out:
172 if (len > size)
173 len = size;
174
175 return len;
176}
177#else
178static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
179 u8 *buf, u32 len, u32 size)
180{
181 return 0;
182}
183#endif
184
185
04cf53f4
SM		 186#undef SIZE_EEPROM_4K
187
b5aec950
S		 188static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
189{
190#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
c46917bb 191 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 192 struct ar5416_eeprom_4k *eep =
193 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
194 u16 *eepdata, temp, magic, magic2;
195 u32 sum = 0, el;
196 bool need_swap = false;
197 int i, addr;
198
199
200 if (!ath9k_hw_use_flash(ah)) {
5bb12791 201 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
b5aec950 202 &magic)) {
3800276a 203 ath_err(common, "Reading Magic # failed\n");
b5aec950
S		 204 return false;
205 }
206
226afe68
JP		 207 ath_dbg(common, ATH_DBG_EEPROM,
208 "Read Magic = 0x%04X\n", magic);
b5aec950
S		 209
210 if (magic != AR5416_EEPROM_MAGIC) {
211 magic2 = swab16(magic);
212
213 if (magic2 == AR5416_EEPROM_MAGIC) {
214 need_swap = true;
215 eepdata = (u16 *) (&ah->eeprom);
216
217 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
218 temp = swab16(*eepdata);
219 *eepdata = temp;
220 eepdata++;
221 }
222 } else {
3800276a 223 ath_err(common,
226afe68 224 "Invalid EEPROM Magic. Endianness mismatch.\n");
b5aec950
S		 225 return -EINVAL;
226 }
227 }
228 }
229
226afe68
JP		 230 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
231 need_swap ? "True" : "False");
b5aec950
S		 232
233 if (need_swap)
234 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
235 else
236 el = ah->eeprom.map4k.baseEepHeader.length;
237
238 if (el > sizeof(struct ar5416_eeprom_4k))
239 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
240 else
241 el = el / sizeof(u16);
242
243 eepdata = (u16 *)(&ah->eeprom);
244
245 for (i = 0; i < el; i++)
246 sum ^= *eepdata++;
247
248 if (need_swap) {
249 u32 integer;
250 u16 word;
251
226afe68
JP		 252 ath_dbg(common, ATH_DBG_EEPROM,
253 "EEPROM Endianness is not native.. Changing\n");
b5aec950
S		 254
255 word = swab16(eep->baseEepHeader.length);
256 eep->baseEepHeader.length = word;
257
258 word = swab16(eep->baseEepHeader.checksum);
259 eep->baseEepHeader.checksum = word;
260
261 word = swab16(eep->baseEepHeader.version);
262 eep->baseEepHeader.version = word;
263
264 word = swab16(eep->baseEepHeader.regDmn[0]);
265 eep->baseEepHeader.regDmn[0] = word;
266
267 word = swab16(eep->baseEepHeader.regDmn[1]);
268 eep->baseEepHeader.regDmn[1] = word;
269
270 word = swab16(eep->baseEepHeader.rfSilent);
271 eep->baseEepHeader.rfSilent = word;
272
273 word = swab16(eep->baseEepHeader.blueToothOptions);
274 eep->baseEepHeader.blueToothOptions = word;
275
276 word = swab16(eep->baseEepHeader.deviceCap);
277 eep->baseEepHeader.deviceCap = word;
278
279 integer = swab32(eep->modalHeader.antCtrlCommon);
280 eep->modalHeader.antCtrlCommon = integer;
281
282 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
283 integer = swab32(eep->modalHeader.antCtrlChain[i]);
284 eep->modalHeader.antCtrlChain[i] = integer;
285 }
286
4ddfcd7d 287 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
b5aec950
S		 288 word = swab16(eep->modalHeader.spurChans[i].spurChan);
289 eep->modalHeader.spurChans[i].spurChan = word;
290 }
291 }
292
293 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
294 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
3800276a
JP		 295 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
296 sum, ah->eep_ops->get_eeprom_ver(ah));
b5aec950
S		 297 return -EINVAL;
298 }
299
300 return 0;
301#undef EEPROM_4K_SIZE
302}
303
304static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
305 enum eeprom_param param)
306{
307 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
308 struct modal_eep_4k_header *pModal = &eep->modalHeader;
309 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
970bf9d4
GJ		 310 u16 ver_minor;
311
312 ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
b5aec950
S		 313
314 switch (param) {
315 case EEP_NFTHRESH_2:
316 return pModal->noiseFloorThreshCh[0];
49101676 317 case EEP_MAC_LSW:
78fa99ab 318 return get_unaligned_be16(pBase->macAddr);
49101676 319 case EEP_MAC_MID:
78fa99ab 320 return get_unaligned_be16(pBase->macAddr + 2);
49101676 321 case EEP_MAC_MSW:
78fa99ab 322 return get_unaligned_be16(pBase->macAddr + 4);
b5aec950
S		 323 case EEP_REG_0:
324 return pBase->regDmn[0];
b5aec950
S		 325 case EEP_OP_CAP:
326 return pBase->deviceCap;
327 case EEP_OP_MODE:
328 return pBase->opCapFlags;
329 case EEP_RF_SILENT:
330 return pBase->rfSilent;
331 case EEP_OB_2:
7f63845f 332 return pModal->ob_0;
b5aec950 333 case EEP_DB_2:
7f63845f 334 return pModal->db1_1;
b5aec950 335 case EEP_MINOR_REV:
970bf9d4 336 return ver_minor;
b5aec950
S		 337 case EEP_TX_MASK:
338 return pBase->txMask;
339 case EEP_RX_MASK:
340 return pBase->rxMask;
341 case EEP_FRAC_N_5G:
342 return 0;
e41f0bfc
SB		 343 case EEP_PWR_TABLE_OFFSET:
344 return AR5416_PWR_TABLE_OFFSET_DB;
754dc536
VT		 345 case EEP_MODAL_VER:
346 return pModal->version;
347 case EEP_ANT_DIV_CTL1:
348 return pModal->antdiv_ctl1;
970bf9d4 349 case EEP_TXGAIN_TYPE:
f3d4505d 350 return pBase->txGainType;
ca2c68cc
FF		 351 case EEP_ANTENNA_GAIN_2G:
352 return pModal->antennaGainCh[0];
b5aec950
S		 353 default:
354 return 0;
355 }
356}
357
b5aec950 358static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
e832bf10 359 struct ath9k_channel *chan)
b5aec950 360{
c46917bb 361 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 362 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
363 struct cal_data_per_freq_4k *pRawDataset;
364 u8 *pCalBChans = NULL;
365 u16 pdGainOverlap_t2;
366 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
4ddfcd7d 367 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
b5aec950 368 u16 numPiers, i, j;
b5aec950
S		 369 u16 numXpdGain, xpdMask;
370 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
371 u32 reg32, regOffset, regChainOffset;
372
373 xpdMask = pEepData->modalHeader.xpdGain;
374
375 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
376 AR5416_EEP_MINOR_VER_2) {
377 pdGainOverlap_t2 =
378 pEepData->modalHeader.pdGainOverlap;
379 } else {
380 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
381 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
382 }
383
384 pCalBChans = pEepData->calFreqPier2G;
385 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
386
387 numXpdGain = 0;
388
4ddfcd7d
FF		 389 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
390 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
b5aec950
S		 391 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
392 break;
393 xpdGainValues[numXpdGain] =
4ddfcd7d 394 (u16)(AR5416_PD_GAINS_IN_MASK - i);
b5aec950
S		 395 numXpdGain++;
396 }
397 }
398
399 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
400 (numXpdGain - 1) & 0x3);
401 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
402 xpdGainValues[0]);
403 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
404 xpdGainValues[1]);
405 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
406
407 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
1b8714f7 408 regChainOffset = i * 0x1000;
b5aec950
S		 409
410 if (pEepData->baseEepHeader.txMask & (1 << i)) {
411 pRawDataset = pEepData->calPierData2G[i];
412
115277a3 413 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
b5aec950
S		 414 pRawDataset, pCalBChans,
415 numPiers, pdGainOverlap_t2,
6eb90d46 416 gainBoundaries,
b5aec950
S		 417 pdadcValues, numXpdGain);
418
7d0d0df0
S		 419 ENABLE_REGWRITE_BUFFER(ah);
420
1b8714f7
FF		 421 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
422 SM(pdGainOverlap_t2,
423 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
424 | SM(gainBoundaries[0],
425 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
426 | SM(gainBoundaries[1],
427 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
428 | SM(gainBoundaries[2],
429 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
430 | SM(gainBoundaries[3],
431 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
b5aec950
S		 432
433 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
434 for (j = 0; j < 32; j++) {
78fa99ab 435 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
b5aec950
S		 436 REG_WRITE(ah, regOffset, reg32);
437
226afe68
JP		 438 ath_dbg(common, ATH_DBG_EEPROM,
439 "PDADC (%d,%4x): %4.4x %8.8x\n",
440 i, regChainOffset, regOffset,
441 reg32);
442 ath_dbg(common, ATH_DBG_EEPROM,
443 "PDADC: Chain %d | "
444 "PDADC %3d Value %3d | "
445 "PDADC %3d Value %3d | "
446 "PDADC %3d Value %3d | "
447 "PDADC %3d Value %3d |\n",
448 i, 4 * j, pdadcValues[4 * j],
449 4 * j + 1, pdadcValues[4 * j + 1],
450 4 * j + 2, pdadcValues[4 * j + 2],
451 4 * j + 3, pdadcValues[4 * j + 3]);
b5aec950
S		 452
453 regOffset += 4;
454 }
7d0d0df0
S		 455
456 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 457 }
458 }
b5aec950
S		 459}
460
461static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
462 struct ath9k_channel *chan,
463 int16_t *ratesArray,
464 u16 cfgCtl,
ca2c68cc 465 u16 antenna_reduction,
b5aec950
S		 466 u16 powerLimit)
467{
180d674b
S		 468#define CMP_TEST_GRP \
469 (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
470 pEepData->ctlIndex[i]) \
471 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
472 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
b5aec950
S		 473
474 int i;
180d674b 475 u16 twiceMinEdgePower;
a261f0e9 476 u16 twiceMaxEdgePower;
ca2c68cc 477 u16 scaledPower = 0, minCtlPower;
07b2fa5a
JP		 478 u16 numCtlModes;
479 const u16 *pCtlMode;
480 u16 ctlMode, freq;
180d674b 481 struct chan_centers centers;
b5aec950 482 struct cal_ctl_data_4k *rep;
180d674b 483 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
b5aec950
S		 484 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
485 0, { 0, 0, 0, 0}
486 };
487 struct cal_target_power_leg targetPowerOfdmExt = {
488 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
489 0, { 0, 0, 0, 0 }
490 };
491 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
492 0, {0, 0, 0, 0}
493 };
07b2fa5a
JP		 494 static const u16 ctlModesFor11g[] = {
495 CTL_11B, CTL_11G, CTL_2GHT20,
496 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
497 };
b5aec950
S		 498
499 ath9k_hw_get_channel_centers(ah, chan, &centers);
500
ca2c68cc 501 scaledPower = powerLimit - antenna_reduction;
b5aec950
S		 502 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
503 pCtlMode = ctlModesFor11g;
504
505 ath9k_hw_get_legacy_target_powers(ah, chan,
506 pEepData->calTargetPowerCck,
507 AR5416_NUM_2G_CCK_TARGET_POWERS,
508 &targetPowerCck, 4, false);
509 ath9k_hw_get_legacy_target_powers(ah, chan,
510 pEepData->calTargetPower2G,
511 AR5416_NUM_2G_20_TARGET_POWERS,
512 &targetPowerOfdm, 4, false);
513 ath9k_hw_get_target_powers(ah, chan,
514 pEepData->calTargetPower2GHT20,
515 AR5416_NUM_2G_20_TARGET_POWERS,
516 &targetPowerHt20, 8, false);
517
518 if (IS_CHAN_HT40(chan)) {
519 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
520 ath9k_hw_get_target_powers(ah, chan,
521 pEepData->calTargetPower2GHT40,
522 AR5416_NUM_2G_40_TARGET_POWERS,
523 &targetPowerHt40, 8, true);
524 ath9k_hw_get_legacy_target_powers(ah, chan,
525 pEepData->calTargetPowerCck,
526 AR5416_NUM_2G_CCK_TARGET_POWERS,
527 &targetPowerCckExt, 4, true);
528 ath9k_hw_get_legacy_target_powers(ah, chan,
529 pEepData->calTargetPower2G,
530 AR5416_NUM_2G_20_TARGET_POWERS,
531 &targetPowerOfdmExt, 4, true);
532 }
533
534 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
535 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
536 (pCtlMode[ctlMode] == CTL_2GHT40);
180d674b 537
b5aec950
S		 538 if (isHt40CtlMode)
539 freq = centers.synth_center;
540 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
541 freq = centers.ext_center;
542 else
543 freq = centers.ctl_center;
544
a261f0e9 545 twiceMaxEdgePower = MAX_RATE_POWER;
b5aec950
S		 546
547 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
180d674b
S		 548 pEepData->ctlIndex[i]; i++) {
549
550 if (CMP_TEST_GRP) {
b5aec950
S		 551 rep = &(pEepData->ctlData[i]);
552
180d674b
S		 553 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
554 freq,
555 rep->ctlEdges[
556 ar5416_get_ntxchains(ah->txchainmask) - 1],
557 IS_CHAN_2GHZ(chan),
558 AR5416_EEP4K_NUM_BAND_EDGES);
b5aec950
S		 559
560 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
561 twiceMaxEdgePower =
562 min(twiceMaxEdgePower,
563 twiceMinEdgePower);
564 } else {
565 twiceMaxEdgePower = twiceMinEdgePower;
566 break;
567 }
568 }
569 }
570
571 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
572
573 switch (pCtlMode[ctlMode]) {
574 case CTL_11B:
180d674b 575 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
b5aec950
S		 576 targetPowerCck.tPow2x[i] =
577 min((u16)targetPowerCck.tPow2x[i],
578 minCtlPower);
579 }
580 break;
581 case CTL_11G:
180d674b 582 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
b5aec950
S		 583 targetPowerOfdm.tPow2x[i] =
584 min((u16)targetPowerOfdm.tPow2x[i],
585 minCtlPower);
586 }
587 break;
588 case CTL_2GHT20:
180d674b 589 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
b5aec950
S		 590 targetPowerHt20.tPow2x[i] =
591 min((u16)targetPowerHt20.tPow2x[i],
592 minCtlPower);
593 }
594 break;
595 case CTL_11B_EXT:
180d674b
S		 596 targetPowerCckExt.tPow2x[0] =
597 min((u16)targetPowerCckExt.tPow2x[0],
598 minCtlPower);
b5aec950
S		 599 break;
600 case CTL_11G_EXT:
180d674b
S		 601 targetPowerOfdmExt.tPow2x[0] =
602 min((u16)targetPowerOfdmExt.tPow2x[0],
603 minCtlPower);
b5aec950
S		 604 break;
605 case CTL_2GHT40:
180d674b 606 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
b5aec950
S		 607 targetPowerHt40.tPow2x[i] =
608 min((u16)targetPowerHt40.tPow2x[i],
609 minCtlPower);
610 }
611 break;
612 default:
613 break;
614 }
615 }
616
180d674b
S		 617 ratesArray[rate6mb] =
618 ratesArray[rate9mb] =
619 ratesArray[rate12mb] =
620 ratesArray[rate18mb] =
621 ratesArray[rate24mb] =
622 targetPowerOfdm.tPow2x[0];
623
b5aec950
S		 624 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
625 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
626 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
627 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
628
629 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
630 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
631
632 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
633 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
634 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
635 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
636
637 if (IS_CHAN_HT40(chan)) {
638 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
639 ratesArray[rateHt40_0 + i] =
640 targetPowerHt40.tPow2x[i];
641 }
642 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
643 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
644 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
645 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
646 }
180d674b
S		 647
648#undef CMP_TEST_GRP
b5aec950
S		 649}
650
651static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
bf466fb6
S		 652 struct ath9k_channel *chan,
653 u16 cfgCtl,
654 u8 twiceAntennaReduction,
de40f316 655 u8 powerLimit, bool test)
b5aec950 656{
608b88cb 657 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 658 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
659 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
660 int16_t ratesArray[Ar5416RateSize];
b5aec950
S		 661 u8 ht40PowerIncForPdadc = 2;
662 int i;
663
664 memset(ratesArray, 0, sizeof(ratesArray));
665
666 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
667 AR5416_EEP_MINOR_VER_2) {
668 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
669 }
670
671 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
bf466fb6
S		 672 &ratesArray[0], cfgCtl,
673 twiceAntennaReduction,
bf466fb6 674 powerLimit);
b5aec950 675
e832bf10 676 ath9k_hw_set_4k_power_cal_table(ah, chan);
b5aec950 677
de40f316 678 regulatory->max_power_level = 0;
b5aec950 679 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4ddfcd7d
FF		 680 if (ratesArray[i] > MAX_RATE_POWER)
681 ratesArray[i] = MAX_RATE_POWER;
de40f316
FF		 682
683 if (ratesArray[i] > regulatory->max_power_level)
684 regulatory->max_power_level = ratesArray[i];
b5aec950
S		 685 }
686
de40f316
FF		 687 if (test)
688 return;
bf466fb6 689
1b8714f7
FF		 690 for (i = 0; i < Ar5416RateSize; i++)
691 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
b5aec950 692
7d0d0df0
S		 693 ENABLE_REGWRITE_BUFFER(ah);
694
bf466fb6 695 /* OFDM power per rate */
b5aec950
S		 696 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
697 ATH9K_POW_SM(ratesArray[rate18mb], 24)
698 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
699 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
700 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
701 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
702 ATH9K_POW_SM(ratesArray[rate54mb], 24)
703 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
704 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
705 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
706
bf466fb6
S		 707 /* CCK power per rate */
708 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
709 ATH9K_POW_SM(ratesArray[rate2s], 24)
710 | ATH9K_POW_SM(ratesArray[rate2l], 16)
711 | ATH9K_POW_SM(ratesArray[rateXr], 8)
712 | ATH9K_POW_SM(ratesArray[rate1l], 0));
713 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
714 ATH9K_POW_SM(ratesArray[rate11s], 24)
715 | ATH9K_POW_SM(ratesArray[rate11l], 16)
716 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
717 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
718
719 /* HT20 power per rate */
b5aec950
S		 720 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
721 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
722 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
723 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
724 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
725 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
726 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
727 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
728 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
729 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
730
bf466fb6 731 /* HT40 power per rate */
b5aec950
S		 732 if (IS_CHAN_HT40(chan)) {
733 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
734 ATH9K_POW_SM(ratesArray[rateHt40_3] +
735 ht40PowerIncForPdadc, 24)
736 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
737 ht40PowerIncForPdadc, 16)
738 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
739 ht40PowerIncForPdadc, 8)
740 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
741 ht40PowerIncForPdadc, 0));
742 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
743 ATH9K_POW_SM(ratesArray[rateHt40_7] +
744 ht40PowerIncForPdadc, 24)
745 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
746 ht40PowerIncForPdadc, 16)
747 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
748 ht40PowerIncForPdadc, 8)
749 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
750 ht40PowerIncForPdadc, 0));
b5aec950
S		 751 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
752 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
753 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
754 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
755 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
756 }
7d0d0df0
S		 757
758 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 759}
760
b5aec950
S		 761static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
762 struct modal_eep_4k_header *pModal,
763 struct ar5416_eeprom_4k *eep,
a37414a2 764 u8 txRxAttenLocal)
b5aec950 765{
a37414a2 766 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
b5aec950
S		 767 pModal->antCtrlChain[0]);
768
a37414a2
S		 769 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
770 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
b5aec950
S		 771 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
772 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
773 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
774 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
775
776 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
777 AR5416_EEP_MINOR_VER_3) {
778 txRxAttenLocal = pModal->txRxAttenCh[0];
779
a37414a2 780 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950 781 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
a37414a2 782 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950 783 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
a37414a2 784 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950
S		 785 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
786 pModal->xatten2Margin[0]);
a37414a2 787 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950
S		 788 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
789
790 /* Set the block 1 value to block 0 value */
791 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
792 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
793 pModal->bswMargin[0]);
794 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
795 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
796 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
797 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
798 pModal->xatten2Margin[0]);
799 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
800 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
801 pModal->xatten2Db[0]);
802 }
803
a37414a2 804 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
b5aec950 805 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
a37414a2 806 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
b5aec950
S		 807 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
808
809 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
810 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
811 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
812 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
b5aec950
S		 813}
814
815/*
816 * Read EEPROM header info and program the device for correct operation
817 * given the channel value.
818 */
819static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
820 struct ath9k_channel *chan)
821{
822 struct modal_eep_4k_header *pModal;
823 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
d88525e8 824 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
b5aec950
S		 825 u8 txRxAttenLocal;
826 u8 ob[5], db1[5], db2[5];
827 u8 ant_div_control1, ant_div_control2;
1b8714f7 828 u8 bb_desired_scale;
b5aec950
S		 829 u32 regVal;
830
831 pModal = &eep->modalHeader;
832 txRxAttenLocal = 23;
833
df3c8b2b 834 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
b5aec950
S		 835
836 /* Single chain for 4K EEPROM*/
a37414a2 837 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
b5aec950
S		 838
839 /* Initialize Ant Diversity settings from EEPROM */
840 if (pModal->version >= 3) {
7f63845f
S		 841 ant_div_control1 = pModal->antdiv_ctl1;
842 ant_div_control2 = pModal->antdiv_ctl2;
843
844 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
845 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
846
847 regVal |= SM(ant_div_control1,
848 AR_PHY_9285_ANT_DIV_CTL);
849 regVal |= SM(ant_div_control2,
850 AR_PHY_9285_ANT_DIV_ALT_LNACONF);
851 regVal |= SM((ant_div_control2 >> 2),
852 AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
853 regVal |= SM((ant_div_control1 >> 1),
854 AR_PHY_9285_ANT_DIV_ALT_GAINTB);
855 regVal |= SM((ant_div_control1 >> 2),
856 AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
857
858
859 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
860 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
861 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
862 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
863 regVal |= SM((ant_div_control1 >> 3),
864 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
865
866 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
867 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
b5aec950
S		 868 }
869
870 if (pModal->version >= 2) {
7f63845f
S		 871 ob[0] = pModal->ob_0;
872 ob[1] = pModal->ob_1;
873 ob[2] = pModal->ob_2;
874 ob[3] = pModal->ob_3;
875 ob[4] = pModal->ob_4;
876
877 db1[0] = pModal->db1_0;
878 db1[1] = pModal->db1_1;
879 db1[2] = pModal->db1_2;
880 db1[3] = pModal->db1_3;
881 db1[4] = pModal->db1_4;
882
883 db2[0] = pModal->db2_0;
884 db2[1] = pModal->db2_1;
885 db2[2] = pModal->db2_2;
886 db2[3] = pModal->db2_3;
887 db2[4] = pModal->db2_4;
b5aec950 888 } else if (pModal->version == 1) {
7f63845f
S		 889 ob[0] = pModal->ob_0;
890 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
891 db1[0] = pModal->db1_0;
892 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
893 db2[0] = pModal->db2_0;
894 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
b5aec950
S		 895 } else {
896 int i;
7f63845f 897
b5aec950 898 for (i = 0; i < 5; i++) {
7f63845f
S		 899 ob[i] = pModal->ob_0;
900 db1[i] = pModal->db1_0;
901 db2[i] = pModal->db1_0;
b5aec950
S		 902 }
903 }
904
905 if (AR_SREV_9271(ah)) {
906 ath9k_hw_analog_shift_rmw(ah,
907 AR9285_AN_RF2G3,
908 AR9271_AN_RF2G3_OB_cck,
909 AR9271_AN_RF2G3_OB_cck_S,
910 ob[0]);
911 ath9k_hw_analog_shift_rmw(ah,
912 AR9285_AN_RF2G3,
913 AR9271_AN_RF2G3_OB_psk,
914 AR9271_AN_RF2G3_OB_psk_S,
915 ob[1]);
916 ath9k_hw_analog_shift_rmw(ah,
917 AR9285_AN_RF2G3,
918 AR9271_AN_RF2G3_OB_qam,
919 AR9271_AN_RF2G3_OB_qam_S,
920 ob[2]);
921 ath9k_hw_analog_shift_rmw(ah,
922 AR9285_AN_RF2G3,
923 AR9271_AN_RF2G3_DB_1,
924 AR9271_AN_RF2G3_DB_1_S,
925 db1[0]);
926 ath9k_hw_analog_shift_rmw(ah,
927 AR9285_AN_RF2G4,
928 AR9271_AN_RF2G4_DB_2,
929 AR9271_AN_RF2G4_DB_2_S,
930 db2[0]);
931 } else {
932 ath9k_hw_analog_shift_rmw(ah,
933 AR9285_AN_RF2G3,
934 AR9285_AN_RF2G3_OB_0,
935 AR9285_AN_RF2G3_OB_0_S,
936 ob[0]);
937 ath9k_hw_analog_shift_rmw(ah,
938 AR9285_AN_RF2G3,
939 AR9285_AN_RF2G3_OB_1,
940 AR9285_AN_RF2G3_OB_1_S,
941 ob[1]);
942 ath9k_hw_analog_shift_rmw(ah,
943 AR9285_AN_RF2G3,
944 AR9285_AN_RF2G3_OB_2,
945 AR9285_AN_RF2G3_OB_2_S,
946 ob[2]);
947 ath9k_hw_analog_shift_rmw(ah,
948 AR9285_AN_RF2G3,
949 AR9285_AN_RF2G3_OB_3,
950 AR9285_AN_RF2G3_OB_3_S,
951 ob[3]);
952 ath9k_hw_analog_shift_rmw(ah,
953 AR9285_AN_RF2G3,
954 AR9285_AN_RF2G3_OB_4,
955 AR9285_AN_RF2G3_OB_4_S,
956 ob[4]);
957
958 ath9k_hw_analog_shift_rmw(ah,
959 AR9285_AN_RF2G3,
960 AR9285_AN_RF2G3_DB1_0,
961 AR9285_AN_RF2G3_DB1_0_S,
962 db1[0]);
963 ath9k_hw_analog_shift_rmw(ah,
964 AR9285_AN_RF2G3,
965 AR9285_AN_RF2G3_DB1_1,
966 AR9285_AN_RF2G3_DB1_1_S,
967 db1[1]);
968 ath9k_hw_analog_shift_rmw(ah,
969 AR9285_AN_RF2G3,
970 AR9285_AN_RF2G3_DB1_2,
971 AR9285_AN_RF2G3_DB1_2_S,
972 db1[2]);
973 ath9k_hw_analog_shift_rmw(ah,
974 AR9285_AN_RF2G4,
975 AR9285_AN_RF2G4_DB1_3,
976 AR9285_AN_RF2G4_DB1_3_S,
977 db1[3]);
978 ath9k_hw_analog_shift_rmw(ah,
979 AR9285_AN_RF2G4,
980 AR9285_AN_RF2G4_DB1_4,
981 AR9285_AN_RF2G4_DB1_4_S, db1[4]);
982
983 ath9k_hw_analog_shift_rmw(ah,
984 AR9285_AN_RF2G4,
985 AR9285_AN_RF2G4_DB2_0,
986 AR9285_AN_RF2G4_DB2_0_S,
987 db2[0]);
988 ath9k_hw_analog_shift_rmw(ah,
989 AR9285_AN_RF2G4,
990 AR9285_AN_RF2G4_DB2_1,
991 AR9285_AN_RF2G4_DB2_1_S,
992 db2[1]);
993 ath9k_hw_analog_shift_rmw(ah,
994 AR9285_AN_RF2G4,
995 AR9285_AN_RF2G4_DB2_2,
996 AR9285_AN_RF2G4_DB2_2_S,
997 db2[2]);
998 ath9k_hw_analog_shift_rmw(ah,
999 AR9285_AN_RF2G4,
1000 AR9285_AN_RF2G4_DB2_3,
1001 AR9285_AN_RF2G4_DB2_3_S,
1002 db2[3]);
1003 ath9k_hw_analog_shift_rmw(ah,
1004 AR9285_AN_RF2G4,
1005 AR9285_AN_RF2G4_DB2_4,
1006 AR9285_AN_RF2G4_DB2_4_S,
1007 db2[4]);
1008 }
1009
1010
b5aec950
S		 1011 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1012 pModal->switchSettling);
1013 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1014 pModal->adcDesiredSize);
1015
1016 REG_WRITE(ah, AR_PHY_RF_CTL4,
1017 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1018 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1019 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1020 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1021
1022 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1023 pModal->txEndToRxOn);
0cab6559
LR		 1024
1025 if (AR_SREV_9271_10(ah))
1026 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1027 pModal->txEndToRxOn);
b5aec950
S		 1028 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1029 pModal->thresh62);
1030 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1031 pModal->thresh62);
1032
1033 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1034 AR5416_EEP_MINOR_VER_2) {
1035 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1036 pModal->txFrameToDataStart);
1037 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1038 pModal->txFrameToPaOn);
1039 }
1040
1041 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1042 AR5416_EEP_MINOR_VER_3) {
1043 if (IS_CHAN_HT40(chan))
1044 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1045 AR_PHY_SETTLING_SWITCH,
1046 pModal->swSettleHt40);
1047 }
1b8714f7
FF		 1048
1049 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
1050 EEP_4K_BB_DESIRED_SCALE_MASK);
1051 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
1052 u32 pwrctrl, mask, clr;
1053
1054 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
1055 pwrctrl = mask * bb_desired_scale;
1056 clr = mask * 0x1f;
1057 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1058 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1059 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1060
1061 mask = BIT(0)|BIT(5)|BIT(15);
1062 pwrctrl = mask * bb_desired_scale;
1063 clr = mask * 0x1f;
1064 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1065
1066 mask = BIT(0)|BIT(5);
1067 pwrctrl = mask * bb_desired_scale;
1068 clr = mask * 0x1f;
1069 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1070 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
d88525e8 1071 }
b5aec950
S		 1072}
1073
b5aec950
S		 1074static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1075{
1076#define EEP_MAP4K_SPURCHAN \
1077 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
c46917bb 1078 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 1079
1080 u16 spur_val = AR_NO_SPUR;
1081
226afe68
JP		 1082 ath_dbg(common, ATH_DBG_ANI,
1083 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1084 i, is2GHz, ah->config.spurchans[i][is2GHz]);
b5aec950
S		 1085
1086 switch (ah->config.spurmode) {
1087 case SPUR_DISABLE:
1088 break;
1089 case SPUR_ENABLE_IOCTL:
1090 spur_val = ah->config.spurchans[i][is2GHz];
226afe68
JP		 1091 ath_dbg(common, ATH_DBG_ANI,
1092 "Getting spur val from new loc. %d\n", spur_val);
b5aec950
S		 1093 break;
1094 case SPUR_ENABLE_EEPROM:
1095 spur_val = EEP_MAP4K_SPURCHAN;
1096 break;
1097 }
1098
1099 return spur_val;
1100
1101#undef EEP_MAP4K_SPURCHAN
1102}
1103
1104const struct eeprom_ops eep_4k_ops = {
1105 .check_eeprom = ath9k_hw_4k_check_eeprom,
1106 .get_eeprom = ath9k_hw_4k_get_eeprom,
1107 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
4f011a2e 1108 .dump_eeprom = ath9k_hw_4k_dump_eeprom,
b5aec950
S		 1109 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1110 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
b5aec950 1111 .set_board_values = ath9k_hw_4k_set_board_values,
b5aec950
S		 1112 .set_txpower = ath9k_hw_4k_set_txpower,
1113 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1114};
Linux kernel - Deliverables
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