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ath9k: sync the dma buffer after changing the retry flag
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / eeprom_4k.c
CommitLineData
b5aec950 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
b5aec950
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
78fa99ab 17#include <asm/unaligned.h>
c46917bb 18#include "hw.h"
8fe65368 19#include "ar9002_phy.h"
b5aec950
S		 20
21static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
22{
23 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
24}
25
26static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
27{
28 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
29}
30
b5aec950 31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
04cf53f4
SM		 32
33static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
34{
c46917bb 35 struct ath_common *common = ath9k_hw_common(ah);
b5aec950 36 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
04cf53f4 37 int addr, eep_start_loc = 64;
b5aec950
S		 38
39 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
5bb12791 40 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
226afe68
JP		 41 ath_dbg(common, ATH_DBG_EEPROM,
42 "Unable to read eeprom region\n");
b5aec950
S		 43 return false;
44 }
45 eep_data++;
46 }
47
48 return true;
b5aec950
S		 49}
50
04cf53f4
SM		 51static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
52{
53 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
54
55 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
56
57 return true;
58}
59
60static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
61{
62 struct ath_common *common = ath9k_hw_common(ah);
63
64 if (!ath9k_hw_use_flash(ah)) {
65 ath_dbg(common, ATH_DBG_EEPROM,
66 "Reading from EEPROM, not flash\n");
67 }
68
69 if (common->bus_ops->ath_bus_type == ATH_USB)
70 return __ath9k_hw_usb_4k_fill_eeprom(ah);
71 else
72 return __ath9k_hw_4k_fill_eeprom(ah);
73}
74
4f011a2e
RM		 75#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
76static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size,
77 struct modal_eep_4k_header *modal_hdr)
78{
79 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
80 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
81 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
82 PR_EEP("Switch Settle", modal_hdr->switchSettling);
83 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
84 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
85 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
86 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
87 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
88 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
89 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
90 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
91 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
92 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
93 PR_EEP("xpdGain", modal_hdr->xpdGain);
94 PR_EEP("External PD", modal_hdr->xpd);
95 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
96 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
97 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
98 PR_EEP("O/D Bias Version", modal_hdr->version);
99 PR_EEP("CCK OutputBias", modal_hdr->ob_0);
100 PR_EEP("BPSK OutputBias", modal_hdr->ob_1);
101 PR_EEP("QPSK OutputBias", modal_hdr->ob_2);
102 PR_EEP("16QAM OutputBias", modal_hdr->ob_3);
103 PR_EEP("64QAM OutputBias", modal_hdr->ob_4);
104 PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0);
105 PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1);
106 PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2);
107 PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3);
108 PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4);
109 PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0);
110 PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1);
111 PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2);
112 PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3);
113 PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4);
114 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
115 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
116 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
117 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
118 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
119 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
120 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
121 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
122 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
123 PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1);
124 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2);
125 PR_EEP("TX Diversity", modal_hdr->tx_diversity);
126
127 return len;
128}
129
130static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
131 u8 *buf, u32 len, u32 size)
132{
133 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
134 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
135
136 if (!dump_base_hdr) {
137 len += snprintf(buf + len, size - len,
138 "%20s :\n", "2GHz modal Header");
139 len += ath9k_dump_4k_modal_eeprom(buf, len, size,
140 &eep->modalHeader);
141 goto out;
142 }
143
144 PR_EEP("Major Version", pBase->version >> 12);
145 PR_EEP("Minor Version", pBase->version & 0xFFF);
146 PR_EEP("Checksum", pBase->checksum);
147 PR_EEP("Length", pBase->length);
148 PR_EEP("RegDomain1", pBase->regDmn[0]);
149 PR_EEP("RegDomain2", pBase->regDmn[1]);
150 PR_EEP("TX Mask", pBase->txMask);
151 PR_EEP("RX Mask", pBase->rxMask);
152 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
153 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
154 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
155 AR5416_OPFLAGS_N_2G_HT20));
156 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
157 AR5416_OPFLAGS_N_2G_HT40));
158 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
159 AR5416_OPFLAGS_N_5G_HT20));
160 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
161 AR5416_OPFLAGS_N_5G_HT40));
162 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
163 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
164 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
165 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
166 PR_EEP("TX Gain type", pBase->txGainType);
167
168 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
169 pBase->macAddr);
170
171out:
172 if (len > size)
173 len = size;
174
175 return len;
176}
177#else
178static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
179 u8 *buf, u32 len, u32 size)
180{
181 return 0;
182}
183#endif
184
185
04cf53f4
SM		 186#undef SIZE_EEPROM_4K
187
b5aec950
S		 188static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
189{
190#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
c46917bb 191 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 192 struct ar5416_eeprom_4k *eep =
193 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
194 u16 *eepdata, temp, magic, magic2;
195 u32 sum = 0, el;
196 bool need_swap = false;
197 int i, addr;
198
199
200 if (!ath9k_hw_use_flash(ah)) {
5bb12791 201 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
b5aec950 202 &magic)) {
3800276a 203 ath_err(common, "Reading Magic # failed\n");
b5aec950
S		 204 return false;
205 }
206
226afe68
JP		 207 ath_dbg(common, ATH_DBG_EEPROM,
208 "Read Magic = 0x%04X\n", magic);
b5aec950
S		 209
210 if (magic != AR5416_EEPROM_MAGIC) {
211 magic2 = swab16(magic);
212
213 if (magic2 == AR5416_EEPROM_MAGIC) {
214 need_swap = true;
215 eepdata = (u16 *) (&ah->eeprom);
216
217 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
218 temp = swab16(*eepdata);
219 *eepdata = temp;
220 eepdata++;
221 }
222 } else {
3800276a 223 ath_err(common,
226afe68 224 "Invalid EEPROM Magic. Endianness mismatch.\n");
b5aec950
S		 225 return -EINVAL;
226 }
227 }
228 }
229
226afe68
JP		 230 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
231 need_swap ? "True" : "False");
b5aec950
S		 232
233 if (need_swap)
234 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
235 else
236 el = ah->eeprom.map4k.baseEepHeader.length;
237
238 if (el > sizeof(struct ar5416_eeprom_4k))
239 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
240 else
241 el = el / sizeof(u16);
242
243 eepdata = (u16 *)(&ah->eeprom);
244
245 for (i = 0; i < el; i++)
246 sum ^= *eepdata++;
247
248 if (need_swap) {
249 u32 integer;
250 u16 word;
251
226afe68
JP		 252 ath_dbg(common, ATH_DBG_EEPROM,
253 "EEPROM Endianness is not native.. Changing\n");
b5aec950
S		 254
255 word = swab16(eep->baseEepHeader.length);
256 eep->baseEepHeader.length = word;
257
258 word = swab16(eep->baseEepHeader.checksum);
259 eep->baseEepHeader.checksum = word;
260
261 word = swab16(eep->baseEepHeader.version);
262 eep->baseEepHeader.version = word;
263
264 word = swab16(eep->baseEepHeader.regDmn[0]);
265 eep->baseEepHeader.regDmn[0] = word;
266
267 word = swab16(eep->baseEepHeader.regDmn[1]);
268 eep->baseEepHeader.regDmn[1] = word;
269
270 word = swab16(eep->baseEepHeader.rfSilent);
271 eep->baseEepHeader.rfSilent = word;
272
273 word = swab16(eep->baseEepHeader.blueToothOptions);
274 eep->baseEepHeader.blueToothOptions = word;
275
276 word = swab16(eep->baseEepHeader.deviceCap);
277 eep->baseEepHeader.deviceCap = word;
278
279 integer = swab32(eep->modalHeader.antCtrlCommon);
280 eep->modalHeader.antCtrlCommon = integer;
281
282 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
283 integer = swab32(eep->modalHeader.antCtrlChain[i]);
284 eep->modalHeader.antCtrlChain[i] = integer;
285 }
286
4ddfcd7d 287 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
b5aec950
S		 288 word = swab16(eep->modalHeader.spurChans[i].spurChan);
289 eep->modalHeader.spurChans[i].spurChan = word;
290 }
291 }
292
293 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
294 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
3800276a
JP		 295 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
296 sum, ah->eep_ops->get_eeprom_ver(ah));
b5aec950
S		 297 return -EINVAL;
298 }
299
300 return 0;
301#undef EEPROM_4K_SIZE
302}
303
304static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
305 enum eeprom_param param)
306{
307 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
308 struct modal_eep_4k_header *pModal = &eep->modalHeader;
309 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
970bf9d4
GJ		 310 u16 ver_minor;
311
312 ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
b5aec950
S		 313
314 switch (param) {
315 case EEP_NFTHRESH_2:
316 return pModal->noiseFloorThreshCh[0];
49101676 317 case EEP_MAC_LSW:
78fa99ab 318 return get_unaligned_be16(pBase->macAddr);
49101676 319 case EEP_MAC_MID:
78fa99ab 320 return get_unaligned_be16(pBase->macAddr + 2);
49101676 321 case EEP_MAC_MSW:
78fa99ab 322 return get_unaligned_be16(pBase->macAddr + 4);
b5aec950
S		 323 case EEP_REG_0:
324 return pBase->regDmn[0];
325 case EEP_REG_1:
326 return pBase->regDmn[1];
327 case EEP_OP_CAP:
328 return pBase->deviceCap;
329 case EEP_OP_MODE:
330 return pBase->opCapFlags;
331 case EEP_RF_SILENT:
332 return pBase->rfSilent;
333 case EEP_OB_2:
7f63845f 334 return pModal->ob_0;
b5aec950 335 case EEP_DB_2:
7f63845f 336 return pModal->db1_1;
b5aec950 337 case EEP_MINOR_REV:
970bf9d4 338 return ver_minor;
b5aec950
S		 339 case EEP_TX_MASK:
340 return pBase->txMask;
341 case EEP_RX_MASK:
342 return pBase->rxMask;
343 case EEP_FRAC_N_5G:
344 return 0;
e41f0bfc
SB		 345 case EEP_PWR_TABLE_OFFSET:
346 return AR5416_PWR_TABLE_OFFSET_DB;
754dc536
VT		 347 case EEP_MODAL_VER:
348 return pModal->version;
349 case EEP_ANT_DIV_CTL1:
350 return pModal->antdiv_ctl1;
970bf9d4 351 case EEP_TXGAIN_TYPE:
f3d4505d 352 return pBase->txGainType;
b5aec950
S		 353 default:
354 return 0;
355 }
356}
357
b5aec950 358static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
e832bf10 359 struct ath9k_channel *chan)
b5aec950 360{
c46917bb 361 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 362 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
363 struct cal_data_per_freq_4k *pRawDataset;
364 u8 *pCalBChans = NULL;
365 u16 pdGainOverlap_t2;
366 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
4ddfcd7d 367 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
b5aec950 368 u16 numPiers, i, j;
b5aec950
S		 369 u16 numXpdGain, xpdMask;
370 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
371 u32 reg32, regOffset, regChainOffset;
372
373 xpdMask = pEepData->modalHeader.xpdGain;
374
375 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
376 AR5416_EEP_MINOR_VER_2) {
377 pdGainOverlap_t2 =
378 pEepData->modalHeader.pdGainOverlap;
379 } else {
380 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
381 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
382 }
383
384 pCalBChans = pEepData->calFreqPier2G;
385 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
386
387 numXpdGain = 0;
388
4ddfcd7d
FF		 389 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
390 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
b5aec950
S		 391 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
392 break;
393 xpdGainValues[numXpdGain] =
4ddfcd7d 394 (u16)(AR5416_PD_GAINS_IN_MASK - i);
b5aec950
S		 395 numXpdGain++;
396 }
397 }
398
399 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
400 (numXpdGain - 1) & 0x3);
401 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
402 xpdGainValues[0]);
403 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
404 xpdGainValues[1]);
405 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
406
407 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
408 if (AR_SREV_5416_20_OR_LATER(ah) &&
409 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
410 (i != 0)) {
411 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
412 } else
413 regChainOffset = i * 0x1000;
414
415 if (pEepData->baseEepHeader.txMask & (1 << i)) {
416 pRawDataset = pEepData->calPierData2G[i];
417
115277a3 418 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
b5aec950
S		 419 pRawDataset, pCalBChans,
420 numPiers, pdGainOverlap_t2,
6eb90d46 421 gainBoundaries,
b5aec950
S		 422 pdadcValues, numXpdGain);
423
7d0d0df0
S		 424 ENABLE_REGWRITE_BUFFER(ah);
425
b5aec950
S		 426 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
427 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
428 SM(pdGainOverlap_t2,
429 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
430 | SM(gainBoundaries[0],
431 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
432 | SM(gainBoundaries[1],
433 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
434 | SM(gainBoundaries[2],
435 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
436 | SM(gainBoundaries[3],
437 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
438 }
439
440 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
441 for (j = 0; j < 32; j++) {
78fa99ab 442 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
b5aec950
S		 443 REG_WRITE(ah, regOffset, reg32);
444
226afe68
JP		 445 ath_dbg(common, ATH_DBG_EEPROM,
446 "PDADC (%d,%4x): %4.4x %8.8x\n",
447 i, regChainOffset, regOffset,
448 reg32);
449 ath_dbg(common, ATH_DBG_EEPROM,
450 "PDADC: Chain %d | "
451 "PDADC %3d Value %3d | "
452 "PDADC %3d Value %3d | "
453 "PDADC %3d Value %3d | "
454 "PDADC %3d Value %3d |\n",
455 i, 4 * j, pdadcValues[4 * j],
456 4 * j + 1, pdadcValues[4 * j + 1],
457 4 * j + 2, pdadcValues[4 * j + 2],
458 4 * j + 3, pdadcValues[4 * j + 3]);
b5aec950
S		 459
460 regOffset += 4;
461 }
7d0d0df0
S		 462
463 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 464 }
465 }
b5aec950
S		 466}
467
468static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
469 struct ath9k_channel *chan,
470 int16_t *ratesArray,
471 u16 cfgCtl,
472 u16 AntennaReduction,
473 u16 twiceMaxRegulatoryPower,
474 u16 powerLimit)
475{
180d674b
S		 476#define CMP_TEST_GRP \
477 (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
478 pEepData->ctlIndex[i]) \
479 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
480 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
b5aec950 481
608b88cb 482 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 483 int i;
484 int16_t twiceLargestAntenna;
180d674b 485 u16 twiceMinEdgePower;
4ddfcd7d 486 u16 twiceMaxEdgePower = MAX_RATE_POWER;
180d674b 487 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
07b2fa5a
JP		 488 u16 numCtlModes;
489 const u16 *pCtlMode;
490 u16 ctlMode, freq;
180d674b 491 struct chan_centers centers;
b5aec950 492 struct cal_ctl_data_4k *rep;
180d674b
S		 493 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
494 static const u16 tpScaleReductionTable[5] =
4ddfcd7d 495 { 0, 3, 6, 9, MAX_RATE_POWER };
b5aec950
S		 496 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
497 0, { 0, 0, 0, 0}
498 };
499 struct cal_target_power_leg targetPowerOfdmExt = {
500 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
501 0, { 0, 0, 0, 0 }
502 };
503 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
504 0, {0, 0, 0, 0}
505 };
07b2fa5a
JP		 506 static const u16 ctlModesFor11g[] = {
507 CTL_11B, CTL_11G, CTL_2GHT20,
508 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
509 };
b5aec950
S		 510
511 ath9k_hw_get_channel_centers(ah, chan, &centers);
512
513 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
b5aec950
S		 514 twiceLargestAntenna = (int16_t)min(AntennaReduction -
515 twiceLargestAntenna, 0);
516
517 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
608b88cb 518 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
b5aec950 519 maxRegAllowedPower -=
608b88cb 520 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
b5aec950
S		 521 }
522
523 scaledPower = min(powerLimit, maxRegAllowedPower);
524 scaledPower = max((u16)0, scaledPower);
525
526 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
527 pCtlMode = ctlModesFor11g;
528
529 ath9k_hw_get_legacy_target_powers(ah, chan,
530 pEepData->calTargetPowerCck,
531 AR5416_NUM_2G_CCK_TARGET_POWERS,
532 &targetPowerCck, 4, false);
533 ath9k_hw_get_legacy_target_powers(ah, chan,
534 pEepData->calTargetPower2G,
535 AR5416_NUM_2G_20_TARGET_POWERS,
536 &targetPowerOfdm, 4, false);
537 ath9k_hw_get_target_powers(ah, chan,
538 pEepData->calTargetPower2GHT20,
539 AR5416_NUM_2G_20_TARGET_POWERS,
540 &targetPowerHt20, 8, false);
541
542 if (IS_CHAN_HT40(chan)) {
543 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
544 ath9k_hw_get_target_powers(ah, chan,
545 pEepData->calTargetPower2GHT40,
546 AR5416_NUM_2G_40_TARGET_POWERS,
547 &targetPowerHt40, 8, true);
548 ath9k_hw_get_legacy_target_powers(ah, chan,
549 pEepData->calTargetPowerCck,
550 AR5416_NUM_2G_CCK_TARGET_POWERS,
551 &targetPowerCckExt, 4, true);
552 ath9k_hw_get_legacy_target_powers(ah, chan,
553 pEepData->calTargetPower2G,
554 AR5416_NUM_2G_20_TARGET_POWERS,
555 &targetPowerOfdmExt, 4, true);
556 }
557
558 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
559 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
560 (pCtlMode[ctlMode] == CTL_2GHT40);
180d674b 561
b5aec950
S		 562 if (isHt40CtlMode)
563 freq = centers.synth_center;
564 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
565 freq = centers.ext_center;
566 else
567 freq = centers.ctl_center;
568
569 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
570 ah->eep_ops->get_eeprom_rev(ah) <= 2)
4ddfcd7d 571 twiceMaxEdgePower = MAX_RATE_POWER;
b5aec950
S		 572
573 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
180d674b
S		 574 pEepData->ctlIndex[i]; i++) {
575
576 if (CMP_TEST_GRP) {
b5aec950
S		 577 rep = &(pEepData->ctlData[i]);
578
180d674b
S		 579 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
580 freq,
581 rep->ctlEdges[
582 ar5416_get_ntxchains(ah->txchainmask) - 1],
583 IS_CHAN_2GHZ(chan),
584 AR5416_EEP4K_NUM_BAND_EDGES);
b5aec950
S		 585
586 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
587 twiceMaxEdgePower =
588 min(twiceMaxEdgePower,
589 twiceMinEdgePower);
590 } else {
591 twiceMaxEdgePower = twiceMinEdgePower;
592 break;
593 }
594 }
595 }
596
597 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
598
599 switch (pCtlMode[ctlMode]) {
600 case CTL_11B:
180d674b 601 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
b5aec950
S		 602 targetPowerCck.tPow2x[i] =
603 min((u16)targetPowerCck.tPow2x[i],
604 minCtlPower);
605 }
606 break;
607 case CTL_11G:
180d674b 608 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
b5aec950
S		 609 targetPowerOfdm.tPow2x[i] =
610 min((u16)targetPowerOfdm.tPow2x[i],
611 minCtlPower);
612 }
613 break;
614 case CTL_2GHT20:
180d674b 615 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
b5aec950
S		 616 targetPowerHt20.tPow2x[i] =
617 min((u16)targetPowerHt20.tPow2x[i],
618 minCtlPower);
619 }
620 break;
621 case CTL_11B_EXT:
180d674b
S		 622 targetPowerCckExt.tPow2x[0] =
623 min((u16)targetPowerCckExt.tPow2x[0],
624 minCtlPower);
b5aec950
S		 625 break;
626 case CTL_11G_EXT:
180d674b
S		 627 targetPowerOfdmExt.tPow2x[0] =
628 min((u16)targetPowerOfdmExt.tPow2x[0],
629 minCtlPower);
b5aec950
S		 630 break;
631 case CTL_2GHT40:
180d674b 632 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
b5aec950
S		 633 targetPowerHt40.tPow2x[i] =
634 min((u16)targetPowerHt40.tPow2x[i],
635 minCtlPower);
636 }
637 break;
638 default:
639 break;
640 }
641 }
642
180d674b
S		 643 ratesArray[rate6mb] =
644 ratesArray[rate9mb] =
645 ratesArray[rate12mb] =
646 ratesArray[rate18mb] =
647 ratesArray[rate24mb] =
648 targetPowerOfdm.tPow2x[0];
649
b5aec950
S		 650 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
651 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
652 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
653 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
654
655 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
656 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
657
658 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
659 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
660 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
661 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
662
663 if (IS_CHAN_HT40(chan)) {
664 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
665 ratesArray[rateHt40_0 + i] =
666 targetPowerHt40.tPow2x[i];
667 }
668 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
669 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
670 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
671 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
672 }
180d674b
S		 673
674#undef CMP_TEST_GRP
b5aec950
S		 675}
676
677static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
bf466fb6
S		 678 struct ath9k_channel *chan,
679 u16 cfgCtl,
680 u8 twiceAntennaReduction,
681 u8 twiceMaxRegulatoryPower,
de40f316 682 u8 powerLimit, bool test)
b5aec950 683{
608b88cb 684 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 685 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
686 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
687 int16_t ratesArray[Ar5416RateSize];
b5aec950
S		 688 u8 ht40PowerIncForPdadc = 2;
689 int i;
690
691 memset(ratesArray, 0, sizeof(ratesArray));
692
693 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
694 AR5416_EEP_MINOR_VER_2) {
695 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
696 }
697
698 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
bf466fb6
S		 699 &ratesArray[0], cfgCtl,
700 twiceAntennaReduction,
701 twiceMaxRegulatoryPower,
702 powerLimit);
b5aec950 703
e832bf10 704 ath9k_hw_set_4k_power_cal_table(ah, chan);
b5aec950 705
de40f316 706 regulatory->max_power_level = 0;
b5aec950 707 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4ddfcd7d
FF		 708 if (ratesArray[i] > MAX_RATE_POWER)
709 ratesArray[i] = MAX_RATE_POWER;
de40f316
FF		 710
711 if (ratesArray[i] > regulatory->max_power_level)
712 regulatory->max_power_level = ratesArray[i];
b5aec950
S		 713 }
714
de40f316
FF		 715 if (test)
716 return;
bf466fb6 717
7a37081e 718 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950 719 for (i = 0; i < Ar5416RateSize; i++)
e41f0bfc 720 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
b5aec950
S		 721 }
722
7d0d0df0
S		 723 ENABLE_REGWRITE_BUFFER(ah);
724
bf466fb6 725 /* OFDM power per rate */
b5aec950
S		 726 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
727 ATH9K_POW_SM(ratesArray[rate18mb], 24)
728 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
729 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
730 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
731 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
732 ATH9K_POW_SM(ratesArray[rate54mb], 24)
733 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
734 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
735 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
736
bf466fb6
S		 737 /* CCK power per rate */
738 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
739 ATH9K_POW_SM(ratesArray[rate2s], 24)
740 | ATH9K_POW_SM(ratesArray[rate2l], 16)
741 | ATH9K_POW_SM(ratesArray[rateXr], 8)
742 | ATH9K_POW_SM(ratesArray[rate1l], 0));
743 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
744 ATH9K_POW_SM(ratesArray[rate11s], 24)
745 | ATH9K_POW_SM(ratesArray[rate11l], 16)
746 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
747 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
748
749 /* HT20 power per rate */
b5aec950
S		 750 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
751 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
752 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
753 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
754 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
755 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
756 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
757 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
758 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
759 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
760
bf466fb6 761 /* HT40 power per rate */
b5aec950
S		 762 if (IS_CHAN_HT40(chan)) {
763 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
764 ATH9K_POW_SM(ratesArray[rateHt40_3] +
765 ht40PowerIncForPdadc, 24)
766 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
767 ht40PowerIncForPdadc, 16)
768 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
769 ht40PowerIncForPdadc, 8)
770 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
771 ht40PowerIncForPdadc, 0));
772 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
773 ATH9K_POW_SM(ratesArray[rateHt40_7] +
774 ht40PowerIncForPdadc, 24)
775 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
776 ht40PowerIncForPdadc, 16)
777 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
778 ht40PowerIncForPdadc, 8)
779 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
780 ht40PowerIncForPdadc, 0));
b5aec950
S		 781 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
782 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
783 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
784 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
785 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
786 }
7d0d0df0
S		 787
788 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 789}
790
791static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
792 struct ath9k_channel *chan)
793{
794 struct modal_eep_4k_header *pModal;
795 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
796 u8 biaslevel;
797
798 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
799 return;
800
801 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
802 return;
803
804 pModal = &eep->modalHeader;
805
806 if (pModal->xpaBiasLvl != 0xff) {
807 biaslevel = pModal->xpaBiasLvl;
808 INI_RA(&ah->iniAddac, 7, 1) =
809 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
810 }
811}
812
813static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
814 struct modal_eep_4k_header *pModal,
815 struct ar5416_eeprom_4k *eep,
a37414a2 816 u8 txRxAttenLocal)
b5aec950 817{
a37414a2 818 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
b5aec950
S		 819 pModal->antCtrlChain[0]);
820
a37414a2
S		 821 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
822 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
b5aec950
S		 823 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
824 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
825 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
826 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
827
828 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
829 AR5416_EEP_MINOR_VER_3) {
830 txRxAttenLocal = pModal->txRxAttenCh[0];
831
a37414a2 832 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950 833 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
a37414a2 834 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950 835 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
a37414a2 836 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950
S		 837 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
838 pModal->xatten2Margin[0]);
a37414a2 839 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
b5aec950
S		 840 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
841
842 /* Set the block 1 value to block 0 value */
843 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
844 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
845 pModal->bswMargin[0]);
846 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
847 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
848 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
849 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
850 pModal->xatten2Margin[0]);
851 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
852 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
853 pModal->xatten2Db[0]);
854 }
855
a37414a2 856 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
b5aec950 857 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
a37414a2 858 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
b5aec950
S		 859 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
860
861 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
862 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
863 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
864 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
b5aec950
S		 865}
866
867/*
868 * Read EEPROM header info and program the device for correct operation
869 * given the channel value.
870 */
871static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
872 struct ath9k_channel *chan)
873{
874 struct modal_eep_4k_header *pModal;
875 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
d88525e8 876 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
b5aec950
S		 877 u8 txRxAttenLocal;
878 u8 ob[5], db1[5], db2[5];
879 u8 ant_div_control1, ant_div_control2;
880 u32 regVal;
881
882 pModal = &eep->modalHeader;
883 txRxAttenLocal = 23;
884
df3c8b2b 885 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
b5aec950
S		 886
887 /* Single chain for 4K EEPROM*/
a37414a2 888 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
b5aec950
S		 889
890 /* Initialize Ant Diversity settings from EEPROM */
891 if (pModal->version >= 3) {
7f63845f
S		 892 ant_div_control1 = pModal->antdiv_ctl1;
893 ant_div_control2 = pModal->antdiv_ctl2;
894
895 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
896 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
897
898 regVal |= SM(ant_div_control1,
899 AR_PHY_9285_ANT_DIV_CTL);
900 regVal |= SM(ant_div_control2,
901 AR_PHY_9285_ANT_DIV_ALT_LNACONF);
902 regVal |= SM((ant_div_control2 >> 2),
903 AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
904 regVal |= SM((ant_div_control1 >> 1),
905 AR_PHY_9285_ANT_DIV_ALT_GAINTB);
906 regVal |= SM((ant_div_control1 >> 2),
907 AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
908
909
910 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
911 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
912 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
913 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
914 regVal |= SM((ant_div_control1 >> 3),
915 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
916
917 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
918 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
b5aec950
S		 919 }
920
921 if (pModal->version >= 2) {
7f63845f
S		 922 ob[0] = pModal->ob_0;
923 ob[1] = pModal->ob_1;
924 ob[2] = pModal->ob_2;
925 ob[3] = pModal->ob_3;
926 ob[4] = pModal->ob_4;
927
928 db1[0] = pModal->db1_0;
929 db1[1] = pModal->db1_1;
930 db1[2] = pModal->db1_2;
931 db1[3] = pModal->db1_3;
932 db1[4] = pModal->db1_4;
933
934 db2[0] = pModal->db2_0;
935 db2[1] = pModal->db2_1;
936 db2[2] = pModal->db2_2;
937 db2[3] = pModal->db2_3;
938 db2[4] = pModal->db2_4;
b5aec950 939 } else if (pModal->version == 1) {
7f63845f
S		 940 ob[0] = pModal->ob_0;
941 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
942 db1[0] = pModal->db1_0;
943 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
944 db2[0] = pModal->db2_0;
945 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
b5aec950
S		 946 } else {
947 int i;
7f63845f 948
b5aec950 949 for (i = 0; i < 5; i++) {
7f63845f
S		 950 ob[i] = pModal->ob_0;
951 db1[i] = pModal->db1_0;
952 db2[i] = pModal->db1_0;
b5aec950
S		 953 }
954 }
955
956 if (AR_SREV_9271(ah)) {
957 ath9k_hw_analog_shift_rmw(ah,
958 AR9285_AN_RF2G3,
959 AR9271_AN_RF2G3_OB_cck,
960 AR9271_AN_RF2G3_OB_cck_S,
961 ob[0]);
962 ath9k_hw_analog_shift_rmw(ah,
963 AR9285_AN_RF2G3,
964 AR9271_AN_RF2G3_OB_psk,
965 AR9271_AN_RF2G3_OB_psk_S,
966 ob[1]);
967 ath9k_hw_analog_shift_rmw(ah,
968 AR9285_AN_RF2G3,
969 AR9271_AN_RF2G3_OB_qam,
970 AR9271_AN_RF2G3_OB_qam_S,
971 ob[2]);
972 ath9k_hw_analog_shift_rmw(ah,
973 AR9285_AN_RF2G3,
974 AR9271_AN_RF2G3_DB_1,
975 AR9271_AN_RF2G3_DB_1_S,
976 db1[0]);
977 ath9k_hw_analog_shift_rmw(ah,
978 AR9285_AN_RF2G4,
979 AR9271_AN_RF2G4_DB_2,
980 AR9271_AN_RF2G4_DB_2_S,
981 db2[0]);
982 } else {
983 ath9k_hw_analog_shift_rmw(ah,
984 AR9285_AN_RF2G3,
985 AR9285_AN_RF2G3_OB_0,
986 AR9285_AN_RF2G3_OB_0_S,
987 ob[0]);
988 ath9k_hw_analog_shift_rmw(ah,
989 AR9285_AN_RF2G3,
990 AR9285_AN_RF2G3_OB_1,
991 AR9285_AN_RF2G3_OB_1_S,
992 ob[1]);
993 ath9k_hw_analog_shift_rmw(ah,
994 AR9285_AN_RF2G3,
995 AR9285_AN_RF2G3_OB_2,
996 AR9285_AN_RF2G3_OB_2_S,
997 ob[2]);
998 ath9k_hw_analog_shift_rmw(ah,
999 AR9285_AN_RF2G3,
1000 AR9285_AN_RF2G3_OB_3,
1001 AR9285_AN_RF2G3_OB_3_S,
1002 ob[3]);
1003 ath9k_hw_analog_shift_rmw(ah,
1004 AR9285_AN_RF2G3,
1005 AR9285_AN_RF2G3_OB_4,
1006 AR9285_AN_RF2G3_OB_4_S,
1007 ob[4]);
1008
1009 ath9k_hw_analog_shift_rmw(ah,
1010 AR9285_AN_RF2G3,
1011 AR9285_AN_RF2G3_DB1_0,
1012 AR9285_AN_RF2G3_DB1_0_S,
1013 db1[0]);
1014 ath9k_hw_analog_shift_rmw(ah,
1015 AR9285_AN_RF2G3,
1016 AR9285_AN_RF2G3_DB1_1,
1017 AR9285_AN_RF2G3_DB1_1_S,
1018 db1[1]);
1019 ath9k_hw_analog_shift_rmw(ah,
1020 AR9285_AN_RF2G3,
1021 AR9285_AN_RF2G3_DB1_2,
1022 AR9285_AN_RF2G3_DB1_2_S,
1023 db1[2]);
1024 ath9k_hw_analog_shift_rmw(ah,
1025 AR9285_AN_RF2G4,
1026 AR9285_AN_RF2G4_DB1_3,
1027 AR9285_AN_RF2G4_DB1_3_S,
1028 db1[3]);
1029 ath9k_hw_analog_shift_rmw(ah,
1030 AR9285_AN_RF2G4,
1031 AR9285_AN_RF2G4_DB1_4,
1032 AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1033
1034 ath9k_hw_analog_shift_rmw(ah,
1035 AR9285_AN_RF2G4,
1036 AR9285_AN_RF2G4_DB2_0,
1037 AR9285_AN_RF2G4_DB2_0_S,
1038 db2[0]);
1039 ath9k_hw_analog_shift_rmw(ah,
1040 AR9285_AN_RF2G4,
1041 AR9285_AN_RF2G4_DB2_1,
1042 AR9285_AN_RF2G4_DB2_1_S,
1043 db2[1]);
1044 ath9k_hw_analog_shift_rmw(ah,
1045 AR9285_AN_RF2G4,
1046 AR9285_AN_RF2G4_DB2_2,
1047 AR9285_AN_RF2G4_DB2_2_S,
1048 db2[2]);
1049 ath9k_hw_analog_shift_rmw(ah,
1050 AR9285_AN_RF2G4,
1051 AR9285_AN_RF2G4_DB2_3,
1052 AR9285_AN_RF2G4_DB2_3_S,
1053 db2[3]);
1054 ath9k_hw_analog_shift_rmw(ah,
1055 AR9285_AN_RF2G4,
1056 AR9285_AN_RF2G4_DB2_4,
1057 AR9285_AN_RF2G4_DB2_4_S,
1058 db2[4]);
1059 }
1060
1061
b5aec950
S		 1062 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1063 pModal->switchSettling);
1064 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1065 pModal->adcDesiredSize);
1066
1067 REG_WRITE(ah, AR_PHY_RF_CTL4,
1068 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1069 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1070 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1071 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1072
1073 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1074 pModal->txEndToRxOn);
0cab6559
LR		 1075
1076 if (AR_SREV_9271_10(ah))
1077 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1078 pModal->txEndToRxOn);
b5aec950
S		 1079 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1080 pModal->thresh62);
1081 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1082 pModal->thresh62);
1083
1084 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1085 AR5416_EEP_MINOR_VER_2) {
1086 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1087 pModal->txFrameToDataStart);
1088 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1089 pModal->txFrameToPaOn);
1090 }
1091
1092 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1093 AR5416_EEP_MINOR_VER_3) {
1094 if (IS_CHAN_HT40(chan))
1095 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1096 AR_PHY_SETTLING_SWITCH,
1097 pModal->swSettleHt40);
1098 }
d88525e8
RM		 1099 if (AR_SREV_9271(ah) || AR_SREV_9285(ah)) {
1100 u8 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
1101 EEP_4K_BB_DESIRED_SCALE_MASK);
1102 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
1103 u32 pwrctrl, mask, clr;
1104
1105 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
1106 pwrctrl = mask * bb_desired_scale;
1107 clr = mask * 0x1f;
1108 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1109 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1110 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1111
1112 mask = BIT(0)|BIT(5)|BIT(15);
1113 pwrctrl = mask * bb_desired_scale;
1114 clr = mask * 0x1f;
1115 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1116
1117 mask = BIT(0)|BIT(5);
1118 pwrctrl = mask * bb_desired_scale;
1119 clr = mask * 0x1f;
1120 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1121 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
1122 }
1123 }
b5aec950
S		 1124}
1125
b5aec950
S		 1126static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1127{
1128#define EEP_MAP4K_SPURCHAN \
1129 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
c46917bb 1130 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 1131
1132 u16 spur_val = AR_NO_SPUR;
1133
226afe68
JP		 1134 ath_dbg(common, ATH_DBG_ANI,
1135 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1136 i, is2GHz, ah->config.spurchans[i][is2GHz]);
b5aec950
S		 1137
1138 switch (ah->config.spurmode) {
1139 case SPUR_DISABLE:
1140 break;
1141 case SPUR_ENABLE_IOCTL:
1142 spur_val = ah->config.spurchans[i][is2GHz];
226afe68
JP		 1143 ath_dbg(common, ATH_DBG_ANI,
1144 "Getting spur val from new loc. %d\n", spur_val);
b5aec950
S		 1145 break;
1146 case SPUR_ENABLE_EEPROM:
1147 spur_val = EEP_MAP4K_SPURCHAN;
1148 break;
1149 }
1150
1151 return spur_val;
1152
1153#undef EEP_MAP4K_SPURCHAN
1154}
1155
1156const struct eeprom_ops eep_4k_ops = {
1157 .check_eeprom = ath9k_hw_4k_check_eeprom,
1158 .get_eeprom = ath9k_hw_4k_get_eeprom,
1159 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
4f011a2e 1160 .dump_eeprom = ath9k_hw_4k_dump_eeprom,
b5aec950
S		 1161 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1162 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
b5aec950
S		 1163 .set_board_values = ath9k_hw_4k_set_board_values,
1164 .set_addac = ath9k_hw_4k_set_addac,
1165 .set_txpower = ath9k_hw_4k_set_txpower,
1166 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1167};
Linux kernel - Deliverables
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