Commit | Line | Data |
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b5aec950 S |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
c46917bb | 17 | #include "hw.h" |
8fe65368 | 18 | #include "ar9002_phy.h" |
b5aec950 S |
19 | |
20 | static void ath9k_get_txgain_index(struct ath_hw *ah, | |
21 | struct ath9k_channel *chan, | |
22 | struct calDataPerFreqOpLoop *rawDatasetOpLoop, | |
23 | u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx) | |
24 | { | |
25 | u8 pcdac, i = 0; | |
26 | u16 idxL = 0, idxR = 0, numPiers; | |
27 | bool match; | |
28 | struct chan_centers centers; | |
29 | ||
30 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
31 | ||
32 | for (numPiers = 0; numPiers < availPiers; numPiers++) | |
33 | if (calChans[numPiers] == AR5416_BCHAN_UNUSED) | |
34 | break; | |
35 | ||
36 | match = ath9k_hw_get_lower_upper_index( | |
37 | (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), | |
38 | calChans, numPiers, &idxL, &idxR); | |
39 | if (match) { | |
40 | pcdac = rawDatasetOpLoop[idxL].pcdac[0][0]; | |
41 | *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0]; | |
42 | } else { | |
43 | pcdac = rawDatasetOpLoop[idxR].pcdac[0][0]; | |
44 | *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] + | |
45 | rawDatasetOpLoop[idxR].pwrPdg[0][0])/2; | |
46 | } | |
47 | ||
48 | while (pcdac > ah->originalGain[i] && | |
49 | i < (AR9280_TX_GAIN_TABLE_SIZE - 1)) | |
50 | i++; | |
51 | ||
52 | *pcdacIdx = i; | |
b5aec950 S |
53 | } |
54 | ||
55 | static void ath9k_olc_get_pdadcs(struct ath_hw *ah, | |
56 | u32 initTxGain, | |
57 | int txPower, | |
58 | u8 *pPDADCValues) | |
59 | { | |
60 | u32 i; | |
61 | u32 offset; | |
62 | ||
63 | REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, | |
64 | AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); | |
65 | REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, | |
66 | AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); | |
67 | ||
68 | REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, | |
69 | AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain); | |
70 | ||
71 | offset = txPower; | |
72 | for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++) | |
73 | if (i < offset) | |
74 | pPDADCValues[i] = 0x0; | |
75 | else | |
76 | pPDADCValues[i] = 0xFF; | |
77 | } | |
78 | ||
79 | static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) | |
80 | { | |
81 | return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF); | |
82 | } | |
83 | ||
84 | static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) | |
85 | { | |
86 | return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF); | |
87 | } | |
88 | ||
89 | static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) | |
90 | { | |
91 | #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) | |
5bb12791 | 92 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
93 | u16 *eep_data = (u16 *)&ah->eeprom.def; |
94 | int addr, ar5416_eep_start_loc = 0x100; | |
95 | ||
96 | for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { | |
5bb12791 | 97 | if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc, |
b5aec950 | 98 | eep_data)) { |
c46917bb LR |
99 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
100 | "Unable to read eeprom region\n"); | |
b5aec950 S |
101 | return false; |
102 | } | |
103 | eep_data++; | |
104 | } | |
105 | return true; | |
106 | #undef SIZE_EEPROM_DEF | |
107 | } | |
108 | ||
109 | static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) | |
110 | { | |
111 | struct ar5416_eeprom_def *eep = | |
112 | (struct ar5416_eeprom_def *) &ah->eeprom.def; | |
c46917bb | 113 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
114 | u16 *eepdata, temp, magic, magic2; |
115 | u32 sum = 0, el; | |
116 | bool need_swap = false; | |
117 | int i, addr, size; | |
118 | ||
5bb12791 | 119 | if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { |
c46917bb | 120 | ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n"); |
b5aec950 S |
121 | return false; |
122 | } | |
123 | ||
124 | if (!ath9k_hw_use_flash(ah)) { | |
c46917bb LR |
125 | ath_print(common, ATH_DBG_EEPROM, |
126 | "Read Magic = 0x%04X\n", magic); | |
b5aec950 S |
127 | |
128 | if (magic != AR5416_EEPROM_MAGIC) { | |
129 | magic2 = swab16(magic); | |
130 | ||
131 | if (magic2 == AR5416_EEPROM_MAGIC) { | |
132 | size = sizeof(struct ar5416_eeprom_def); | |
133 | need_swap = true; | |
134 | eepdata = (u16 *) (&ah->eeprom); | |
135 | ||
136 | for (addr = 0; addr < size / sizeof(u16); addr++) { | |
137 | temp = swab16(*eepdata); | |
138 | *eepdata = temp; | |
139 | eepdata++; | |
140 | } | |
141 | } else { | |
c46917bb LR |
142 | ath_print(common, ATH_DBG_FATAL, |
143 | "Invalid EEPROM Magic. " | |
144 | "Endianness mismatch.\n"); | |
b5aec950 S |
145 | return -EINVAL; |
146 | } | |
147 | } | |
148 | } | |
149 | ||
c46917bb LR |
150 | ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", |
151 | need_swap ? "True" : "False"); | |
b5aec950 S |
152 | |
153 | if (need_swap) | |
154 | el = swab16(ah->eeprom.def.baseEepHeader.length); | |
155 | else | |
156 | el = ah->eeprom.def.baseEepHeader.length; | |
157 | ||
158 | if (el > sizeof(struct ar5416_eeprom_def)) | |
159 | el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); | |
160 | else | |
161 | el = el / sizeof(u16); | |
162 | ||
163 | eepdata = (u16 *)(&ah->eeprom); | |
164 | ||
165 | for (i = 0; i < el; i++) | |
166 | sum ^= *eepdata++; | |
167 | ||
168 | if (need_swap) { | |
169 | u32 integer, j; | |
170 | u16 word; | |
171 | ||
c46917bb LR |
172 | ath_print(common, ATH_DBG_EEPROM, |
173 | "EEPROM Endianness is not native.. Changing.\n"); | |
b5aec950 S |
174 | |
175 | word = swab16(eep->baseEepHeader.length); | |
176 | eep->baseEepHeader.length = word; | |
177 | ||
178 | word = swab16(eep->baseEepHeader.checksum); | |
179 | eep->baseEepHeader.checksum = word; | |
180 | ||
181 | word = swab16(eep->baseEepHeader.version); | |
182 | eep->baseEepHeader.version = word; | |
183 | ||
184 | word = swab16(eep->baseEepHeader.regDmn[0]); | |
185 | eep->baseEepHeader.regDmn[0] = word; | |
186 | ||
187 | word = swab16(eep->baseEepHeader.regDmn[1]); | |
188 | eep->baseEepHeader.regDmn[1] = word; | |
189 | ||
190 | word = swab16(eep->baseEepHeader.rfSilent); | |
191 | eep->baseEepHeader.rfSilent = word; | |
192 | ||
193 | word = swab16(eep->baseEepHeader.blueToothOptions); | |
194 | eep->baseEepHeader.blueToothOptions = word; | |
195 | ||
196 | word = swab16(eep->baseEepHeader.deviceCap); | |
197 | eep->baseEepHeader.deviceCap = word; | |
198 | ||
199 | for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { | |
200 | struct modal_eep_header *pModal = | |
201 | &eep->modalHeader[j]; | |
202 | integer = swab32(pModal->antCtrlCommon); | |
203 | pModal->antCtrlCommon = integer; | |
204 | ||
205 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
206 | integer = swab32(pModal->antCtrlChain[i]); | |
207 | pModal->antCtrlChain[i] = integer; | |
208 | } | |
209 | ||
210 | for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { | |
211 | word = swab16(pModal->spurChans[i].spurChan); | |
212 | pModal->spurChans[i].spurChan = word; | |
213 | } | |
214 | } | |
215 | } | |
216 | ||
217 | if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || | |
218 | ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { | |
c46917bb LR |
219 | ath_print(common, ATH_DBG_FATAL, |
220 | "Bad EEPROM checksum 0x%x or revision 0x%04x\n", | |
b5aec950 S |
221 | sum, ah->eep_ops->get_eeprom_ver(ah)); |
222 | return -EINVAL; | |
223 | } | |
224 | ||
57b98384 | 225 | /* Enable fixup for AR_AN_TOP2 if necessary */ |
7a37081e | 226 | if (AR_SREV_9280_20_OR_LATER(ah) && |
57b98384 FF |
227 | (eep->baseEepHeader.version & 0xff) > 0x0a && |
228 | eep->baseEepHeader.pwdclkind == 0) | |
229 | ah->need_an_top2_fixup = 1; | |
230 | ||
b5aec950 S |
231 | return 0; |
232 | } | |
233 | ||
234 | static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, | |
235 | enum eeprom_param param) | |
236 | { | |
237 | struct ar5416_eeprom_def *eep = &ah->eeprom.def; | |
238 | struct modal_eep_header *pModal = eep->modalHeader; | |
239 | struct base_eep_header *pBase = &eep->baseEepHeader; | |
240 | ||
241 | switch (param) { | |
242 | case EEP_NFTHRESH_5: | |
243 | return pModal[0].noiseFloorThreshCh[0]; | |
244 | case EEP_NFTHRESH_2: | |
245 | return pModal[1].noiseFloorThreshCh[0]; | |
49101676 | 246 | case EEP_MAC_LSW: |
b5aec950 | 247 | return pBase->macAddr[0] << 8 | pBase->macAddr[1]; |
49101676 | 248 | case EEP_MAC_MID: |
b5aec950 | 249 | return pBase->macAddr[2] << 8 | pBase->macAddr[3]; |
49101676 | 250 | case EEP_MAC_MSW: |
b5aec950 S |
251 | return pBase->macAddr[4] << 8 | pBase->macAddr[5]; |
252 | case EEP_REG_0: | |
253 | return pBase->regDmn[0]; | |
254 | case EEP_REG_1: | |
255 | return pBase->regDmn[1]; | |
256 | case EEP_OP_CAP: | |
257 | return pBase->deviceCap; | |
258 | case EEP_OP_MODE: | |
259 | return pBase->opCapFlags; | |
260 | case EEP_RF_SILENT: | |
261 | return pBase->rfSilent; | |
262 | case EEP_OB_5: | |
263 | return pModal[0].ob; | |
264 | case EEP_DB_5: | |
265 | return pModal[0].db; | |
266 | case EEP_OB_2: | |
267 | return pModal[1].ob; | |
268 | case EEP_DB_2: | |
269 | return pModal[1].db; | |
270 | case EEP_MINOR_REV: | |
271 | return AR5416_VER_MASK; | |
272 | case EEP_TX_MASK: | |
273 | return pBase->txMask; | |
274 | case EEP_RX_MASK: | |
275 | return pBase->rxMask; | |
5b75d0fc FF |
276 | case EEP_FSTCLK_5G: |
277 | return pBase->fastClk5g; | |
b5aec950 S |
278 | case EEP_RXGAIN_TYPE: |
279 | return pBase->rxGainType; | |
280 | case EEP_TXGAIN_TYPE: | |
281 | return pBase->txGainType; | |
282 | case EEP_OL_PWRCTRL: | |
283 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) | |
284 | return pBase->openLoopPwrCntl ? true : false; | |
285 | else | |
286 | return false; | |
287 | case EEP_RC_CHAIN_MASK: | |
288 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) | |
289 | return pBase->rcChainMask; | |
290 | else | |
291 | return 0; | |
292 | case EEP_DAC_HPWR_5G: | |
293 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) | |
294 | return pBase->dacHiPwrMode_5G; | |
295 | else | |
296 | return 0; | |
297 | case EEP_FRAC_N_5G: | |
298 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22) | |
299 | return pBase->frac_n_5g; | |
300 | else | |
301 | return 0; | |
e41f0bfc SB |
302 | case EEP_PWR_TABLE_OFFSET: |
303 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21) | |
304 | return pBase->pwr_table_offset; | |
305 | else | |
306 | return AR5416_PWR_TABLE_OFFSET_DB; | |
b5aec950 S |
307 | default: |
308 | return 0; | |
309 | } | |
310 | } | |
311 | ||
312 | static void ath9k_hw_def_set_gain(struct ath_hw *ah, | |
313 | struct modal_eep_header *pModal, | |
314 | struct ar5416_eeprom_def *eep, | |
315 | u8 txRxAttenLocal, int regChainOffset, int i) | |
316 | { | |
317 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { | |
318 | txRxAttenLocal = pModal->txRxAttenCh[i]; | |
319 | ||
7a37081e | 320 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
b5aec950 S |
321 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, |
322 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, | |
323 | pModal->bswMargin[i]); | |
324 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
325 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, | |
326 | pModal->bswAtten[i]); | |
327 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
328 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, | |
329 | pModal->xatten2Margin[i]); | |
330 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
331 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, | |
332 | pModal->xatten2Db[i]); | |
333 | } else { | |
334 | REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
335 | (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & | |
336 | ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | |
337 | | SM(pModal-> bswMargin[i], | |
338 | AR_PHY_GAIN_2GHZ_BSW_MARGIN)); | |
339 | REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
340 | (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & | |
341 | ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | |
342 | | SM(pModal->bswAtten[i], | |
343 | AR_PHY_GAIN_2GHZ_BSW_ATTEN)); | |
344 | } | |
345 | } | |
346 | ||
7a37081e | 347 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
b5aec950 S |
348 | REG_RMW_FIELD(ah, |
349 | AR_PHY_RXGAIN + regChainOffset, | |
350 | AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); | |
351 | REG_RMW_FIELD(ah, | |
352 | AR_PHY_RXGAIN + regChainOffset, | |
353 | AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]); | |
354 | } else { | |
355 | REG_WRITE(ah, | |
356 | AR_PHY_RXGAIN + regChainOffset, | |
357 | (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & | |
358 | ~AR_PHY_RXGAIN_TXRX_ATTEN) | |
359 | | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN)); | |
360 | REG_WRITE(ah, | |
361 | AR_PHY_GAIN_2GHZ + regChainOffset, | |
362 | (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & | |
363 | ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | | |
364 | SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); | |
365 | } | |
366 | } | |
367 | ||
368 | static void ath9k_hw_def_set_board_values(struct ath_hw *ah, | |
369 | struct ath9k_channel *chan) | |
370 | { | |
371 | struct modal_eep_header *pModal; | |
372 | struct ar5416_eeprom_def *eep = &ah->eeprom.def; | |
373 | int i, regChainOffset; | |
374 | u8 txRxAttenLocal; | |
375 | ||
376 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
377 | txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; | |
378 | ||
379 | REG_WRITE(ah, AR_PHY_SWITCH_COM, | |
380 | ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); | |
381 | ||
382 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
383 | if (AR_SREV_9280(ah)) { | |
384 | if (i >= 2) | |
385 | break; | |
386 | } | |
387 | ||
388 | if (AR_SREV_5416_20_OR_LATER(ah) && | |
389 | (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) | |
390 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | |
391 | else | |
392 | regChainOffset = i * 0x1000; | |
393 | ||
394 | REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, | |
395 | pModal->antCtrlChain[i]); | |
396 | ||
397 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, | |
398 | (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & | |
399 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | | |
400 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | | |
401 | SM(pModal->iqCalICh[i], | |
402 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | | |
403 | SM(pModal->iqCalQCh[i], | |
404 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); | |
405 | ||
406 | if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) | |
407 | ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal, | |
408 | regChainOffset, i); | |
409 | } | |
410 | ||
7a37081e | 411 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
b5aec950 S |
412 | if (IS_CHAN_2GHZ(chan)) { |
413 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, | |
414 | AR_AN_RF2G1_CH0_OB, | |
415 | AR_AN_RF2G1_CH0_OB_S, | |
416 | pModal->ob); | |
417 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, | |
418 | AR_AN_RF2G1_CH0_DB, | |
419 | AR_AN_RF2G1_CH0_DB_S, | |
420 | pModal->db); | |
421 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, | |
422 | AR_AN_RF2G1_CH1_OB, | |
423 | AR_AN_RF2G1_CH1_OB_S, | |
424 | pModal->ob_ch1); | |
425 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, | |
426 | AR_AN_RF2G1_CH1_DB, | |
427 | AR_AN_RF2G1_CH1_DB_S, | |
428 | pModal->db_ch1); | |
429 | } else { | |
430 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, | |
431 | AR_AN_RF5G1_CH0_OB5, | |
432 | AR_AN_RF5G1_CH0_OB5_S, | |
433 | pModal->ob); | |
434 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, | |
435 | AR_AN_RF5G1_CH0_DB5, | |
436 | AR_AN_RF5G1_CH0_DB5_S, | |
437 | pModal->db); | |
438 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, | |
439 | AR_AN_RF5G1_CH1_OB5, | |
440 | AR_AN_RF5G1_CH1_OB5_S, | |
441 | pModal->ob_ch1); | |
442 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, | |
443 | AR_AN_RF5G1_CH1_DB5, | |
444 | AR_AN_RF5G1_CH1_DB5_S, | |
445 | pModal->db_ch1); | |
446 | } | |
447 | ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, | |
448 | AR_AN_TOP2_XPABIAS_LVL, | |
449 | AR_AN_TOP2_XPABIAS_LVL_S, | |
450 | pModal->xpaBiasLvl); | |
451 | ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, | |
452 | AR_AN_TOP2_LOCALBIAS, | |
453 | AR_AN_TOP2_LOCALBIAS_S, | |
f67e07eb FF |
454 | !!(pModal->lna_ctl & |
455 | LNA_CTL_LOCAL_BIAS)); | |
b5aec950 | 456 | REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, |
f67e07eb | 457 | !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA)); |
b5aec950 S |
458 | } |
459 | ||
460 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, | |
461 | pModal->switchSettling); | |
462 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, | |
463 | pModal->adcDesiredSize); | |
464 | ||
7a37081e | 465 | if (!AR_SREV_9280_20_OR_LATER(ah)) |
b5aec950 S |
466 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, |
467 | AR_PHY_DESIRED_SZ_PGA, | |
468 | pModal->pgaDesiredSize); | |
469 | ||
470 | REG_WRITE(ah, AR_PHY_RF_CTL4, | |
471 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | |
472 | | SM(pModal->txEndToXpaOff, | |
473 | AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | |
474 | | SM(pModal->txFrameToXpaOn, | |
475 | AR_PHY_RF_CTL4_FRAME_XPAA_ON) | |
476 | | SM(pModal->txFrameToXpaOn, | |
477 | AR_PHY_RF_CTL4_FRAME_XPAB_ON)); | |
478 | ||
479 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | |
480 | pModal->txEndToRxOn); | |
481 | ||
7a37081e | 482 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
b5aec950 S |
483 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, |
484 | pModal->thresh62); | |
485 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, | |
486 | AR_PHY_EXT_CCA0_THRESH62, | |
487 | pModal->thresh62); | |
488 | } else { | |
489 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, | |
490 | pModal->thresh62); | |
491 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, | |
492 | AR_PHY_EXT_CCA_THRESH62, | |
493 | pModal->thresh62); | |
494 | } | |
495 | ||
496 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { | |
497 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, | |
498 | AR_PHY_TX_END_DATA_START, | |
499 | pModal->txFrameToDataStart); | |
500 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, | |
501 | pModal->txFrameToPaOn); | |
502 | } | |
503 | ||
504 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { | |
505 | if (IS_CHAN_HT40(chan)) | |
506 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | |
507 | AR_PHY_SETTLING_SWITCH, | |
508 | pModal->swSettleHt40); | |
509 | } | |
510 | ||
511 | if (AR_SREV_9280_20_OR_LATER(ah) && | |
512 | AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) | |
513 | REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, | |
514 | AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, | |
515 | pModal->miscBits); | |
516 | ||
517 | ||
518 | if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) { | |
519 | if (IS_CHAN_2GHZ(chan)) | |
520 | REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, | |
521 | eep->baseEepHeader.dacLpMode); | |
522 | else if (eep->baseEepHeader.dacHiPwrMode_5G) | |
523 | REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); | |
524 | else | |
525 | REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, | |
526 | eep->baseEepHeader.dacLpMode); | |
527 | ||
d865ca6c SB |
528 | udelay(100); |
529 | ||
b5aec950 S |
530 | REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, |
531 | pModal->miscBits >> 2); | |
532 | ||
533 | REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, | |
534 | AR_PHY_TX_DESIRED_SCALE_CCK, | |
535 | eep->baseEepHeader.desiredScaleCCK); | |
536 | } | |
537 | } | |
538 | ||
539 | static void ath9k_hw_def_set_addac(struct ath_hw *ah, | |
540 | struct ath9k_channel *chan) | |
541 | { | |
542 | #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) | |
543 | struct modal_eep_header *pModal; | |
544 | struct ar5416_eeprom_def *eep = &ah->eeprom.def; | |
545 | u8 biaslevel; | |
546 | ||
547 | if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) | |
548 | return; | |
549 | ||
550 | if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) | |
551 | return; | |
552 | ||
553 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
554 | ||
555 | if (pModal->xpaBiasLvl != 0xff) { | |
556 | biaslevel = pModal->xpaBiasLvl; | |
557 | } else { | |
558 | u16 resetFreqBin, freqBin, freqCount = 0; | |
559 | struct chan_centers centers; | |
560 | ||
561 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
562 | ||
563 | resetFreqBin = FREQ2FBIN(centers.synth_center, | |
564 | IS_CHAN_2GHZ(chan)); | |
565 | freqBin = XPA_LVL_FREQ(0) & 0xff; | |
566 | biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14); | |
567 | ||
568 | freqCount++; | |
569 | ||
570 | while (freqCount < 3) { | |
571 | if (XPA_LVL_FREQ(freqCount) == 0x0) | |
572 | break; | |
573 | ||
574 | freqBin = XPA_LVL_FREQ(freqCount) & 0xff; | |
575 | if (resetFreqBin >= freqBin) | |
576 | biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14); | |
577 | else | |
578 | break; | |
579 | freqCount++; | |
580 | } | |
581 | } | |
582 | ||
583 | if (IS_CHAN_2GHZ(chan)) { | |
584 | INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac, | |
585 | 7, 1) & (~0x18)) | biaslevel << 3; | |
586 | } else { | |
587 | INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac, | |
588 | 6, 1) & (~0xc0)) | biaslevel << 6; | |
589 | } | |
590 | #undef XPA_LVL_FREQ | |
591 | } | |
592 | ||
593 | static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, | |
594 | struct ath9k_channel *chan, | |
595 | struct cal_data_per_freq *pRawDataSet, | |
596 | u8 *bChans, u16 availPiers, | |
6eb90d46 | 597 | u16 tPdGainOverlap, |
b5aec950 S |
598 | u16 *pPdGainBoundaries, u8 *pPDADCValues, |
599 | u16 numXpdGains) | |
600 | { | |
601 | int i, j, k; | |
602 | int16_t ss; | |
603 | u16 idxL = 0, idxR = 0, numPiers; | |
604 | static u8 vpdTableL[AR5416_NUM_PD_GAINS] | |
605 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
606 | static u8 vpdTableR[AR5416_NUM_PD_GAINS] | |
607 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
608 | static u8 vpdTableI[AR5416_NUM_PD_GAINS] | |
609 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
610 | ||
611 | u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; | |
612 | u8 minPwrT4[AR5416_NUM_PD_GAINS]; | |
613 | u8 maxPwrT4[AR5416_NUM_PD_GAINS]; | |
614 | int16_t vpdStep; | |
615 | int16_t tmpVal; | |
616 | u16 sizeCurrVpdTable, maxIndex, tgtIndex; | |
617 | bool match; | |
618 | int16_t minDelta = 0; | |
619 | struct chan_centers centers; | |
620 | ||
a5fdbcad | 621 | memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS); |
b5aec950 S |
622 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
623 | ||
624 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | |
625 | if (bChans[numPiers] == AR5416_BCHAN_UNUSED) | |
626 | break; | |
627 | } | |
628 | ||
629 | match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center, | |
630 | IS_CHAN_2GHZ(chan)), | |
631 | bChans, numPiers, &idxL, &idxR); | |
632 | ||
633 | if (match) { | |
634 | for (i = 0; i < numXpdGains; i++) { | |
635 | minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; | |
636 | maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; | |
637 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
638 | pRawDataSet[idxL].pwrPdg[i], | |
639 | pRawDataSet[idxL].vpdPdg[i], | |
640 | AR5416_PD_GAIN_ICEPTS, | |
641 | vpdTableI[i]); | |
642 | } | |
643 | } else { | |
644 | for (i = 0; i < numXpdGains; i++) { | |
645 | pVpdL = pRawDataSet[idxL].vpdPdg[i]; | |
646 | pPwrL = pRawDataSet[idxL].pwrPdg[i]; | |
647 | pVpdR = pRawDataSet[idxR].vpdPdg[i]; | |
648 | pPwrR = pRawDataSet[idxR].pwrPdg[i]; | |
649 | ||
650 | minPwrT4[i] = max(pPwrL[0], pPwrR[0]); | |
651 | ||
652 | maxPwrT4[i] = | |
653 | min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], | |
654 | pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); | |
655 | ||
656 | ||
657 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
658 | pPwrL, pVpdL, | |
659 | AR5416_PD_GAIN_ICEPTS, | |
660 | vpdTableL[i]); | |
661 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
662 | pPwrR, pVpdR, | |
663 | AR5416_PD_GAIN_ICEPTS, | |
664 | vpdTableR[i]); | |
665 | ||
666 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { | |
667 | vpdTableI[i][j] = | |
668 | (u8)(ath9k_hw_interpolate((u16) | |
669 | FREQ2FBIN(centers. | |
670 | synth_center, | |
671 | IS_CHAN_2GHZ | |
672 | (chan)), | |
673 | bChans[idxL], bChans[idxR], | |
674 | vpdTableL[i][j], vpdTableR[i][j])); | |
675 | } | |
676 | } | |
677 | } | |
678 | ||
b5aec950 S |
679 | k = 0; |
680 | ||
681 | for (i = 0; i < numXpdGains; i++) { | |
682 | if (i == (numXpdGains - 1)) | |
683 | pPdGainBoundaries[i] = | |
684 | (u16)(maxPwrT4[i] / 2); | |
685 | else | |
686 | pPdGainBoundaries[i] = | |
687 | (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); | |
688 | ||
689 | pPdGainBoundaries[i] = | |
690 | min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); | |
691 | ||
692 | if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { | |
693 | minDelta = pPdGainBoundaries[0] - 23; | |
694 | pPdGainBoundaries[0] = 23; | |
695 | } else { | |
696 | minDelta = 0; | |
697 | } | |
698 | ||
699 | if (i == 0) { | |
7a37081e | 700 | if (AR_SREV_9280_20_OR_LATER(ah)) |
b5aec950 S |
701 | ss = (int16_t)(0 - (minPwrT4[i] / 2)); |
702 | else | |
703 | ss = 0; | |
704 | } else { | |
705 | ss = (int16_t)((pPdGainBoundaries[i - 1] - | |
706 | (minPwrT4[i] / 2)) - | |
707 | tPdGainOverlap + 1 + minDelta); | |
708 | } | |
709 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); | |
710 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
711 | ||
712 | while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
713 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); | |
714 | pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); | |
715 | ss++; | |
716 | } | |
717 | ||
718 | sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); | |
719 | tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - | |
720 | (minPwrT4[i] / 2)); | |
721 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? | |
722 | tgtIndex : sizeCurrVpdTable; | |
723 | ||
724 | while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
725 | pPDADCValues[k++] = vpdTableI[i][ss++]; | |
726 | } | |
727 | ||
728 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - | |
729 | vpdTableI[i][sizeCurrVpdTable - 2]); | |
730 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
731 | ||
03b4776c | 732 | if (tgtIndex >= maxIndex) { |
b5aec950 S |
733 | while ((ss <= tgtIndex) && |
734 | (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
735 | tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + | |
736 | (ss - maxIndex + 1) * vpdStep)); | |
737 | pPDADCValues[k++] = (u8)((tmpVal > 255) ? | |
738 | 255 : tmpVal); | |
739 | ss++; | |
740 | } | |
741 | } | |
742 | } | |
743 | ||
744 | while (i < AR5416_PD_GAINS_IN_MASK) { | |
745 | pPdGainBoundaries[i] = pPdGainBoundaries[i - 1]; | |
746 | i++; | |
747 | } | |
748 | ||
749 | while (k < AR5416_NUM_PDADC_VALUES) { | |
750 | pPDADCValues[k] = pPDADCValues[k - 1]; | |
751 | k++; | |
752 | } | |
b5aec950 S |
753 | } |
754 | ||
e41f0bfc SB |
755 | static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah, |
756 | u16 *gb, | |
757 | u16 numXpdGain, | |
758 | u16 pdGainOverlap_t2, | |
759 | int8_t pwr_table_offset, | |
760 | int16_t *diff) | |
761 | ||
762 | { | |
763 | u16 k; | |
764 | ||
765 | /* Prior to writing the boundaries or the pdadc vs. power table | |
766 | * into the chip registers the default starting point on the pdadc | |
767 | * vs. power table needs to be checked and the curve boundaries | |
768 | * adjusted accordingly | |
769 | */ | |
770 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
771 | u16 gb_limit; | |
772 | ||
773 | if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) { | |
774 | /* get the difference in dB */ | |
775 | *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB); | |
776 | /* get the number of half dB steps */ | |
777 | *diff *= 2; | |
778 | /* change the original gain boundary settings | |
779 | * by the number of half dB steps | |
780 | */ | |
781 | for (k = 0; k < numXpdGain; k++) | |
782 | gb[k] = (u16)(gb[k] - *diff); | |
783 | } | |
784 | /* Because of a hardware limitation, ensure the gain boundary | |
785 | * is not larger than (63 - overlap) | |
786 | */ | |
787 | gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2); | |
788 | ||
789 | for (k = 0; k < numXpdGain; k++) | |
790 | gb[k] = (u16)min(gb_limit, gb[k]); | |
791 | } | |
792 | ||
793 | return *diff; | |
794 | } | |
795 | ||
796 | static void ath9k_adjust_pdadc_values(struct ath_hw *ah, | |
797 | int8_t pwr_table_offset, | |
798 | int16_t diff, | |
799 | u8 *pdadcValues) | |
800 | { | |
801 | #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff) | |
802 | u16 k; | |
803 | ||
804 | /* If this is a board that has a pwrTableOffset that differs from | |
805 | * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the | |
806 | * pdadc vs pwr table needs to be adjusted prior to writing to the | |
807 | * chip. | |
808 | */ | |
809 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
810 | if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) { | |
811 | /* shift the table to start at the new offset */ | |
812 | for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) { | |
813 | pdadcValues[k] = pdadcValues[k + diff]; | |
814 | } | |
815 | ||
816 | /* fill the back of the table */ | |
817 | for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) { | |
818 | pdadcValues[k] = pdadcValues[NUM_PDADC(diff)]; | |
819 | } | |
820 | } | |
821 | } | |
822 | #undef NUM_PDADC | |
823 | } | |
824 | ||
b5aec950 S |
825 | static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, |
826 | struct ath9k_channel *chan, | |
827 | int16_t *pTxPowerIndexOffset) | |
828 | { | |
829 | #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x) | |
830 | #define SM_PDGAIN_B(x, y) \ | |
831 | SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y) | |
c46917bb | 832 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
833 | struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; |
834 | struct cal_data_per_freq *pRawDataset; | |
835 | u8 *pCalBChans = NULL; | |
836 | u16 pdGainOverlap_t2; | |
837 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; | |
838 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; | |
839 | u16 numPiers, i, j; | |
6eb90d46 | 840 | int16_t diff = 0; |
b5aec950 S |
841 | u16 numXpdGain, xpdMask; |
842 | u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; | |
843 | u32 reg32, regOffset, regChainOffset; | |
844 | int16_t modalIdx; | |
e41f0bfc | 845 | int8_t pwr_table_offset; |
b5aec950 S |
846 | |
847 | modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; | |
848 | xpdMask = pEepData->modalHeader[modalIdx].xpdGain; | |
849 | ||
e41f0bfc SB |
850 | pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET); |
851 | ||
b5aec950 S |
852 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= |
853 | AR5416_EEP_MINOR_VER_2) { | |
854 | pdGainOverlap_t2 = | |
855 | pEepData->modalHeader[modalIdx].pdGainOverlap; | |
856 | } else { | |
857 | pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), | |
858 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); | |
859 | } | |
860 | ||
861 | if (IS_CHAN_2GHZ(chan)) { | |
862 | pCalBChans = pEepData->calFreqPier2G; | |
863 | numPiers = AR5416_NUM_2G_CAL_PIERS; | |
864 | } else { | |
865 | pCalBChans = pEepData->calFreqPier5G; | |
866 | numPiers = AR5416_NUM_5G_CAL_PIERS; | |
867 | } | |
868 | ||
869 | if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) { | |
870 | pRawDataset = pEepData->calPierData2G[0]; | |
871 | ah->initPDADC = ((struct calDataPerFreqOpLoop *) | |
872 | pRawDataset)->vpdPdg[0][0]; | |
873 | } | |
874 | ||
875 | numXpdGain = 0; | |
876 | ||
877 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { | |
878 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { | |
879 | if (numXpdGain >= AR5416_NUM_PD_GAINS) | |
880 | break; | |
881 | xpdGainValues[numXpdGain] = | |
882 | (u16)(AR5416_PD_GAINS_IN_MASK - i); | |
883 | numXpdGain++; | |
884 | } | |
885 | } | |
886 | ||
887 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, | |
888 | (numXpdGain - 1) & 0x3); | |
889 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, | |
890 | xpdGainValues[0]); | |
891 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, | |
892 | xpdGainValues[1]); | |
893 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, | |
894 | xpdGainValues[2]); | |
895 | ||
896 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
897 | if (AR_SREV_5416_20_OR_LATER(ah) && | |
898 | (ah->rxchainmask == 5 || ah->txchainmask == 5) && | |
899 | (i != 0)) { | |
900 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | |
901 | } else | |
902 | regChainOffset = i * 0x1000; | |
903 | ||
904 | if (pEepData->baseEepHeader.txMask & (1 << i)) { | |
905 | if (IS_CHAN_2GHZ(chan)) | |
906 | pRawDataset = pEepData->calPierData2G[i]; | |
907 | else | |
908 | pRawDataset = pEepData->calPierData5G[i]; | |
909 | ||
910 | ||
911 | if (OLC_FOR_AR9280_20_LATER) { | |
912 | u8 pcdacIdx; | |
913 | u8 txPower; | |
914 | ||
915 | ath9k_get_txgain_index(ah, chan, | |
916 | (struct calDataPerFreqOpLoop *)pRawDataset, | |
917 | pCalBChans, numPiers, &txPower, &pcdacIdx); | |
918 | ath9k_olc_get_pdadcs(ah, pcdacIdx, | |
919 | txPower/2, pdadcValues); | |
920 | } else { | |
921 | ath9k_hw_get_def_gain_boundaries_pdadcs(ah, | |
922 | chan, pRawDataset, | |
923 | pCalBChans, numPiers, | |
924 | pdGainOverlap_t2, | |
b5aec950 S |
925 | gainBoundaries, |
926 | pdadcValues, | |
927 | numXpdGain); | |
928 | } | |
929 | ||
e41f0bfc SB |
930 | diff = ath9k_change_gain_boundary_setting(ah, |
931 | gainBoundaries, | |
932 | numXpdGain, | |
933 | pdGainOverlap_t2, | |
934 | pwr_table_offset, | |
935 | &diff); | |
936 | ||
b5aec950 S |
937 | if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { |
938 | if (OLC_FOR_AR9280_20_LATER) { | |
939 | REG_WRITE(ah, | |
940 | AR_PHY_TPCRG5 + regChainOffset, | |
941 | SM(0x6, | |
942 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | | |
943 | SM_PD_GAIN(1) | SM_PD_GAIN(2) | | |
944 | SM_PD_GAIN(3) | SM_PD_GAIN(4)); | |
945 | } else { | |
946 | REG_WRITE(ah, | |
947 | AR_PHY_TPCRG5 + regChainOffset, | |
948 | SM(pdGainOverlap_t2, | |
949 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)| | |
950 | SM_PDGAIN_B(0, 1) | | |
951 | SM_PDGAIN_B(1, 2) | | |
952 | SM_PDGAIN_B(2, 3) | | |
953 | SM_PDGAIN_B(3, 4)); | |
954 | } | |
955 | } | |
956 | ||
e41f0bfc SB |
957 | |
958 | ath9k_adjust_pdadc_values(ah, pwr_table_offset, | |
959 | diff, pdadcValues); | |
960 | ||
b5aec950 S |
961 | regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; |
962 | for (j = 0; j < 32; j++) { | |
963 | reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | | |
964 | ((pdadcValues[4 * j + 1] & 0xFF) << 8) | | |
965 | ((pdadcValues[4 * j + 2] & 0xFF) << 16)| | |
966 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); | |
967 | REG_WRITE(ah, regOffset, reg32); | |
968 | ||
c46917bb LR |
969 | ath_print(common, ATH_DBG_EEPROM, |
970 | "PDADC (%d,%4x): %4.4x %8.8x\n", | |
971 | i, regChainOffset, regOffset, | |
972 | reg32); | |
973 | ath_print(common, ATH_DBG_EEPROM, | |
974 | "PDADC: Chain %d | PDADC %3d " | |
975 | "Value %3d | PDADC %3d Value %3d | " | |
976 | "PDADC %3d Value %3d | PDADC %3d " | |
977 | "Value %3d |\n", | |
978 | i, 4 * j, pdadcValues[4 * j], | |
979 | 4 * j + 1, pdadcValues[4 * j + 1], | |
980 | 4 * j + 2, pdadcValues[4 * j + 2], | |
981 | 4 * j + 3, | |
982 | pdadcValues[4 * j + 3]); | |
b5aec950 S |
983 | |
984 | regOffset += 4; | |
985 | } | |
986 | } | |
987 | } | |
988 | ||
989 | *pTxPowerIndexOffset = 0; | |
990 | #undef SM_PD_GAIN | |
991 | #undef SM_PDGAIN_B | |
992 | } | |
993 | ||
994 | static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, | |
995 | struct ath9k_channel *chan, | |
996 | int16_t *ratesArray, | |
997 | u16 cfgCtl, | |
998 | u16 AntennaReduction, | |
999 | u16 twiceMaxRegulatoryPower, | |
1000 | u16 powerLimit) | |
1001 | { | |
1002 | #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ | |
d865ca6c | 1003 | #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */ |
b5aec950 | 1004 | |
608b88cb | 1005 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
b5aec950 S |
1006 | struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; |
1007 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | |
1008 | static const u16 tpScaleReductionTable[5] = | |
1009 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | |
1010 | ||
1011 | int i; | |
1012 | int16_t twiceLargestAntenna; | |
1013 | struct cal_ctl_data *rep; | |
1014 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { | |
1015 | 0, { 0, 0, 0, 0} | |
1016 | }; | |
1017 | struct cal_target_power_leg targetPowerOfdmExt = { | |
1018 | 0, { 0, 0, 0, 0} }, targetPowerCckExt = { | |
1019 | 0, { 0, 0, 0, 0 } | |
1020 | }; | |
1021 | struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { | |
1022 | 0, {0, 0, 0, 0} | |
1023 | }; | |
1024 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; | |
07b2fa5a JP |
1025 | static const u16 ctlModesFor11a[] = { |
1026 | CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 | |
1027 | }; | |
1028 | static const u16 ctlModesFor11g[] = { | |
1029 | CTL_11B, CTL_11G, CTL_2GHT20, | |
1030 | CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 | |
1031 | }; | |
1032 | u16 numCtlModes; | |
1033 | const u16 *pCtlMode; | |
1034 | u16 ctlMode, freq; | |
b5aec950 S |
1035 | struct chan_centers centers; |
1036 | int tx_chainmask; | |
1037 | u16 twiceMinEdgePower; | |
1038 | ||
1039 | tx_chainmask = ah->txchainmask; | |
1040 | ||
1041 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
1042 | ||
1043 | twiceLargestAntenna = max( | |
1044 | pEepData->modalHeader | |
1045 | [IS_CHAN_2GHZ(chan)].antennaGainCh[0], | |
1046 | pEepData->modalHeader | |
1047 | [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); | |
1048 | ||
1049 | twiceLargestAntenna = max((u8)twiceLargestAntenna, | |
1050 | pEepData->modalHeader | |
1051 | [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); | |
1052 | ||
1053 | twiceLargestAntenna = (int16_t)min(AntennaReduction - | |
1054 | twiceLargestAntenna, 0); | |
1055 | ||
1056 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; | |
1057 | ||
608b88cb | 1058 | if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) { |
b5aec950 | 1059 | maxRegAllowedPower -= |
608b88cb | 1060 | (tpScaleReductionTable[(regulatory->tp_scale)] * 2); |
b5aec950 S |
1061 | } |
1062 | ||
1063 | scaledPower = min(powerLimit, maxRegAllowedPower); | |
1064 | ||
1065 | switch (ar5416_get_ntxchains(tx_chainmask)) { | |
1066 | case 1: | |
1067 | break; | |
1068 | case 2: | |
1069 | scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; | |
1070 | break; | |
1071 | case 3: | |
1072 | scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; | |
1073 | break; | |
1074 | } | |
1075 | ||
1076 | scaledPower = max((u16)0, scaledPower); | |
1077 | ||
1078 | if (IS_CHAN_2GHZ(chan)) { | |
1079 | numCtlModes = ARRAY_SIZE(ctlModesFor11g) - | |
1080 | SUB_NUM_CTL_MODES_AT_2G_40; | |
1081 | pCtlMode = ctlModesFor11g; | |
1082 | ||
1083 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1084 | pEepData->calTargetPowerCck, | |
1085 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
1086 | &targetPowerCck, 4, false); | |
1087 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1088 | pEepData->calTargetPower2G, | |
1089 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1090 | &targetPowerOfdm, 4, false); | |
1091 | ath9k_hw_get_target_powers(ah, chan, | |
1092 | pEepData->calTargetPower2GHT20, | |
1093 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1094 | &targetPowerHt20, 8, false); | |
1095 | ||
1096 | if (IS_CHAN_HT40(chan)) { | |
1097 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
1098 | ath9k_hw_get_target_powers(ah, chan, | |
1099 | pEepData->calTargetPower2GHT40, | |
1100 | AR5416_NUM_2G_40_TARGET_POWERS, | |
1101 | &targetPowerHt40, 8, true); | |
1102 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1103 | pEepData->calTargetPowerCck, | |
1104 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
1105 | &targetPowerCckExt, 4, true); | |
1106 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1107 | pEepData->calTargetPower2G, | |
1108 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1109 | &targetPowerOfdmExt, 4, true); | |
1110 | } | |
1111 | } else { | |
1112 | numCtlModes = ARRAY_SIZE(ctlModesFor11a) - | |
1113 | SUB_NUM_CTL_MODES_AT_5G_40; | |
1114 | pCtlMode = ctlModesFor11a; | |
1115 | ||
1116 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1117 | pEepData->calTargetPower5G, | |
1118 | AR5416_NUM_5G_20_TARGET_POWERS, | |
1119 | &targetPowerOfdm, 4, false); | |
1120 | ath9k_hw_get_target_powers(ah, chan, | |
1121 | pEepData->calTargetPower5GHT20, | |
1122 | AR5416_NUM_5G_20_TARGET_POWERS, | |
1123 | &targetPowerHt20, 8, false); | |
1124 | ||
1125 | if (IS_CHAN_HT40(chan)) { | |
1126 | numCtlModes = ARRAY_SIZE(ctlModesFor11a); | |
1127 | ath9k_hw_get_target_powers(ah, chan, | |
1128 | pEepData->calTargetPower5GHT40, | |
1129 | AR5416_NUM_5G_40_TARGET_POWERS, | |
1130 | &targetPowerHt40, 8, true); | |
1131 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1132 | pEepData->calTargetPower5G, | |
1133 | AR5416_NUM_5G_20_TARGET_POWERS, | |
1134 | &targetPowerOfdmExt, 4, true); | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
1139 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
1140 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
1141 | if (isHt40CtlMode) | |
1142 | freq = centers.synth_center; | |
1143 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
1144 | freq = centers.ext_center; | |
1145 | else | |
1146 | freq = centers.ctl_center; | |
1147 | ||
1148 | if (ah->eep_ops->get_eeprom_ver(ah) == 14 && | |
1149 | ah->eep_ops->get_eeprom_rev(ah) <= 2) | |
1150 | twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | |
1151 | ||
1152 | for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { | |
1153 | if ((((cfgCtl & ~CTL_MODE_M) | | |
1154 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
1155 | pEepData->ctlIndex[i]) || | |
1156 | (((cfgCtl & ~CTL_MODE_M) | | |
1157 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
1158 | ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { | |
1159 | rep = &(pEepData->ctlData[i]); | |
1160 | ||
1161 | twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, | |
1162 | rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], | |
1163 | IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); | |
1164 | ||
1165 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { | |
1166 | twiceMaxEdgePower = min(twiceMaxEdgePower, | |
1167 | twiceMinEdgePower); | |
1168 | } else { | |
1169 | twiceMaxEdgePower = twiceMinEdgePower; | |
1170 | break; | |
1171 | } | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | minCtlPower = min(twiceMaxEdgePower, scaledPower); | |
1176 | ||
1177 | switch (pCtlMode[ctlMode]) { | |
1178 | case CTL_11B: | |
1179 | for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { | |
1180 | targetPowerCck.tPow2x[i] = | |
1181 | min((u16)targetPowerCck.tPow2x[i], | |
1182 | minCtlPower); | |
1183 | } | |
1184 | break; | |
1185 | case CTL_11A: | |
1186 | case CTL_11G: | |
1187 | for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { | |
1188 | targetPowerOfdm.tPow2x[i] = | |
1189 | min((u16)targetPowerOfdm.tPow2x[i], | |
1190 | minCtlPower); | |
1191 | } | |
1192 | break; | |
1193 | case CTL_5GHT20: | |
1194 | case CTL_2GHT20: | |
1195 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { | |
1196 | targetPowerHt20.tPow2x[i] = | |
1197 | min((u16)targetPowerHt20.tPow2x[i], | |
1198 | minCtlPower); | |
1199 | } | |
1200 | break; | |
1201 | case CTL_11B_EXT: | |
1202 | targetPowerCckExt.tPow2x[0] = min((u16) | |
1203 | targetPowerCckExt.tPow2x[0], | |
1204 | minCtlPower); | |
1205 | break; | |
1206 | case CTL_11A_EXT: | |
1207 | case CTL_11G_EXT: | |
1208 | targetPowerOfdmExt.tPow2x[0] = min((u16) | |
1209 | targetPowerOfdmExt.tPow2x[0], | |
1210 | minCtlPower); | |
1211 | break; | |
1212 | case CTL_5GHT40: | |
1213 | case CTL_2GHT40: | |
1214 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
1215 | targetPowerHt40.tPow2x[i] = | |
1216 | min((u16)targetPowerHt40.tPow2x[i], | |
1217 | minCtlPower); | |
1218 | } | |
1219 | break; | |
1220 | default: | |
1221 | break; | |
1222 | } | |
1223 | } | |
1224 | ||
1225 | ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = | |
1226 | ratesArray[rate18mb] = ratesArray[rate24mb] = | |
1227 | targetPowerOfdm.tPow2x[0]; | |
1228 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; | |
1229 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; | |
1230 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; | |
1231 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; | |
1232 | ||
1233 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) | |
1234 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; | |
1235 | ||
1236 | if (IS_CHAN_2GHZ(chan)) { | |
1237 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; | |
1238 | ratesArray[rate2s] = ratesArray[rate2l] = | |
1239 | targetPowerCck.tPow2x[1]; | |
1240 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = | |
1241 | targetPowerCck.tPow2x[2]; | |
1242 | ratesArray[rate11s] = ratesArray[rate11l] = | |
1243 | targetPowerCck.tPow2x[3]; | |
1244 | } | |
1245 | if (IS_CHAN_HT40(chan)) { | |
1246 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
1247 | ratesArray[rateHt40_0 + i] = | |
1248 | targetPowerHt40.tPow2x[i]; | |
1249 | } | |
1250 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; | |
1251 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; | |
1252 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; | |
1253 | if (IS_CHAN_2GHZ(chan)) { | |
1254 | ratesArray[rateExtCck] = | |
1255 | targetPowerCckExt.tPow2x[0]; | |
1256 | } | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | static void ath9k_hw_def_set_txpower(struct ath_hw *ah, | |
1261 | struct ath9k_channel *chan, | |
1262 | u16 cfgCtl, | |
1263 | u8 twiceAntennaReduction, | |
1264 | u8 twiceMaxRegulatoryPower, | |
de40f316 | 1265 | u8 powerLimit, bool test) |
b5aec950 S |
1266 | { |
1267 | #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta) | |
608b88cb | 1268 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
b5aec950 S |
1269 | struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; |
1270 | struct modal_eep_header *pModal = | |
1271 | &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); | |
1272 | int16_t ratesArray[Ar5416RateSize]; | |
1273 | int16_t txPowerIndexOffset = 0; | |
1274 | u8 ht40PowerIncForPdadc = 2; | |
1275 | int i, cck_ofdm_delta = 0; | |
1276 | ||
1277 | memset(ratesArray, 0, sizeof(ratesArray)); | |
1278 | ||
1279 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1280 | AR5416_EEP_MINOR_VER_2) { | |
1281 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; | |
1282 | } | |
1283 | ||
1284 | ath9k_hw_set_def_power_per_rate_table(ah, chan, | |
1285 | &ratesArray[0], cfgCtl, | |
1286 | twiceAntennaReduction, | |
1287 | twiceMaxRegulatoryPower, | |
1288 | powerLimit); | |
1289 | ||
1290 | ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset); | |
1291 | ||
de40f316 | 1292 | regulatory->max_power_level = 0; |
b5aec950 S |
1293 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
1294 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | |
1295 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) | |
1296 | ratesArray[i] = AR5416_MAX_RATE_POWER; | |
de40f316 FF |
1297 | if (ratesArray[i] > regulatory->max_power_level) |
1298 | regulatory->max_power_level = ratesArray[i]; | |
b5aec950 S |
1299 | } |
1300 | ||
de40f316 FF |
1301 | if (!test) { |
1302 | i = rate6mb; | |
1303 | ||
1304 | if (IS_CHAN_HT40(chan)) | |
1305 | i = rateHt40_0; | |
1306 | else if (IS_CHAN_HT20(chan)) | |
1307 | i = rateHt20_0; | |
1308 | ||
1309 | regulatory->max_power_level = ratesArray[i]; | |
1310 | } | |
1311 | ||
1312 | switch(ar5416_get_ntxchains(ah->txchainmask)) { | |
1313 | case 1: | |
1314 | break; | |
1315 | case 2: | |
1316 | regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN; | |
1317 | break; | |
1318 | case 3: | |
1319 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; | |
1320 | break; | |
1321 | default: | |
1322 | ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM, | |
1323 | "Invalid chainmask configuration\n"); | |
1324 | break; | |
1325 | } | |
1326 | ||
1327 | if (test) | |
1328 | return; | |
1329 | ||
7a37081e | 1330 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
e41f0bfc SB |
1331 | for (i = 0; i < Ar5416RateSize; i++) { |
1332 | int8_t pwr_table_offset; | |
1333 | ||
1334 | pwr_table_offset = ah->eep_ops->get_eeprom(ah, | |
1335 | EEP_PWR_TABLE_OFFSET); | |
1336 | ratesArray[i] -= pwr_table_offset * 2; | |
1337 | } | |
b5aec950 S |
1338 | } |
1339 | ||
1340 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, | |
1341 | ATH9K_POW_SM(ratesArray[rate18mb], 24) | |
1342 | | ATH9K_POW_SM(ratesArray[rate12mb], 16) | |
1343 | | ATH9K_POW_SM(ratesArray[rate9mb], 8) | |
1344 | | ATH9K_POW_SM(ratesArray[rate6mb], 0)); | |
1345 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, | |
1346 | ATH9K_POW_SM(ratesArray[rate54mb], 24) | |
1347 | | ATH9K_POW_SM(ratesArray[rate48mb], 16) | |
1348 | | ATH9K_POW_SM(ratesArray[rate36mb], 8) | |
1349 | | ATH9K_POW_SM(ratesArray[rate24mb], 0)); | |
1350 | ||
1351 | if (IS_CHAN_2GHZ(chan)) { | |
1352 | if (OLC_FOR_AR9280_20_LATER) { | |
1353 | cck_ofdm_delta = 2; | |
1354 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | |
1355 | ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24) | |
1356 | | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16) | |
1357 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | |
1358 | | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0)); | |
1359 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | |
1360 | ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24) | |
1361 | | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16) | |
1362 | | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8) | |
1363 | | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0)); | |
1364 | } else { | |
1365 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | |
1366 | ATH9K_POW_SM(ratesArray[rate2s], 24) | |
1367 | | ATH9K_POW_SM(ratesArray[rate2l], 16) | |
1368 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | |
1369 | | ATH9K_POW_SM(ratesArray[rate1l], 0)); | |
1370 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | |
1371 | ATH9K_POW_SM(ratesArray[rate11s], 24) | |
1372 | | ATH9K_POW_SM(ratesArray[rate11l], 16) | |
1373 | | ATH9K_POW_SM(ratesArray[rate5_5s], 8) | |
1374 | | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); | |
1375 | } | |
1376 | } | |
1377 | ||
1378 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, | |
1379 | ATH9K_POW_SM(ratesArray[rateHt20_3], 24) | |
1380 | | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | |
1381 | | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) | |
1382 | | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); | |
1383 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, | |
1384 | ATH9K_POW_SM(ratesArray[rateHt20_7], 24) | |
1385 | | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) | |
1386 | | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | |
1387 | | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); | |
1388 | ||
1389 | if (IS_CHAN_HT40(chan)) { | |
1390 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | |
1391 | ATH9K_POW_SM(ratesArray[rateHt40_3] + | |
1392 | ht40PowerIncForPdadc, 24) | |
1393 | | ATH9K_POW_SM(ratesArray[rateHt40_2] + | |
1394 | ht40PowerIncForPdadc, 16) | |
1395 | | ATH9K_POW_SM(ratesArray[rateHt40_1] + | |
1396 | ht40PowerIncForPdadc, 8) | |
1397 | | ATH9K_POW_SM(ratesArray[rateHt40_0] + | |
1398 | ht40PowerIncForPdadc, 0)); | |
1399 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | |
1400 | ATH9K_POW_SM(ratesArray[rateHt40_7] + | |
1401 | ht40PowerIncForPdadc, 24) | |
1402 | | ATH9K_POW_SM(ratesArray[rateHt40_6] + | |
1403 | ht40PowerIncForPdadc, 16) | |
1404 | | ATH9K_POW_SM(ratesArray[rateHt40_5] + | |
1405 | ht40PowerIncForPdadc, 8) | |
1406 | | ATH9K_POW_SM(ratesArray[rateHt40_4] + | |
1407 | ht40PowerIncForPdadc, 0)); | |
1408 | if (OLC_FOR_AR9280_20_LATER) { | |
1409 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, | |
1410 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | |
1411 | | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16) | |
1412 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | |
1413 | | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0)); | |
1414 | } else { | |
1415 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, | |
1416 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | |
1417 | | ATH9K_POW_SM(ratesArray[rateExtCck], 16) | |
1418 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | |
1419 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); | |
1420 | } | |
1421 | } | |
1422 | ||
1423 | REG_WRITE(ah, AR_PHY_POWER_TX_SUB, | |
1424 | ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) | |
1425 | | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); | |
b5aec950 S |
1426 | } |
1427 | ||
1428 | static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, | |
f799a301 | 1429 | enum ath9k_hal_freq_band freq_band) |
b5aec950 S |
1430 | { |
1431 | struct ar5416_eeprom_def *eep = &ah->eeprom.def; | |
1432 | struct modal_eep_header *pModal = | |
f799a301 | 1433 | &(eep->modalHeader[freq_band]); |
b5aec950 S |
1434 | struct base_eep_header *pBase = &eep->baseEepHeader; |
1435 | u8 num_ant_config; | |
1436 | ||
1437 | num_ant_config = 1; | |
1438 | ||
f67e07eb FF |
1439 | if (pBase->version >= 0x0E0D && |
1440 | (pModal->lna_ctl & LNA_CTL_USE_ANT1)) | |
1441 | num_ant_config += 1; | |
b5aec950 S |
1442 | |
1443 | return num_ant_config; | |
1444 | } | |
1445 | ||
601e0cb1 | 1446 | static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah, |
b5aec950 S |
1447 | struct ath9k_channel *chan) |
1448 | { | |
1449 | struct ar5416_eeprom_def *eep = &ah->eeprom.def; | |
1450 | struct modal_eep_header *pModal = | |
1451 | &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
1452 | ||
601e0cb1 | 1453 | return pModal->antCtrlCommon; |
b5aec950 S |
1454 | } |
1455 | ||
1456 | static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) | |
1457 | { | |
1458 | #define EEP_DEF_SPURCHAN \ | |
1459 | (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) | |
c46917bb | 1460 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
1461 | |
1462 | u16 spur_val = AR_NO_SPUR; | |
1463 | ||
c46917bb LR |
1464 | ath_print(common, ATH_DBG_ANI, |
1465 | "Getting spur idx %d is2Ghz. %d val %x\n", | |
1466 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | |
b5aec950 S |
1467 | |
1468 | switch (ah->config.spurmode) { | |
1469 | case SPUR_DISABLE: | |
1470 | break; | |
1471 | case SPUR_ENABLE_IOCTL: | |
1472 | spur_val = ah->config.spurchans[i][is2GHz]; | |
c46917bb LR |
1473 | ath_print(common, ATH_DBG_ANI, |
1474 | "Getting spur val from new loc. %d\n", spur_val); | |
b5aec950 S |
1475 | break; |
1476 | case SPUR_ENABLE_EEPROM: | |
1477 | spur_val = EEP_DEF_SPURCHAN; | |
1478 | break; | |
1479 | } | |
1480 | ||
1481 | return spur_val; | |
1482 | ||
1483 | #undef EEP_DEF_SPURCHAN | |
1484 | } | |
1485 | ||
1486 | const struct eeprom_ops eep_def_ops = { | |
1487 | .check_eeprom = ath9k_hw_def_check_eeprom, | |
1488 | .get_eeprom = ath9k_hw_def_get_eeprom, | |
1489 | .fill_eeprom = ath9k_hw_def_fill_eeprom, | |
1490 | .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver, | |
1491 | .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev, | |
1492 | .get_num_ant_config = ath9k_hw_def_get_num_ant_config, | |
1493 | .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg, | |
1494 | .set_board_values = ath9k_hw_def_set_board_values, | |
1495 | .set_addac = ath9k_hw_def_set_addac, | |
1496 | .set_txpower = ath9k_hw_def_set_txpower, | |
1497 | .get_spur_channel = ath9k_hw_def_get_spur_channel | |
1498 | }; |