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ath9k: set beacon related ps flags on bss_info change
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / eeprom_def.c
CommitLineData
b5aec950
S		 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
c46917bb 17#include "hw.h"
8fe65368 18#include "ar9002_phy.h"
b5aec950
S		 19
20static void ath9k_get_txgain_index(struct ath_hw *ah,
21 struct ath9k_channel *chan,
22 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
23 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
24{
25 u8 pcdac, i = 0;
26 u16 idxL = 0, idxR = 0, numPiers;
27 bool match;
28 struct chan_centers centers;
29
30 ath9k_hw_get_channel_centers(ah, chan, &centers);
31
32 for (numPiers = 0; numPiers < availPiers; numPiers++)
33 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
34 break;
35
36 match = ath9k_hw_get_lower_upper_index(
37 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
38 calChans, numPiers, &idxL, &idxR);
39 if (match) {
40 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
41 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
42 } else {
43 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
44 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
45 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
46 }
47
48 while (pcdac > ah->originalGain[i] &&
49 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
50 i++;
51
52 *pcdacIdx = i;
b5aec950
S		 53}
54
55static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
56 u32 initTxGain,
57 int txPower,
58 u8 *pPDADCValues)
59{
60 u32 i;
61 u32 offset;
62
63 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
64 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
65 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
66 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
67
68 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
69 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
70
71 offset = txPower;
72 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
73 if (i < offset)
74 pPDADCValues[i] = 0x0;
75 else
76 pPDADCValues[i] = 0xFF;
77}
78
79static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
80{
81 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
82}
83
84static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
85{
86 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
87}
88
b5aec950 89#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
04cf53f4
SM		 90
91static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
92{
5bb12791 93 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 94 u16 *eep_data = (u16 *)&ah->eeprom.def;
95 int addr, ar5416_eep_start_loc = 0x100;
96
97 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
5bb12791 98 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
b5aec950 99 eep_data)) {
3800276a
JP		 100 ath_err(ath9k_hw_common(ah),
101 "Unable to read eeprom region\n");
b5aec950
S		 102 return false;
103 }
104 eep_data++;
105 }
106 return true;
b5aec950
S		 107}
108
04cf53f4
SM		 109static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
110{
111 u16 *eep_data = (u16 *)&ah->eeprom.def;
112
113 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
114 0x100, SIZE_EEPROM_DEF);
115 return true;
116}
117
118static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
119{
120 struct ath_common *common = ath9k_hw_common(ah);
121
122 if (!ath9k_hw_use_flash(ah)) {
123 ath_dbg(common, ATH_DBG_EEPROM,
124 "Reading from EEPROM, not flash\n");
125 }
126
127 if (common->bus_ops->ath_bus_type == ATH_USB)
128 return __ath9k_hw_usb_def_fill_eeprom(ah);
129 else
130 return __ath9k_hw_def_fill_eeprom(ah);
131}
132
133#undef SIZE_EEPROM_DEF
134
b5aec950
S		 135static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
136{
137 struct ar5416_eeprom_def *eep =
138 (struct ar5416_eeprom_def *) &ah->eeprom.def;
c46917bb 139 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 140 u16 *eepdata, temp, magic, magic2;
141 u32 sum = 0, el;
142 bool need_swap = false;
143 int i, addr, size;
144
5bb12791 145 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
3800276a 146 ath_err(common, "Reading Magic # failed\n");
b5aec950
S		 147 return false;
148 }
149
150 if (!ath9k_hw_use_flash(ah)) {
226afe68
JP		 151 ath_dbg(common, ATH_DBG_EEPROM,
152 "Read Magic = 0x%04X\n", magic);
b5aec950
S		 153
154 if (magic != AR5416_EEPROM_MAGIC) {
155 magic2 = swab16(magic);
156
157 if (magic2 == AR5416_EEPROM_MAGIC) {
158 size = sizeof(struct ar5416_eeprom_def);
159 need_swap = true;
160 eepdata = (u16 *) (&ah->eeprom);
161
162 for (addr = 0; addr < size / sizeof(u16); addr++) {
163 temp = swab16(*eepdata);
164 *eepdata = temp;
165 eepdata++;
166 }
167 } else {
3800276a
JP		 168 ath_err(common,
169 "Invalid EEPROM Magic. Endianness mismatch.\n");
b5aec950
S		 170 return -EINVAL;
171 }
172 }
173 }
174
226afe68
JP		 175 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
176 need_swap ? "True" : "False");
b5aec950
S		 177
178 if (need_swap)
179 el = swab16(ah->eeprom.def.baseEepHeader.length);
180 else
181 el = ah->eeprom.def.baseEepHeader.length;
182
183 if (el > sizeof(struct ar5416_eeprom_def))
184 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
185 else
186 el = el / sizeof(u16);
187
188 eepdata = (u16 *)(&ah->eeprom);
189
190 for (i = 0; i < el; i++)
191 sum ^= *eepdata++;
192
193 if (need_swap) {
194 u32 integer, j;
195 u16 word;
196
226afe68
JP		 197 ath_dbg(common, ATH_DBG_EEPROM,
198 "EEPROM Endianness is not native.. Changing.\n");
b5aec950
S		 199
200 word = swab16(eep->baseEepHeader.length);
201 eep->baseEepHeader.length = word;
202
203 word = swab16(eep->baseEepHeader.checksum);
204 eep->baseEepHeader.checksum = word;
205
206 word = swab16(eep->baseEepHeader.version);
207 eep->baseEepHeader.version = word;
208
209 word = swab16(eep->baseEepHeader.regDmn[0]);
210 eep->baseEepHeader.regDmn[0] = word;
211
212 word = swab16(eep->baseEepHeader.regDmn[1]);
213 eep->baseEepHeader.regDmn[1] = word;
214
215 word = swab16(eep->baseEepHeader.rfSilent);
216 eep->baseEepHeader.rfSilent = word;
217
218 word = swab16(eep->baseEepHeader.blueToothOptions);
219 eep->baseEepHeader.blueToothOptions = word;
220
221 word = swab16(eep->baseEepHeader.deviceCap);
222 eep->baseEepHeader.deviceCap = word;
223
224 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
225 struct modal_eep_header *pModal =
226 &eep->modalHeader[j];
227 integer = swab32(pModal->antCtrlCommon);
228 pModal->antCtrlCommon = integer;
229
230 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
231 integer = swab32(pModal->antCtrlChain[i]);
232 pModal->antCtrlChain[i] = integer;
233 }
234
4ddfcd7d 235 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
b5aec950
S		 236 word = swab16(pModal->spurChans[i].spurChan);
237 pModal->spurChans[i].spurChan = word;
238 }
239 }
240 }
241
242 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
243 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
3800276a 244 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
b5aec950
S		 245 sum, ah->eep_ops->get_eeprom_ver(ah));
246 return -EINVAL;
247 }
248
57b98384 249 /* Enable fixup for AR_AN_TOP2 if necessary */
4d906740
SM		 250 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
251 ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
252 (eep->baseEepHeader.pwdclkind == 0))
57b98384
FF		 253 ah->need_an_top2_fixup = 1;
254
69bdacc8
SM		 255 if ((common->bus_ops->ath_bus_type == ATH_USB) &&
256 (AR_SREV_9280(ah)))
257 eep->modalHeader[0].xpaBiasLvl = 0;
258
b5aec950
S		 259 return 0;
260}
261
262static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
263 enum eeprom_param param)
264{
265 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
266 struct modal_eep_header *pModal = eep->modalHeader;
267 struct base_eep_header *pBase = &eep->baseEepHeader;
268
269 switch (param) {
270 case EEP_NFTHRESH_5:
271 return pModal[0].noiseFloorThreshCh[0];
272 case EEP_NFTHRESH_2:
273 return pModal[1].noiseFloorThreshCh[0];
49101676 274 case EEP_MAC_LSW:
b5aec950 275 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
49101676 276 case EEP_MAC_MID:
b5aec950 277 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
49101676 278 case EEP_MAC_MSW:
b5aec950
S		 279 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
280 case EEP_REG_0:
281 return pBase->regDmn[0];
282 case EEP_REG_1:
283 return pBase->regDmn[1];
284 case EEP_OP_CAP:
285 return pBase->deviceCap;
286 case EEP_OP_MODE:
287 return pBase->opCapFlags;
288 case EEP_RF_SILENT:
289 return pBase->rfSilent;
290 case EEP_OB_5:
291 return pModal[0].ob;
292 case EEP_DB_5:
293 return pModal[0].db;
294 case EEP_OB_2:
295 return pModal[1].ob;
296 case EEP_DB_2:
297 return pModal[1].db;
298 case EEP_MINOR_REV:
299 return AR5416_VER_MASK;
300 case EEP_TX_MASK:
301 return pBase->txMask;
302 case EEP_RX_MASK:
303 return pBase->rxMask;
5b75d0fc
FF		 304 case EEP_FSTCLK_5G:
305 return pBase->fastClk5g;
b5aec950
S		 306 case EEP_RXGAIN_TYPE:
307 return pBase->rxGainType;
308 case EEP_TXGAIN_TYPE:
309 return pBase->txGainType;
310 case EEP_OL_PWRCTRL:
311 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
312 return pBase->openLoopPwrCntl ? true : false;
313 else
314 return false;
315 case EEP_RC_CHAIN_MASK:
316 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
317 return pBase->rcChainMask;
318 else
319 return 0;
320 case EEP_DAC_HPWR_5G:
321 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
322 return pBase->dacHiPwrMode_5G;
323 else
324 return 0;
325 case EEP_FRAC_N_5G:
326 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
327 return pBase->frac_n_5g;
328 else
329 return 0;
e41f0bfc
SB		 330 case EEP_PWR_TABLE_OFFSET:
331 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
332 return pBase->pwr_table_offset;
333 else
334 return AR5416_PWR_TABLE_OFFSET_DB;
b5aec950
S		 335 default:
336 return 0;
337 }
338}
339
340static void ath9k_hw_def_set_gain(struct ath_hw *ah,
341 struct modal_eep_header *pModal,
342 struct ar5416_eeprom_def *eep,
343 u8 txRxAttenLocal, int regChainOffset, int i)
344{
345 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
346 txRxAttenLocal = pModal->txRxAttenCh[i];
347
7a37081e 348 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 349 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
350 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
351 pModal->bswMargin[i]);
352 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
353 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
354 pModal->bswAtten[i]);
355 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
356 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
357 pModal->xatten2Margin[i]);
358 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
359 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
360 pModal->xatten2Db[i]);
361 } else {
362 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
363 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
364 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
365 | SM(pModal-> bswMargin[i],
366 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
367 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
368 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
369 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
370 | SM(pModal->bswAtten[i],
371 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
372 }
373 }
374
7a37081e 375 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 376 REG_RMW_FIELD(ah,
377 AR_PHY_RXGAIN + regChainOffset,
378 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
379 REG_RMW_FIELD(ah,
380 AR_PHY_RXGAIN + regChainOffset,
381 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
382 } else {
383 REG_WRITE(ah,
384 AR_PHY_RXGAIN + regChainOffset,
385 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
386 ~AR_PHY_RXGAIN_TXRX_ATTEN)
387 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
388 REG_WRITE(ah,
389 AR_PHY_GAIN_2GHZ + regChainOffset,
390 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
391 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
392 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
393 }
394}
395
396static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
397 struct ath9k_channel *chan)
398{
399 struct modal_eep_header *pModal;
400 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
401 int i, regChainOffset;
402 u8 txRxAttenLocal;
403
404 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
405 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
406
df3c8b2b 407 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
b5aec950
S		 408
409 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
410 if (AR_SREV_9280(ah)) {
411 if (i >= 2)
412 break;
413 }
414
415 if (AR_SREV_5416_20_OR_LATER(ah) &&
416 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
417 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
418 else
419 regChainOffset = i * 0x1000;
420
421 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
422 pModal->antCtrlChain[i]);
423
424 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
425 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
426 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
427 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
428 SM(pModal->iqCalICh[i],
429 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
430 SM(pModal->iqCalQCh[i],
431 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
432
433 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
434 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
435 regChainOffset, i);
436 }
437
7a37081e 438 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 439 if (IS_CHAN_2GHZ(chan)) {
440 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
441 AR_AN_RF2G1_CH0_OB,
442 AR_AN_RF2G1_CH0_OB_S,
443 pModal->ob);
444 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
445 AR_AN_RF2G1_CH0_DB,
446 AR_AN_RF2G1_CH0_DB_S,
447 pModal->db);
448 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
449 AR_AN_RF2G1_CH1_OB,
450 AR_AN_RF2G1_CH1_OB_S,
451 pModal->ob_ch1);
452 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
453 AR_AN_RF2G1_CH1_DB,
454 AR_AN_RF2G1_CH1_DB_S,
455 pModal->db_ch1);
456 } else {
457 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
458 AR_AN_RF5G1_CH0_OB5,
459 AR_AN_RF5G1_CH0_OB5_S,
460 pModal->ob);
461 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
462 AR_AN_RF5G1_CH0_DB5,
463 AR_AN_RF5G1_CH0_DB5_S,
464 pModal->db);
465 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
466 AR_AN_RF5G1_CH1_OB5,
467 AR_AN_RF5G1_CH1_OB5_S,
468 pModal->ob_ch1);
469 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
470 AR_AN_RF5G1_CH1_DB5,
471 AR_AN_RF5G1_CH1_DB5_S,
472 pModal->db_ch1);
473 }
474 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
475 AR_AN_TOP2_XPABIAS_LVL,
476 AR_AN_TOP2_XPABIAS_LVL_S,
477 pModal->xpaBiasLvl);
478 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
479 AR_AN_TOP2_LOCALBIAS,
480 AR_AN_TOP2_LOCALBIAS_S,
f67e07eb
FF		 481 !!(pModal->lna_ctl &
482 LNA_CTL_LOCAL_BIAS));
b5aec950 483 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
f67e07eb 484 !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
b5aec950
S		 485 }
486
487 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
488 pModal->switchSettling);
489 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
490 pModal->adcDesiredSize);
491
7a37081e 492 if (!AR_SREV_9280_20_OR_LATER(ah))
b5aec950
S		 493 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
494 AR_PHY_DESIRED_SZ_PGA,
495 pModal->pgaDesiredSize);
496
497 REG_WRITE(ah, AR_PHY_RF_CTL4,
498 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
499 | SM(pModal->txEndToXpaOff,
500 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
501 | SM(pModal->txFrameToXpaOn,
502 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
503 | SM(pModal->txFrameToXpaOn,
504 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
505
506 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
507 pModal->txEndToRxOn);
508
7a37081e 509 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 510 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
511 pModal->thresh62);
512 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
513 AR_PHY_EXT_CCA0_THRESH62,
514 pModal->thresh62);
515 } else {
516 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
517 pModal->thresh62);
518 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
519 AR_PHY_EXT_CCA_THRESH62,
520 pModal->thresh62);
521 }
522
523 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
524 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
525 AR_PHY_TX_END_DATA_START,
526 pModal->txFrameToDataStart);
527 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
528 pModal->txFrameToPaOn);
529 }
530
531 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
532 if (IS_CHAN_HT40(chan))
533 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
534 AR_PHY_SETTLING_SWITCH,
535 pModal->swSettleHt40);
536 }
537
538 if (AR_SREV_9280_20_OR_LATER(ah) &&
539 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
540 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
541 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
542 pModal->miscBits);
543
544
545 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
546 if (IS_CHAN_2GHZ(chan))
547 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
548 eep->baseEepHeader.dacLpMode);
549 else if (eep->baseEepHeader.dacHiPwrMode_5G)
550 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
551 else
552 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
553 eep->baseEepHeader.dacLpMode);
554
d865ca6c
SB		 555 udelay(100);
556
b5aec950
S		 557 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
558 pModal->miscBits >> 2);
559
560 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
561 AR_PHY_TX_DESIRED_SCALE_CCK,
562 eep->baseEepHeader.desiredScaleCCK);
563 }
564}
565
566static void ath9k_hw_def_set_addac(struct ath_hw *ah,
567 struct ath9k_channel *chan)
568{
569#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
570 struct modal_eep_header *pModal;
571 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
572 u8 biaslevel;
573
574 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
575 return;
576
577 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
578 return;
579
580 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
581
582 if (pModal->xpaBiasLvl != 0xff) {
583 biaslevel = pModal->xpaBiasLvl;
584 } else {
585 u16 resetFreqBin, freqBin, freqCount = 0;
586 struct chan_centers centers;
587
588 ath9k_hw_get_channel_centers(ah, chan, &centers);
589
590 resetFreqBin = FREQ2FBIN(centers.synth_center,
591 IS_CHAN_2GHZ(chan));
592 freqBin = XPA_LVL_FREQ(0) & 0xff;
593 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
594
595 freqCount++;
596
597 while (freqCount < 3) {
598 if (XPA_LVL_FREQ(freqCount) == 0x0)
599 break;
600
601 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
602 if (resetFreqBin >= freqBin)
603 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
604 else
605 break;
606 freqCount++;
607 }
608 }
609
610 if (IS_CHAN_2GHZ(chan)) {
611 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
612 7, 1) & (~0x18)) | biaslevel << 3;
613 } else {
614 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
615 6, 1) & (~0xc0)) | biaslevel << 6;
616 }
617#undef XPA_LVL_FREQ
618}
619
e41f0bfc
SB		 620static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
621 u16 *gb,
622 u16 numXpdGain,
623 u16 pdGainOverlap_t2,
624 int8_t pwr_table_offset,
625 int16_t *diff)
626
627{
628 u16 k;
629
630 /* Prior to writing the boundaries or the pdadc vs. power table
631 * into the chip registers the default starting point on the pdadc
632 * vs. power table needs to be checked and the curve boundaries
633 * adjusted accordingly
634 */
635 if (AR_SREV_9280_20_OR_LATER(ah)) {
636 u16 gb_limit;
637
638 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
639 /* get the difference in dB */
640 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
641 /* get the number of half dB steps */
642 *diff *= 2;
643 /* change the original gain boundary settings
644 * by the number of half dB steps
645 */
646 for (k = 0; k < numXpdGain; k++)
647 gb[k] = (u16)(gb[k] - *diff);
648 }
649 /* Because of a hardware limitation, ensure the gain boundary
650 * is not larger than (63 - overlap)
651 */
4ddfcd7d 652 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
e41f0bfc
SB		 653
654 for (k = 0; k < numXpdGain; k++)
655 gb[k] = (u16)min(gb_limit, gb[k]);
656 }
657
658 return *diff;
659}
660
661static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
662 int8_t pwr_table_offset,
663 int16_t diff,
664 u8 *pdadcValues)
665{
666#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
667 u16 k;
668
669 /* If this is a board that has a pwrTableOffset that differs from
670 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
671 * pdadc vs pwr table needs to be adjusted prior to writing to the
672 * chip.
673 */
674 if (AR_SREV_9280_20_OR_LATER(ah)) {
675 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
676 /* shift the table to start at the new offset */
677 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
678 pdadcValues[k] = pdadcValues[k + diff];
679 }
680
681 /* fill the back of the table */
682 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
683 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
684 }
685 }
686 }
687#undef NUM_PDADC
688}
689
b5aec950
S		 690static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
691 struct ath9k_channel *chan,
692 int16_t *pTxPowerIndexOffset)
693{
694#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
695#define SM_PDGAIN_B(x, y) \
696 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
c46917bb 697 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 698 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
699 struct cal_data_per_freq *pRawDataset;
700 u8 *pCalBChans = NULL;
701 u16 pdGainOverlap_t2;
702 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
703 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
704 u16 numPiers, i, j;
6eb90d46 705 int16_t diff = 0;
b5aec950
S		 706 u16 numXpdGain, xpdMask;
707 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
708 u32 reg32, regOffset, regChainOffset;
709 int16_t modalIdx;
e41f0bfc 710 int8_t pwr_table_offset;
b5aec950
S		 711
712 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
713 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
714
e41f0bfc
SB		 715 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
716
b5aec950
S		 717 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
718 AR5416_EEP_MINOR_VER_2) {
719 pdGainOverlap_t2 =
720 pEepData->modalHeader[modalIdx].pdGainOverlap;
721 } else {
722 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
723 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
724 }
725
726 if (IS_CHAN_2GHZ(chan)) {
727 pCalBChans = pEepData->calFreqPier2G;
728 numPiers = AR5416_NUM_2G_CAL_PIERS;
729 } else {
730 pCalBChans = pEepData->calFreqPier5G;
731 numPiers = AR5416_NUM_5G_CAL_PIERS;
732 }
733
734 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
735 pRawDataset = pEepData->calPierData2G[0];
736 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
737 pRawDataset)->vpdPdg[0][0];
738 }
739
740 numXpdGain = 0;
741
742 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
743 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
744 if (numXpdGain >= AR5416_NUM_PD_GAINS)
745 break;
746 xpdGainValues[numXpdGain] =
747 (u16)(AR5416_PD_GAINS_IN_MASK - i);
748 numXpdGain++;
749 }
750 }
751
752 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
753 (numXpdGain - 1) & 0x3);
754 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
755 xpdGainValues[0]);
756 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
757 xpdGainValues[1]);
758 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
759 xpdGainValues[2]);
760
761 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
762 if (AR_SREV_5416_20_OR_LATER(ah) &&
763 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
764 (i != 0)) {
765 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
766 } else
767 regChainOffset = i * 0x1000;
768
769 if (pEepData->baseEepHeader.txMask & (1 << i)) {
770 if (IS_CHAN_2GHZ(chan))
771 pRawDataset = pEepData->calPierData2G[i];
772 else
773 pRawDataset = pEepData->calPierData5G[i];
774
775
776 if (OLC_FOR_AR9280_20_LATER) {
777 u8 pcdacIdx;
778 u8 txPower;
779
780 ath9k_get_txgain_index(ah, chan,
781 (struct calDataPerFreqOpLoop *)pRawDataset,
782 pCalBChans, numPiers, &txPower, &pcdacIdx);
783 ath9k_olc_get_pdadcs(ah, pcdacIdx,
784 txPower/2, pdadcValues);
785 } else {
115277a3 786 ath9k_hw_get_gain_boundaries_pdadcs(ah,
b5aec950
S		 787 chan, pRawDataset,
788 pCalBChans, numPiers,
789 pdGainOverlap_t2,
b5aec950
S		 790 gainBoundaries,
791 pdadcValues,
792 numXpdGain);
793 }
794
e41f0bfc
SB		 795 diff = ath9k_change_gain_boundary_setting(ah,
796 gainBoundaries,
797 numXpdGain,
798 pdGainOverlap_t2,
799 pwr_table_offset,
800 &diff);
801
e7fc6338
RM		 802 ENABLE_REGWRITE_BUFFER(ah);
803
b5aec950
S		 804 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
805 if (OLC_FOR_AR9280_20_LATER) {
806 REG_WRITE(ah,
807 AR_PHY_TPCRG5 + regChainOffset,
808 SM(0x6,
809 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
810 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
811 SM_PD_GAIN(3) | SM_PD_GAIN(4));
812 } else {
813 REG_WRITE(ah,
814 AR_PHY_TPCRG5 + regChainOffset,
815 SM(pdGainOverlap_t2,
816 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
817 SM_PDGAIN_B(0, 1) |
818 SM_PDGAIN_B(1, 2) |
819 SM_PDGAIN_B(2, 3) |
820 SM_PDGAIN_B(3, 4));
821 }
822 }
823
e41f0bfc
SB		 824
825 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
826 diff, pdadcValues);
827
b5aec950
S		 828 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
829 for (j = 0; j < 32; j++) {
830 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
831 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
832 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
833 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
834 REG_WRITE(ah, regOffset, reg32);
835
226afe68
JP		 836 ath_dbg(common, ATH_DBG_EEPROM,
837 "PDADC (%d,%4x): %4.4x %8.8x\n",
838 i, regChainOffset, regOffset,
839 reg32);
840 ath_dbg(common, ATH_DBG_EEPROM,
841 "PDADC: Chain %d | PDADC %3d "
842 "Value %3d | PDADC %3d Value %3d | "
843 "PDADC %3d Value %3d | PDADC %3d "
844 "Value %3d |\n",
845 i, 4 * j, pdadcValues[4 * j],
846 4 * j + 1, pdadcValues[4 * j + 1],
847 4 * j + 2, pdadcValues[4 * j + 2],
848 4 * j + 3, pdadcValues[4 * j + 3]);
b5aec950
S		 849
850 regOffset += 4;
851 }
e7fc6338 852 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 853 }
854 }
855
856 *pTxPowerIndexOffset = 0;
857#undef SM_PD_GAIN
858#undef SM_PDGAIN_B
859}
860
861static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
862 struct ath9k_channel *chan,
863 int16_t *ratesArray,
864 u16 cfgCtl,
865 u16 AntennaReduction,
866 u16 twiceMaxRegulatoryPower,
867 u16 powerLimit)
868{
869#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
d865ca6c 870#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
b5aec950 871
608b88cb 872 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950 873 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
4ddfcd7d 874 u16 twiceMaxEdgePower = MAX_RATE_POWER;
b5aec950 875 static const u16 tpScaleReductionTable[5] =
4ddfcd7d 876 { 0, 3, 6, 9, MAX_RATE_POWER };
b5aec950
S		 877
878 int i;
879 int16_t twiceLargestAntenna;
880 struct cal_ctl_data *rep;
881 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
882 0, { 0, 0, 0, 0}
883 };
884 struct cal_target_power_leg targetPowerOfdmExt = {
885 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
886 0, { 0, 0, 0, 0 }
887 };
888 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
889 0, {0, 0, 0, 0}
890 };
891 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
07b2fa5a
JP		 892 static const u16 ctlModesFor11a[] = {
893 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
894 };
895 static const u16 ctlModesFor11g[] = {
896 CTL_11B, CTL_11G, CTL_2GHT20,
897 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
898 };
899 u16 numCtlModes;
900 const u16 *pCtlMode;
901 u16 ctlMode, freq;
b5aec950
S		 902 struct chan_centers centers;
903 int tx_chainmask;
904 u16 twiceMinEdgePower;
905
906 tx_chainmask = ah->txchainmask;
907
908 ath9k_hw_get_channel_centers(ah, chan, &centers);
909
910 twiceLargestAntenna = max(
911 pEepData->modalHeader
912 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
913 pEepData->modalHeader
914 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
915
916 twiceLargestAntenna = max((u8)twiceLargestAntenna,
917 pEepData->modalHeader
918 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
919
920 twiceLargestAntenna = (int16_t)min(AntennaReduction -
921 twiceLargestAntenna, 0);
922
923 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
924
608b88cb 925 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
b5aec950 926 maxRegAllowedPower -=
608b88cb 927 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
b5aec950
S		 928 }
929
930 scaledPower = min(powerLimit, maxRegAllowedPower);
931
932 switch (ar5416_get_ntxchains(tx_chainmask)) {
933 case 1:
934 break;
935 case 2:
84105160
MC		 936 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
937 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
938 else
939 scaledPower = 0;
b5aec950
S		 940 break;
941 case 3:
84105160
MC		 942 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
943 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
944 else
945 scaledPower = 0;
b5aec950
S		 946 break;
947 }
948
b5aec950
S		 949 if (IS_CHAN_2GHZ(chan)) {
950 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
951 SUB_NUM_CTL_MODES_AT_2G_40;
952 pCtlMode = ctlModesFor11g;
953
954 ath9k_hw_get_legacy_target_powers(ah, chan,
955 pEepData->calTargetPowerCck,
956 AR5416_NUM_2G_CCK_TARGET_POWERS,
957 &targetPowerCck, 4, false);
958 ath9k_hw_get_legacy_target_powers(ah, chan,
959 pEepData->calTargetPower2G,
960 AR5416_NUM_2G_20_TARGET_POWERS,
961 &targetPowerOfdm, 4, false);
962 ath9k_hw_get_target_powers(ah, chan,
963 pEepData->calTargetPower2GHT20,
964 AR5416_NUM_2G_20_TARGET_POWERS,
965 &targetPowerHt20, 8, false);
966
967 if (IS_CHAN_HT40(chan)) {
968 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
969 ath9k_hw_get_target_powers(ah, chan,
970 pEepData->calTargetPower2GHT40,
971 AR5416_NUM_2G_40_TARGET_POWERS,
972 &targetPowerHt40, 8, true);
973 ath9k_hw_get_legacy_target_powers(ah, chan,
974 pEepData->calTargetPowerCck,
975 AR5416_NUM_2G_CCK_TARGET_POWERS,
976 &targetPowerCckExt, 4, true);
977 ath9k_hw_get_legacy_target_powers(ah, chan,
978 pEepData->calTargetPower2G,
979 AR5416_NUM_2G_20_TARGET_POWERS,
980 &targetPowerOfdmExt, 4, true);
981 }
982 } else {
983 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
984 SUB_NUM_CTL_MODES_AT_5G_40;
985 pCtlMode = ctlModesFor11a;
986
987 ath9k_hw_get_legacy_target_powers(ah, chan,
988 pEepData->calTargetPower5G,
989 AR5416_NUM_5G_20_TARGET_POWERS,
990 &targetPowerOfdm, 4, false);
991 ath9k_hw_get_target_powers(ah, chan,
992 pEepData->calTargetPower5GHT20,
993 AR5416_NUM_5G_20_TARGET_POWERS,
994 &targetPowerHt20, 8, false);
995
996 if (IS_CHAN_HT40(chan)) {
997 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
998 ath9k_hw_get_target_powers(ah, chan,
999 pEepData->calTargetPower5GHT40,
1000 AR5416_NUM_5G_40_TARGET_POWERS,
1001 &targetPowerHt40, 8, true);
1002 ath9k_hw_get_legacy_target_powers(ah, chan,
1003 pEepData->calTargetPower5G,
1004 AR5416_NUM_5G_20_TARGET_POWERS,
1005 &targetPowerOfdmExt, 4, true);
1006 }
1007 }
1008
1009 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1010 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1011 (pCtlMode[ctlMode] == CTL_2GHT40);
1012 if (isHt40CtlMode)
1013 freq = centers.synth_center;
1014 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1015 freq = centers.ext_center;
1016 else
1017 freq = centers.ctl_center;
1018
1019 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1020 ah->eep_ops->get_eeprom_rev(ah) <= 2)
4ddfcd7d 1021 twiceMaxEdgePower = MAX_RATE_POWER;
b5aec950
S		 1022
1023 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1024 if ((((cfgCtl & ~CTL_MODE_M) |
1025 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1026 pEepData->ctlIndex[i]) ||
1027 (((cfgCtl & ~CTL_MODE_M) |
1028 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1029 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1030 rep = &(pEepData->ctlData[i]);
1031
1032 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1033 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1034 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1035
1036 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1037 twiceMaxEdgePower = min(twiceMaxEdgePower,
1038 twiceMinEdgePower);
1039 } else {
1040 twiceMaxEdgePower = twiceMinEdgePower;
1041 break;
1042 }
1043 }
1044 }
1045
1046 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1047
1048 switch (pCtlMode[ctlMode]) {
1049 case CTL_11B:
1050 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1051 targetPowerCck.tPow2x[i] =
1052 min((u16)targetPowerCck.tPow2x[i],
1053 minCtlPower);
1054 }
1055 break;
1056 case CTL_11A:
1057 case CTL_11G:
1058 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1059 targetPowerOfdm.tPow2x[i] =
1060 min((u16)targetPowerOfdm.tPow2x[i],
1061 minCtlPower);
1062 }
1063 break;
1064 case CTL_5GHT20:
1065 case CTL_2GHT20:
1066 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1067 targetPowerHt20.tPow2x[i] =
1068 min((u16)targetPowerHt20.tPow2x[i],
1069 minCtlPower);
1070 }
1071 break;
1072 case CTL_11B_EXT:
1073 targetPowerCckExt.tPow2x[0] = min((u16)
1074 targetPowerCckExt.tPow2x[0],
1075 minCtlPower);
1076 break;
1077 case CTL_11A_EXT:
1078 case CTL_11G_EXT:
1079 targetPowerOfdmExt.tPow2x[0] = min((u16)
1080 targetPowerOfdmExt.tPow2x[0],
1081 minCtlPower);
1082 break;
1083 case CTL_5GHT40:
1084 case CTL_2GHT40:
1085 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1086 targetPowerHt40.tPow2x[i] =
1087 min((u16)targetPowerHt40.tPow2x[i],
1088 minCtlPower);
1089 }
1090 break;
1091 default:
1092 break;
1093 }
1094 }
1095
1096 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1097 ratesArray[rate18mb] = ratesArray[rate24mb] =
1098 targetPowerOfdm.tPow2x[0];
1099 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1100 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1101 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1102 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1103
1104 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1105 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1106
1107 if (IS_CHAN_2GHZ(chan)) {
1108 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1109 ratesArray[rate2s] = ratesArray[rate2l] =
1110 targetPowerCck.tPow2x[1];
1111 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1112 targetPowerCck.tPow2x[2];
1113 ratesArray[rate11s] = ratesArray[rate11l] =
1114 targetPowerCck.tPow2x[3];
1115 }
1116 if (IS_CHAN_HT40(chan)) {
1117 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1118 ratesArray[rateHt40_0 + i] =
1119 targetPowerHt40.tPow2x[i];
1120 }
1121 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1122 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1123 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1124 if (IS_CHAN_2GHZ(chan)) {
1125 ratesArray[rateExtCck] =
1126 targetPowerCckExt.tPow2x[0];
1127 }
1128 }
1129}
1130
1131static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1132 struct ath9k_channel *chan,
1133 u16 cfgCtl,
1134 u8 twiceAntennaReduction,
1135 u8 twiceMaxRegulatoryPower,
de40f316 1136 u8 powerLimit, bool test)
b5aec950
S		 1137{
1138#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
608b88cb 1139 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 1140 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1141 struct modal_eep_header *pModal =
1142 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1143 int16_t ratesArray[Ar5416RateSize];
1144 int16_t txPowerIndexOffset = 0;
1145 u8 ht40PowerIncForPdadc = 2;
1146 int i, cck_ofdm_delta = 0;
1147
1148 memset(ratesArray, 0, sizeof(ratesArray));
1149
1150 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1151 AR5416_EEP_MINOR_VER_2) {
1152 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1153 }
1154
1155 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1156 &ratesArray[0], cfgCtl,
1157 twiceAntennaReduction,
1158 twiceMaxRegulatoryPower,
1159 powerLimit);
1160
1161 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1162
de40f316 1163 regulatory->max_power_level = 0;
b5aec950
S		 1164 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1165 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
4ddfcd7d
FF		 1166 if (ratesArray[i] > MAX_RATE_POWER)
1167 ratesArray[i] = MAX_RATE_POWER;
de40f316
FF		 1168 if (ratesArray[i] > regulatory->max_power_level)
1169 regulatory->max_power_level = ratesArray[i];
b5aec950
S		 1170 }
1171
de40f316
FF		 1172 if (!test) {
1173 i = rate6mb;
1174
1175 if (IS_CHAN_HT40(chan))
1176 i = rateHt40_0;
1177 else if (IS_CHAN_HT20(chan))
1178 i = rateHt20_0;
1179
1180 regulatory->max_power_level = ratesArray[i];
1181 }
1182
1183 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1184 case 1:
1185 break;
1186 case 2:
1187 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1188 break;
1189 case 3:
1190 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1191 break;
1192 default:
226afe68
JP		 1193 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1194 "Invalid chainmask configuration\n");
de40f316
FF		 1195 break;
1196 }
1197
1198 if (test)
1199 return;
1200
7a37081e 1201 if (AR_SREV_9280_20_OR_LATER(ah)) {
e41f0bfc
SB		 1202 for (i = 0; i < Ar5416RateSize; i++) {
1203 int8_t pwr_table_offset;
1204
1205 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1206 EEP_PWR_TABLE_OFFSET);
1207 ratesArray[i] -= pwr_table_offset * 2;
1208 }
b5aec950
S		 1209 }
1210
e7fc6338
RM		 1211 ENABLE_REGWRITE_BUFFER(ah);
1212
b5aec950
S		 1213 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1214 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1215 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1216 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1217 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1218 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1219 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1220 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1221 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1222 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1223
1224 if (IS_CHAN_2GHZ(chan)) {
1225 if (OLC_FOR_AR9280_20_LATER) {
1226 cck_ofdm_delta = 2;
1227 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1228 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1229 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1230 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1231 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1232 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1233 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1234 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1235 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1236 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1237 } else {
1238 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1239 ATH9K_POW_SM(ratesArray[rate2s], 24)
1240 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1241 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1242 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1243 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1244 ATH9K_POW_SM(ratesArray[rate11s], 24)
1245 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1246 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1247 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1248 }
1249 }
1250
1251 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1252 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1253 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1254 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1255 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1256 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1257 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1258 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1259 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1260 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1261
1262 if (IS_CHAN_HT40(chan)) {
1263 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1264 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1265 ht40PowerIncForPdadc, 24)
1266 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1267 ht40PowerIncForPdadc, 16)
1268 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1269 ht40PowerIncForPdadc, 8)
1270 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1271 ht40PowerIncForPdadc, 0));
1272 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1273 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1274 ht40PowerIncForPdadc, 24)
1275 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1276 ht40PowerIncForPdadc, 16)
1277 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1278 ht40PowerIncForPdadc, 8)
1279 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1280 ht40PowerIncForPdadc, 0));
1281 if (OLC_FOR_AR9280_20_LATER) {
1282 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1283 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1284 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1285 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1286 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1287 } else {
1288 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1289 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1290 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1291 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1292 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1293 }
1294 }
1295
1296 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1297 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1298 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
e7fc6338
RM		 1299
1300 REGWRITE_BUFFER_FLUSH(ah);
b5aec950
S		 1301}
1302
b5aec950
S		 1303static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1304{
1305#define EEP_DEF_SPURCHAN \
1306 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
c46917bb 1307 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 1308
1309 u16 spur_val = AR_NO_SPUR;
1310
226afe68
JP		 1311 ath_dbg(common, ATH_DBG_ANI,
1312 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1313 i, is2GHz, ah->config.spurchans[i][is2GHz]);
b5aec950
S		 1314
1315 switch (ah->config.spurmode) {
1316 case SPUR_DISABLE:
1317 break;
1318 case SPUR_ENABLE_IOCTL:
1319 spur_val = ah->config.spurchans[i][is2GHz];
226afe68
JP		 1320 ath_dbg(common, ATH_DBG_ANI,
1321 "Getting spur val from new loc. %d\n", spur_val);
b5aec950
S		 1322 break;
1323 case SPUR_ENABLE_EEPROM:
1324 spur_val = EEP_DEF_SPURCHAN;
1325 break;
1326 }
1327
1328 return spur_val;
1329
1330#undef EEP_DEF_SPURCHAN
1331}
1332
1333const struct eeprom_ops eep_def_ops = {
1334 .check_eeprom = ath9k_hw_def_check_eeprom,
1335 .get_eeprom = ath9k_hw_def_get_eeprom,
1336 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1337 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1338 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
b5aec950
S		 1339 .set_board_values = ath9k_hw_def_set_board_values,
1340 .set_addac = ath9k_hw_def_set_addac,
1341 .set_txpower = ath9k_hw_def_set_txpower,
1342 .get_spur_channel = ath9k_hw_def_get_spur_channel
1343};
Linux kernel - Deliverables
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