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ath9k_hw: fix endian issues with CTLs on AR9003
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / eeprom_def.c
CommitLineData
b5aec950
S		 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
c46917bb 17#include "hw.h"
8fe65368 18#include "ar9002_phy.h"
b5aec950
S		 19
20static void ath9k_get_txgain_index(struct ath_hw *ah,
21 struct ath9k_channel *chan,
22 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
23 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
24{
25 u8 pcdac, i = 0;
26 u16 idxL = 0, idxR = 0, numPiers;
27 bool match;
28 struct chan_centers centers;
29
30 ath9k_hw_get_channel_centers(ah, chan, &centers);
31
32 for (numPiers = 0; numPiers < availPiers; numPiers++)
33 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
34 break;
35
36 match = ath9k_hw_get_lower_upper_index(
37 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
38 calChans, numPiers, &idxL, &idxR);
39 if (match) {
40 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
41 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
42 } else {
43 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
44 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
45 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
46 }
47
48 while (pcdac > ah->originalGain[i] &&
49 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
50 i++;
51
52 *pcdacIdx = i;
b5aec950
S		 53}
54
55static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
56 u32 initTxGain,
57 int txPower,
58 u8 *pPDADCValues)
59{
60 u32 i;
61 u32 offset;
62
63 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
64 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
65 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
66 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
67
68 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
69 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
70
71 offset = txPower;
72 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
73 if (i < offset)
74 pPDADCValues[i] = 0x0;
75 else
76 pPDADCValues[i] = 0xFF;
77}
78
79static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
80{
81 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
82}
83
84static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
85{
86 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
87}
88
89static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
90{
91#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
5bb12791 92 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 93 u16 *eep_data = (u16 *)&ah->eeprom.def;
94 int addr, ar5416_eep_start_loc = 0x100;
95
96 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
5bb12791 97 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
b5aec950 98 eep_data)) {
c46917bb
LR		 99 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
100 "Unable to read eeprom region\n");
b5aec950
S		 101 return false;
102 }
103 eep_data++;
104 }
105 return true;
106#undef SIZE_EEPROM_DEF
107}
108
109static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
110{
111 struct ar5416_eeprom_def *eep =
112 (struct ar5416_eeprom_def *) &ah->eeprom.def;
c46917bb 113 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 114 u16 *eepdata, temp, magic, magic2;
115 u32 sum = 0, el;
116 bool need_swap = false;
117 int i, addr, size;
118
5bb12791 119 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
c46917bb 120 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
b5aec950
S		 121 return false;
122 }
123
124 if (!ath9k_hw_use_flash(ah)) {
c46917bb
LR		 125 ath_print(common, ATH_DBG_EEPROM,
126 "Read Magic = 0x%04X\n", magic);
b5aec950
S		 127
128 if (magic != AR5416_EEPROM_MAGIC) {
129 magic2 = swab16(magic);
130
131 if (magic2 == AR5416_EEPROM_MAGIC) {
132 size = sizeof(struct ar5416_eeprom_def);
133 need_swap = true;
134 eepdata = (u16 *) (&ah->eeprom);
135
136 for (addr = 0; addr < size / sizeof(u16); addr++) {
137 temp = swab16(*eepdata);
138 *eepdata = temp;
139 eepdata++;
140 }
141 } else {
c46917bb
LR		 142 ath_print(common, ATH_DBG_FATAL,
143 "Invalid EEPROM Magic. "
144 "Endianness mismatch.\n");
b5aec950
S		 145 return -EINVAL;
146 }
147 }
148 }
149
c46917bb
LR		 150 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
151 need_swap ? "True" : "False");
b5aec950
S		 152
153 if (need_swap)
154 el = swab16(ah->eeprom.def.baseEepHeader.length);
155 else
156 el = ah->eeprom.def.baseEepHeader.length;
157
158 if (el > sizeof(struct ar5416_eeprom_def))
159 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
160 else
161 el = el / sizeof(u16);
162
163 eepdata = (u16 *)(&ah->eeprom);
164
165 for (i = 0; i < el; i++)
166 sum ^= *eepdata++;
167
168 if (need_swap) {
169 u32 integer, j;
170 u16 word;
171
c46917bb
LR		 172 ath_print(common, ATH_DBG_EEPROM,
173 "EEPROM Endianness is not native.. Changing.\n");
b5aec950
S		 174
175 word = swab16(eep->baseEepHeader.length);
176 eep->baseEepHeader.length = word;
177
178 word = swab16(eep->baseEepHeader.checksum);
179 eep->baseEepHeader.checksum = word;
180
181 word = swab16(eep->baseEepHeader.version);
182 eep->baseEepHeader.version = word;
183
184 word = swab16(eep->baseEepHeader.regDmn[0]);
185 eep->baseEepHeader.regDmn[0] = word;
186
187 word = swab16(eep->baseEepHeader.regDmn[1]);
188 eep->baseEepHeader.regDmn[1] = word;
189
190 word = swab16(eep->baseEepHeader.rfSilent);
191 eep->baseEepHeader.rfSilent = word;
192
193 word = swab16(eep->baseEepHeader.blueToothOptions);
194 eep->baseEepHeader.blueToothOptions = word;
195
196 word = swab16(eep->baseEepHeader.deviceCap);
197 eep->baseEepHeader.deviceCap = word;
198
199 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
200 struct modal_eep_header *pModal =
201 &eep->modalHeader[j];
202 integer = swab32(pModal->antCtrlCommon);
203 pModal->antCtrlCommon = integer;
204
205 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
206 integer = swab32(pModal->antCtrlChain[i]);
207 pModal->antCtrlChain[i] = integer;
208 }
209
210 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
211 word = swab16(pModal->spurChans[i].spurChan);
212 pModal->spurChans[i].spurChan = word;
213 }
214 }
215 }
216
217 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
218 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
c46917bb
LR		 219 ath_print(common, ATH_DBG_FATAL,
220 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
b5aec950
S		 221 sum, ah->eep_ops->get_eeprom_ver(ah));
222 return -EINVAL;
223 }
224
57b98384 225 /* Enable fixup for AR_AN_TOP2 if necessary */
7a37081e 226 if (AR_SREV_9280_20_OR_LATER(ah) &&
57b98384
FF		 227 (eep->baseEepHeader.version & 0xff) > 0x0a &&
228 eep->baseEepHeader.pwdclkind == 0)
229 ah->need_an_top2_fixup = 1;
230
b5aec950
S		 231 return 0;
232}
233
234static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
235 enum eeprom_param param)
236{
237 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
238 struct modal_eep_header *pModal = eep->modalHeader;
239 struct base_eep_header *pBase = &eep->baseEepHeader;
240
241 switch (param) {
242 case EEP_NFTHRESH_5:
243 return pModal[0].noiseFloorThreshCh[0];
244 case EEP_NFTHRESH_2:
245 return pModal[1].noiseFloorThreshCh[0];
49101676 246 case EEP_MAC_LSW:
b5aec950 247 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
49101676 248 case EEP_MAC_MID:
b5aec950 249 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
49101676 250 case EEP_MAC_MSW:
b5aec950
S		 251 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
252 case EEP_REG_0:
253 return pBase->regDmn[0];
254 case EEP_REG_1:
255 return pBase->regDmn[1];
256 case EEP_OP_CAP:
257 return pBase->deviceCap;
258 case EEP_OP_MODE:
259 return pBase->opCapFlags;
260 case EEP_RF_SILENT:
261 return pBase->rfSilent;
262 case EEP_OB_5:
263 return pModal[0].ob;
264 case EEP_DB_5:
265 return pModal[0].db;
266 case EEP_OB_2:
267 return pModal[1].ob;
268 case EEP_DB_2:
269 return pModal[1].db;
270 case EEP_MINOR_REV:
271 return AR5416_VER_MASK;
272 case EEP_TX_MASK:
273 return pBase->txMask;
274 case EEP_RX_MASK:
275 return pBase->rxMask;
5b75d0fc
FF		 276 case EEP_FSTCLK_5G:
277 return pBase->fastClk5g;
b5aec950
S		 278 case EEP_RXGAIN_TYPE:
279 return pBase->rxGainType;
280 case EEP_TXGAIN_TYPE:
281 return pBase->txGainType;
282 case EEP_OL_PWRCTRL:
283 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
284 return pBase->openLoopPwrCntl ? true : false;
285 else
286 return false;
287 case EEP_RC_CHAIN_MASK:
288 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
289 return pBase->rcChainMask;
290 else
291 return 0;
292 case EEP_DAC_HPWR_5G:
293 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
294 return pBase->dacHiPwrMode_5G;
295 else
296 return 0;
297 case EEP_FRAC_N_5G:
298 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
299 return pBase->frac_n_5g;
300 else
301 return 0;
e41f0bfc
SB		 302 case EEP_PWR_TABLE_OFFSET:
303 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
304 return pBase->pwr_table_offset;
305 else
306 return AR5416_PWR_TABLE_OFFSET_DB;
b5aec950
S		 307 default:
308 return 0;
309 }
310}
311
312static void ath9k_hw_def_set_gain(struct ath_hw *ah,
313 struct modal_eep_header *pModal,
314 struct ar5416_eeprom_def *eep,
315 u8 txRxAttenLocal, int regChainOffset, int i)
316{
317 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
318 txRxAttenLocal = pModal->txRxAttenCh[i];
319
7a37081e 320 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 321 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
322 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
323 pModal->bswMargin[i]);
324 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
325 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
326 pModal->bswAtten[i]);
327 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
328 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
329 pModal->xatten2Margin[i]);
330 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
331 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
332 pModal->xatten2Db[i]);
333 } else {
334 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
335 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
336 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
337 | SM(pModal-> bswMargin[i],
338 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
339 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
340 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
341 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
342 | SM(pModal->bswAtten[i],
343 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
344 }
345 }
346
7a37081e 347 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 348 REG_RMW_FIELD(ah,
349 AR_PHY_RXGAIN + regChainOffset,
350 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
351 REG_RMW_FIELD(ah,
352 AR_PHY_RXGAIN + regChainOffset,
353 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
354 } else {
355 REG_WRITE(ah,
356 AR_PHY_RXGAIN + regChainOffset,
357 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
358 ~AR_PHY_RXGAIN_TXRX_ATTEN)
359 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
360 REG_WRITE(ah,
361 AR_PHY_GAIN_2GHZ + regChainOffset,
362 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
363 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
364 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
365 }
366}
367
368static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
369 struct ath9k_channel *chan)
370{
371 struct modal_eep_header *pModal;
372 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
373 int i, regChainOffset;
374 u8 txRxAttenLocal;
375
376 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
377 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
378
379 REG_WRITE(ah, AR_PHY_SWITCH_COM,
380 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
381
382 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
383 if (AR_SREV_9280(ah)) {
384 if (i >= 2)
385 break;
386 }
387
388 if (AR_SREV_5416_20_OR_LATER(ah) &&
389 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
390 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
391 else
392 regChainOffset = i * 0x1000;
393
394 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
395 pModal->antCtrlChain[i]);
396
397 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
398 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
399 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
400 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
401 SM(pModal->iqCalICh[i],
402 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
403 SM(pModal->iqCalQCh[i],
404 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
405
406 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
407 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
408 regChainOffset, i);
409 }
410
7a37081e 411 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 412 if (IS_CHAN_2GHZ(chan)) {
413 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
414 AR_AN_RF2G1_CH0_OB,
415 AR_AN_RF2G1_CH0_OB_S,
416 pModal->ob);
417 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
418 AR_AN_RF2G1_CH0_DB,
419 AR_AN_RF2G1_CH0_DB_S,
420 pModal->db);
421 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
422 AR_AN_RF2G1_CH1_OB,
423 AR_AN_RF2G1_CH1_OB_S,
424 pModal->ob_ch1);
425 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
426 AR_AN_RF2G1_CH1_DB,
427 AR_AN_RF2G1_CH1_DB_S,
428 pModal->db_ch1);
429 } else {
430 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
431 AR_AN_RF5G1_CH0_OB5,
432 AR_AN_RF5G1_CH0_OB5_S,
433 pModal->ob);
434 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
435 AR_AN_RF5G1_CH0_DB5,
436 AR_AN_RF5G1_CH0_DB5_S,
437 pModal->db);
438 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
439 AR_AN_RF5G1_CH1_OB5,
440 AR_AN_RF5G1_CH1_OB5_S,
441 pModal->ob_ch1);
442 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
443 AR_AN_RF5G1_CH1_DB5,
444 AR_AN_RF5G1_CH1_DB5_S,
445 pModal->db_ch1);
446 }
447 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
448 AR_AN_TOP2_XPABIAS_LVL,
449 AR_AN_TOP2_XPABIAS_LVL_S,
450 pModal->xpaBiasLvl);
451 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
452 AR_AN_TOP2_LOCALBIAS,
453 AR_AN_TOP2_LOCALBIAS_S,
454 pModal->local_bias);
455 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
456 pModal->force_xpaon);
457 }
458
459 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
460 pModal->switchSettling);
461 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
462 pModal->adcDesiredSize);
463
7a37081e 464 if (!AR_SREV_9280_20_OR_LATER(ah))
b5aec950
S		 465 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
466 AR_PHY_DESIRED_SZ_PGA,
467 pModal->pgaDesiredSize);
468
469 REG_WRITE(ah, AR_PHY_RF_CTL4,
470 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
471 | SM(pModal->txEndToXpaOff,
472 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
473 | SM(pModal->txFrameToXpaOn,
474 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
475 | SM(pModal->txFrameToXpaOn,
476 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
477
478 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
479 pModal->txEndToRxOn);
480
7a37081e 481 if (AR_SREV_9280_20_OR_LATER(ah)) {
b5aec950
S		 482 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
483 pModal->thresh62);
484 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
485 AR_PHY_EXT_CCA0_THRESH62,
486 pModal->thresh62);
487 } else {
488 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
489 pModal->thresh62);
490 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
491 AR_PHY_EXT_CCA_THRESH62,
492 pModal->thresh62);
493 }
494
495 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
496 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
497 AR_PHY_TX_END_DATA_START,
498 pModal->txFrameToDataStart);
499 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
500 pModal->txFrameToPaOn);
501 }
502
503 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
504 if (IS_CHAN_HT40(chan))
505 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
506 AR_PHY_SETTLING_SWITCH,
507 pModal->swSettleHt40);
508 }
509
510 if (AR_SREV_9280_20_OR_LATER(ah) &&
511 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
512 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
513 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
514 pModal->miscBits);
515
516
517 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
518 if (IS_CHAN_2GHZ(chan))
519 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
520 eep->baseEepHeader.dacLpMode);
521 else if (eep->baseEepHeader.dacHiPwrMode_5G)
522 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
523 else
524 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
525 eep->baseEepHeader.dacLpMode);
526
d865ca6c
SB		 527 udelay(100);
528
b5aec950
S		 529 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
530 pModal->miscBits >> 2);
531
532 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
533 AR_PHY_TX_DESIRED_SCALE_CCK,
534 eep->baseEepHeader.desiredScaleCCK);
535 }
536}
537
538static void ath9k_hw_def_set_addac(struct ath_hw *ah,
539 struct ath9k_channel *chan)
540{
541#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
542 struct modal_eep_header *pModal;
543 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
544 u8 biaslevel;
545
546 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
547 return;
548
549 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
550 return;
551
552 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
553
554 if (pModal->xpaBiasLvl != 0xff) {
555 biaslevel = pModal->xpaBiasLvl;
556 } else {
557 u16 resetFreqBin, freqBin, freqCount = 0;
558 struct chan_centers centers;
559
560 ath9k_hw_get_channel_centers(ah, chan, &centers);
561
562 resetFreqBin = FREQ2FBIN(centers.synth_center,
563 IS_CHAN_2GHZ(chan));
564 freqBin = XPA_LVL_FREQ(0) & 0xff;
565 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
566
567 freqCount++;
568
569 while (freqCount < 3) {
570 if (XPA_LVL_FREQ(freqCount) == 0x0)
571 break;
572
573 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
574 if (resetFreqBin >= freqBin)
575 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
576 else
577 break;
578 freqCount++;
579 }
580 }
581
582 if (IS_CHAN_2GHZ(chan)) {
583 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
584 7, 1) & (~0x18)) | biaslevel << 3;
585 } else {
586 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
587 6, 1) & (~0xc0)) | biaslevel << 6;
588 }
589#undef XPA_LVL_FREQ
590}
591
592static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
593 struct ath9k_channel *chan,
594 struct cal_data_per_freq *pRawDataSet,
595 u8 *bChans, u16 availPiers,
6eb90d46 596 u16 tPdGainOverlap,
b5aec950
S		 597 u16 *pPdGainBoundaries, u8 *pPDADCValues,
598 u16 numXpdGains)
599{
600 int i, j, k;
601 int16_t ss;
602 u16 idxL = 0, idxR = 0, numPiers;
603 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
604 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
605 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
606 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
607 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
608 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
609
610 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
611 u8 minPwrT4[AR5416_NUM_PD_GAINS];
612 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
613 int16_t vpdStep;
614 int16_t tmpVal;
615 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
616 bool match;
617 int16_t minDelta = 0;
618 struct chan_centers centers;
619
a5fdbcad 620 memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
b5aec950
S		 621 ath9k_hw_get_channel_centers(ah, chan, &centers);
622
623 for (numPiers = 0; numPiers < availPiers; numPiers++) {
624 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
625 break;
626 }
627
628 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
629 IS_CHAN_2GHZ(chan)),
630 bChans, numPiers, &idxL, &idxR);
631
632 if (match) {
633 for (i = 0; i < numXpdGains; i++) {
634 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
635 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
636 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
637 pRawDataSet[idxL].pwrPdg[i],
638 pRawDataSet[idxL].vpdPdg[i],
639 AR5416_PD_GAIN_ICEPTS,
640 vpdTableI[i]);
641 }
642 } else {
643 for (i = 0; i < numXpdGains; i++) {
644 pVpdL = pRawDataSet[idxL].vpdPdg[i];
645 pPwrL = pRawDataSet[idxL].pwrPdg[i];
646 pVpdR = pRawDataSet[idxR].vpdPdg[i];
647 pPwrR = pRawDataSet[idxR].pwrPdg[i];
648
649 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
650
651 maxPwrT4[i] =
652 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
653 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
654
655
656 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
657 pPwrL, pVpdL,
658 AR5416_PD_GAIN_ICEPTS,
659 vpdTableL[i]);
660 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
661 pPwrR, pVpdR,
662 AR5416_PD_GAIN_ICEPTS,
663 vpdTableR[i]);
664
665 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
666 vpdTableI[i][j] =
667 (u8)(ath9k_hw_interpolate((u16)
668 FREQ2FBIN(centers.
669 synth_center,
670 IS_CHAN_2GHZ
671 (chan)),
672 bChans[idxL], bChans[idxR],
673 vpdTableL[i][j], vpdTableR[i][j]));
674 }
675 }
676 }
677
b5aec950
S		 678 k = 0;
679
680 for (i = 0; i < numXpdGains; i++) {
681 if (i == (numXpdGains - 1))
682 pPdGainBoundaries[i] =
683 (u16)(maxPwrT4[i] / 2);
684 else
685 pPdGainBoundaries[i] =
686 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
687
688 pPdGainBoundaries[i] =
689 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
690
691 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
692 minDelta = pPdGainBoundaries[0] - 23;
693 pPdGainBoundaries[0] = 23;
694 } else {
695 minDelta = 0;
696 }
697
698 if (i == 0) {
7a37081e 699 if (AR_SREV_9280_20_OR_LATER(ah))
b5aec950
S		 700 ss = (int16_t)(0 - (minPwrT4[i] / 2));
701 else
702 ss = 0;
703 } else {
704 ss = (int16_t)((pPdGainBoundaries[i - 1] -
705 (minPwrT4[i] / 2)) -
706 tPdGainOverlap + 1 + minDelta);
707 }
708 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
709 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
710
711 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
712 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
713 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
714 ss++;
715 }
716
717 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
718 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
719 (minPwrT4[i] / 2));
720 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
721 tgtIndex : sizeCurrVpdTable;
722
723 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
724 pPDADCValues[k++] = vpdTableI[i][ss++];
725 }
726
727 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
728 vpdTableI[i][sizeCurrVpdTable - 2]);
729 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
730
03b4776c 731 if (tgtIndex >= maxIndex) {
b5aec950
S		 732 while ((ss <= tgtIndex) &&
733 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
734 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
735 (ss - maxIndex + 1) * vpdStep));
736 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
737 255 : tmpVal);
738 ss++;
739 }
740 }
741 }
742
743 while (i < AR5416_PD_GAINS_IN_MASK) {
744 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
745 i++;
746 }
747
748 while (k < AR5416_NUM_PDADC_VALUES) {
749 pPDADCValues[k] = pPDADCValues[k - 1];
750 k++;
751 }
b5aec950
S		 752}
753
e41f0bfc
SB		 754static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
755 u16 *gb,
756 u16 numXpdGain,
757 u16 pdGainOverlap_t2,
758 int8_t pwr_table_offset,
759 int16_t *diff)
760
761{
762 u16 k;
763
764 /* Prior to writing the boundaries or the pdadc vs. power table
765 * into the chip registers the default starting point on the pdadc
766 * vs. power table needs to be checked and the curve boundaries
767 * adjusted accordingly
768 */
769 if (AR_SREV_9280_20_OR_LATER(ah)) {
770 u16 gb_limit;
771
772 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
773 /* get the difference in dB */
774 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
775 /* get the number of half dB steps */
776 *diff *= 2;
777 /* change the original gain boundary settings
778 * by the number of half dB steps
779 */
780 for (k = 0; k < numXpdGain; k++)
781 gb[k] = (u16)(gb[k] - *diff);
782 }
783 /* Because of a hardware limitation, ensure the gain boundary
784 * is not larger than (63 - overlap)
785 */
786 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
787
788 for (k = 0; k < numXpdGain; k++)
789 gb[k] = (u16)min(gb_limit, gb[k]);
790 }
791
792 return *diff;
793}
794
795static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
796 int8_t pwr_table_offset,
797 int16_t diff,
798 u8 *pdadcValues)
799{
800#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
801 u16 k;
802
803 /* If this is a board that has a pwrTableOffset that differs from
804 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
805 * pdadc vs pwr table needs to be adjusted prior to writing to the
806 * chip.
807 */
808 if (AR_SREV_9280_20_OR_LATER(ah)) {
809 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
810 /* shift the table to start at the new offset */
811 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
812 pdadcValues[k] = pdadcValues[k + diff];
813 }
814
815 /* fill the back of the table */
816 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
817 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
818 }
819 }
820 }
821#undef NUM_PDADC
822}
823
b5aec950
S		 824static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
825 struct ath9k_channel *chan,
826 int16_t *pTxPowerIndexOffset)
827{
828#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
829#define SM_PDGAIN_B(x, y) \
830 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
c46917bb 831 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 832 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
833 struct cal_data_per_freq *pRawDataset;
834 u8 *pCalBChans = NULL;
835 u16 pdGainOverlap_t2;
836 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
837 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
838 u16 numPiers, i, j;
6eb90d46 839 int16_t diff = 0;
b5aec950
S		 840 u16 numXpdGain, xpdMask;
841 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
842 u32 reg32, regOffset, regChainOffset;
843 int16_t modalIdx;
e41f0bfc 844 int8_t pwr_table_offset;
b5aec950
S		 845
846 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
847 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
848
e41f0bfc
SB		 849 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
850
b5aec950
S		 851 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
852 AR5416_EEP_MINOR_VER_2) {
853 pdGainOverlap_t2 =
854 pEepData->modalHeader[modalIdx].pdGainOverlap;
855 } else {
856 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
857 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
858 }
859
860 if (IS_CHAN_2GHZ(chan)) {
861 pCalBChans = pEepData->calFreqPier2G;
862 numPiers = AR5416_NUM_2G_CAL_PIERS;
863 } else {
864 pCalBChans = pEepData->calFreqPier5G;
865 numPiers = AR5416_NUM_5G_CAL_PIERS;
866 }
867
868 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
869 pRawDataset = pEepData->calPierData2G[0];
870 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
871 pRawDataset)->vpdPdg[0][0];
872 }
873
874 numXpdGain = 0;
875
876 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
877 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
878 if (numXpdGain >= AR5416_NUM_PD_GAINS)
879 break;
880 xpdGainValues[numXpdGain] =
881 (u16)(AR5416_PD_GAINS_IN_MASK - i);
882 numXpdGain++;
883 }
884 }
885
886 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
887 (numXpdGain - 1) & 0x3);
888 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
889 xpdGainValues[0]);
890 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
891 xpdGainValues[1]);
892 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
893 xpdGainValues[2]);
894
895 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
896 if (AR_SREV_5416_20_OR_LATER(ah) &&
897 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
898 (i != 0)) {
899 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
900 } else
901 regChainOffset = i * 0x1000;
902
903 if (pEepData->baseEepHeader.txMask & (1 << i)) {
904 if (IS_CHAN_2GHZ(chan))
905 pRawDataset = pEepData->calPierData2G[i];
906 else
907 pRawDataset = pEepData->calPierData5G[i];
908
909
910 if (OLC_FOR_AR9280_20_LATER) {
911 u8 pcdacIdx;
912 u8 txPower;
913
914 ath9k_get_txgain_index(ah, chan,
915 (struct calDataPerFreqOpLoop *)pRawDataset,
916 pCalBChans, numPiers, &txPower, &pcdacIdx);
917 ath9k_olc_get_pdadcs(ah, pcdacIdx,
918 txPower/2, pdadcValues);
919 } else {
920 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
921 chan, pRawDataset,
922 pCalBChans, numPiers,
923 pdGainOverlap_t2,
b5aec950
S		 924 gainBoundaries,
925 pdadcValues,
926 numXpdGain);
927 }
928
e41f0bfc
SB		 929 diff = ath9k_change_gain_boundary_setting(ah,
930 gainBoundaries,
931 numXpdGain,
932 pdGainOverlap_t2,
933 pwr_table_offset,
934 &diff);
935
b5aec950
S		 936 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
937 if (OLC_FOR_AR9280_20_LATER) {
938 REG_WRITE(ah,
939 AR_PHY_TPCRG5 + regChainOffset,
940 SM(0x6,
941 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
942 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
943 SM_PD_GAIN(3) | SM_PD_GAIN(4));
944 } else {
945 REG_WRITE(ah,
946 AR_PHY_TPCRG5 + regChainOffset,
947 SM(pdGainOverlap_t2,
948 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
949 SM_PDGAIN_B(0, 1) |
950 SM_PDGAIN_B(1, 2) |
951 SM_PDGAIN_B(2, 3) |
952 SM_PDGAIN_B(3, 4));
953 }
954 }
955
e41f0bfc
SB		 956
957 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
958 diff, pdadcValues);
959
b5aec950
S		 960 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
961 for (j = 0; j < 32; j++) {
962 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
963 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
964 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
965 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
966 REG_WRITE(ah, regOffset, reg32);
967
c46917bb
LR		 968 ath_print(common, ATH_DBG_EEPROM,
969 "PDADC (%d,%4x): %4.4x %8.8x\n",
970 i, regChainOffset, regOffset,
971 reg32);
972 ath_print(common, ATH_DBG_EEPROM,
973 "PDADC: Chain %d | PDADC %3d "
974 "Value %3d | PDADC %3d Value %3d | "
975 "PDADC %3d Value %3d | PDADC %3d "
976 "Value %3d |\n",
977 i, 4 * j, pdadcValues[4 * j],
978 4 * j + 1, pdadcValues[4 * j + 1],
979 4 * j + 2, pdadcValues[4 * j + 2],
980 4 * j + 3,
981 pdadcValues[4 * j + 3]);
b5aec950
S		 982
983 regOffset += 4;
984 }
985 }
986 }
987
988 *pTxPowerIndexOffset = 0;
989#undef SM_PD_GAIN
990#undef SM_PDGAIN_B
991}
992
993static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
994 struct ath9k_channel *chan,
995 int16_t *ratesArray,
996 u16 cfgCtl,
997 u16 AntennaReduction,
998 u16 twiceMaxRegulatoryPower,
999 u16 powerLimit)
1000{
1001#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
d865ca6c 1002#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
b5aec950 1003
608b88cb 1004 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 1005 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1006 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1007 static const u16 tpScaleReductionTable[5] =
1008 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1009
1010 int i;
1011 int16_t twiceLargestAntenna;
1012 struct cal_ctl_data *rep;
1013 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1014 0, { 0, 0, 0, 0}
1015 };
1016 struct cal_target_power_leg targetPowerOfdmExt = {
1017 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1018 0, { 0, 0, 0, 0 }
1019 };
1020 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1021 0, {0, 0, 0, 0}
1022 };
1023 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1024 u16 ctlModesFor11a[] =
1025 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
1026 u16 ctlModesFor11g[] =
1027 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
1028 CTL_2GHT40
1029 };
1030 u16 numCtlModes, *pCtlMode, ctlMode, freq;
1031 struct chan_centers centers;
1032 int tx_chainmask;
1033 u16 twiceMinEdgePower;
1034
1035 tx_chainmask = ah->txchainmask;
1036
1037 ath9k_hw_get_channel_centers(ah, chan, &centers);
1038
1039 twiceLargestAntenna = max(
1040 pEepData->modalHeader
1041 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1042 pEepData->modalHeader
1043 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1044
1045 twiceLargestAntenna = max((u8)twiceLargestAntenna,
1046 pEepData->modalHeader
1047 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1048
1049 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1050 twiceLargestAntenna, 0);
1051
1052 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1053
608b88cb 1054 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
b5aec950 1055 maxRegAllowedPower -=
608b88cb 1056 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
b5aec950
S		 1057 }
1058
1059 scaledPower = min(powerLimit, maxRegAllowedPower);
1060
1061 switch (ar5416_get_ntxchains(tx_chainmask)) {
1062 case 1:
1063 break;
1064 case 2:
1065 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1066 break;
1067 case 3:
1068 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1069 break;
1070 }
1071
1072 scaledPower = max((u16)0, scaledPower);
1073
1074 if (IS_CHAN_2GHZ(chan)) {
1075 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1076 SUB_NUM_CTL_MODES_AT_2G_40;
1077 pCtlMode = ctlModesFor11g;
1078
1079 ath9k_hw_get_legacy_target_powers(ah, chan,
1080 pEepData->calTargetPowerCck,
1081 AR5416_NUM_2G_CCK_TARGET_POWERS,
1082 &targetPowerCck, 4, false);
1083 ath9k_hw_get_legacy_target_powers(ah, chan,
1084 pEepData->calTargetPower2G,
1085 AR5416_NUM_2G_20_TARGET_POWERS,
1086 &targetPowerOfdm, 4, false);
1087 ath9k_hw_get_target_powers(ah, chan,
1088 pEepData->calTargetPower2GHT20,
1089 AR5416_NUM_2G_20_TARGET_POWERS,
1090 &targetPowerHt20, 8, false);
1091
1092 if (IS_CHAN_HT40(chan)) {
1093 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1094 ath9k_hw_get_target_powers(ah, chan,
1095 pEepData->calTargetPower2GHT40,
1096 AR5416_NUM_2G_40_TARGET_POWERS,
1097 &targetPowerHt40, 8, true);
1098 ath9k_hw_get_legacy_target_powers(ah, chan,
1099 pEepData->calTargetPowerCck,
1100 AR5416_NUM_2G_CCK_TARGET_POWERS,
1101 &targetPowerCckExt, 4, true);
1102 ath9k_hw_get_legacy_target_powers(ah, chan,
1103 pEepData->calTargetPower2G,
1104 AR5416_NUM_2G_20_TARGET_POWERS,
1105 &targetPowerOfdmExt, 4, true);
1106 }
1107 } else {
1108 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1109 SUB_NUM_CTL_MODES_AT_5G_40;
1110 pCtlMode = ctlModesFor11a;
1111
1112 ath9k_hw_get_legacy_target_powers(ah, chan,
1113 pEepData->calTargetPower5G,
1114 AR5416_NUM_5G_20_TARGET_POWERS,
1115 &targetPowerOfdm, 4, false);
1116 ath9k_hw_get_target_powers(ah, chan,
1117 pEepData->calTargetPower5GHT20,
1118 AR5416_NUM_5G_20_TARGET_POWERS,
1119 &targetPowerHt20, 8, false);
1120
1121 if (IS_CHAN_HT40(chan)) {
1122 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1123 ath9k_hw_get_target_powers(ah, chan,
1124 pEepData->calTargetPower5GHT40,
1125 AR5416_NUM_5G_40_TARGET_POWERS,
1126 &targetPowerHt40, 8, true);
1127 ath9k_hw_get_legacy_target_powers(ah, chan,
1128 pEepData->calTargetPower5G,
1129 AR5416_NUM_5G_20_TARGET_POWERS,
1130 &targetPowerOfdmExt, 4, true);
1131 }
1132 }
1133
1134 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1135 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1136 (pCtlMode[ctlMode] == CTL_2GHT40);
1137 if (isHt40CtlMode)
1138 freq = centers.synth_center;
1139 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1140 freq = centers.ext_center;
1141 else
1142 freq = centers.ctl_center;
1143
1144 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1145 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1146 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1147
1148 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1149 if ((((cfgCtl & ~CTL_MODE_M) |
1150 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1151 pEepData->ctlIndex[i]) ||
1152 (((cfgCtl & ~CTL_MODE_M) |
1153 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1154 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1155 rep = &(pEepData->ctlData[i]);
1156
1157 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1158 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1159 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1160
1161 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1162 twiceMaxEdgePower = min(twiceMaxEdgePower,
1163 twiceMinEdgePower);
1164 } else {
1165 twiceMaxEdgePower = twiceMinEdgePower;
1166 break;
1167 }
1168 }
1169 }
1170
1171 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1172
1173 switch (pCtlMode[ctlMode]) {
1174 case CTL_11B:
1175 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1176 targetPowerCck.tPow2x[i] =
1177 min((u16)targetPowerCck.tPow2x[i],
1178 minCtlPower);
1179 }
1180 break;
1181 case CTL_11A:
1182 case CTL_11G:
1183 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1184 targetPowerOfdm.tPow2x[i] =
1185 min((u16)targetPowerOfdm.tPow2x[i],
1186 minCtlPower);
1187 }
1188 break;
1189 case CTL_5GHT20:
1190 case CTL_2GHT20:
1191 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1192 targetPowerHt20.tPow2x[i] =
1193 min((u16)targetPowerHt20.tPow2x[i],
1194 minCtlPower);
1195 }
1196 break;
1197 case CTL_11B_EXT:
1198 targetPowerCckExt.tPow2x[0] = min((u16)
1199 targetPowerCckExt.tPow2x[0],
1200 minCtlPower);
1201 break;
1202 case CTL_11A_EXT:
1203 case CTL_11G_EXT:
1204 targetPowerOfdmExt.tPow2x[0] = min((u16)
1205 targetPowerOfdmExt.tPow2x[0],
1206 minCtlPower);
1207 break;
1208 case CTL_5GHT40:
1209 case CTL_2GHT40:
1210 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1211 targetPowerHt40.tPow2x[i] =
1212 min((u16)targetPowerHt40.tPow2x[i],
1213 minCtlPower);
1214 }
1215 break;
1216 default:
1217 break;
1218 }
1219 }
1220
1221 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1222 ratesArray[rate18mb] = ratesArray[rate24mb] =
1223 targetPowerOfdm.tPow2x[0];
1224 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1225 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1226 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1227 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1228
1229 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1230 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1231
1232 if (IS_CHAN_2GHZ(chan)) {
1233 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1234 ratesArray[rate2s] = ratesArray[rate2l] =
1235 targetPowerCck.tPow2x[1];
1236 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1237 targetPowerCck.tPow2x[2];
1238 ratesArray[rate11s] = ratesArray[rate11l] =
1239 targetPowerCck.tPow2x[3];
1240 }
1241 if (IS_CHAN_HT40(chan)) {
1242 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1243 ratesArray[rateHt40_0 + i] =
1244 targetPowerHt40.tPow2x[i];
1245 }
1246 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1247 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1248 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1249 if (IS_CHAN_2GHZ(chan)) {
1250 ratesArray[rateExtCck] =
1251 targetPowerCckExt.tPow2x[0];
1252 }
1253 }
1254}
1255
1256static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1257 struct ath9k_channel *chan,
1258 u16 cfgCtl,
1259 u8 twiceAntennaReduction,
1260 u8 twiceMaxRegulatoryPower,
1261 u8 powerLimit)
1262{
1263#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
608b88cb 1264 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 1265 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1266 struct modal_eep_header *pModal =
1267 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1268 int16_t ratesArray[Ar5416RateSize];
1269 int16_t txPowerIndexOffset = 0;
1270 u8 ht40PowerIncForPdadc = 2;
1271 int i, cck_ofdm_delta = 0;
1272
1273 memset(ratesArray, 0, sizeof(ratesArray));
1274
1275 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1276 AR5416_EEP_MINOR_VER_2) {
1277 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1278 }
1279
1280 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1281 &ratesArray[0], cfgCtl,
1282 twiceAntennaReduction,
1283 twiceMaxRegulatoryPower,
1284 powerLimit);
1285
1286 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1287
1288 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1289 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1290 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1291 ratesArray[i] = AR5416_MAX_RATE_POWER;
1292 }
1293
7a37081e 1294 if (AR_SREV_9280_20_OR_LATER(ah)) {
e41f0bfc
SB		 1295 for (i = 0; i < Ar5416RateSize; i++) {
1296 int8_t pwr_table_offset;
1297
1298 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1299 EEP_PWR_TABLE_OFFSET);
1300 ratesArray[i] -= pwr_table_offset * 2;
1301 }
b5aec950
S		 1302 }
1303
1304 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1305 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1306 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1307 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1308 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1309 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1310 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1311 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1312 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1313 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1314
1315 if (IS_CHAN_2GHZ(chan)) {
1316 if (OLC_FOR_AR9280_20_LATER) {
1317 cck_ofdm_delta = 2;
1318 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1319 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1320 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1321 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1322 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1323 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1324 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1325 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1326 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1327 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1328 } else {
1329 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1330 ATH9K_POW_SM(ratesArray[rate2s], 24)
1331 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1332 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1333 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1334 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1335 ATH9K_POW_SM(ratesArray[rate11s], 24)
1336 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1337 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1338 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1339 }
1340 }
1341
1342 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1343 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1344 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1345 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1346 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1347 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1348 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1349 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1350 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1351 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1352
1353 if (IS_CHAN_HT40(chan)) {
1354 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1355 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1356 ht40PowerIncForPdadc, 24)
1357 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1358 ht40PowerIncForPdadc, 16)
1359 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1360 ht40PowerIncForPdadc, 8)
1361 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1362 ht40PowerIncForPdadc, 0));
1363 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1364 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1365 ht40PowerIncForPdadc, 24)
1366 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1367 ht40PowerIncForPdadc, 16)
1368 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1369 ht40PowerIncForPdadc, 8)
1370 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1371 ht40PowerIncForPdadc, 0));
1372 if (OLC_FOR_AR9280_20_LATER) {
1373 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1374 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1375 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1376 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1377 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1378 } else {
1379 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1380 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1381 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1382 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1383 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1384 }
1385 }
1386
1387 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1388 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1389 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1390
1391 i = rate6mb;
1392
1393 if (IS_CHAN_HT40(chan))
1394 i = rateHt40_0;
1395 else if (IS_CHAN_HT20(chan))
1396 i = rateHt20_0;
1397
7a37081e 1398 if (AR_SREV_9280_20_OR_LATER(ah))
608b88cb 1399 regulatory->max_power_level =
e41f0bfc 1400 ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
b5aec950 1401 else
608b88cb 1402 regulatory->max_power_level = ratesArray[i];
b5aec950
S		 1403
1404 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1405 case 1:
1406 break;
1407 case 2:
608b88cb 1408 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
b5aec950
S		 1409 break;
1410 case 3:
608b88cb 1411 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
b5aec950
S		 1412 break;
1413 default:
c46917bb
LR		 1414 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1415 "Invalid chainmask configuration\n");
b5aec950
S		 1416 break;
1417 }
1418}
1419
1420static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
f799a301 1421 enum ath9k_hal_freq_band freq_band)
b5aec950
S		 1422{
1423 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1424 struct modal_eep_header *pModal =
f799a301 1425 &(eep->modalHeader[freq_band]);
b5aec950
S		 1426 struct base_eep_header *pBase = &eep->baseEepHeader;
1427 u8 num_ant_config;
1428
1429 num_ant_config = 1;
1430
1431 if (pBase->version >= 0x0E0D)
1432 if (pModal->useAnt1)
1433 num_ant_config += 1;
1434
1435 return num_ant_config;
1436}
1437
601e0cb1 1438static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
b5aec950
S		 1439 struct ath9k_channel *chan)
1440{
1441 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1442 struct modal_eep_header *pModal =
1443 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1444
601e0cb1 1445 return pModal->antCtrlCommon;
b5aec950
S		 1446}
1447
1448static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1449{
1450#define EEP_DEF_SPURCHAN \
1451 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
c46917bb 1452 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 1453
1454 u16 spur_val = AR_NO_SPUR;
1455
c46917bb
LR		 1456 ath_print(common, ATH_DBG_ANI,
1457 "Getting spur idx %d is2Ghz. %d val %x\n",
1458 i, is2GHz, ah->config.spurchans[i][is2GHz]);
b5aec950
S		 1459
1460 switch (ah->config.spurmode) {
1461 case SPUR_DISABLE:
1462 break;
1463 case SPUR_ENABLE_IOCTL:
1464 spur_val = ah->config.spurchans[i][is2GHz];
c46917bb
LR		 1465 ath_print(common, ATH_DBG_ANI,
1466 "Getting spur val from new loc. %d\n", spur_val);
b5aec950
S		 1467 break;
1468 case SPUR_ENABLE_EEPROM:
1469 spur_val = EEP_DEF_SPURCHAN;
1470 break;
1471 }
1472
1473 return spur_val;
1474
1475#undef EEP_DEF_SPURCHAN
1476}
1477
1478const struct eeprom_ops eep_def_ops = {
1479 .check_eeprom = ath9k_hw_def_check_eeprom,
1480 .get_eeprom = ath9k_hw_def_get_eeprom,
1481 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1482 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1483 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1484 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
1485 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1486 .set_board_values = ath9k_hw_def_set_board_values,
1487 .set_addac = ath9k_hw_def_set_addac,
1488 .set_txpower = ath9k_hw_def_set_txpower,
1489 .get_spur_channel = ath9k_hw_def_get_spur_channel
1490};
Linux kernel - Deliverables
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