Commit | Line | Data |
---|---|---|
0fca65c1 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
0fca65c1 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "ath9k.h" | |
18 | ||
19 | /********************************/ | |
20 | /* LED functions */ | |
21 | /********************************/ | |
22 | ||
0cf55c21 | 23 | #ifdef CONFIG_MAC80211_LEDS |
0fca65c1 S |
24 | static void ath_led_brightness(struct led_classdev *led_cdev, |
25 | enum led_brightness brightness) | |
26 | { | |
0cf55c21 FF |
27 | struct ath_softc *sc = container_of(led_cdev, struct ath_softc, led_cdev); |
28 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, (brightness == LED_OFF)); | |
0fca65c1 S |
29 | } |
30 | ||
31 | void ath_deinit_leds(struct ath_softc *sc) | |
32 | { | |
0cf55c21 FF |
33 | if (!sc->led_registered) |
34 | return; | |
35 | ||
36 | ath_led_brightness(&sc->led_cdev, LED_OFF); | |
37 | led_classdev_unregister(&sc->led_cdev); | |
0fca65c1 S |
38 | } |
39 | ||
40 | void ath_init_leds(struct ath_softc *sc) | |
41 | { | |
0fca65c1 S |
42 | int ret; |
43 | ||
7b27ba4e FF |
44 | if (AR_SREV_9100(sc->sc_ah)) |
45 | return; | |
46 | ||
6de66dd9 FF |
47 | if (sc->sc_ah->led_pin < 0) { |
48 | if (AR_SREV_9287(sc->sc_ah)) | |
49 | sc->sc_ah->led_pin = ATH_LED_PIN_9287; | |
50 | else if (AR_SREV_9485(sc->sc_ah)) | |
51 | sc->sc_ah->led_pin = ATH_LED_PIN_9485; | |
353e5019 SB |
52 | else if (AR_SREV_9300(sc->sc_ah)) |
53 | sc->sc_ah->led_pin = ATH_LED_PIN_9300; | |
423e38e8 RM |
54 | else if (AR_SREV_9462(sc->sc_ah)) |
55 | sc->sc_ah->led_pin = ATH_LED_PIN_9462; | |
6de66dd9 FF |
56 | else |
57 | sc->sc_ah->led_pin = ATH_LED_PIN_DEF; | |
58 | } | |
0fca65c1 S |
59 | |
60 | /* Configure gpio 1 for output */ | |
61 | ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, | |
62 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
63 | /* LED off, active low */ | |
64 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); | |
65 | ||
0cf55c21 FF |
66 | if (!led_blink) |
67 | sc->led_cdev.default_trigger = | |
68 | ieee80211_get_radio_led_name(sc->hw); | |
69 | ||
70 | snprintf(sc->led_name, sizeof(sc->led_name), | |
71 | "ath9k-%s", wiphy_name(sc->hw->wiphy)); | |
72 | sc->led_cdev.name = sc->led_name; | |
73 | sc->led_cdev.brightness_set = ath_led_brightness; | |
74 | ||
75 | ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &sc->led_cdev); | |
76 | if (ret < 0) | |
77 | return; | |
78 | ||
79 | sc->led_registered = true; | |
0fca65c1 | 80 | } |
0cf55c21 | 81 | #endif |
0fca65c1 S |
82 | |
83 | /*******************/ | |
84 | /* Rfkill */ | |
85 | /*******************/ | |
86 | ||
87 | static bool ath_is_rfkill_set(struct ath_softc *sc) | |
88 | { | |
89 | struct ath_hw *ah = sc->sc_ah; | |
90826313 | 90 | bool is_blocked; |
0fca65c1 | 91 | |
90826313 MSS |
92 | ath9k_ps_wakeup(sc); |
93 | is_blocked = ath9k_hw_gpio_get(ah, ah->rfkill_gpio) == | |
0fca65c1 | 94 | ah->rfkill_polarity; |
90826313 MSS |
95 | ath9k_ps_restore(sc); |
96 | ||
97 | return is_blocked; | |
0fca65c1 S |
98 | } |
99 | ||
100 | void ath9k_rfkill_poll_state(struct ieee80211_hw *hw) | |
101 | { | |
9ac58615 | 102 | struct ath_softc *sc = hw->priv; |
0fca65c1 S |
103 | bool blocked = !!ath_is_rfkill_set(sc); |
104 | ||
105 | wiphy_rfkill_set_hw_state(hw->wiphy, blocked); | |
106 | } | |
107 | ||
108 | void ath_start_rfkill_poll(struct ath_softc *sc) | |
109 | { | |
110 | struct ath_hw *ah = sc->sc_ah; | |
111 | ||
112 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
113 | wiphy_rfkill_start_polling(sc->hw->wiphy); | |
114 | } | |
115 | ||
4daa7760 SM |
116 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
117 | ||
0fca65c1 S |
118 | /******************/ |
119 | /* BTCOEX */ | |
120 | /******************/ | |
121 | ||
122 | /* | |
123 | * Detects if there is any priority bt traffic | |
124 | */ | |
125 | static void ath_detect_bt_priority(struct ath_softc *sc) | |
126 | { | |
127 | struct ath_btcoex *btcoex = &sc->btcoex; | |
128 | struct ath_hw *ah = sc->sc_ah; | |
129 | ||
130 | if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio)) | |
131 | btcoex->bt_priority_cnt++; | |
132 | ||
133 | if (time_after(jiffies, btcoex->bt_priority_time + | |
134 | msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) { | |
e6930c4b SM |
135 | clear_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags); |
136 | clear_bit(BT_OP_SCAN, &btcoex->op_flags); | |
58da1318 VT |
137 | /* Detect if colocated bt started scanning */ |
138 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { | |
d2182b69 | 139 | ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX, |
226afe68 | 140 | "BT scan detected\n"); |
e6930c4b SM |
141 | set_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags); |
142 | set_bit(BT_OP_SCAN, &btcoex->op_flags); | |
58da1318 | 143 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { |
d2182b69 | 144 | ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX, |
226afe68 | 145 | "BT priority traffic detected\n"); |
e6930c4b | 146 | set_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags); |
0fca65c1 S |
147 | } |
148 | ||
149 | btcoex->bt_priority_cnt = 0; | |
150 | btcoex->bt_priority_time = jiffies; | |
151 | } | |
152 | } | |
153 | ||
0fca65c1 S |
154 | static void ath9k_gen_timer_start(struct ath_hw *ah, |
155 | struct ath_gen_timer *timer, | |
788f6875 | 156 | u32 trig_timeout, |
0fca65c1 S |
157 | u32 timer_period) |
158 | { | |
788f6875 | 159 | ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period); |
0fca65c1 | 160 | |
3069168c | 161 | if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { |
4df3071e | 162 | ath9k_hw_disable_interrupts(ah); |
3069168c | 163 | ah->imask |= ATH9K_INT_GENTIMER; |
72d874c6 | 164 | ath9k_hw_set_interrupts(ah); |
b037b693 | 165 | ath9k_hw_enable_interrupts(ah); |
0fca65c1 S |
166 | } |
167 | } | |
168 | ||
169 | static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) | |
170 | { | |
0fca65c1 S |
171 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
172 | ||
173 | ath9k_hw_gen_timer_stop(ah, timer); | |
174 | ||
175 | /* if no timer is enabled, turn off interrupt mask */ | |
176 | if (timer_table->timer_mask.val == 0) { | |
4df3071e | 177 | ath9k_hw_disable_interrupts(ah); |
3069168c | 178 | ah->imask &= ~ATH9K_INT_GENTIMER; |
72d874c6 | 179 | ath9k_hw_set_interrupts(ah); |
b037b693 | 180 | ath9k_hw_enable_interrupts(ah); |
0fca65c1 S |
181 | } |
182 | } | |
183 | ||
184 | /* | |
185 | * This is the master bt coex timer which runs for every | |
186 | * 45ms, bt traffic will be given priority during 55% of this | |
187 | * period while wlan gets remaining 45% | |
188 | */ | |
189 | static void ath_btcoex_period_timer(unsigned long data) | |
190 | { | |
191 | struct ath_softc *sc = (struct ath_softc *) data; | |
192 | struct ath_hw *ah = sc->sc_ah; | |
193 | struct ath_btcoex *btcoex = &sc->btcoex; | |
6995fb80 | 194 | struct ath_mci_profile *mci = &btcoex->mci; |
58da1318 VT |
195 | u32 timer_period; |
196 | bool is_btscan; | |
08d4df41 RM |
197 | unsigned long flags; |
198 | ||
199 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
200 | if (sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP) { | |
201 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
202 | goto skip_hw_wakeup; | |
203 | } | |
204 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
0fca65c1 | 205 | |
a039a993 | 206 | ath9k_ps_wakeup(sc); |
7dc181c2 RM |
207 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) |
208 | ath_detect_bt_priority(sc); | |
e6930c4b | 209 | is_btscan = test_bit(BT_OP_SCAN, &btcoex->op_flags); |
58da1318 | 210 | |
6995fb80 RM |
211 | btcoex->bt_wait_time += btcoex->btcoex_period; |
212 | if (btcoex->bt_wait_time > ATH_BTCOEX_RX_WAIT_TIME) { | |
b98ccec0 | 213 | if (ar9003_mci_state(ah, MCI_STATE_NEED_FTP_STOMP) && |
6995fb80 RM |
214 | (mci->num_pan || mci->num_other_acl)) |
215 | ah->btcoex_hw.mci.stomp_ftp = | |
216 | (sc->rx.num_pkts < ATH_BTCOEX_STOMP_FTP_THRESH); | |
217 | else | |
218 | ah->btcoex_hw.mci.stomp_ftp = false; | |
219 | btcoex->bt_wait_time = 0; | |
220 | sc->rx.num_pkts = 0; | |
221 | } | |
222 | ||
0fca65c1 S |
223 | spin_lock_bh(&btcoex->btcoex_lock); |
224 | ||
978f78bf | 225 | ath9k_hw_btcoex_bt_stomp(ah, is_btscan ? ATH_BTCOEX_STOMP_ALL : |
58da1318 | 226 | btcoex->bt_stomp_type); |
0fca65c1 | 227 | |
bc6d5c29 | 228 | ath9k_hw_btcoex_enable(ah); |
0fca65c1 S |
229 | spin_unlock_bh(&btcoex->btcoex_lock); |
230 | ||
231 | if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) { | |
232 | if (btcoex->hw_timer_enabled) | |
233 | ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer); | |
234 | ||
58da1318 VT |
235 | timer_period = is_btscan ? btcoex->btscan_no_stomp : |
236 | btcoex->btcoex_no_stomp; | |
788f6875 | 237 | ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period, |
8eb1dabb | 238 | timer_period * 10); |
0fca65c1 S |
239 | btcoex->hw_timer_enabled = true; |
240 | } | |
241 | ||
a039a993 | 242 | ath9k_ps_restore(sc); |
08d4df41 | 243 | skip_hw_wakeup: |
dfd0587a | 244 | timer_period = btcoex->btcoex_period; |
e6930c4b | 245 | mod_timer(&btcoex->period_timer, jiffies + msecs_to_jiffies(timer_period)); |
0fca65c1 S |
246 | } |
247 | ||
248 | /* | |
249 | * Generic tsf based hw timer which configures weight | |
250 | * registers to time slice between wlan and bt traffic | |
251 | */ | |
252 | static void ath_btcoex_no_stomp_timer(void *arg) | |
253 | { | |
254 | struct ath_softc *sc = (struct ath_softc *)arg; | |
255 | struct ath_hw *ah = sc->sc_ah; | |
256 | struct ath_btcoex *btcoex = &sc->btcoex; | |
d99eeb87 | 257 | struct ath_common *common = ath9k_hw_common(ah); |
0fca65c1 | 258 | |
d2182b69 | 259 | ath_dbg(common, BTCOEX, "no stomp timer running\n"); |
0fca65c1 | 260 | |
a039a993 | 261 | ath9k_ps_wakeup(sc); |
0fca65c1 S |
262 | spin_lock_bh(&btcoex->btcoex_lock); |
263 | ||
e6930c4b SM |
264 | if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || |
265 | test_bit(BT_OP_SCAN, &btcoex->op_flags)) | |
978f78bf | 266 | ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE); |
0fca65c1 | 267 | else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL) |
978f78bf | 268 | ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW); |
0fca65c1 | 269 | |
bc6d5c29 | 270 | ath9k_hw_btcoex_enable(ah); |
0fca65c1 | 271 | spin_unlock_bh(&btcoex->btcoex_lock); |
a039a993 | 272 | ath9k_ps_restore(sc); |
0fca65c1 S |
273 | } |
274 | ||
df198b17 | 275 | static int ath_init_btcoex_timer(struct ath_softc *sc) |
0fca65c1 S |
276 | { |
277 | struct ath_btcoex *btcoex = &sc->btcoex; | |
278 | ||
dfd0587a RM |
279 | btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD; |
280 | btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 1000 * | |
0fca65c1 | 281 | btcoex->btcoex_period / 100; |
dfd0587a | 282 | btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 1000 * |
58da1318 | 283 | btcoex->btcoex_period / 100; |
0fca65c1 S |
284 | |
285 | setup_timer(&btcoex->period_timer, ath_btcoex_period_timer, | |
286 | (unsigned long) sc); | |
287 | ||
288 | spin_lock_init(&btcoex->btcoex_lock); | |
289 | ||
290 | btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah, | |
291 | ath_btcoex_no_stomp_timer, | |
292 | ath_btcoex_no_stomp_timer, | |
293 | (void *) sc, AR_FIRST_NDP_TIMER); | |
294 | ||
295 | if (!btcoex->no_stomp_timer) | |
296 | return -ENOMEM; | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | /* | |
302 | * (Re)start btcoex timers | |
303 | */ | |
304 | void ath9k_btcoex_timer_resume(struct ath_softc *sc) | |
305 | { | |
306 | struct ath_btcoex *btcoex = &sc->btcoex; | |
307 | struct ath_hw *ah = sc->sc_ah; | |
308 | ||
d2182b69 | 309 | ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n"); |
0fca65c1 S |
310 | |
311 | /* make sure duty cycle timer is also stopped when resuming */ | |
312 | if (btcoex->hw_timer_enabled) | |
313 | ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer); | |
314 | ||
315 | btcoex->bt_priority_cnt = 0; | |
316 | btcoex->bt_priority_time = jiffies; | |
c11216d1 MSS |
317 | clear_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags); |
318 | clear_bit(BT_OP_SCAN, &btcoex->op_flags); | |
0fca65c1 S |
319 | |
320 | mod_timer(&btcoex->period_timer, jiffies); | |
321 | } | |
322 | ||
323 | ||
324 | /* | |
325 | * Pause btcoex timer and bt duty cycle timer | |
326 | */ | |
327 | void ath9k_btcoex_timer_pause(struct ath_softc *sc) | |
328 | { | |
329 | struct ath_btcoex *btcoex = &sc->btcoex; | |
330 | struct ath_hw *ah = sc->sc_ah; | |
331 | ||
332 | del_timer_sync(&btcoex->period_timer); | |
333 | ||
334 | if (btcoex->hw_timer_enabled) | |
335 | ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer); | |
336 | ||
337 | btcoex->hw_timer_enabled = false; | |
338 | } | |
5908120f | 339 | |
08d4df41 RM |
340 | void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) |
341 | { | |
342 | struct ath_btcoex *btcoex = &sc->btcoex; | |
343 | ||
5d9b6f26 MSS |
344 | if (btcoex->hw_timer_enabled) |
345 | ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer); | |
08d4df41 RM |
346 | } |
347 | ||
c0ac53fa SM |
348 | u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen) |
349 | { | |
e6930c4b | 350 | struct ath_btcoex *btcoex = &sc->btcoex; |
c0ac53fa SM |
351 | struct ath_mci_profile *mci = &sc->btcoex.mci; |
352 | u16 aggr_limit = 0; | |
353 | ||
354 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit) | |
355 | aggr_limit = (max_4ms_framelen * mci->aggr_limit) >> 4; | |
e6930c4b | 356 | else if (test_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags)) |
c0ac53fa SM |
357 | aggr_limit = min((max_4ms_framelen * 3) / 8, |
358 | (u32)ATH_AMPDU_LIMIT_MAX); | |
359 | ||
360 | return aggr_limit; | |
361 | } | |
362 | ||
56ca0dba SM |
363 | void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status) |
364 | { | |
365 | struct ath_hw *ah = sc->sc_ah; | |
366 | ||
367 | if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) | |
368 | if (status & ATH9K_INT_GENTIMER) | |
369 | ath_gen_timer_isr(sc->sc_ah); | |
370 | ||
9a15858f | 371 | if (status & ATH9K_INT_MCI) |
56ca0dba SM |
372 | ath_mci_intr(sc); |
373 | } | |
374 | ||
df198b17 SM |
375 | void ath9k_start_btcoex(struct ath_softc *sc) |
376 | { | |
377 | struct ath_hw *ah = sc->sc_ah; | |
378 | ||
379 | if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && | |
380 | !ah->btcoex_hw.enabled) { | |
381 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) | |
382 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, | |
383 | AR_STOMP_LOW_WLAN_WGHT); | |
384 | ath9k_hw_btcoex_enable(ah); | |
385 | ||
386 | if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) | |
387 | ath9k_btcoex_timer_resume(sc); | |
388 | } | |
389 | } | |
390 | ||
391 | void ath9k_stop_btcoex(struct ath_softc *sc) | |
392 | { | |
393 | struct ath_hw *ah = sc->sc_ah; | |
394 | ||
395 | if (ah->btcoex_hw.enabled && | |
396 | ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { | |
df198b17 SM |
397 | if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) |
398 | ath9k_btcoex_timer_pause(sc); | |
c32cdbd8 | 399 | ath9k_hw_btcoex_disable(ah); |
0466e254 | 400 | if (AR_SREV_9462(ah)) |
bff2ec2b | 401 | ath_mci_flush_profile(&sc->btcoex.mci); |
df198b17 SM |
402 | } |
403 | } | |
404 | ||
5908120f SM |
405 | void ath9k_deinit_btcoex(struct ath_softc *sc) |
406 | { | |
dd89f05a MSS |
407 | struct ath_hw *ah = sc->sc_ah; |
408 | ||
5908120f SM |
409 | if ((sc->btcoex.no_stomp_timer) && |
410 | ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE) | |
411 | ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); | |
412 | ||
dd89f05a | 413 | if (ath9k_hw_mci_is_enabled(ah)) |
5908120f SM |
414 | ath_mci_cleanup(sc); |
415 | } | |
416 | ||
417 | int ath9k_init_btcoex(struct ath_softc *sc) | |
418 | { | |
419 | struct ath_txq *txq; | |
420 | struct ath_hw *ah = sc->sc_ah; | |
421 | int r; | |
422 | ||
d68475de SM |
423 | ath9k_hw_btcoex_init_scheme(ah); |
424 | ||
5908120f SM |
425 | switch (ath9k_hw_get_btcoex_scheme(sc->sc_ah)) { |
426 | case ATH_BTCOEX_CFG_NONE: | |
427 | break; | |
428 | case ATH_BTCOEX_CFG_2WIRE: | |
429 | ath9k_hw_btcoex_init_2wire(sc->sc_ah); | |
430 | break; | |
431 | case ATH_BTCOEX_CFG_3WIRE: | |
432 | ath9k_hw_btcoex_init_3wire(sc->sc_ah); | |
433 | r = ath_init_btcoex_timer(sc); | |
434 | if (r) | |
435 | return -1; | |
436 | txq = sc->tx.txq_map[WME_AC_BE]; | |
437 | ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); | |
438 | sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; | |
81294489 | 439 | if (ath9k_hw_mci_is_enabled(ah)) { |
0466e254 RM |
440 | sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE; |
441 | INIT_LIST_HEAD(&sc->btcoex.mci.info); | |
5908120f | 442 | |
0466e254 RM |
443 | r = ath_mci_setup(sc); |
444 | if (r) | |
445 | return r; | |
5908120f | 446 | |
0466e254 RM |
447 | ath9k_hw_btcoex_init_mci(ah); |
448 | } | |
5908120f SM |
449 | |
450 | break; | |
451 | default: | |
452 | WARN_ON(1); | |
453 | break; | |
454 | } | |
455 | ||
456 | return 0; | |
457 | } | |
4daa7760 SM |
458 | |
459 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |