ath9k: fill channel mode in caldata
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / gpio.c
CommitLineData
0fca65c1 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
0fca65c1
S
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19/********************************/
20/* LED functions */
21/********************************/
22
0cf55c21 23#ifdef CONFIG_MAC80211_LEDS
0fca65c1
S
24static void ath_led_brightness(struct led_classdev *led_cdev,
25 enum led_brightness brightness)
26{
0cf55c21
FF
27 struct ath_softc *sc = container_of(led_cdev, struct ath_softc, led_cdev);
28 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, (brightness == LED_OFF));
0fca65c1
S
29}
30
31void ath_deinit_leds(struct ath_softc *sc)
32{
0cf55c21
FF
33 if (!sc->led_registered)
34 return;
35
36 ath_led_brightness(&sc->led_cdev, LED_OFF);
37 led_classdev_unregister(&sc->led_cdev);
0fca65c1
S
38}
39
40void ath_init_leds(struct ath_softc *sc)
41{
0fca65c1
S
42 int ret;
43
7b27ba4e
FF
44 if (AR_SREV_9100(sc->sc_ah))
45 return;
46
0cf55c21
FF
47 if (!led_blink)
48 sc->led_cdev.default_trigger =
49 ieee80211_get_radio_led_name(sc->hw);
50
51 snprintf(sc->led_name, sizeof(sc->led_name),
52 "ath9k-%s", wiphy_name(sc->hw->wiphy));
53 sc->led_cdev.name = sc->led_name;
54 sc->led_cdev.brightness_set = ath_led_brightness;
55
56 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &sc->led_cdev);
57 if (ret < 0)
58 return;
59
60 sc->led_registered = true;
0fca65c1 61}
8f176a3a
RM
62
63void ath_fill_led_pin(struct ath_softc *sc)
64{
65 struct ath_hw *ah = sc->sc_ah;
66
67 if (AR_SREV_9100(ah) || (ah->led_pin >= 0))
68 return;
69
70 if (AR_SREV_9287(ah))
71 ah->led_pin = ATH_LED_PIN_9287;
72 else if (AR_SREV_9485(sc->sc_ah))
73 ah->led_pin = ATH_LED_PIN_9485;
74 else if (AR_SREV_9300(sc->sc_ah))
75 ah->led_pin = ATH_LED_PIN_9300;
76 else if (AR_SREV_9462(sc->sc_ah) || AR_SREV_9565(sc->sc_ah))
77 ah->led_pin = ATH_LED_PIN_9462;
78 else
79 ah->led_pin = ATH_LED_PIN_DEF;
80
81 /* Configure gpio 1 for output */
82 ath9k_hw_cfg_output(ah, ah->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
83
84 /* LED off, active low */
85 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
86}
0cf55c21 87#endif
0fca65c1
S
88
89/*******************/
90/* Rfkill */
91/*******************/
92
93static bool ath_is_rfkill_set(struct ath_softc *sc)
94{
95 struct ath_hw *ah = sc->sc_ah;
90826313 96 bool is_blocked;
0fca65c1 97
90826313
MSS
98 ath9k_ps_wakeup(sc);
99 is_blocked = ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
0fca65c1 100 ah->rfkill_polarity;
90826313
MSS
101 ath9k_ps_restore(sc);
102
103 return is_blocked;
0fca65c1
S
104}
105
106void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
107{
9ac58615 108 struct ath_softc *sc = hw->priv;
0fca65c1
S
109 bool blocked = !!ath_is_rfkill_set(sc);
110
111 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
112}
113
114void ath_start_rfkill_poll(struct ath_softc *sc)
115{
116 struct ath_hw *ah = sc->sc_ah;
117
118 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
119 wiphy_rfkill_start_polling(sc->hw->wiphy);
120}
121
4daa7760
SM
122#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
123
0fca65c1
S
124/******************/
125/* BTCOEX */
126/******************/
127
128/*
129 * Detects if there is any priority bt traffic
130 */
131static void ath_detect_bt_priority(struct ath_softc *sc)
132{
133 struct ath_btcoex *btcoex = &sc->btcoex;
134 struct ath_hw *ah = sc->sc_ah;
135
136 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
137 btcoex->bt_priority_cnt++;
138
139 if (time_after(jiffies, btcoex->bt_priority_time +
140 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
e6930c4b
SM
141 clear_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags);
142 clear_bit(BT_OP_SCAN, &btcoex->op_flags);
58da1318
VT
143 /* Detect if colocated bt started scanning */
144 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
d2182b69 145 ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX,
226afe68 146 "BT scan detected\n");
e6930c4b
SM
147 set_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags);
148 set_bit(BT_OP_SCAN, &btcoex->op_flags);
58da1318 149 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
d2182b69 150 ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX,
226afe68 151 "BT priority traffic detected\n");
e6930c4b 152 set_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags);
0fca65c1
S
153 }
154
155 btcoex->bt_priority_cnt = 0;
156 btcoex->bt_priority_time = jiffies;
157 }
158}
159
0fca65c1
S
160static void ath9k_gen_timer_start(struct ath_hw *ah,
161 struct ath_gen_timer *timer,
788f6875 162 u32 trig_timeout,
0fca65c1
S
163 u32 timer_period)
164{
788f6875 165 ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period);
0fca65c1 166
3069168c 167 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
4df3071e 168 ath9k_hw_disable_interrupts(ah);
3069168c 169 ah->imask |= ATH9K_INT_GENTIMER;
72d874c6 170 ath9k_hw_set_interrupts(ah);
b037b693 171 ath9k_hw_enable_interrupts(ah);
0fca65c1
S
172 }
173}
174
175static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
176{
0fca65c1
S
177 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
178
179 ath9k_hw_gen_timer_stop(ah, timer);
180
181 /* if no timer is enabled, turn off interrupt mask */
182 if (timer_table->timer_mask.val == 0) {
4df3071e 183 ath9k_hw_disable_interrupts(ah);
3069168c 184 ah->imask &= ~ATH9K_INT_GENTIMER;
72d874c6 185 ath9k_hw_set_interrupts(ah);
b037b693 186 ath9k_hw_enable_interrupts(ah);
0fca65c1
S
187 }
188}
189
78b1775b
SM
190static void ath_mci_ftp_adjust(struct ath_softc *sc)
191{
192 struct ath_btcoex *btcoex = &sc->btcoex;
193 struct ath_mci_profile *mci = &btcoex->mci;
194 struct ath_hw *ah = sc->sc_ah;
195
78b1775b
SM
196 if (btcoex->bt_wait_time > ATH_BTCOEX_RX_WAIT_TIME) {
197 if (ar9003_mci_state(ah, MCI_STATE_NEED_FTP_STOMP) &&
198 (mci->num_pan || mci->num_other_acl))
199 ah->btcoex_hw.mci.stomp_ftp =
200 (sc->rx.num_pkts < ATH_BTCOEX_STOMP_FTP_THRESH);
201 else
202 ah->btcoex_hw.mci.stomp_ftp = false;
203 btcoex->bt_wait_time = 0;
204 sc->rx.num_pkts = 0;
205 }
206}
207
0fca65c1
S
208/*
209 * This is the master bt coex timer which runs for every
210 * 45ms, bt traffic will be given priority during 55% of this
211 * period while wlan gets remaining 45%
212 */
213static void ath_btcoex_period_timer(unsigned long data)
214{
215 struct ath_softc *sc = (struct ath_softc *) data;
216 struct ath_hw *ah = sc->sc_ah;
217 struct ath_btcoex *btcoex = &sc->btcoex;
750f32cf 218 enum ath_stomp_type stomp_type;
58da1318 219 u32 timer_period;
08d4df41
RM
220 unsigned long flags;
221
222 spin_lock_irqsave(&sc->sc_pm_lock, flags);
223 if (sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP) {
be41b052 224 btcoex->bt_wait_time += btcoex->btcoex_period;
08d4df41
RM
225 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
226 goto skip_hw_wakeup;
227 }
228 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0fca65c1 229
a039a993 230 ath9k_ps_wakeup(sc);
750f32cf 231
7dc181c2
RM
232 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI))
233 ath_detect_bt_priority(sc);
58da1318 234
78b1775b
SM
235 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
236 ath_mci_ftp_adjust(sc);
6995fb80 237
0fca65c1
S
238 spin_lock_bh(&btcoex->btcoex_lock);
239
750f32cf
SM
240 stomp_type = btcoex->bt_stomp_type;
241 timer_period = btcoex->btcoex_no_stomp;
242
243 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) {
244 if (test_bit(BT_OP_SCAN, &btcoex->op_flags)) {
245 stomp_type = ATH_BTCOEX_STOMP_ALL;
246 timer_period = btcoex->btscan_no_stomp;
247 }
248 }
0fca65c1 249
750f32cf 250 ath9k_hw_btcoex_bt_stomp(ah, stomp_type);
bc6d5c29 251 ath9k_hw_btcoex_enable(ah);
750f32cf 252
0fca65c1
S
253 spin_unlock_bh(&btcoex->btcoex_lock);
254
94ae77ea
MSS
255 /*
256 * btcoex_period is in msec while (btocex/btscan_)no_stomp are in usec,
257 * ensure that we properly convert btcoex_period to usec
258 * for any comparision with (btcoex/btscan_)no_stomp.
259 */
260 if (btcoex->btcoex_period * 1000 != btcoex->btcoex_no_stomp) {
0fca65c1
S
261 if (btcoex->hw_timer_enabled)
262 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
263
788f6875 264 ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period,
8eb1dabb 265 timer_period * 10);
0fca65c1
S
266 btcoex->hw_timer_enabled = true;
267 }
268
a039a993 269 ath9k_ps_restore(sc);
750f32cf 270
08d4df41 271skip_hw_wakeup:
750f32cf
SM
272 mod_timer(&btcoex->period_timer,
273 jiffies + msecs_to_jiffies(btcoex->btcoex_period));
0fca65c1
S
274}
275
276/*
277 * Generic tsf based hw timer which configures weight
278 * registers to time slice between wlan and bt traffic
279 */
280static void ath_btcoex_no_stomp_timer(void *arg)
281{
282 struct ath_softc *sc = (struct ath_softc *)arg;
283 struct ath_hw *ah = sc->sc_ah;
284 struct ath_btcoex *btcoex = &sc->btcoex;
d99eeb87 285 struct ath_common *common = ath9k_hw_common(ah);
0fca65c1 286
d2182b69 287 ath_dbg(common, BTCOEX, "no stomp timer running\n");
0fca65c1 288
a039a993 289 ath9k_ps_wakeup(sc);
0fca65c1
S
290 spin_lock_bh(&btcoex->btcoex_lock);
291
e6930c4b 292 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW ||
750f32cf
SM
293 (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI) &&
294 test_bit(BT_OP_SCAN, &btcoex->op_flags)))
978f78bf 295 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
0fca65c1 296 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
978f78bf 297 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW);
0fca65c1 298
bc6d5c29 299 ath9k_hw_btcoex_enable(ah);
0fca65c1 300 spin_unlock_bh(&btcoex->btcoex_lock);
a039a993 301 ath9k_ps_restore(sc);
0fca65c1
S
302}
303
df198b17 304static int ath_init_btcoex_timer(struct ath_softc *sc)
0fca65c1
S
305{
306 struct ath_btcoex *btcoex = &sc->btcoex;
307
dfd0587a
RM
308 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD;
309 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 1000 *
0fca65c1 310 btcoex->btcoex_period / 100;
dfd0587a 311 btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 1000 *
58da1318 312 btcoex->btcoex_period / 100;
0fca65c1
S
313
314 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
315 (unsigned long) sc);
316
317 spin_lock_init(&btcoex->btcoex_lock);
318
319 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
320 ath_btcoex_no_stomp_timer,
321 ath_btcoex_no_stomp_timer,
322 (void *) sc, AR_FIRST_NDP_TIMER);
323
324 if (!btcoex->no_stomp_timer)
325 return -ENOMEM;
326
327 return 0;
328}
329
330/*
331 * (Re)start btcoex timers
332 */
333void ath9k_btcoex_timer_resume(struct ath_softc *sc)
334{
335 struct ath_btcoex *btcoex = &sc->btcoex;
336 struct ath_hw *ah = sc->sc_ah;
337
d2182b69 338 ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n");
0fca65c1
S
339
340 /* make sure duty cycle timer is also stopped when resuming */
5418b0f0 341 if (btcoex->hw_timer_enabled) {
0fca65c1 342 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
5418b0f0
MSS
343 btcoex->hw_timer_enabled = false;
344 }
0fca65c1
S
345
346 btcoex->bt_priority_cnt = 0;
347 btcoex->bt_priority_time = jiffies;
c11216d1
MSS
348 clear_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags);
349 clear_bit(BT_OP_SCAN, &btcoex->op_flags);
0fca65c1
S
350
351 mod_timer(&btcoex->period_timer, jiffies);
352}
353
354
355/*
356 * Pause btcoex timer and bt duty cycle timer
357 */
358void ath9k_btcoex_timer_pause(struct ath_softc *sc)
359{
360 struct ath_btcoex *btcoex = &sc->btcoex;
361 struct ath_hw *ah = sc->sc_ah;
362
363 del_timer_sync(&btcoex->period_timer);
364
5418b0f0 365 if (btcoex->hw_timer_enabled) {
0fca65c1 366 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
5418b0f0
MSS
367 btcoex->hw_timer_enabled = false;
368 }
0fca65c1 369}
5908120f 370
08d4df41
RM
371void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
372{
373 struct ath_btcoex *btcoex = &sc->btcoex;
374
5418b0f0 375 if (btcoex->hw_timer_enabled) {
5d9b6f26 376 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
5418b0f0
MSS
377 btcoex->hw_timer_enabled = false;
378 }
08d4df41
RM
379}
380
c0ac53fa
SM
381u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen)
382{
e6930c4b 383 struct ath_btcoex *btcoex = &sc->btcoex;
c0ac53fa
SM
384 struct ath_mci_profile *mci = &sc->btcoex.mci;
385 u16 aggr_limit = 0;
386
387 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit)
388 aggr_limit = (max_4ms_framelen * mci->aggr_limit) >> 4;
e6930c4b 389 else if (test_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags))
c0ac53fa
SM
390 aggr_limit = min((max_4ms_framelen * 3) / 8,
391 (u32)ATH_AMPDU_LIMIT_MAX);
392
393 return aggr_limit;
394}
395
56ca0dba
SM
396void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status)
397{
398 struct ath_hw *ah = sc->sc_ah;
399
400 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
401 if (status & ATH9K_INT_GENTIMER)
402 ath_gen_timer_isr(sc->sc_ah);
403
9a15858f 404 if (status & ATH9K_INT_MCI)
56ca0dba
SM
405 ath_mci_intr(sc);
406}
407
df198b17
SM
408void ath9k_start_btcoex(struct ath_softc *sc)
409{
410 struct ath_hw *ah = sc->sc_ah;
411
412 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
413 !ah->btcoex_hw.enabled) {
414 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI))
415 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
5160b46f
SM
416 AR_STOMP_LOW_WLAN_WGHT, 0);
417 else
418 ath9k_hw_btcoex_set_weight(ah, 0, 0,
419 ATH_BTCOEX_STOMP_NONE);
df198b17
SM
420 ath9k_hw_btcoex_enable(ah);
421
422 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
423 ath9k_btcoex_timer_resume(sc);
424 }
425}
426
427void ath9k_stop_btcoex(struct ath_softc *sc)
428{
429 struct ath_hw *ah = sc->sc_ah;
430
431 if (ah->btcoex_hw.enabled &&
432 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
df198b17
SM
433 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
434 ath9k_btcoex_timer_pause(sc);
c32cdbd8 435 ath9k_hw_btcoex_disable(ah);
6a73f507 436 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
bff2ec2b 437 ath_mci_flush_profile(&sc->btcoex.mci);
df198b17
SM
438 }
439}
440
5908120f
SM
441void ath9k_deinit_btcoex(struct ath_softc *sc)
442{
dd89f05a
MSS
443 struct ath_hw *ah = sc->sc_ah;
444
5908120f
SM
445 if ((sc->btcoex.no_stomp_timer) &&
446 ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE)
447 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
448
dd89f05a 449 if (ath9k_hw_mci_is_enabled(ah))
5908120f
SM
450 ath_mci_cleanup(sc);
451}
452
453int ath9k_init_btcoex(struct ath_softc *sc)
454{
455 struct ath_txq *txq;
456 struct ath_hw *ah = sc->sc_ah;
457 int r;
458
d68475de
SM
459 ath9k_hw_btcoex_init_scheme(ah);
460
5908120f
SM
461 switch (ath9k_hw_get_btcoex_scheme(sc->sc_ah)) {
462 case ATH_BTCOEX_CFG_NONE:
463 break;
464 case ATH_BTCOEX_CFG_2WIRE:
465 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
466 break;
467 case ATH_BTCOEX_CFG_3WIRE:
468 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
469 r = ath_init_btcoex_timer(sc);
470 if (r)
471 return -1;
472 txq = sc->tx.txq_map[WME_AC_BE];
473 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
474 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
81294489 475 if (ath9k_hw_mci_is_enabled(ah)) {
0466e254
RM
476 sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
477 INIT_LIST_HEAD(&sc->btcoex.mci.info);
5908120f 478
0466e254
RM
479 r = ath_mci_setup(sc);
480 if (r)
481 return r;
5908120f 482
0466e254
RM
483 ath9k_hw_btcoex_init_mci(ah);
484 }
5908120f
SM
485
486 break;
487 default:
488 WARN_ON(1);
489 break;
490 }
491
492 return 0;
493}
4daa7760
SM
494
495#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
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