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Merge tag 'efi-urgent' into x86/urgent
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / htc_drv_init.c
CommitLineData
fb9987d0 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
fb9987d0
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
516304b0
JP		 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
fb9987d0
S		 19#include "htc.h"
20
21MODULE_AUTHOR("Atheros Communications");
22MODULE_LICENSE("Dual BSD/GPL");
23MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
24
25static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
26module_param_named(debug, ath9k_debug, uint, 0);
27MODULE_PARM_DESC(debug, "Debugging mask");
28
e1572c5e
S		 29int htc_modparam_nohwcrypt;
30module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
fb9987d0
S		 31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
7f34778e
MSS		 33static int ath9k_htc_btcoex_enable;
34module_param_named(btcoex_enable, ath9k_htc_btcoex_enable, int, 0444);
35MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
36
fb9987d0
S		 37#define CHAN2G(_freq, _idx) { \
38 .center_freq = (_freq), \
39 .hw_value = (_idx), \
40 .max_power = 20, \
41}
42
ea46e644
S		 43#define CHAN5G(_freq, _idx) { \
44 .band = IEEE80211_BAND_5GHZ, \
45 .center_freq = (_freq), \
46 .hw_value = (_idx), \
47 .max_power = 20, \
48}
49
fb9987d0
S		 50static struct ieee80211_channel ath9k_2ghz_channels[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
ea46e644
S		 67static struct ieee80211_channel ath9k_5ghz_channels[] = {
68 /* _We_ call this UNII 1 */
69 CHAN5G(5180, 14), /* Channel 36 */
70 CHAN5G(5200, 15), /* Channel 40 */
71 CHAN5G(5220, 16), /* Channel 44 */
72 CHAN5G(5240, 17), /* Channel 48 */
73 /* _We_ call this UNII 2 */
74 CHAN5G(5260, 18), /* Channel 52 */
75 CHAN5G(5280, 19), /* Channel 56 */
76 CHAN5G(5300, 20), /* Channel 60 */
77 CHAN5G(5320, 21), /* Channel 64 */
78 /* _We_ call this "Middle band" */
79 CHAN5G(5500, 22), /* Channel 100 */
80 CHAN5G(5520, 23), /* Channel 104 */
81 CHAN5G(5540, 24), /* Channel 108 */
82 CHAN5G(5560, 25), /* Channel 112 */
83 CHAN5G(5580, 26), /* Channel 116 */
84 CHAN5G(5600, 27), /* Channel 120 */
85 CHAN5G(5620, 28), /* Channel 124 */
86 CHAN5G(5640, 29), /* Channel 128 */
87 CHAN5G(5660, 30), /* Channel 132 */
88 CHAN5G(5680, 31), /* Channel 136 */
89 CHAN5G(5700, 32), /* Channel 140 */
90 /* _We_ call this UNII 3 */
91 CHAN5G(5745, 33), /* Channel 149 */
92 CHAN5G(5765, 34), /* Channel 153 */
93 CHAN5G(5785, 35), /* Channel 157 */
94 CHAN5G(5805, 36), /* Channel 161 */
95 CHAN5G(5825, 37), /* Channel 165 */
96};
97
fb9987d0
S		 98/* Atheros hardware rate code addition for short premble */
99#define SHPCHECK(__hw_rate, __flags) \
100 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
101
102#define RATE(_bitrate, _hw_rate, _flags) { \
103 .bitrate = (_bitrate), \
104 .flags = (_flags), \
105 .hw_value = (_hw_rate), \
106 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
107}
108
109static struct ieee80211_rate ath9k_legacy_rates[] = {
110 RATE(10, 0x1b, 0),
111 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
112 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
113 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
114 RATE(60, 0x0b, 0),
115 RATE(90, 0x0f, 0),
116 RATE(120, 0x0a, 0),
117 RATE(180, 0x0e, 0),
118 RATE(240, 0x09, 0),
119 RATE(360, 0x0d, 0),
120 RATE(480, 0x08, 0),
121 RATE(540, 0x0c, 0),
122};
123
d244f21e
SM		 124#ifdef CONFIG_MAC80211_LEDS
125static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
126 { .throughput = 0 * 1024, .blink_time = 334 },
127 { .throughput = 1 * 1024, .blink_time = 260 },
128 { .throughput = 5 * 1024, .blink_time = 220 },
129 { .throughput = 10 * 1024, .blink_time = 190 },
130 { .throughput = 20 * 1024, .blink_time = 170 },
131 { .throughput = 50 * 1024, .blink_time = 150 },
132 { .throughput = 70 * 1024, .blink_time = 130 },
133 { .throughput = 100 * 1024, .blink_time = 110 },
134 { .throughput = 200 * 1024, .blink_time = 80 },
135 { .throughput = 300 * 1024, .blink_time = 50 },
136};
137#endif
138
fb9987d0
S		 139static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
140{
141 int time_left;
142
d8c49ffb
SM		 143 if (atomic_read(&priv->htc->tgt_ready) > 0) {
144 atomic_dec(&priv->htc->tgt_ready);
145 return 0;
146 }
147
fb9987d0
S		 148 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
149 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
150 if (!time_left) {
151 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
152 return -ETIMEDOUT;
153 }
154
d8c49ffb
SM		 155 atomic_dec(&priv->htc->tgt_ready);
156
fb9987d0
S		 157 return 0;
158}
159
160static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
161{
fb9987d0 162 ath9k_hw_deinit(priv->ah);
fb9987d0
S		 163 kfree(priv->ah);
164 priv->ah = NULL;
165}
166
167static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
168{
169 struct ieee80211_hw *hw = priv->hw;
170
171 wiphy_rfkill_stop_polling(hw->wiphy);
172 ath9k_deinit_leds(priv);
173 ieee80211_unregister_hw(hw);
174 ath9k_rx_cleanup(priv);
175 ath9k_tx_cleanup(priv);
176 ath9k_deinit_priv(priv);
177}
178
179static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
180 u16 service_id,
181 void (*tx) (void *,
182 struct sk_buff *,
183 enum htc_endpoint_id,
184 bool txok),
185 enum htc_endpoint_id *ep_id)
186{
187 struct htc_service_connreq req;
188
189 memset(&req, 0, sizeof(struct htc_service_connreq));
190
191 req.service_id = service_id;
192 req.ep_callbacks.priv = priv;
193 req.ep_callbacks.rx = ath9k_htc_rxep;
194 req.ep_callbacks.tx = tx;
195
196 return htc_connect_service(priv->htc, &req, ep_id);
197}
198
fa6e15e0
RM		 199static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
200 u32 drv_info)
fb9987d0
S		 201{
202 int ret;
203
204 /* WMI CMD*/
205 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
206 if (ret)
207 goto err;
208
209 /* Beacon */
9c6dda4e 210 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
fb9987d0
S		 211 &priv->beacon_ep);
212 if (ret)
213 goto err;
214
215 /* CAB */
216 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
217 &priv->cab_ep);
218 if (ret)
219 goto err;
220
221
222 /* UAPSD */
223 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
224 &priv->uapsd_ep);
225 if (ret)
226 goto err;
227
228 /* MGMT */
229 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
230 &priv->mgmt_ep);
231 if (ret)
232 goto err;
233
234 /* DATA BE */
235 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
236 &priv->data_be_ep);
237 if (ret)
238 goto err;
239
240 /* DATA BK */
241 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
242 &priv->data_bk_ep);
243 if (ret)
244 goto err;
245
246 /* DATA VI */
247 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
248 &priv->data_vi_ep);
249 if (ret)
250 goto err;
251
252 /* DATA VO */
253 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
254 &priv->data_vo_ep);
255 if (ret)
256 goto err;
257
6267dc70
S		 258 /*
259 * Setup required credits before initializing HTC.
260 * This is a bit hacky, but, since queuing is done in
261 * the HIF layer, shouldn't matter much.
262 */
263
0b5ead91 264 if (IS_AR7010_DEVICE(drv_info))
d108e8b9 265 priv->htc->credits = 45;
fa6e15e0 266 else
4e63f768 267 priv->htc->credits = 33;
6267dc70 268
fb9987d0
S		 269 ret = htc_init(priv->htc);
270 if (ret)
271 goto err;
272
6267dc70
S		 273 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
274 priv->htc->credits);
275
fb9987d0
S		 276 return 0;
277
278err:
279 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
280 return ret;
281}
282
0c0280bd
LR		 283static void ath9k_reg_notifier(struct wiphy *wiphy,
284 struct regulatory_request *request)
fb9987d0
S		 285{
286 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
287 struct ath9k_htc_priv *priv = hw->priv;
288
0c0280bd
LR		 289 ath_reg_notifier_apply(wiphy, request,
290 ath9k_hw_regulatory(priv->ah));
fb9987d0
S		 291}
292
4a22fe10 293static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
fb9987d0
S		 294{
295 struct ath_hw *ah = (struct ath_hw *) hw_priv;
296 struct ath_common *common = ath9k_hw_common(ah);
297 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
298 __be32 val, reg = cpu_to_be32(reg_offset);
299 int r;
300
301 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
302 (u8 *) &reg, sizeof(reg),
303 (u8 *) &val, sizeof(val),
304 100);
305 if (unlikely(r)) {
d2182b69 306 ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
226afe68 307 reg_offset, r);
fb9987d0
S		 308 return -EIO;
309 }
310
311 return be32_to_cpu(val);
312}
313
09a525d3
SM		 314static void ath9k_multi_regread(void *hw_priv, u32 *addr,
315 u32 *val, u16 count)
316{
317 struct ath_hw *ah = (struct ath_hw *) hw_priv;
318 struct ath_common *common = ath9k_hw_common(ah);
319 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
320 __be32 tmpaddr[8];
321 __be32 tmpval[8];
322 int i, ret;
323
324 for (i = 0; i < count; i++) {
325 tmpaddr[i] = cpu_to_be32(addr[i]);
326 }
327
328 ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
329 (u8 *)tmpaddr , sizeof(u32) * count,
330 (u8 *)tmpval, sizeof(u32) * count,
331 100);
332 if (unlikely(ret)) {
d2182b69 333 ath_dbg(common, WMI,
09a525d3
SM		 334 "Multiple REGISTER READ FAILED (count: %d)\n", count);
335 }
336
337 for (i = 0; i < count; i++) {
338 val[i] = be32_to_cpu(tmpval[i]);
339 }
340}
341
4a22fe10 342static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
fb9987d0
S		 343{
344 struct ath_hw *ah = (struct ath_hw *) hw_priv;
345 struct ath_common *common = ath9k_hw_common(ah);
346 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
07b2fa5a 347 const __be32 buf[2] = {
fb9987d0
S		 348 cpu_to_be32(reg_offset),
349 cpu_to_be32(val),
350 };
351 int r;
352
353 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
354 (u8 *) &buf, sizeof(buf),
355 (u8 *) &val, sizeof(val),
356 100);
357 if (unlikely(r)) {
d2182b69 358 ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n",
226afe68 359 reg_offset, r);
fb9987d0
S		 360 }
361}
362
4a22fe10
S		 363static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
364{
365 struct ath_hw *ah = (struct ath_hw *) hw_priv;
366 struct ath_common *common = ath9k_hw_common(ah);
367 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
368 u32 rsp_status;
369 int r;
370
371 mutex_lock(&priv->wmi->multi_write_mutex);
372
373 /* Store the register/value */
374 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
375 cpu_to_be32(reg_offset);
376 priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
377 cpu_to_be32(val);
378
379 priv->wmi->multi_write_idx++;
380
381 /* If the buffer is full, send it out. */
382 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
383 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
384 (u8 *) &priv->wmi->multi_write,
385 sizeof(struct register_write) * priv->wmi->multi_write_idx,
386 (u8 *) &rsp_status, sizeof(rsp_status),
387 100);
388 if (unlikely(r)) {
d2182b69 389 ath_dbg(common, WMI,
226afe68
JP		 390 "REGISTER WRITE FAILED, multi len: %d\n",
391 priv->wmi->multi_write_idx);
4a22fe10
S		 392 }
393 priv->wmi->multi_write_idx = 0;
394 }
395
396 mutex_unlock(&priv->wmi->multi_write_mutex);
397}
398
399static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
400{
401 struct ath_hw *ah = (struct ath_hw *) hw_priv;
402 struct ath_common *common = ath9k_hw_common(ah);
403 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
404
405 if (atomic_read(&priv->wmi->mwrite_cnt))
406 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
407 else
408 ath9k_regwrite_single(hw_priv, val, reg_offset);
409}
410
411static void ath9k_enable_regwrite_buffer(void *hw_priv)
412{
413 struct ath_hw *ah = (struct ath_hw *) hw_priv;
414 struct ath_common *common = ath9k_hw_common(ah);
415 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
416
417 atomic_inc(&priv->wmi->mwrite_cnt);
418}
419
4a22fe10
S		 420static void ath9k_regwrite_flush(void *hw_priv)
421{
422 struct ath_hw *ah = (struct ath_hw *) hw_priv;
423 struct ath_common *common = ath9k_hw_common(ah);
424 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
425 u32 rsp_status;
426 int r;
427
435c1610
FF		 428 atomic_dec(&priv->wmi->mwrite_cnt);
429
4a22fe10
S		 430 mutex_lock(&priv->wmi->multi_write_mutex);
431
432 if (priv->wmi->multi_write_idx) {
433 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
434 (u8 *) &priv->wmi->multi_write,
435 sizeof(struct register_write) * priv->wmi->multi_write_idx,
436 (u8 *) &rsp_status, sizeof(rsp_status),
437 100);
438 if (unlikely(r)) {
d2182b69 439 ath_dbg(common, WMI,
226afe68
JP		 440 "REGISTER WRITE FAILED, multi len: %d\n",
441 priv->wmi->multi_write_idx);
4a22fe10
S		 442 }
443 priv->wmi->multi_write_idx = 0;
444 }
445
446 mutex_unlock(&priv->wmi->multi_write_mutex);
447}
448
845e03c9
FF		 449static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
450{
451 u32 val;
452
453 val = ath9k_regread(hw_priv, reg_offset);
454 val &= ~clr;
455 val |= set;
456 ath9k_regwrite(hw_priv, val, reg_offset);
457 return val;
458}
459
fb9987d0
S		 460static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
461{
462 *csz = L1_CACHE_BYTES >> 2;
463}
464
465static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
466{
467 struct ath_hw *ah = (struct ath_hw *) common->ah;
468
469 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
470
471 if (!ath9k_hw_wait(ah,
472 AR_EEPROM_STATUS_DATA,
473 AR_EEPROM_STATUS_DATA_BUSY |
474 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
475 AH_WAIT_TIMEOUT))
476 return false;
477
478 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
479 AR_EEPROM_STATUS_DATA_VAL);
480
481 return true;
482}
483
484static const struct ath_bus_ops ath9k_usb_bus_ops = {
497ad9ad 485 .ath_bus_type = ATH_USB,
fb9987d0
S		 486 .read_cachesize = ath_usb_read_cachesize,
487 .eeprom_read = ath_usb_eeprom_read,
488};
489
490static void setup_ht_cap(struct ath9k_htc_priv *priv,
491 struct ieee80211_sta_ht_cap *ht_info)
492{
6debecad
S		 493 struct ath_common *common = ath9k_hw_common(priv->ah);
494 u8 tx_streams, rx_streams;
495 int i;
496
fb9987d0
S		 497 ht_info->ht_supported = true;
498 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
499 IEEE80211_HT_CAP_SM_PS |
500 IEEE80211_HT_CAP_SGI_40 |
501 IEEE80211_HT_CAP_DSSSCCK40;
502
b4dec5e8
S		 503 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
504 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
505
17525f96
S		 506 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
507
fb9987d0
S		 508 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
509 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
510
511 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
6debecad
S		 512
513 /* ath9k_htc supports only 1 or 2 stream devices */
82b2d334
FF		 514 tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2);
515 rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2);
6debecad 516
d2182b69 517 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
226afe68 518 tx_streams, rx_streams);
6debecad 519
a226c3d9
OR		 520 if (tx_streams >= 2)
521 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
522
6debecad
S		 523 if (tx_streams != rx_streams) {
524 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
525 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
526 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
527 }
528
529 for (i = 0; i < rx_streams; i++)
530 ht_info->mcs.rx_mask[i] = 0xff;
531
fb9987d0
S		 532 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
533}
534
535static int ath9k_init_queues(struct ath9k_htc_priv *priv)
536{
537 struct ath_common *common = ath9k_hw_common(priv->ah);
538 int i;
539
540 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
541 priv->hwq_map[i] = -1;
542
ca74b83b
S		 543 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
544 if (priv->beaconq == -1) {
3800276a 545 ath_err(common, "Unable to setup BEACON xmit queue\n");
ca74b83b
S		 546 goto err;
547 }
548
549 priv->cabq = ath9k_htc_cabq_setup(priv);
550 if (priv->cabq == -1) {
3800276a 551 ath_err(common, "Unable to setup CAB xmit queue\n");
ca74b83b
S		 552 goto err;
553 }
554
bea843c7 555 if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BE)) {
3800276a 556 ath_err(common, "Unable to setup xmit queue for BE traffic\n");
fb9987d0
S		 557 goto err;
558 }
559
bea843c7 560 if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BK)) {
3800276a 561 ath_err(common, "Unable to setup xmit queue for BK traffic\n");
fb9987d0
S		 562 goto err;
563 }
bea843c7 564 if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VI)) {
3800276a 565 ath_err(common, "Unable to setup xmit queue for VI traffic\n");
fb9987d0
S		 566 goto err;
567 }
bea843c7 568 if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VO)) {
3800276a 569 ath_err(common, "Unable to setup xmit queue for VO traffic\n");
fb9987d0
S		 570 goto err;
571 }
572
573 return 0;
574
575err:
576 return -EINVAL;
577}
578
fb9987d0
S		 579static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
580{
d4659912 581 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
fb9987d0
S		 582 priv->sbands[IEEE80211_BAND_2GHZ].channels =
583 ath9k_2ghz_channels;
584 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
585 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
586 ARRAY_SIZE(ath9k_2ghz_channels);
587 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
588 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
589 ARRAY_SIZE(ath9k_legacy_rates);
590 }
ea46e644 591
d4659912 592 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
ea46e644
S		 593 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
594 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
595 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
596 ARRAY_SIZE(ath9k_5ghz_channels);
597 priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
598 ath9k_legacy_rates + 4;
599 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
600 ARRAY_SIZE(ath9k_legacy_rates) - 4;
601 }
fb9987d0
S		 602}
603
604static void ath9k_init_misc(struct ath9k_htc_priv *priv)
605{
606 struct ath_common *common = ath9k_hw_common(priv->ah);
607
364734fa 608 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
fb9987d0 609
9f01a84e 610 priv->ah->opmode = NL80211_IFTYPE_STATION;
fb9987d0
S		 611}
612
21cb9879 613static int ath9k_init_priv(struct ath9k_htc_priv *priv,
fa6e15e0
RM		 614 u16 devid, char *product,
615 u32 drv_info)
fb9987d0
S		 616{
617 struct ath_hw *ah = NULL;
618 struct ath_common *common;
832f6a18 619 int i, ret = 0, csz = 0;
fb9987d0 620
d8a2c51c 621 set_bit(OP_INVALID, &priv->op_flags);
fb9987d0
S		 622
623 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
624 if (!ah)
625 return -ENOMEM;
626
627 ah->hw_version.devid = devid;
0b5ead91 628 ah->hw_version.usbdev = drv_info;
f8afa42b 629 ah->ah_flags |= AH_USE_EEPROM;
f9f84e96
FF		 630 ah->reg_ops.read = ath9k_regread;
631 ah->reg_ops.multi_read = ath9k_multi_regread;
632 ah->reg_ops.write = ath9k_regwrite;
633 ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
634 ah->reg_ops.write_flush = ath9k_regwrite_flush;
845e03c9 635 ah->reg_ops.rmw = ath9k_reg_rmw;
fb9987d0
S		 636 priv->ah = ah;
637
638 common = ath9k_hw_common(ah);
f9f84e96 639 common->ops = &ah->reg_ops;
fb9987d0
S		 640 common->bus_ops = &ath9k_usb_bus_ops;
641 common->ah = ah;
642 common->hw = priv->hw;
643 common->priv = priv;
644 common->debug_mask = ath9k_debug;
7f34778e 645 common->btcoex_enabled = ath9k_htc_btcoex_enable == 1;
fb9987d0 646
fb9987d0 647 spin_lock_init(&priv->beacon_lock);
658ef04f 648 spin_lock_init(&priv->tx.tx_lock);
fb9987d0 649 mutex_init(&priv->mutex);
bde748a4 650 mutex_init(&priv->htc_pm_lock);
fb9987d0
S		 651 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
652 (unsigned long)priv);
27876a29 653 tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
73908674 654 (unsigned long)priv);
a236254c 655 INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
bde748a4 656 INIT_WORK(&priv->ps_work, ath9k_ps_work);
73908674 657 INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
859c3ca1
SM		 658 setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
659 (unsigned long)priv);
fb9987d0
S		 660
661 /*
662 * Cache line size is used to size and align various
663 * structures used to communicate with the hardware.
664 */
665 ath_read_cachesize(common, &csz);
666 common->cachelsz = csz << 2; /* convert to bytes */
667
668 ret = ath9k_hw_init(ah);
669 if (ret) {
3800276a
JP		 670 ath_err(common,
671 "Unable to initialize hardware; initialization status: %d\n",
672 ret);
fb9987d0
S		 673 goto err_hw;
674 }
675
fb9987d0
S		 676 ret = ath9k_init_queues(priv);
677 if (ret)
678 goto err_queues;
679
832f6a18
SM		 680 for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
681 priv->cur_beacon_conf.bslot[i] = NULL;
682
f82b4bde 683 ath9k_cmn_init_crypto(ah);
fb9987d0
S		 684 ath9k_init_channels_rates(priv);
685 ath9k_init_misc(priv);
cee5341d 686 ath9k_htc_init_btcoex(priv, product);
21cb9879 687
fb9987d0
S		 688 return 0;
689
690err_queues:
fb9987d0
S		 691 ath9k_hw_deinit(ah);
692err_hw:
693
694 kfree(ah);
695 priv->ah = NULL;
696
697 return ret;
698}
699
8b0b6be5
MSS		 700static const struct ieee80211_iface_limit if_limits[] = {
701 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
702 BIT(NL80211_IFTYPE_P2P_CLIENT) },
703 { .max = 2, .types = BIT(NL80211_IFTYPE_AP) |
0c9acaa8
TP		 704#ifdef CONFIG_MAC80211_MESH
705 BIT(NL80211_IFTYPE_MESH_POINT) |
706#endif
707 BIT(NL80211_IFTYPE_P2P_GO) },
8b0b6be5
MSS		 708};
709
710static const struct ieee80211_iface_combination if_comb = {
711 .limits = if_limits,
712 .n_limits = ARRAY_SIZE(if_limits),
713 .max_interfaces = 2,
714 .num_different_channels = 1,
715};
716
fb9987d0
S		 717static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
718 struct ieee80211_hw *hw)
719{
720 struct ath_common *common = ath9k_hw_common(priv->ah);
156652bb 721 struct base_eep_header *pBase;
fb9987d0
S		 722
723 hw->flags = IEEE80211_HW_SIGNAL_DBM |
724 IEEE80211_HW_AMPDU_AGGREGATION |
725 IEEE80211_HW_SPECTRUM_MGMT |
32fbccaf 726 IEEE80211_HW_HAS_RATE_CONTROL |
bde748a4
VN		 727 IEEE80211_HW_RX_INCLUDES_FCS |
728 IEEE80211_HW_SUPPORTS_PS |
7d547eb4 729 IEEE80211_HW_PS_NULLFUNC_STACK |
8ae2e12f 730 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
bd4a85ee 731 IEEE80211_HW_MFP_CAPABLE |
7d547eb4 732 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
fb9987d0
S		 733
734 hw->wiphy->interface_modes =
735 BIT(NL80211_IFTYPE_STATION) |
09d5b94d
SM		 736 BIT(NL80211_IFTYPE_ADHOC) |
737 BIT(NL80211_IFTYPE_AP) |
738 BIT(NL80211_IFTYPE_P2P_GO) |
594e65b6
JC		 739 BIT(NL80211_IFTYPE_P2P_CLIENT) |
740 BIT(NL80211_IFTYPE_MESH_POINT);
fb9987d0 741
8b0b6be5
MSS		 742 hw->wiphy->iface_combinations = &if_comb;
743 hw->wiphy->n_iface_combinations = 1;
744
bde748a4
VN		 745 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
746
81ddbb5c
JB		 747 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN |
748 WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
d7d312ca 749
fb9987d0 750 hw->queues = 4;
fb1c078e 751 hw->max_listen_interval = 1;
3a0593ef 752
fb9987d0
S		 753 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
754 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
755
756 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
757 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
758 sizeof(struct htc_frame_hdr) + 4;
759
d4659912 760 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
fb9987d0
S		 761 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
762 &priv->sbands[IEEE80211_BAND_2GHZ];
d4659912 763 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
ea46e644
S		 764 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
765 &priv->sbands[IEEE80211_BAND_5GHZ];
fb9987d0
S		 766
767 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
d4659912 768 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
fb9987d0
S		 769 setup_ht_cap(priv,
770 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
d4659912 771 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
ea46e644
S		 772 setup_ht_cap(priv,
773 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
fb9987d0
S		 774 }
775
156652bb
BG		 776 pBase = ath9k_htc_get_eeprom_base(priv);
777 if (pBase) {
778 hw->wiphy->available_antennas_rx = pBase->rxMask;
779 hw->wiphy->available_antennas_tx = pBase->txMask;
780 }
781
fb9987d0
S		 782 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
783}
784
29bbfb24
SM		 785static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
786{
787 struct ieee80211_hw *hw = priv->hw;
788 struct wmi_fw_version cmd_rsp;
789 int ret;
790
791 memset(&cmd_rsp, 0, sizeof(cmd_rsp));
792
793 WMI_CMD(WMI_GET_FW_VERSION);
794 if (ret)
795 return -EINVAL;
796
797 priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
798 priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
799
81135548 800 snprintf(hw->wiphy->fw_version, sizeof(hw->wiphy->fw_version), "%d.%d",
29bbfb24
SM		 801 priv->fw_version_major,
802 priv->fw_version_minor);
803
804 dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
805 priv->fw_version_major,
806 priv->fw_version_minor);
807
3a0593ef
SM		 808 /*
809 * Check if the available FW matches the driver's
810 * required version.
811 */
812 if (priv->fw_version_major != MAJOR_VERSION_REQ ||
319e7bd9 813 priv->fw_version_minor < MINOR_VERSION_REQ) {
3a0593ef
SM		 814 dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
815 MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
816 return -EINVAL;
817 }
818
29bbfb24
SM		 819 return 0;
820}
821
21cb9879 822static int ath9k_init_device(struct ath9k_htc_priv *priv,
fa6e15e0 823 u16 devid, char *product, u32 drv_info)
fb9987d0
S		 824{
825 struct ieee80211_hw *hw = priv->hw;
826 struct ath_common *common;
827 struct ath_hw *ah;
828 int error = 0;
829 struct ath_regulatory *reg;
3e3f1d19 830 char hw_name[64];
fb9987d0
S		 831
832 /* Bring up device */
fa6e15e0 833 error = ath9k_init_priv(priv, devid, product, drv_info);
fb9987d0
S		 834 if (error != 0)
835 goto err_init;
836
837 ah = priv->ah;
838 common = ath9k_hw_common(ah);
839 ath9k_set_hw_capab(priv, hw);
840
29bbfb24
SM		 841 error = ath9k_init_firmware_version(priv);
842 if (error != 0)
843 goto err_fw;
844
fb9987d0
S		 845 /* Initialize regulatory */
846 error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
847 ath9k_reg_notifier);
848 if (error)
849 goto err_regd;
850
851 reg = &common->regulatory;
852
853 /* Setup TX */
854 error = ath9k_tx_init(priv);
855 if (error != 0)
856 goto err_tx;
857
858 /* Setup RX */
859 error = ath9k_rx_init(priv);
860 if (error != 0)
861 goto err_rx;
862
dc2a87f5 863 ath9k_hw_disable(priv->ah);
d244f21e
SM		 864#ifdef CONFIG_MAC80211_LEDS
865 /* must be initialized before ieee80211_register_hw */
866 priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
867 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
868 ARRAY_SIZE(ath9k_htc_tpt_blink));
869#endif
870
fb9987d0
S		 871 /* Register with mac80211 */
872 error = ieee80211_register_hw(hw);
873 if (error)
874 goto err_register;
875
876 /* Handle world regulatory */
877 if (!ath_is_world_regd(reg)) {
878 error = regulatory_hint(hw->wiphy, reg->alpha2);
879 if (error)
880 goto err_world;
881 }
882
e5facc75
RM		 883 error = ath9k_htc_init_debug(priv->ah);
884 if (error) {
885 ath_err(common, "Unable to create debugfs files\n");
886 goto err_world;
887 }
888
d2182b69
JP		 889 ath_dbg(common, CONFIG,
890 "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n",
3e3f1d19
SM		 891 priv->wmi_cmd_ep,
892 priv->beacon_ep,
893 priv->cab_ep,
894 priv->uapsd_ep,
895 priv->mgmt_ep,
896 priv->data_be_ep,
897 priv->data_bk_ep,
898 priv->data_vi_ep,
899 priv->data_vo_ep);
900
901 ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
902 wiphy_info(hw->wiphy, "%s\n", hw_name);
903
fb9987d0
S		 904 ath9k_init_leds(priv);
905 ath9k_start_rfkill_poll(priv);
906
907 return 0;
908
909err_world:
910 ieee80211_unregister_hw(hw);
911err_register:
912 ath9k_rx_cleanup(priv);
913err_rx:
914 ath9k_tx_cleanup(priv);
915err_tx:
916 /* Nothing */
917err_regd:
29bbfb24
SM		 918 /* Nothing */
919err_fw:
fb9987d0
S		 920 ath9k_deinit_priv(priv);
921err_init:
922 return error;
923}
924
925int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
fa6e15e0 926 u16 devid, char *product, u32 drv_info)
fb9987d0
S		 927{
928 struct ieee80211_hw *hw;
929 struct ath9k_htc_priv *priv;
930 int ret;
931
932 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
933 if (!hw)
934 return -ENOMEM;
935
936 priv = hw->priv;
937 priv->hw = hw;
938 priv->htc = htc_handle;
939 priv->dev = dev;
940 htc_handle->drv_priv = priv;
941 SET_IEEE80211_DEV(hw, priv->dev);
942
943 ret = ath9k_htc_wait_for_target(priv);
944 if (ret)
945 goto err_free;
946
947 priv->wmi = ath9k_init_wmi(priv);
948 if (!priv->wmi) {
949 ret = -EINVAL;
950 goto err_free;
951 }
952
fa6e15e0 953 ret = ath9k_init_htc_services(priv, devid, drv_info);
fb9987d0
S		 954 if (ret)
955 goto err_init;
956
fa6e15e0 957 ret = ath9k_init_device(priv, devid, product, drv_info);
fb9987d0
S		 958 if (ret)
959 goto err_init;
960
961 return 0;
962
963err_init:
964 ath9k_deinit_wmi(priv);
965err_free:
966 ieee80211_free_hw(hw);
967 return ret;
968}
969
970void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
971{
972 if (htc_handle->drv_priv) {
a3be14b7
S		 973
974 /* Check if the device has been yanked out. */
975 if (hotunplug)
97dcec57 976 htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
a3be14b7 977
fb9987d0
S		 978 ath9k_deinit_device(htc_handle->drv_priv);
979 ath9k_deinit_wmi(htc_handle->drv_priv);
980 ieee80211_free_hw(htc_handle->drv_priv->hw);
981 }
982}
983
984#ifdef CONFIG_PM
f933ebed
SM		 985
986void ath9k_htc_suspend(struct htc_target *htc_handle)
987{
988 ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
989}
990
fb9987d0
S		 991int ath9k_htc_resume(struct htc_target *htc_handle)
992{
fa6e15e0 993 struct ath9k_htc_priv *priv = htc_handle->drv_priv;
fb9987d0
S		 994 int ret;
995
fa6e15e0 996 ret = ath9k_htc_wait_for_target(priv);
fb9987d0
S		 997 if (ret)
998 return ret;
999
fa6e15e0 1000 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
0b5ead91 1001 priv->ah->hw_version.usbdev);
1e51acaa
OR		 1002 ath9k_configure_leds(priv);
1003
fb9987d0
S		 1004 return ret;
1005}
1006#endif
1007
1008static int __init ath9k_htc_init(void)
1009{
e5facc75 1010 if (ath9k_hif_usb_init() < 0) {
516304b0 1011 pr_err("No USB devices found, driver not installed\n");
e5facc75 1012 return -ENODEV;
fb9987d0
S		 1013 }
1014
1015 return 0;
fb9987d0
S		 1016}
1017module_init(ath9k_htc_init);
1018
1019static void __exit ath9k_htc_exit(void)
1020{
1021 ath9k_hif_usb_exit();
516304b0 1022 pr_info("Driver unloaded\n");
fb9987d0
S		 1023}
1024module_exit(ath9k_htc_exit);
Linux kernel - Deliverables
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