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ath9k: optimize ath9k_flush
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
f078f209
LR		 20#include <asm/unaligned.h>
21
af03abec 22#include "hw.h"
d70357d5 23#include "hw-ops.h"
cfe8cba9 24#include "rc.h"
b622a720 25#include "ar9003_mac.h"
f4701b5a 26#include "ar9003_mci.h"
362cd03f 27#include "ar9003_phy.h"
462e58f2
BG		 28#include "debug.h"
29#include "ath9k.h"
f078f209 30
cbe61d8a 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 32
7322fd19
LR		 33MODULE_AUTHOR("Atheros Communications");
34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36MODULE_LICENSE("Dual BSD/GPL");
37
38static int __init ath9k_init(void)
39{
40 return 0;
41}
42module_init(ath9k_init);
43
44static void __exit ath9k_exit(void)
45{
46 return;
47}
48module_exit(ath9k_exit);
49
d70357d5
LR		 50/* Private hardware callbacks */
51
52static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
55}
56
64773964
LR		 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59{
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61}
62
991312d8
LR		 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64{
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69}
70
e36b27af
LR		 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72{
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78}
79
f1dc5600
S		 80/********************/
81/* Helper Functions */
82/********************/
f078f209 83
462e58f2
BG		 84#ifdef CONFIG_ATH9K_DEBUGFS
85
86void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
87{
88 struct ath_softc *sc = common->priv;
89 if (sync_cause)
90 sc->debug.stats.istats.sync_cause_all++;
91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
92 sc->debug.stats.istats.sync_rtc_irq++;
93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
94 sc->debug.stats.istats.sync_mac_irq++;
95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
96 sc->debug.stats.istats.eeprom_illegal_access++;
97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
98 sc->debug.stats.istats.apb_timeout++;
99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
100 sc->debug.stats.istats.pci_mode_conflict++;
101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
102 sc->debug.stats.istats.host1_fatal++;
103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
104 sc->debug.stats.istats.host1_perr++;
105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
106 sc->debug.stats.istats.trcv_fifo_perr++;
107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
108 sc->debug.stats.istats.radm_cpl_ep++;
109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
110 sc->debug.stats.istats.radm_cpl_dllp_abort++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
112 sc->debug.stats.istats.radm_cpl_tlp_abort++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
114 sc->debug.stats.istats.radm_cpl_ecrc_err++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
116 sc->debug.stats.istats.radm_cpl_timeout++;
117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
118 sc->debug.stats.istats.local_timeout++;
119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
120 sc->debug.stats.istats.pm_access++;
121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
122 sc->debug.stats.istats.mac_awake++;
123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
124 sc->debug.stats.istats.mac_asleep++;
125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
126 sc->debug.stats.istats.mac_sleep_access++;
127}
128#endif
129
130
dfdac8ac 131static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 132{
dfdac8ac 133 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 134 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 135 unsigned int clockrate;
cbe61d8a 136
087b6ff6
FF		 137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
139 clockrate = 117;
e4744ec7 140 else if (!chan) /* should really check for CCK instead */
dfdac8ac 141 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 142 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 146 else
dfdac8ac
FF		 147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
148
e4744ec7 149 if (IS_CHAN_HT40(chan))
dfdac8ac
FF		 150 clockrate *= 2;
151
906c7205 152 if (ah->curchan) {
e4744ec7 153 if (IS_CHAN_HALF_RATE(chan))
906c7205 154 clockrate /= 2;
e4744ec7 155 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 156 clockrate /= 4;
157 }
158
dfdac8ac 159 common->clockrate = clockrate;
f1dc5600
S		 160}
161
cbe61d8a 162static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 163{
dfdac8ac 164 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 165
dfdac8ac 166 return usecs * common->clockrate;
f1dc5600 167}
f078f209 168
0caa7b14 169bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 170{
171 int i;
172
0caa7b14
S		 173 BUG_ON(timeout < AH_TIME_QUANTUM);
174
175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 176 if ((REG_READ(ah, reg) & mask) == val)
177 return true;
178
179 udelay(AH_TIME_QUANTUM);
180 }
04bd4638 181
d2182b69 182 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
184 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 185
f1dc5600 186 return false;
f078f209 187}
7322fd19 188EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 189
7c5adc8d
FF		 190void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
191 int hw_delay)
192{
1a5e6326 193 hw_delay /= 10;
7c5adc8d
FF		 194
195 if (IS_CHAN_HALF_RATE(chan))
196 hw_delay *= 2;
197 else if (IS_CHAN_QUARTER_RATE(chan))
198 hw_delay *= 4;
199
200 udelay(hw_delay + BASE_ACTIVATE_DELAY);
201}
202
0166b4be 203void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 204 int column, unsigned int *writecnt)
205{
206 int r;
207
208 ENABLE_REGWRITE_BUFFER(ah);
209 for (r = 0; r < array->ia_rows; r++) {
210 REG_WRITE(ah, INI_RA(array, r, 0),
211 INI_RA(array, r, column));
212 DO_DELAY(*writecnt);
213 }
214 REGWRITE_BUFFER_FLUSH(ah);
215}
216
f078f209
LR		 217u32 ath9k_hw_reverse_bits(u32 val, u32 n)
218{
219 u32 retval;
220 int i;
221
222 for (i = 0, retval = 0; i < n; i++) {
223 retval = (retval << 1) | (val & 1);
224 val >>= 1;
225 }
226 return retval;
227}
228
cbe61d8a 229u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 230 u8 phy, int kbps,
f1dc5600
S		 231 u32 frameLen, u16 rateix,
232 bool shortPreamble)
f078f209 233{
f1dc5600 234 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 235
f1dc5600
S		 236 if (kbps == 0)
237 return 0;
f078f209 238
545750d3 239 switch (phy) {
46d14a58 240 case WLAN_RC_PHY_CCK:
f1dc5600 241 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 242 if (shortPreamble)
f1dc5600
S		 243 phyTime >>= 1;
244 numBits = frameLen << 3;
245 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
246 break;
46d14a58 247 case WLAN_RC_PHY_OFDM:
2660b81a 248 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 249 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
250 numBits = OFDM_PLCP_BITS + (frameLen << 3);
251 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
252 txTime = OFDM_SIFS_TIME_QUARTER
253 + OFDM_PREAMBLE_TIME_QUARTER
254 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 255 } else if (ah->curchan &&
256 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 257 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
258 numBits = OFDM_PLCP_BITS + (frameLen << 3);
259 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
260 txTime = OFDM_SIFS_TIME_HALF +
261 OFDM_PREAMBLE_TIME_HALF
262 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
263 } else {
264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
268 + (numSymbols * OFDM_SYMBOL_TIME);
269 }
270 break;
271 default:
3800276a
JP		 272 ath_err(ath9k_hw_common(ah),
273 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 274 txTime = 0;
275 break;
276 }
f078f209 277
f1dc5600
S		 278 return txTime;
279}
7322fd19 280EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 281
cbe61d8a 282void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 283 struct ath9k_channel *chan,
284 struct chan_centers *centers)
f078f209 285{
f1dc5600 286 int8_t extoff;
f078f209 287
f1dc5600
S		 288 if (!IS_CHAN_HT40(chan)) {
289 centers->ctl_center = centers->ext_center =
290 centers->synth_center = chan->channel;
291 return;
f078f209 292 }
f078f209 293
8896934c 294 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 295 centers->synth_center =
296 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
297 extoff = 1;
298 } else {
299 centers->synth_center =
300 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
301 extoff = -1;
302 }
f078f209 303
f1dc5600
S		 304 centers->ctl_center =
305 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 306 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 307 centers->ext_center =
6420014c 308 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 309}
310
f1dc5600
S		 311/******************/
312/* Chip Revisions */
313/******************/
314
cbe61d8a 315static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 316{
f1dc5600 317 u32 val;
f078f209 318
ecb1d385
VT		 319 switch (ah->hw_version.devid) {
320 case AR5416_AR9100_DEVID:
321 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
322 break;
3762561a
GJ		 323 case AR9300_DEVID_AR9330:
324 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
325 if (ah->get_mac_revision) {
326 ah->hw_version.macRev = ah->get_mac_revision();
327 } else {
328 val = REG_READ(ah, AR_SREV);
329 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
330 }
331 return;
ecb1d385
VT		 332 case AR9300_DEVID_AR9340:
333 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
334 val = REG_READ(ah, AR_SREV);
335 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
336 return;
813831dc
GJ		 337 case AR9300_DEVID_QCA955X:
338 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
339 return;
ecb1d385
VT		 340 }
341
f1dc5600 342 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 343
f1dc5600
S		 344 if (val == 0xFF) {
345 val = REG_READ(ah, AR_SREV);
d535a42a
S		 346 ah->hw_version.macVersion =
347 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
348 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 349
77fac465 350 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 351 ah->is_pciexpress = true;
352 else
353 ah->is_pciexpress = (val &
354 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 355 } else {
356 if (!AR_SREV_9100(ah))
d535a42a 357 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 358
d535a42a 359 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 360
d535a42a 361 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 362 ah->is_pciexpress = true;
f1dc5600 363 }
f078f209
LR		 364}
365
f1dc5600
S		 366/************************************/
367/* HW Attach, Detach, Init Routines */
368/************************************/
369
cbe61d8a 370static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 371{
040b74f7 372 if (!AR_SREV_5416(ah))
f1dc5600 373 return;
f078f209 374
f1dc5600
S		 375 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
376 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
377 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
378 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
379 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 384
f1dc5600 385 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 386}
387
1f3f0618 388/* This should work for all families including legacy */
cbe61d8a 389static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 390{
c46917bb 391 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 392 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 393 u32 regHold[2];
07b2fa5a
JP		 394 static const u32 patternData[4] = {
395 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
396 };
1f3f0618 397 int i, j, loop_max;
f078f209 398
1f3f0618
SB		 399 if (!AR_SREV_9300_20_OR_LATER(ah)) {
400 loop_max = 2;
401 regAddr[1] = AR_PHY_BASE + (8 << 2);
402 } else
403 loop_max = 1;
404
405 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 406 u32 addr = regAddr[i];
407 u32 wrData, rdData;
f078f209 408
f1dc5600
S		 409 regHold[i] = REG_READ(ah, addr);
410 for (j = 0; j < 0x100; j++) {
411 wrData = (j << 16) | j;
412 REG_WRITE(ah, addr, wrData);
413 rdData = REG_READ(ah, addr);
414 if (rdData != wrData) {
3800276a
JP		 415 ath_err(common,
416 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
417 addr, wrData, rdData);
f1dc5600
S		 418 return false;
419 }
420 }
421 for (j = 0; j < 4; j++) {
422 wrData = patternData[j];
423 REG_WRITE(ah, addr, wrData);
424 rdData = REG_READ(ah, addr);
425 if (wrData != rdData) {
3800276a
JP		 426 ath_err(common,
427 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
428 addr, wrData, rdData);
f1dc5600
S		 429 return false;
430 }
f078f209 431 }
f1dc5600 432 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 433 }
f1dc5600 434 udelay(100);
cbe61d8a 435
f078f209
LR		 436 return true;
437}
438
b8b0f377 439static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 440{
441 int i;
f078f209 442
689e756f
FF		 443 ah->config.dma_beacon_response_time = 1;
444 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 445 ah->config.additional_swba_backoff = 0;
446 ah->config.ack_6mb = 0x0;
447 ah->config.cwm_ignore_extcca = 0;
2660b81a 448 ah->config.pcie_clock_req = 0;
2660b81a 449 ah->config.analog_shiftreg = 1;
f078f209 450
f1dc5600 451 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 452 ah->config.spurchans[i][0] = AR_NO_SPUR;
453 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 454 }
455
0ce024cb 456 ah->config.rx_intr_mitigation = true;
6158425b
LR		 457
458 /*
459 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
460 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
461 * This means we use it for all AR5416 devices, and the few
462 * minor PCI AR9280 devices out there.
463 *
464 * Serialization is required because these devices do not handle
465 * well the case of two concurrent reads/writes due to the latency
466 * involved. During one read/write another read/write can be issued
467 * on another CPU while the previous read/write may still be working
468 * on our hardware, if we hit this case the hardware poops in a loop.
469 * We prevent this by serializing reads and writes.
470 *
471 * This issue is not present on PCI-Express devices or pre-AR5416
472 * devices (legacy, 802.11abg).
473 */
474 if (num_possible_cpus() > 1)
2d6a5e95 475 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 476}
477
50aca25b 478static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 479{
608b88cb
LR		 480 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
481
482 regulatory->country_code = CTRY_DEFAULT;
483 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 484
d535a42a 485 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 486 ah->hw_version.subvendorid = 0;
f078f209 487
2660b81a 488 ah->atim_window = 0;
16f2411f
FF		 489 ah->sta_id1_defaults =
490 AR_STA_ID1_CRPT_MIC_ENABLE |
491 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 492 if (AR_SREV_9100(ah))
493 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 494 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 495 ah->globaltxtimeout = (u32) -1;
cbdec975 496 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 497 ah->htc_reset_init = true;
f078f209
LR		 498}
499
cbe61d8a 500static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 501{
1510718d 502 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 503 u32 sum;
504 int i;
505 u16 eeval;
07b2fa5a 506 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 507
508 sum = 0;
509 for (i = 0; i < 3; i++) {
49101676 510 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 511 sum += eeval;
1510718d
LR		 512 common->macaddr[2 * i] = eeval >> 8;
513 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 514 }
d8baa939 515 if (sum == 0 || sum == 0xffff * 3)
f078f209 516 return -EADDRNOTAVAIL;
f078f209
LR		 517
518 return 0;
519}
520
f637cfd6 521static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 522{
6cae913d 523 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 524 int ecode;
f078f209 525
6cae913d 526 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 527 if (!ath9k_hw_chip_test(ah))
528 return -ENODEV;
529 }
f078f209 530
ebd5a14a
LR		 531 if (!AR_SREV_9300_20_OR_LATER(ah)) {
532 ecode = ar9002_hw_rf_claim(ah);
533 if (ecode != 0)
534 return ecode;
535 }
f078f209 536
f637cfd6 537 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 538 if (ecode != 0)
539 return ecode;
7d01b221 540
d2182b69 541 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 542 ah->eep_ops->get_eeprom_ver(ah),
543 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 544
e323300d 545 ath9k_hw_ani_init(ah);
f078f209 546
d3b371cb
SM		 547 /*
548 * EEPROM needs to be initialized before we do this.
549 * This is required for regulatory compliance.
550 */
551 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
552 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
553 if ((regdmn & 0xF0) == CTL_FCC) {
554 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
555 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
556 }
557 }
558
f078f209
LR		 559 return 0;
560}
561
c1b976d2 562static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 563{
c1b976d2
FF		 564 if (!AR_SREV_9300_20_OR_LATER(ah))
565 return ar9002_hw_attach_ops(ah);
566
567 ar9003_hw_attach_ops(ah);
568 return 0;
aa4058ae
LR		 569}
570
d70357d5
LR		 571/* Called for all hardware families */
572static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 573{
c46917bb 574 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 575 int r = 0;
aa4058ae 576
ac45c12d
SB		 577 ath9k_hw_read_revisions(ah);
578
0a8d7cb0
SB		 579 /*
580 * Read back AR_WA into a permanent copy and set bits 14 and 17.
581 * We need to do this to avoid RMW of this register. We cannot
582 * read the reg when chip is asleep.
583 */
27251e00
SM		 584 if (AR_SREV_9300_20_OR_LATER(ah)) {
585 ah->WARegVal = REG_READ(ah, AR_WA);
586 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
587 AR_WA_ASPM_TIMER_BASED_DISABLE);
588 }
0a8d7cb0 589
aa4058ae 590 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 591 ath_err(common, "Couldn't reset chip\n");
95fafca2 592 return -EIO;
aa4058ae
LR		 593 }
594
a4a2954f
SM		 595 if (AR_SREV_9565(ah)) {
596 ah->WARegVal |= AR_WA_BIT22;
597 REG_WRITE(ah, AR_WA, ah->WARegVal);
598 }
599
bab1f62e
LR		 600 ath9k_hw_init_defaults(ah);
601 ath9k_hw_init_config(ah);
602
c1b976d2
FF		 603 r = ath9k_hw_attach_ops(ah);
604 if (r)
605 return r;
d70357d5 606
9ecdef4b 607 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 608 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 609 return -EIO;
aa4058ae
LR		 610 }
611
f3eef645 612 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 613 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
7508b657 614 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
4c85ab11 615 !ah->is_pciexpress)) {
aa4058ae
LR		 616 ah->config.serialize_regmode =
617 SER_REG_MODE_ON;
618 } else {
619 ah->config.serialize_regmode =
620 SER_REG_MODE_OFF;
621 }
622 }
623
d2182b69 624 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 625 ah->config.serialize_regmode);
626
f4709fdf
LR		 627 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
628 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
629 else
630 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
631
6da5a720
FF		 632 switch (ah->hw_version.macVersion) {
633 case AR_SREV_VERSION_5416_PCI:
634 case AR_SREV_VERSION_5416_PCIE:
635 case AR_SREV_VERSION_9160:
636 case AR_SREV_VERSION_9100:
637 case AR_SREV_VERSION_9280:
638 case AR_SREV_VERSION_9285:
639 case AR_SREV_VERSION_9287:
640 case AR_SREV_VERSION_9271:
641 case AR_SREV_VERSION_9300:
2c8e5937 642 case AR_SREV_VERSION_9330:
6da5a720 643 case AR_SREV_VERSION_9485:
bca04689 644 case AR_SREV_VERSION_9340:
423e38e8 645 case AR_SREV_VERSION_9462:
2b943a33 646 case AR_SREV_VERSION_9550:
77fac465 647 case AR_SREV_VERSION_9565:
6da5a720
FF		 648 break;
649 default:
3800276a
JP		 650 ath_err(common,
651 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
652 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 653 return -EOPNOTSUPP;
aa4058ae
LR		 654 }
655
2c8e5937 656 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 657 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 658 ah->is_pciexpress = false;
659
aa4058ae 660 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 661 ath9k_hw_init_cal_settings(ah);
662
663 ah->ani_function = ATH9K_ANI_ALL;
e36b27af
LR		 664 if (!AR_SREV_9300_20_OR_LATER(ah))
665 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 666
69ce674b 667 if (!ah->is_pciexpress)
aa4058ae
LR		 668 ath9k_hw_disablepcie(ah);
669
f637cfd6 670 r = ath9k_hw_post_init(ah);
aa4058ae 671 if (r)
95fafca2 672 return r;
aa4058ae
LR		 673
674 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 675 r = ath9k_hw_fill_cap_info(ah);
676 if (r)
677 return r;
678
4f3acf81
LR		 679 r = ath9k_hw_init_macaddr(ah);
680 if (r) {
3800276a 681 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 682 return r;
f078f209
LR		 683 }
684
d7e7d229 685 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 686 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 687 else
2660b81a 688 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 689
88e641df
GJ		 690 if (AR_SREV_9330(ah))
691 ah->bb_watchdog_timeout_ms = 85;
692 else
693 ah->bb_watchdog_timeout_ms = 25;
f078f209 694
211f5859
LR		 695 common->state = ATH_HW_INITIALIZED;
696
4f3acf81 697 return 0;
f078f209
LR		 698}
699
d70357d5 700int ath9k_hw_init(struct ath_hw *ah)
f078f209 701{
d70357d5
LR		 702 int ret;
703 struct ath_common *common = ath9k_hw_common(ah);
f078f209 704
77fac465 705 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 706 switch (ah->hw_version.devid) {
707 case AR5416_DEVID_PCI:
708 case AR5416_DEVID_PCIE:
709 case AR5416_AR9100_DEVID:
710 case AR9160_DEVID_PCI:
711 case AR9280_DEVID_PCI:
712 case AR9280_DEVID_PCIE:
713 case AR9285_DEVID_PCIE:
db3cc53a
SB		 714 case AR9287_DEVID_PCI:
715 case AR9287_DEVID_PCIE:
d70357d5 716 case AR2427_DEVID_PCIE:
db3cc53a 717 case AR9300_DEVID_PCIE:
3050c914 718 case AR9300_DEVID_AR9485_PCIE:
999a7a88 719 case AR9300_DEVID_AR9330:
bca04689 720 case AR9300_DEVID_AR9340:
2b943a33 721 case AR9300_DEVID_QCA955X:
5a63ef0f 722 case AR9300_DEVID_AR9580:
423e38e8 723 case AR9300_DEVID_AR9462:
d4e5979c 724 case AR9485_DEVID_AR1111:
77fac465 725 case AR9300_DEVID_AR9565:
d70357d5
LR		 726 break;
727 default:
728 if (common->bus_ops->ath_bus_type == ATH_USB)
729 break;
3800276a
JP		 730 ath_err(common, "Hardware device ID 0x%04x not supported\n",
731 ah->hw_version.devid);
d70357d5
LR		 732 return -EOPNOTSUPP;
733 }
f078f209 734
d70357d5
LR		 735 ret = __ath9k_hw_init(ah);
736 if (ret) {
3800276a
JP		 737 ath_err(common,
738 "Unable to initialize hardware; initialization status: %d\n",
739 ret);
d70357d5
LR		 740 return ret;
741 }
f078f209 742
d70357d5 743 return 0;
f078f209 744}
d70357d5 745EXPORT_SYMBOL(ath9k_hw_init);
f078f209 746
cbe61d8a 747static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 748{
7d0d0df0
S		 749 ENABLE_REGWRITE_BUFFER(ah);
750
f1dc5600
S		 751 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
752 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 753
f1dc5600
S		 754 REG_WRITE(ah, AR_QOS_NO_ACK,
755 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
756 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
757 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
758
759 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
760 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
761 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
762 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
763 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 764
765 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 766}
767
b84628eb 768u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 769{
f18e3c6b
MSS		 770 struct ath_common *common = ath9k_hw_common(ah);
771 int i = 0;
772
ca7a4deb
FF		 773 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
774 udelay(100);
775 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 776
f18e3c6b
MSS		 777 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
778
ca7a4deb 779 udelay(100);
b1415819 780
f18e3c6b
MSS		 781 if (WARN_ON_ONCE(i >= 100)) {
782 ath_err(common, "PLL4 meaurement not done\n");
783 break;
784 }
785
786 i++;
787 }
788
ca7a4deb 789 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 790}
791EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
792
cbe61d8a 793static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 794 struct ath9k_channel *chan)
f078f209 795{
d09b17f7
VT		 796 u32 pll;
797
a4a2954f 798 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 799 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
800 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
801 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
803 AR_CH0_DPLL2_KD, 0x40);
804 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
805 AR_CH0_DPLL2_KI, 0x4);
22983c30 806
3dfd7f60
VT		 807 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
808 AR_CH0_BB_DPLL1_REFDIV, 0x5);
809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
810 AR_CH0_BB_DPLL1_NINI, 0x58);
811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
812 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 813
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 815 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
817 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 819 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 820
3dfd7f60 821 /* program BB PLL phase_shift to 0x6 */
22983c30 822 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 823 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
824
825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
826 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 827 udelay(1000);
a5415d62
GJ		 828 } else if (AR_SREV_9330(ah)) {
829 u32 ddr_dpll2, pll_control2, kd;
830
831 if (ah->is_clk_25mhz) {
832 ddr_dpll2 = 0x18e82f01;
833 pll_control2 = 0xe04a3d;
834 kd = 0x1d;
835 } else {
836 ddr_dpll2 = 0x19e82f01;
837 pll_control2 = 0x886666;
838 kd = 0x3d;
839 }
840
841 /* program DDR PLL ki and kd value */
842 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
843
844 /* program DDR PLL phase_shift */
845 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
846 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
847
848 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
849 udelay(1000);
850
851 /* program refdiv, nint, frac to RTC register */
852 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
853
854 /* program BB PLL kd and ki value */
855 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
856 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
857
858 /* program BB PLL phase_shift */
859 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
860 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
fc05a317 861 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 862 u32 regval, pll2_divint, pll2_divfrac, refdiv;
863
864 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
865 udelay(1000);
866
867 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
868 udelay(100);
869
870 if (ah->is_clk_25mhz) {
871 pll2_divint = 0x54;
872 pll2_divfrac = 0x1eb85;
873 refdiv = 3;
874 } else {
fc05a317
GJ		 875 if (AR_SREV_9340(ah)) {
876 pll2_divint = 88;
877 pll2_divfrac = 0;
878 refdiv = 5;
879 } else {
880 pll2_divint = 0x11;
881 pll2_divfrac = 0x26666;
882 refdiv = 1;
883 }
0b488ac6
VT		 884 }
885
886 regval = REG_READ(ah, AR_PHY_PLL_MODE);
887 regval |= (0x1 << 16);
888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
889 udelay(100);
890
891 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
892 (pll2_divint << 18) | pll2_divfrac);
893 udelay(100);
894
895 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317
GJ		 896 if (AR_SREV_9340(ah))
897 regval = (regval & 0x80071fff) | (0x1 << 30) |
898 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
899 else
900 regval = (regval & 0x80071fff) | (0x3 << 30) |
901 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
0b488ac6
VT		 902 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
903 REG_WRITE(ah, AR_PHY_PLL_MODE,
904 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
905 udelay(1000);
22983c30 906 }
d09b17f7
VT		 907
908 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 909 if (AR_SREV_9565(ah))
910 pll |= 0x40000;
d03a66c1 911 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 912
fc05a317
GJ		 913 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
914 AR_SREV_9550(ah))
3dfd7f60
VT		 915 udelay(1000);
916
c75724d1
LR		 917 /* Switch the core clock for ar9271 to 117Mhz */
918 if (AR_SREV_9271(ah)) {
25e2ab17
S		 919 udelay(500);
920 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 921 }
922
f1dc5600
S		 923 udelay(RTC_PLL_SETTLE_DELAY);
924
925 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 926
fc05a317 927 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 928 if (ah->is_clk_25mhz) {
929 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
930 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
931 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
932 } else {
933 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
934 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
935 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
936 }
937 udelay(100);
938 }
f078f209
LR		 939}
940
cbe61d8a 941static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 942 enum nl80211_iftype opmode)
f078f209 943{
79d1d2b8 944 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 945 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 946 AR_IMR_TXURN |
947 AR_IMR_RXERR |
948 AR_IMR_RXORN |
949 AR_IMR_BCNMISC;
f078f209 950
3b8a0577 951 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
79d1d2b8
VT		 952 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
953
66860240
VT		 954 if (AR_SREV_9300_20_OR_LATER(ah)) {
955 imr_reg |= AR_IMR_RXOK_HP;
956 if (ah->config.rx_intr_mitigation)
957 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
958 else
959 imr_reg |= AR_IMR_RXOK_LP;
f078f209 960
66860240
VT		 961 } else {
962 if (ah->config.rx_intr_mitigation)
963 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
964 else
965 imr_reg |= AR_IMR_RXOK;
966 }
f078f209 967
66860240
VT		 968 if (ah->config.tx_intr_mitigation)
969 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
970 else
971 imr_reg |= AR_IMR_TXOK;
f078f209 972
7d0d0df0
S		 973 ENABLE_REGWRITE_BUFFER(ah);
974
152d530d 975 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 976 ah->imrs2_reg |= AR_IMR_S2_GTT;
977 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 978
f1dc5600
S		 979 if (!AR_SREV_9100(ah)) {
980 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 981 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 982 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
983 }
66860240 984
7d0d0df0 985 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 986
66860240
VT		 987 if (AR_SREV_9300_20_OR_LATER(ah)) {
988 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
989 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
990 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
991 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
992 }
f078f209
LR		 993}
994
b6ba41bb
FF		 995static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
996{
997 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
998 val = min(val, (u32) 0xFFFF);
999 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1000}
1001
0005baf4 1002static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 1003{
0005baf4
FF		 1004 u32 val = ath9k_hw_mac_to_clks(ah, us);
1005 val = min(val, (u32) 0xFFFF);
1006 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 1007}
1008
0005baf4 1009static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1010{
0005baf4
FF		 1011 u32 val = ath9k_hw_mac_to_clks(ah, us);
1012 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1013 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1014}
1015
1016static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1017{
1018 u32 val = ath9k_hw_mac_to_clks(ah, us);
1019 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1020 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1021}
f1dc5600 1022
cbe61d8a 1023static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1024{
f078f209 1025 if (tu > 0xFFFF) {
d2182b69
JP		 1026 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1027 tu);
2660b81a 1028 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1029 return false;
1030 } else {
1031 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1032 ah->globaltxtimeout = tu;
f078f209
LR		 1033 return true;
1034 }
1035}
1036
0005baf4 1037void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1038{
b6ba41bb 1039 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 1040 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1041 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1042 int slottime;
0005baf4 1043 int sifstime;
b6ba41bb
FF		 1044 int rx_lat = 0, tx_lat = 0, eifs = 0;
1045 u32 reg;
0005baf4 1046
d2182b69 1047 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1048 ah->misc_mode);
f078f209 1049
b6ba41bb
FF		 1050 if (!chan)
1051 return;
1052
2660b81a 1053 if (ah->misc_mode != 0)
ca7a4deb 1054 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1055
81a91d57
RM		 1056 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1057 rx_lat = 41;
1058 else
1059 rx_lat = 37;
b6ba41bb
FF		 1060 tx_lat = 54;
1061
e88e4861
FF		 1062 if (IS_CHAN_5GHZ(chan))
1063 sifstime = 16;
1064 else
1065 sifstime = 10;
1066
b6ba41bb
FF		 1067 if (IS_CHAN_HALF_RATE(chan)) {
1068 eifs = 175;
1069 rx_lat *= 2;
1070 tx_lat *= 2;
1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1072 tx_lat += 11;
1073
92367fe7 1074 sifstime = 32;
e115b7ec 1075 ack_offset = 16;
b6ba41bb 1076 slottime = 13;
b6ba41bb
FF		 1077 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1078 eifs = 340;
81a91d57 1079 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1080 tx_lat *= 4;
1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1082 tx_lat += 22;
1083
92367fe7 1084 sifstime = 64;
e115b7ec 1085 ack_offset = 32;
b6ba41bb 1086 slottime = 21;
b6ba41bb 1087 } else {
a7be039d
RM		 1088 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1089 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1090 reg = AR_USEC_ASYNC_FIFO;
1091 } else {
1092 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1093 common->clockrate;
1094 reg = REG_READ(ah, AR_USEC);
1095 }
b6ba41bb
FF		 1096 rx_lat = MS(reg, AR_USEC_RX_LAT);
1097 tx_lat = MS(reg, AR_USEC_TX_LAT);
1098
1099 slottime = ah->slottime;
b6ba41bb 1100 }
0005baf4 1101
e239d859 1102 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1103 slottime += 3 * ah->coverage_class;
1104 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1105 ctstimeout = acktimeout;
42c4568a
FF		 1106
1107 /*
1108 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1109 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1110 * This was initially only meant to work around an issue with delayed
1111 * BA frames in some implementations, but it has been found to fix ACK
1112 * timeout issues in other cases as well.
1113 */
e4744ec7 1114 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1115 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1116 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1117 ctstimeout += 48 - sifstime - ah->slottime;
1118 }
1119
b6ba41bb
FF		 1120 ath9k_hw_set_sifs_time(ah, sifstime);
1121 ath9k_hw_setslottime(ah, slottime);
0005baf4 1122 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1123 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1124 if (ah->globaltxtimeout != (u32) -1)
1125 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1126
1127 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1128 REG_RMW(ah, AR_USEC,
1129 (common->clockrate - 1) |
1130 SM(rx_lat, AR_USEC_RX_LAT) |
1131 SM(tx_lat, AR_USEC_TX_LAT),
1132 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1133
f1dc5600 1134}
0005baf4 1135EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1136
285f2dda 1137void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1138{
211f5859
LR		 1139 struct ath_common *common = ath9k_hw_common(ah);
1140
736b3a27 1141 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1142 return;
211f5859 1143
9ecdef4b 1144 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1145}
285f2dda 1146EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1147
f1dc5600
S		 1148/*******/
1149/* INI */
1150/*******/
1151
8fe65368 1152u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1153{
1154 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1155
6b21fd20 1156 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1157 ctl |= CTL_11G;
1158 else
1159 ctl |= CTL_11A;
1160
1161 return ctl;
1162}
1163
f1dc5600
S		 1164/****************************************/
1165/* Reset and Channel Switching Routines */
1166/****************************************/
f1dc5600 1167
cbe61d8a 1168static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1169{
57b32227 1170 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1171 int txbuf_size;
f1dc5600 1172
7d0d0df0
S		 1173 ENABLE_REGWRITE_BUFFER(ah);
1174
d7e7d229
LR		 1175 /*
1176 * set AHB_MODE not to do cacheline prefetches
1177 */
ca7a4deb
FF		 1178 if (!AR_SREV_9300_20_OR_LATER(ah))
1179 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1180
d7e7d229
LR		 1181 /*
1182 * let mac dma reads be in 128 byte chunks
1183 */
ca7a4deb 1184 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1185
7d0d0df0 1186 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1187
d7e7d229
LR		 1188 /*
1189 * Restore TX Trigger Level to its pre-reset value.
1190 * The initial value depends on whether aggregation is enabled, and is
1191 * adjusted whenever underruns are detected.
1192 */
57b32227
FF		 1193 if (!AR_SREV_9300_20_OR_LATER(ah))
1194 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1195
7d0d0df0 1196 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1197
d7e7d229
LR		 1198 /*
1199 * let mac dma writes be in 128 byte chunks
1200 */
ca7a4deb 1201 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1202
d7e7d229
LR		 1203 /*
1204 * Setup receive FIFO threshold to hold off TX activities
1205 */
f1dc5600
S		 1206 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1207
57b32227
FF		 1208 if (AR_SREV_9300_20_OR_LATER(ah)) {
1209 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1210 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1211
1212 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1213 ah->caps.rx_status_len);
1214 }
1215
d7e7d229
LR		 1216 /*
1217 * reduce the number of usable entries in PCU TXBUF to avoid
1218 * wrap around issues.
1219 */
f1dc5600 1220 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1221 /* For AR9285 the number of Fifos are reduced to half.
1222 * So set the usable tx buf size also to half to
1223 * avoid data/delimiter underruns
1224 */
86c157b3
FF		 1225 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1226 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1227 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1228 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1229 } else {
1230 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1231 }
744d4025 1232
86c157b3
FF		 1233 if (!AR_SREV_9271(ah))
1234 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1235
7d0d0df0 1236 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1237
744d4025
VT		 1238 if (AR_SREV_9300_20_OR_LATER(ah))
1239 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1240}
1241
cbe61d8a 1242static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1243{
ca7a4deb
FF		 1244 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1245 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1246
f1dc5600 1247 switch (opmode) {
d97809db 1248 case NL80211_IFTYPE_ADHOC:
ca7a4deb 1249 set |= AR_STA_ID1_ADHOC;
f1dc5600 1250 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1251 break;
2664d666 1252 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1253 case NL80211_IFTYPE_AP:
1254 set |= AR_STA_ID1_STA_AP;
1255 /* fall through */
d97809db 1256 case NL80211_IFTYPE_STATION:
ca7a4deb 1257 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1258 break;
5f841b41 1259 default:
ca7a4deb
FF		 1260 if (!ah->is_monitoring)
1261 set = 0;
5f841b41 1262 break;
f1dc5600 1263 }
ca7a4deb 1264 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1265}
1266
8fe65368
LR		 1267void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1268 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1269{
1270 u32 coef_exp, coef_man;
1271
1272 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1273 if ((coef_scaled >> coef_exp) & 0x1)
1274 break;
1275
1276 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1277
1278 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1279
1280 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1281 *coef_exponent = coef_exp - 16;
1282}
1283
cbe61d8a 1284static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1285{
1286 u32 rst_flags;
1287 u32 tmpReg;
1288
70768496 1289 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1290 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1291 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1292 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1293 }
1294
7d0d0df0
S		 1295 ENABLE_REGWRITE_BUFFER(ah);
1296
9a658d2b
LR		 1297 if (AR_SREV_9300_20_OR_LATER(ah)) {
1298 REG_WRITE(ah, AR_WA, ah->WARegVal);
1299 udelay(10);
1300 }
1301
f1dc5600
S		 1302 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1303 AR_RTC_FORCE_WAKE_ON_INT);
1304
1305 if (AR_SREV_9100(ah)) {
1306 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1307 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1308 } else {
1309 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1310 if (AR_SREV_9340(ah))
1311 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1312 else
1313 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1314 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1315
1316 if (tmpReg) {
42d5bc3f 1317 u32 val;
f1dc5600 1318 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1319
1320 val = AR_RC_HOSTIF;
1321 if (!AR_SREV_9300_20_OR_LATER(ah))
1322 val |= AR_RC_AHB;
1323 REG_WRITE(ah, AR_RC, val);
1324
1325 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1326 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1327
1328 rst_flags = AR_RTC_RC_MAC_WARM;
1329 if (type == ATH9K_RESET_COLD)
1330 rst_flags |= AR_RTC_RC_MAC_COLD;
1331 }
1332
7d95847c
GJ		 1333 if (AR_SREV_9330(ah)) {
1334 int npend = 0;
1335 int i;
1336
1337 /* AR9330 WAR:
1338 * call external reset function to reset WMAC if:
1339 * - doing a cold reset
1340 * - we have pending frames in the TX queues
1341 */
1342
1343 for (i = 0; i < AR_NUM_QCU; i++) {
1344 npend = ath9k_hw_numtxpending(ah, i);
1345 if (npend)
1346 break;
1347 }
1348
1349 if (ah->external_reset &&
1350 (npend || type == ATH9K_RESET_COLD)) {
1351 int reset_err = 0;
1352
d2182b69 1353 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1354 "reset MAC via external reset\n");
1355
1356 reset_err = ah->external_reset();
1357 if (reset_err) {
1358 ath_err(ath9k_hw_common(ah),
1359 "External reset failed, err=%d\n",
1360 reset_err);
1361 return false;
1362 }
1363
1364 REG_WRITE(ah, AR_RTC_RESET, 1);
1365 }
1366 }
1367
3863495b 1368 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1369 ar9003_mci_check_gpm_offset(ah);
3863495b 1370
d03a66c1 1371 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1372
1373 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1374
f1dc5600
S		 1375 udelay(50);
1376
d03a66c1 1377 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1378 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1379 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1380 return false;
1381 }
1382
1383 if (!AR_SREV_9100(ah))
1384 REG_WRITE(ah, AR_RC, 0);
1385
f1dc5600
S		 1386 if (AR_SREV_9100(ah))
1387 udelay(50);
1388
1389 return true;
1390}
1391
cbe61d8a 1392static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1393{
7d0d0df0
S		 1394 ENABLE_REGWRITE_BUFFER(ah);
1395
9a658d2b
LR		 1396 if (AR_SREV_9300_20_OR_LATER(ah)) {
1397 REG_WRITE(ah, AR_WA, ah->WARegVal);
1398 udelay(10);
1399 }
1400
f1dc5600
S		 1401 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1402 AR_RTC_FORCE_WAKE_ON_INT);
1403
42d5bc3f 1404 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1405 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1406
d03a66c1 1407 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1408
7d0d0df0 1409 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1410
84e2169b
SB		 1411 if (!AR_SREV_9300_20_OR_LATER(ah))
1412 udelay(2);
1413
1414 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1415 REG_WRITE(ah, AR_RC, 0);
1416
d03a66c1 1417 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1418
1419 if (!ath9k_hw_wait(ah,
1420 AR_RTC_STATUS,
1421 AR_RTC_STATUS_M,
0caa7b14
S		 1422 AR_RTC_STATUS_ON,
1423 AH_WAIT_TIMEOUT)) {
d2182b69 1424 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1425 return false;
f078f209
LR		 1426 }
1427
f1dc5600
S		 1428 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1429}
1430
cbe61d8a 1431static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1432{
7a9233ff 1433 bool ret = false;
2577c6e8 1434
9a658d2b
LR		 1435 if (AR_SREV_9300_20_OR_LATER(ah)) {
1436 REG_WRITE(ah, AR_WA, ah->WARegVal);
1437 udelay(10);
1438 }
1439
f1dc5600
S		 1440 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1441 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1442
ceb26a60
FF		 1443 if (!ah->reset_power_on)
1444 type = ATH9K_RESET_POWER_ON;
1445
f1dc5600
S		 1446 switch (type) {
1447 case ATH9K_RESET_POWER_ON:
7a9233ff 1448 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1449 if (ret)
ceb26a60 1450 ah->reset_power_on = true;
7a9233ff 1451 break;
f1dc5600
S		 1452 case ATH9K_RESET_WARM:
1453 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1454 ret = ath9k_hw_set_reset(ah, type);
1455 break;
f1dc5600 1456 default:
7a9233ff 1457 break;
f1dc5600 1458 }
7a9233ff 1459
7a9233ff 1460 return ret;
f078f209
LR		 1461}
1462
cbe61d8a 1463static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1464 struct ath9k_channel *chan)
f078f209 1465{
9c083af8
FF		 1466 int reset_type = ATH9K_RESET_WARM;
1467
1468 if (AR_SREV_9280(ah)) {
1469 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1470 reset_type = ATH9K_RESET_POWER_ON;
1471 else
1472 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1473 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1474 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1475 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1476
1477 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1478 return false;
f078f209 1479
9ecdef4b 1480 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1481 return false;
f078f209 1482
2660b81a 1483 ah->chip_fullsleep = false;
bfc441a4
FF		 1484
1485 if (AR_SREV_9330(ah))
1486 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1487 ath9k_hw_init_pll(ah, chan);
f1dc5600 1488 ath9k_hw_set_rfmode(ah, chan);
f078f209 1489
f1dc5600 1490 return true;
f078f209
LR		 1491}
1492
cbe61d8a 1493static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1494 struct ath9k_channel *chan)
f078f209 1495{
c46917bb 1496 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1497 struct ath9k_hw_capabilities *pCap = &ah->caps;
1498 bool band_switch = false, mode_diff = false;
70e89a71 1499 u8 ini_reloaded = 0;
8fe65368 1500 u32 qnum;
0a3b7bac 1501 int r;
5f0c04ea 1502
b840cffe 1503 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
8896934c 1504 band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
6b21fd20 1505 mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
b840cffe 1506 }
f078f209
LR		 1507
1508 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1509 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1510 ath_dbg(common, QUEUE,
226afe68 1511 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1512 return false;
1513 }
1514 }
1515
8fe65368 1516 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1517 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1518 return false;
1519 }
1520
b840cffe 1521 if (band_switch || mode_diff) {
5f0c04ea
RM		 1522 ath9k_hw_mark_phy_inactive(ah);
1523 udelay(5);
1524
5f35c0fa
SM		 1525 if (band_switch)
1526 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1527
1528 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1529 ath_err(common, "Failed to do fast channel change\n");
1530 return false;
1531 }
1532 }
1533
8fe65368 1534 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1535
8fe65368 1536 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1537 if (r) {
3800276a 1538 ath_err(common, "Failed to set channel\n");
0a3b7bac 1539 return false;
f078f209 1540 }
dfdac8ac 1541 ath9k_hw_set_clockrate(ah);
64ea57d0 1542 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1543
81c507a8 1544 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1545 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1546
70e89a71
SM		 1547 if (band_switch || ini_reloaded)
1548 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1549
70e89a71
SM		 1550 ath9k_hw_init_bb(ah, chan);
1551 ath9k_hw_rfbus_done(ah);
5f0c04ea 1552
70e89a71
SM		 1553 if (band_switch || ini_reloaded) {
1554 ah->ah_flags |= AH_FASTCC;
1555 ath9k_hw_init_cal(ah, chan);
a126ff51 1556 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1557 }
1558
f1dc5600
S		 1559 return true;
1560}
1561
691680b8
FF		 1562static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1563{
1564 u32 gpio_mask = ah->gpio_mask;
1565 int i;
1566
1567 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1568 if (!(gpio_mask & 1))
1569 continue;
1570
1571 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1572 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1573 }
1574}
1575
01e18918
RM		 1576static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1577 int *hang_state, int *hang_pos)
1578{
1579 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1580 u32 chain_state, dcs_pos, i;
1581
1582 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1583 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1584 for (i = 0; i < 3; i++) {
1585 if (chain_state == dcu_chain_state[i]) {
1586 *hang_state = chain_state;
1587 *hang_pos = dcs_pos;
1588 return true;
1589 }
1590 }
1591 }
1592 return false;
1593}
1594
1595#define DCU_COMPLETE_STATE 1
1596#define DCU_COMPLETE_STATE_MASK 0x3
1597#define NUM_STATUS_READS 50
1598static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1599{
1600 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1601 u32 i, hang_pos, hang_state, num_state = 6;
1602
1603 comp_state = REG_READ(ah, AR_DMADBG_6);
1604
1605 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1606 ath_dbg(ath9k_hw_common(ah), RESET,
1607 "MAC Hang signature not found at DCU complete\n");
1608 return false;
1609 }
1610
1611 chain_state = REG_READ(ah, dcs_reg);
1612 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1613 goto hang_check_iter;
1614
1615 dcs_reg = AR_DMADBG_5;
1616 num_state = 4;
1617 chain_state = REG_READ(ah, dcs_reg);
1618 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1619 goto hang_check_iter;
1620
1621 ath_dbg(ath9k_hw_common(ah), RESET,
1622 "MAC Hang signature 1 not found\n");
1623 return false;
1624
1625hang_check_iter:
1626 ath_dbg(ath9k_hw_common(ah), RESET,
1627 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1628 chain_state, comp_state, hang_state, hang_pos);
1629
1630 for (i = 0; i < NUM_STATUS_READS; i++) {
1631 chain_state = REG_READ(ah, dcs_reg);
1632 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1633 comp_state = REG_READ(ah, AR_DMADBG_6);
1634
1635 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1636 DCU_COMPLETE_STATE) ||
1637 (chain_state != hang_state))
1638 return false;
1639 }
1640
1641 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1642
1643 return true;
1644}
1645
1e516ca7
SM		 1646void ath9k_hw_check_nav(struct ath_hw *ah)
1647{
1648 struct ath_common *common = ath9k_hw_common(ah);
1649 u32 val;
1650
1651 val = REG_READ(ah, AR_NAV);
1652 if (val != 0xdeadbeef && val > 0x7fff) {
1653 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1654 REG_WRITE(ah, AR_NAV, 0);
1655 }
1656}
1657EXPORT_SYMBOL(ath9k_hw_check_nav);
1658
c9c99e5e 1659bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1660{
c9c99e5e
FF		 1661 int count = 50;
1662 u32 reg;
1663
01e18918
RM		 1664 if (AR_SREV_9300(ah))
1665 return !ath9k_hw_detect_mac_hang(ah);
1666
e17f83ea 1667 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1668 return true;
1669
1670 do {
1671 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1672
c9c99e5e
FF		 1673 if ((reg & 0x7E7FFFEF) == 0x00702400)
1674 continue;
1675
1676 switch (reg & 0x7E000B00) {
1677 case 0x1E000000:
1678 case 0x52000B00:
1679 case 0x18000B00:
1680 continue;
1681 default:
1682 return true;
1683 }
1684 } while (count-- > 0);
3b319aae 1685
c9c99e5e 1686 return false;
3b319aae 1687}
c9c99e5e 1688EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1689
15d2b585
SM		 1690static void ath9k_hw_init_mfp(struct ath_hw *ah)
1691{
1692 /* Setup MFP options for CCMP */
1693 if (AR_SREV_9280_20_OR_LATER(ah)) {
1694 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1695 * frames when constructing CCMP AAD. */
1696 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1697 0xc7ff);
1698 ah->sw_mgmt_crypto = false;
1699 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1700 /* Disable hardware crypto for management frames */
1701 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1702 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1703 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1704 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1705 ah->sw_mgmt_crypto = true;
1706 } else {
1707 ah->sw_mgmt_crypto = true;
1708 }
1709}
1710
1711static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1712 u32 macStaId1, u32 saveDefAntenna)
1713{
1714 struct ath_common *common = ath9k_hw_common(ah);
1715
1716 ENABLE_REGWRITE_BUFFER(ah);
1717
ecbbed32 1718 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585
SM		 1719 | AR_STA_ID1_RTS_USE_DEF
1720 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
ecbbed32
FF		 1721 | ah->sta_id1_defaults,
1722 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1723 ath_hw_setbssidmask(common);
1724 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1725 ath9k_hw_write_associd(ah);
1726 REG_WRITE(ah, AR_ISR, ~0);
1727 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1728
1729 REGWRITE_BUFFER_FLUSH(ah);
1730
1731 ath9k_hw_set_operating_mode(ah, ah->opmode);
1732}
1733
1734static void ath9k_hw_init_queues(struct ath_hw *ah)
1735{
1736 int i;
1737
1738 ENABLE_REGWRITE_BUFFER(ah);
1739
1740 for (i = 0; i < AR_NUM_DCU; i++)
1741 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1742
1743 REGWRITE_BUFFER_FLUSH(ah);
1744
1745 ah->intr_txqs = 0;
1746 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1747 ath9k_hw_resettxqueue(ah, i);
1748}
1749
1750/*
1751 * For big endian systems turn on swapping for descriptors
1752 */
1753static void ath9k_hw_init_desc(struct ath_hw *ah)
1754{
1755 struct ath_common *common = ath9k_hw_common(ah);
1756
1757 if (AR_SREV_9100(ah)) {
1758 u32 mask;
1759 mask = REG_READ(ah, AR_CFG);
1760 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1761 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1762 mask);
1763 } else {
1764 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1765 REG_WRITE(ah, AR_CFG, mask);
1766 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1767 REG_READ(ah, AR_CFG));
1768 }
1769 } else {
1770 if (common->bus_ops->ath_bus_type == ATH_USB) {
1771 /* Configure AR9271 target WLAN */
1772 if (AR_SREV_9271(ah))
1773 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1774 else
1775 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1776 }
1777#ifdef __BIG_ENDIAN
1778 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1779 AR_SREV_9550(ah))
1780 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1781 else
1782 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1783#endif
1784 }
1785}
1786
caed6579
SM		 1787/*
1788 * Fast channel change:
1789 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1790 */
1791static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1792{
1793 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1794 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1795 int ret;
1796
1797 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1798 goto fail;
1799
1800 if (ah->chip_fullsleep)
1801 goto fail;
1802
1803 if (!ah->curchan)
1804 goto fail;
1805
1806 if (chan->channel == ah->curchan->channel)
1807 goto fail;
1808
feb7bc99
FF		 1809 if ((ah->curchan->channelFlags | chan->channelFlags) &
1810 (CHANNEL_HALF | CHANNEL_QUARTER))
1811 goto fail;
1812
b840cffe 1813 /*
6b21fd20 1814 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1815 */
6b21fd20
FF		 1816 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1817 chan->channelFlags != ah->curchan->channelFlags)
1818 goto fail;
caed6579
SM		 1819
1820 if (!ath9k_hw_check_alive(ah))
1821 goto fail;
1822
1823 /*
1824 * For AR9462, make sure that calibration data for
1825 * re-using are present.
1826 */
8a90555f 1827 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1828 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1829 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1830 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1831 goto fail;
1832
1833 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1834 ah->curchan->channel, chan->channel);
1835
1836 ret = ath9k_hw_channel_change(ah, chan);
1837 if (!ret)
1838 goto fail;
1839
5955b2b0 1840 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1841 ar9003_mci_2g5g_switch(ah, false);
caed6579 1842
88033318
RM		 1843 ath9k_hw_loadnf(ah, ah->curchan);
1844 ath9k_hw_start_nfcal(ah, true);
1845
caed6579
SM		 1846 if (AR_SREV_9271(ah))
1847 ar9002_hw_load_ani_reg(ah, chan);
1848
1849 return 0;
1850fail:
1851 return -EINVAL;
1852}
1853
cbe61d8a 1854int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1855 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1856{
1510718d 1857 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1858 u32 saveLedState;
f078f209
LR		 1859 u32 saveDefAntenna;
1860 u32 macStaId1;
46fe782c 1861 u64 tsf = 0;
15d2b585 1862 int r;
caed6579 1863 bool start_mci_reset = false;
63d32967
MSS		 1864 bool save_fullsleep = ah->chip_fullsleep;
1865
5955b2b0 1866 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1867 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1868 if (start_mci_reset)
1869 return 0;
63d32967
MSS		 1870 }
1871
9ecdef4b 1872 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1873 return -EIO;
f078f209 1874
caed6579
SM		 1875 if (ah->curchan && !ah->chip_fullsleep)
1876 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1877
20bd2a09 1878 ah->caldata = caldata;
fcb9a3de 1879 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1880 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1881 /* Operating channel changed, reset channel calibration data */
1882 memset(caldata, 0, sizeof(*caldata));
1883 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1884 } else if (caldata) {
4b9b42bf 1885 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1886 }
5bc225ac 1887 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1888
caed6579
SM		 1889 if (fastcc) {
1890 r = ath9k_hw_do_fastcc(ah, chan);
1891 if (!r)
1892 return r;
f078f209
LR		 1893 }
1894
5955b2b0 1895 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1896 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1897
f078f209
LR		 1898 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1899 if (saveDefAntenna == 0)
1900 saveDefAntenna = 1;
1901
1902 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1903
46fe782c 1904 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1905 if (AR_SREV_9100(ah) ||
1906 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1907 tsf = ath9k_hw_gettsf64(ah);
1908
f078f209
LR		 1909 saveLedState = REG_READ(ah, AR_CFG_LED) &
1910 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1911 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1912
1913 ath9k_hw_mark_phy_inactive(ah);
1914
45ef6a0b
VT		 1915 ah->paprd_table_write_done = false;
1916
05020d23 1917 /* Only required on the first reset */
d7e7d229
LR		 1918 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1919 REG_WRITE(ah,
1920 AR9271_RESET_POWER_DOWN_CONTROL,
1921 AR9271_RADIO_RF_RST);
1922 udelay(50);
1923 }
1924
f078f209 1925 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1926 ath_err(common, "Chip reset failed\n");
ae8d2858 1927 return -EINVAL;
f078f209
LR		 1928 }
1929
05020d23 1930 /* Only required on the first reset */
d7e7d229
LR		 1931 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1932 ah->htc_reset_init = false;
1933 REG_WRITE(ah,
1934 AR9271_RESET_POWER_DOWN_CONTROL,
1935 AR9271_GATE_MAC_CTL);
1936 udelay(50);
1937 }
1938
46fe782c 1939 /* Restore TSF */
f860d526 1940 if (tsf)
46fe782c
S		 1941 ath9k_hw_settsf64(ah, tsf);
1942
7a37081e 1943 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1944 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1945
e9141f71
S		 1946 if (!AR_SREV_9300_20_OR_LATER(ah))
1947 ar9002_hw_enable_async_fifo(ah);
1948
25c56eec 1949 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1950 if (r)
1951 return r;
f078f209 1952
5955b2b0 1953 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1954 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1955
f860d526
FF		 1956 /*
1957 * Some AR91xx SoC devices frequently fail to accept TSF writes
1958 * right after the chip reset. When that happens, write a new
1959 * value after the initvals have been applied, with an offset
1960 * based on measured time difference
1961 */
1962 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1963 tsf += 1500;
1964 ath9k_hw_settsf64(ah, tsf);
1965 }
1966
15d2b585 1967 ath9k_hw_init_mfp(ah);
0ced0e17 1968
81c507a8 1969 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1970 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1971 ah->eep_ops->set_board_values(ah, chan);
a7765828 1972
15d2b585 1973 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1974
8fe65368 1975 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1976 if (r)
1977 return r;
f078f209 1978
dfdac8ac
FF		 1979 ath9k_hw_set_clockrate(ah);
1980
15d2b585 1981 ath9k_hw_init_queues(ah);
2660b81a 1982 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1983 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1984 ath9k_hw_init_qos(ah);
1985
2660b81a 1986 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1987 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1988
0005baf4 1989 ath9k_hw_init_global_settings(ah);
f078f209 1990
fe2b6afb
FF		 1991 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1992 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1993 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1994 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1995 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1996 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1997 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1998 }
1999
ca7a4deb 2000 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 2001
2002 ath9k_hw_set_dma(ah);
2003
ed6ebd8b
RM		 2004 if (!ath9k_hw_mci_is_enabled(ah))
2005 REG_WRITE(ah, AR_OBS, 8);
f078f209 2006
0ce024cb 2007 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 2008 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2009 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2010 }
2011
7f62a136
VT		 2012 if (ah->config.tx_intr_mitigation) {
2013 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2014 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2015 }
2016
f078f209
LR		 2017 ath9k_hw_init_bb(ah, chan);
2018
77a5a664 2019 if (caldata) {
4b9b42bf
SM		 2020 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2021 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 2022 }
ae8d2858 2023 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2024 return -EIO;
f078f209 2025
5955b2b0 2026 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 2027 return -EIO;
63d32967 2028
7d0d0df0 2029 ENABLE_REGWRITE_BUFFER(ah);
f078f209 2030
8fe65368 2031 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 2032 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2033
7d0d0df0 2034 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2035
15d2b585 2036 ath9k_hw_init_desc(ah);
f078f209 2037
dbccdd1d 2038 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2039 ath9k_hw_btcoex_enable(ah);
2040
5955b2b0 2041 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2042 ar9003_mci_check_bt(ah);
63d32967 2043
1fe860ed
RM		 2044 ath9k_hw_loadnf(ah, chan);
2045 ath9k_hw_start_nfcal(ah, true);
2046
51ac8cbb 2047 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 2048 ar9003_hw_bb_watchdog_config(ah);
51ac8cbb
RM		 2049 ar9003_hw_disable_phy_restart(ah);
2050 }
2051
691680b8
FF		 2052 ath9k_hw_apply_gpio_override(ah);
2053
7bdea96a 2054 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 2055 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2056
ae8d2858 2057 return 0;
f078f209 2058}
7322fd19 2059EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2060
f1dc5600
S		 2061/******************************/
2062/* Power Management (Chipset) */
2063/******************************/
2064
42d5bc3f
LR		 2065/*
2066 * Notify Power Mgt is disabled in self-generated frames.
2067 * If requested, force chip to sleep.
2068 */
31604cf0 2069static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2070{
f1dc5600 2071 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2072
a4a2954f 2073 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2074 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2075 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2076 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2077 /* xxx Required for WLAN only case ? */
2078 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2079 udelay(100);
2080 }
2577c6e8 2081
31604cf0
SM		 2082 /*
2083 * Clear the RTC force wake bit to allow the
2084 * mac to go to sleep.
2085 */
2086 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2087
153dccd4 2088 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2089 udelay(100);
2577c6e8 2090
31604cf0
SM		 2091 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2092 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2093
31604cf0
SM		 2094 /* Shutdown chip. Active low */
2095 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2096 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2097 udelay(2);
f1dc5600 2098 }
9a658d2b
LR		 2099
2100 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2101 if (AR_SREV_9300_20_OR_LATER(ah))
2102 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2103}
2104
bbd79af5
LR		 2105/*
2106 * Notify Power Management is enabled in self-generating
2107 * frames. If request, set power mode of chip to
2108 * auto/normal. Duration in units of 128us (1/8 TU).
2109 */
31604cf0 2110static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2111{
31604cf0 2112 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2113
f1dc5600 2114 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2115
31604cf0
SM		 2116 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2117 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2118 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2119 AR_RTC_FORCE_WAKE_ON_INT);
2120 } else {
2577c6e8 2121
31604cf0
SM		 2122 /* When chip goes into network sleep, it could be waken
2123 * up by MCI_INT interrupt caused by BT's HW messages
2124 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2125 * rate (~100us). This will cause chip to leave and
2126 * re-enter network sleep mode frequently, which in
2127 * consequence will have WLAN MCI HW to generate lots of
2128 * SYS_WAKING and SYS_SLEEPING messages which will make
2129 * BT CPU to busy to process.
2130 */
153dccd4
RM		 2131 if (ath9k_hw_mci_is_enabled(ah))
2132 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2133 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2134 /*
2135 * Clear the RTC force wake bit to allow the
2136 * mac to go to sleep.
2137 */
153dccd4 2138 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2139
153dccd4 2140 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2141 udelay(30);
f078f209 2142 }
9a658d2b
LR		 2143
2144 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2145 if (AR_SREV_9300_20_OR_LATER(ah))
2146 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2147}
2148
31604cf0 2149static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2150{
f1dc5600
S		 2151 u32 val;
2152 int i;
f078f209 2153
9a658d2b
LR		 2154 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2155 if (AR_SREV_9300_20_OR_LATER(ah)) {
2156 REG_WRITE(ah, AR_WA, ah->WARegVal);
2157 udelay(10);
2158 }
2159
31604cf0
SM		 2160 if ((REG_READ(ah, AR_RTC_STATUS) &
2161 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2162 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2163 return false;
f1dc5600 2164 }
31604cf0
SM		 2165 if (!AR_SREV_9300_20_OR_LATER(ah))
2166 ath9k_hw_init_pll(ah, NULL);
2167 }
2168 if (AR_SREV_9100(ah))
2169 REG_SET_BIT(ah, AR_RTC_RESET,
2170 AR_RTC_RESET_EN);
2171
2172 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2173 AR_RTC_FORCE_WAKE_EN);
2174 udelay(50);
f078f209 2175
31604cf0
SM		 2176 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2177 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2178 if (val == AR_RTC_STATUS_ON)
2179 break;
2180 udelay(50);
f1dc5600
S		 2181 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2182 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2183 }
2184 if (i == 0) {
2185 ath_err(ath9k_hw_common(ah),
2186 "Failed to wakeup in %uus\n",
2187 POWER_UP_TIME / 20);
2188 return false;
f078f209
LR		 2189 }
2190
cdbe408d
RM		 2191 if (ath9k_hw_mci_is_enabled(ah))
2192 ar9003_mci_set_power_awake(ah);
2193
f1dc5600 2194 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2195
f1dc5600 2196 return true;
f078f209
LR		 2197}
2198
9ecdef4b 2199bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2200{
c46917bb 2201 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2202 int status = true;
f1dc5600
S		 2203 static const char *modes[] = {
2204 "AWAKE",
2205 "FULL-SLEEP",
2206 "NETWORK SLEEP",
2207 "UNDEFINED"
2208 };
f1dc5600 2209
cbdec975
GJ		 2210 if (ah->power_mode == mode)
2211 return status;
2212
d2182b69 2213 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2214 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2215
2216 switch (mode) {
2217 case ATH9K_PM_AWAKE:
31604cf0 2218 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2219 break;
2220 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2221 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2222 ar9003_mci_set_full_sleep(ah);
1010911e 2223
31604cf0 2224 ath9k_set_power_sleep(ah);
2660b81a 2225 ah->chip_fullsleep = true;
f1dc5600
S		 2226 break;
2227 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2228 ath9k_set_power_network_sleep(ah);
f1dc5600 2229 break;
f078f209 2230 default:
3800276a 2231 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2232 return false;
2233 }
2660b81a 2234 ah->power_mode = mode;
f1dc5600 2235
69f4aab1
LR		 2236 /*
2237 * XXX: If this warning never comes up after a while then
2238 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2239 * ath9k_hw_setpower() return type void.
2240 */
97dcec57
SM		 2241
2242 if (!(ah->ah_flags & AH_UNPLUGGED))
2243 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2244
f1dc5600 2245 return status;
f078f209 2246}
7322fd19 2247EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2248
f1dc5600
S		 2249/*******************/
2250/* Beacon Handling */
2251/*******************/
2252
cbe61d8a 2253void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2254{
f078f209
LR		 2255 int flags = 0;
2256
7d0d0df0
S		 2257 ENABLE_REGWRITE_BUFFER(ah);
2258
2660b81a 2259 switch (ah->opmode) {
d97809db 2260 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2261 REG_SET_BIT(ah, AR_TXCFG,
2262 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 2263 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2264 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 2265 flags |= AR_NDP_TIMER_EN;
2664d666 2266 case NL80211_IFTYPE_MESH_POINT:
d97809db 2267 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2268 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2269 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2270 TU_TO_USEC(ah->config.dma_beacon_response_time));
2271 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2272 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2273 flags |=
2274 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2275 break;
d97809db 2276 default:
d2182b69
JP		 2277 ath_dbg(ath9k_hw_common(ah), BEACON,
2278 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2279 return;
2280 break;
f078f209
LR		 2281 }
2282
dd347f2f
FF		 2283 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2284 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2285 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2286 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 2287
7d0d0df0 2288 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2289
f078f209
LR		 2290 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2291}
7322fd19 2292EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2293
cbe61d8a 2294void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2295 const struct ath9k_beacon_state *bs)
f078f209
LR		 2296{
2297 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2298 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2299 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2300
7d0d0df0
S		 2301 ENABLE_REGWRITE_BUFFER(ah);
2302
f078f209
LR		 2303 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2304
2305 REG_WRITE(ah, AR_BEACON_PERIOD,
f29f5c08 2306 TU_TO_USEC(bs->bs_intval));
f078f209 2307 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
f29f5c08 2308 TU_TO_USEC(bs->bs_intval));
f078f209 2309
7d0d0df0 2310 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2311
f078f209
LR		 2312 REG_RMW_FIELD(ah, AR_RSSI_THR,
2313 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2314
f29f5c08 2315 beaconintval = bs->bs_intval;
f078f209
LR		 2316
2317 if (bs->bs_sleepduration > beaconintval)
2318 beaconintval = bs->bs_sleepduration;
2319
2320 dtimperiod = bs->bs_dtimperiod;
2321 if (bs->bs_sleepduration > dtimperiod)
2322 dtimperiod = bs->bs_sleepduration;
2323
2324 if (beaconintval == dtimperiod)
2325 nextTbtt = bs->bs_nextdtim;
2326 else
2327 nextTbtt = bs->bs_nexttbtt;
2328
d2182b69
JP		 2329 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2330 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2331 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2332 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2333
7d0d0df0
S		 2334 ENABLE_REGWRITE_BUFFER(ah);
2335
f1dc5600
S		 2336 REG_WRITE(ah, AR_NEXT_DTIM,
2337 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2338 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2339
f1dc5600
S		 2340 REG_WRITE(ah, AR_SLEEP1,
2341 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2342 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2343
f1dc5600
S		 2344 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2345 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2346 else
2347 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2348
f1dc5600
S		 2349 REG_WRITE(ah, AR_SLEEP2,
2350 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2351
f1dc5600
S		 2352 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2353 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2354
7d0d0df0 2355 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2356
f1dc5600
S		 2357 REG_SET_BIT(ah, AR_TIMER_MODE,
2358 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2359 AR_DTIM_TIMER_EN);
f078f209 2360
4af9cf4f
S		 2361 /* TSF Out of Range Threshold */
2362 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2363}
7322fd19 2364EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2365
f1dc5600
S		 2366/*******************/
2367/* HW Capabilities */
2368/*******************/
2369
6054069a
FF		 2370static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2371{
2372 eeprom_chainmask &= chip_chainmask;
2373 if (eeprom_chainmask)
2374 return eeprom_chainmask;
2375 else
2376 return chip_chainmask;
2377}
2378
9a66af33
ZK		 2379/**
2380 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2381 * @ah: the atheros hardware data structure
2382 *
2383 * We enable DFS support upstream on chipsets which have passed a series
2384 * of tests. The testing requirements are going to be documented. Desired
2385 * test requirements are documented at:
2386 *
2387 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2388 *
2389 * Once a new chipset gets properly tested an individual commit can be used
2390 * to document the testing for DFS for that chipset.
2391 */
2392static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2393{
2394
2395 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2396 /* for temporary testing DFS with 9280 */
2397 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2398 /* AR9580 will likely be our first target to get testing on */
2399 case AR_SREV_VERSION_9580:
73e4937d 2400 return true;
9a66af33
ZK		 2401 default:
2402 return false;
2403 }
2404}
2405
a9a29ce6 2406int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2407{
2660b81a 2408 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2410 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2411 unsigned int chip_chainmask;
608b88cb 2412
0ff2b5c0 2413 u16 eeval;
47c80de6 2414 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2415
f74df6fb 2416 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2417 regulatory->current_rd = eeval;
f078f209 2418
2660b81a 2419 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2420 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2421 if (regulatory->current_rd == 0x64 ||
2422 regulatory->current_rd == 0x65)
2423 regulatory->current_rd += 5;
2424 else if (regulatory->current_rd == 0x41)
2425 regulatory->current_rd = 0x43;
d2182b69
JP		 2426 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2427 regulatory->current_rd);
f1dc5600 2428 }
f078f209 2429
f74df6fb 2430 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2431 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2432 ath_err(common,
2433 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2434 return -EINVAL;
2435 }
2436
d4659912
FF		 2437 if (eeval & AR5416_OPFLAGS_11A)
2438 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2439
d4659912
FF		 2440 if (eeval & AR5416_OPFLAGS_11G)
2441 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2442
e41db61d
SM		 2443 if (AR_SREV_9485(ah) ||
2444 AR_SREV_9285(ah) ||
2445 AR_SREV_9330(ah) ||
2446 AR_SREV_9565(ah))
6054069a 2447 chip_chainmask = 1;
ba5736a5
MSS		 2448 else if (AR_SREV_9462(ah))
2449 chip_chainmask = 3;
6054069a
FF		 2450 else if (!AR_SREV_9280_20_OR_LATER(ah))
2451 chip_chainmask = 7;
2452 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2453 chip_chainmask = 3;
2454 else
2455 chip_chainmask = 7;
2456
f74df6fb 2457 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2458 /*
2459 * For AR9271 we will temporarilly uses the rx chainmax as read from
2460 * the EEPROM.
2461 */
8147f5de 2462 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2463 !(eeval & AR5416_OPFLAGS_11A) &&
2464 !(AR_SREV_9271(ah)))
2465 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2466 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2467 else if (AR_SREV_9100(ah))
2468 pCap->rx_chainmask = 0x7;
8147f5de 2469 else
d7e7d229 2470 /* Use rx_chainmask from EEPROM. */
8147f5de 2471 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2472
6054069a
FF		 2473 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2474 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2475 ah->txchainmask = pCap->tx_chainmask;
2476 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2477
7a37081e 2478 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2479
02d2ebb2
FF		 2480 /* enable key search for every frame in an aggregate */
2481 if (AR_SREV_9300_20_OR_LATER(ah))
2482 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2483
ce2220d1
BR		 2484 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2485
0db156e9 2486 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2487 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2488 else
2489 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2490
5b5fa355
S		 2491 if (AR_SREV_9271(ah))
2492 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2493 else if (AR_DEVID_7010(ah))
2494 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2495 else if (AR_SREV_9300_20_OR_LATER(ah))
2496 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2497 else if (AR_SREV_9287_11_OR_LATER(ah))
2498 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2499 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2500 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2501 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2502 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2503 else
2504 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2505
1b2538b2 2506 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2507 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2508 else
f1dc5600 2509 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2510
74e13060 2511#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2512 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2513 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2514 ah->rfkill_gpio =
2515 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2516 ah->rfkill_polarity =
2517 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2518
2519 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2520 }
f1dc5600 2521#endif
d5d1154f 2522 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2523 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2524 else
2525 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2526
e7594072 2527 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2528 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2529 else
2530 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2531
ceb26445 2532 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2533 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2534 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2535 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2536
ceb26445
VT		 2537 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2538 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2539 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2540 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2541 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2542 } else {
2543 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2544 if (AR_SREV_9280_20(ah))
6b42e8d0 2545 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2546 }
1adf02ff 2547
6c84ce08
VT		 2548 if (AR_SREV_9300_20_OR_LATER(ah))
2549 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2550
6ee63f55
SB		 2551 if (AR_SREV_9300_20_OR_LATER(ah))
2552 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2553
a42acef0 2554 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2555 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2556
f85c3371 2557 if (AR_SREV_9285(ah)) {
754dc536
VT		 2558 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2559 ant_div_ctl1 =
2560 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2561 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2562 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2563 ath_info(common, "Enable LNA combining\n");
2564 }
754dc536 2565 }
f85c3371
SM		 2566 }
2567
ea066d5a
MSS		 2568 if (AR_SREV_9300_20_OR_LATER(ah)) {
2569 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2570 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2571 }
2572
06236e53 2573 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2574 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2575 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2576 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2577 ath_info(common, "Enable LNA combining\n");
2578 }
21d2c63a 2579 }
754dc536 2580
9a66af33
ZK		 2581 if (ath9k_hw_dfs_tested(ah))
2582 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2583
47c80de6
VT		 2584 tx_chainmask = pCap->tx_chainmask;
2585 rx_chainmask = pCap->rx_chainmask;
2586 while (tx_chainmask || rx_chainmask) {
2587 if (tx_chainmask & BIT(0))
2588 pCap->max_txchains++;
2589 if (rx_chainmask & BIT(0))
2590 pCap->max_rxchains++;
2591
2592 tx_chainmask >>= 1;
2593 rx_chainmask >>= 1;
2594 }
2595
a4a2954f 2596 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2597 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2598 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2599
2b5e54e2 2600 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2601 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2602 }
2603
846e438f
SM		 2604 if (AR_SREV_9462(ah))
2605 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2606
0f21ee8d
SM		 2607 if (AR_SREV_9300_20_OR_LATER(ah) &&
2608 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2609 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2610
81dc75b5
SM		 2611 /*
2612 * Fast channel change across bands is available
2613 * only for AR9462 and AR9565.
2614 */
2615 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2616 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
2617
a9a29ce6 2618 return 0;
f078f209
LR		 2619}
2620
f1dc5600
S		 2621/****************************/
2622/* GPIO / RFKILL / Antennae */
2623/****************************/
f078f209 2624
cbe61d8a 2625static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2626 u32 gpio, u32 type)
2627{
2628 int addr;
2629 u32 gpio_shift, tmp;
f078f209 2630
f1dc5600
S		 2631 if (gpio > 11)
2632 addr = AR_GPIO_OUTPUT_MUX3;
2633 else if (gpio > 5)
2634 addr = AR_GPIO_OUTPUT_MUX2;
2635 else
2636 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2637
f1dc5600 2638 gpio_shift = (gpio % 6) * 5;
f078f209 2639
f1dc5600
S		 2640 if (AR_SREV_9280_20_OR_LATER(ah)
2641 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2642 REG_RMW(ah, addr, (type << gpio_shift),
2643 (0x1f << gpio_shift));
f078f209 2644 } else {
f1dc5600
S		 2645 tmp = REG_READ(ah, addr);
2646 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2647 tmp &= ~(0x1f << gpio_shift);
2648 tmp |= (type << gpio_shift);
2649 REG_WRITE(ah, addr, tmp);
f078f209 2650 }
f078f209
LR		 2651}
2652
cbe61d8a 2653void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2654{
f1dc5600 2655 u32 gpio_shift;
f078f209 2656
9680e8a3 2657 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2658
88c1f4f6
S		 2659 if (AR_DEVID_7010(ah)) {
2660 gpio_shift = gpio;
2661 REG_RMW(ah, AR7010_GPIO_OE,
2662 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2663 (AR7010_GPIO_OE_MASK << gpio_shift));
2664 return;
2665 }
f078f209 2666
88c1f4f6 2667 gpio_shift = gpio << 1;
f1dc5600
S		 2668 REG_RMW(ah,
2669 AR_GPIO_OE_OUT,
2670 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2671 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2672}
7322fd19 2673EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2674
cbe61d8a 2675u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2676{
cb33c412
SB		 2677#define MS_REG_READ(x, y) \
2678 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2679
2660b81a 2680 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2681 return 0xffffffff;
f078f209 2682
88c1f4f6
S		 2683 if (AR_DEVID_7010(ah)) {
2684 u32 val;
2685 val = REG_READ(ah, AR7010_GPIO_IN);
2686 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2687 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2688 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2689 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2690 else if (AR_SREV_9271(ah))
5b5fa355 2691 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2692 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2693 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2694 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2695 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2696 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2697 return MS_REG_READ(AR928X, gpio) != 0;
2698 else
2699 return MS_REG_READ(AR, gpio) != 0;
f078f209 2700}
7322fd19 2701EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2702
cbe61d8a 2703void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2704 u32 ah_signal_type)
f078f209 2705{
f1dc5600 2706 u32 gpio_shift;
f078f209 2707
88c1f4f6
S		 2708 if (AR_DEVID_7010(ah)) {
2709 gpio_shift = gpio;
2710 REG_RMW(ah, AR7010_GPIO_OE,
2711 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2712 (AR7010_GPIO_OE_MASK << gpio_shift));
2713 return;
2714 }
f078f209 2715
88c1f4f6 2716 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2717 gpio_shift = 2 * gpio;
f1dc5600
S		 2718 REG_RMW(ah,
2719 AR_GPIO_OE_OUT,
2720 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2721 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2722}
7322fd19 2723EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2724
cbe61d8a 2725void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2726{
88c1f4f6
S		 2727 if (AR_DEVID_7010(ah)) {
2728 val = val ? 0 : 1;
2729 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2730 AR_GPIO_BIT(gpio));
2731 return;
2732 }
2733
5b5fa355
S		 2734 if (AR_SREV_9271(ah))
2735 val = ~val;
2736
f1dc5600
S		 2737 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2738 AR_GPIO_BIT(gpio));
f078f209 2739}
7322fd19 2740EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2741
cbe61d8a 2742void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2743{
f1dc5600 2744 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2745}
7322fd19 2746EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2747
f1dc5600
S		 2748/*********************/
2749/* General Operation */
2750/*********************/
2751
cbe61d8a 2752u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2753{
f1dc5600
S		 2754 u32 bits = REG_READ(ah, AR_RX_FILTER);
2755 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2756
f1dc5600
S		 2757 if (phybits & AR_PHY_ERR_RADAR)
2758 bits |= ATH9K_RX_FILTER_PHYRADAR;
2759 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2760 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2761
f1dc5600 2762 return bits;
f078f209 2763}
7322fd19 2764EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2765
cbe61d8a 2766void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2767{
f1dc5600 2768 u32 phybits;
f078f209 2769
7d0d0df0
S		 2770 ENABLE_REGWRITE_BUFFER(ah);
2771
a4a2954f 2772 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2773 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2774
7ea310be
S		 2775 REG_WRITE(ah, AR_RX_FILTER, bits);
2776
f1dc5600
S		 2777 phybits = 0;
2778 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2779 phybits |= AR_PHY_ERR_RADAR;
2780 if (bits & ATH9K_RX_FILTER_PHYERR)
2781 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2782 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2783
f1dc5600 2784 if (phybits)
ca7a4deb 2785 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2786 else
ca7a4deb 2787 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2788
2789 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2790}
7322fd19 2791EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2792
cbe61d8a 2793bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2794{
99922a45
RM		 2795 if (ath9k_hw_mci_is_enabled(ah))
2796 ar9003_mci_bt_gain_ctrl(ah);
2797
63a75b91
SB		 2798 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2799 return false;
2800
2801 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2802 ah->htc_reset_init = true;
63a75b91 2803 return true;
f1dc5600 2804}
7322fd19 2805EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2806
cbe61d8a 2807bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2808{
9ecdef4b 2809 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2810 return false;
f078f209 2811
63a75b91
SB		 2812 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2813 return false;
2814
2815 ath9k_hw_init_pll(ah, NULL);
2816 return true;
f078f209 2817}
7322fd19 2818EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2819
ca2c68cc
FF		 2820static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2821{
2822 enum eeprom_param gain_param;
2823
2824 if (IS_CHAN_2GHZ(chan))
2825 gain_param = EEP_ANTENNA_GAIN_2G;
2826 else
2827 gain_param = EEP_ANTENNA_GAIN_5G;
2828
2829 return ah->eep_ops->get_eeprom(ah, gain_param);
2830}
2831
64ea57d0
GJ		 2832void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2833 bool test)
ca2c68cc
FF		 2834{
2835 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2836 struct ieee80211_channel *channel;
2837 int chan_pwr, new_pwr, max_gain;
2838 int ant_gain, ant_reduction = 0;
2839
2840 if (!chan)
2841 return;
2842
2843 channel = chan->chan;
2844 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2845 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2846 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2847
2848 ant_gain = get_antenna_gain(ah, chan);
2849 if (ant_gain > max_gain)
2850 ant_reduction = ant_gain - max_gain;
2851
2852 ah->eep_ops->set_txpower(ah, chan,
2853 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2854 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2855}
2856
de40f316 2857void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2858{
ca2c68cc 2859 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2860 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2861 struct ieee80211_channel *channel = chan->chan;
9c204b46 2862
48ef5c42 2863 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2864 if (test)
ca2c68cc 2865 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2866
64ea57d0 2867 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2868
ca2c68cc
FF		 2869 if (test)
2870 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2871}
7322fd19 2872EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2873
cbe61d8a 2874void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2875{
2660b81a 2876 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2877}
7322fd19 2878EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2879
cbe61d8a 2880void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2881{
f1dc5600
S		 2882 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2883 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2884}
7322fd19 2885EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2886
f2b2143e 2887void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2888{
1510718d
LR		 2889 struct ath_common *common = ath9k_hw_common(ah);
2890
2891 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2892 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2893 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2894}
7322fd19 2895EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2896
1c0fc65e
BP		 2897#define ATH9K_MAX_TSF_READ 10
2898
cbe61d8a 2899u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2900{
1c0fc65e
BP		 2901 u32 tsf_lower, tsf_upper1, tsf_upper2;
2902 int i;
2903
2904 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2905 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2906 tsf_lower = REG_READ(ah, AR_TSF_L32);
2907 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2908 if (tsf_upper2 == tsf_upper1)
2909 break;
2910 tsf_upper1 = tsf_upper2;
2911 }
f078f209 2912
1c0fc65e 2913 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2914
1c0fc65e 2915 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2916}
7322fd19 2917EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2918
cbe61d8a 2919void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2920{
27abe060 2921 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2922 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2923}
7322fd19 2924EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2925
cbe61d8a 2926void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2927{
f9b604f6
GJ		 2928 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2929 AH_TSF_WRITE_TIMEOUT))
d2182b69 2930 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2931 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2932
f1dc5600
S		 2933 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2934}
7322fd19 2935EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2936
60ca9f87 2937void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2938{
60ca9f87 2939 if (set)
2660b81a 2940 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2941 else
2660b81a 2942 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2943}
7322fd19 2944EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2945
e4744ec7 2946void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2947{
2948 u32 macmode;
2949
e4744ec7 2950 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2951 macmode = AR_2040_JOINED_RX_CLEAR;
2952 else
2953 macmode = 0;
f078f209 2954
f1dc5600 2955 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2956}
ff155a45
VT		 2957
2958/* HW Generic timers configuration */
2959
2960static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2961{
2962 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2963 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2964 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2965 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2966 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2967 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2968 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2969 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2970 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2971 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2972 AR_NDP2_TIMER_MODE, 0x0002},
2973 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2974 AR_NDP2_TIMER_MODE, 0x0004},
2975 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2976 AR_NDP2_TIMER_MODE, 0x0008},
2977 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2978 AR_NDP2_TIMER_MODE, 0x0010},
2979 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2980 AR_NDP2_TIMER_MODE, 0x0020},
2981 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2982 AR_NDP2_TIMER_MODE, 0x0040},
2983 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2984 AR_NDP2_TIMER_MODE, 0x0080}
2985};
2986
2987/* HW generic timer primitives */
2988
2989/* compute and clear index of rightmost 1 */
2990static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2991{
2992 u32 b;
2993
2994 b = *mask;
2995 b &= (0-b);
2996 *mask &= ~b;
2997 b *= debruijn32;
2998 b >>= 27;
2999
3000 return timer_table->gen_timer_index[b];
3001}
3002
dd347f2f 3003u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 3004{
3005 return REG_READ(ah, AR_TSF_L32);
3006}
dd347f2f 3007EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 3008
3009struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3010 void (*trigger)(void *),
3011 void (*overflow)(void *),
3012 void *arg,
3013 u8 timer_index)
3014{
3015 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3016 struct ath_gen_timer *timer;
3017
3018 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 3019 if (timer == NULL)
ff155a45 3020 return NULL;
ff155a45
VT		 3021
3022 /* allocate a hardware generic timer slot */
3023 timer_table->timers[timer_index] = timer;
3024 timer->index = timer_index;
3025 timer->trigger = trigger;
3026 timer->overflow = overflow;
3027 timer->arg = arg;
3028
3029 return timer;
3030}
7322fd19 3031EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3032
cd9bf689
LR		 3033void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3034 struct ath_gen_timer *timer,
788f6875 3035 u32 trig_timeout,
cd9bf689 3036 u32 timer_period)
ff155a45
VT		 3037{
3038 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
788f6875 3039 u32 tsf, timer_next;
ff155a45
VT		 3040
3041 BUG_ON(!timer_period);
3042
3043 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3044
3045 tsf = ath9k_hw_gettsf32(ah);
3046
788f6875
VT		 3047 timer_next = tsf + trig_timeout;
3048
14335310 3049 ath_dbg(ath9k_hw_common(ah), BTCOEX,
226afe68
JP		 3050 "current tsf %x period %x timer_next %x\n",
3051 tsf, timer_period, timer_next);
ff155a45 3052
ff155a45
VT		 3053 /*
3054 * Program generic timer registers
3055 */
3056 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3057 timer_next);
3058 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3059 timer_period);
3060 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3061 gen_tmr_configuration[timer->index].mode_mask);
3062
a4a2954f 3063 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3064 /*
423e38e8 3065 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3066 * to use. But we still follow the old rule, 0 - 7 use tsf and
3067 * 8 - 15 use tsf2.
3068 */
3069 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3070 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3071 (1 << timer->index));
3072 else
3073 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3074 (1 << timer->index));
3075 }
3076
ff155a45
VT		 3077 /* Enable both trigger and thresh interrupt masks */
3078 REG_SET_BIT(ah, AR_IMR_S5,
3079 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3080 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3081}
7322fd19 3082EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3083
cd9bf689 3084void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3085{
3086 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3087
3088 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3089 (timer->index >= ATH_MAX_GEN_TIMER)) {
3090 return;
3091 }
3092
3093 /* Clear generic timer enable bits. */
3094 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3095 gen_tmr_configuration[timer->index].mode_mask);
3096
b7f59766
SM		 3097 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3098 /*
3099 * Need to switch back to TSF if it was using TSF2.
3100 */
3101 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3102 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3103 (1 << timer->index));
3104 }
3105 }
3106
ff155a45
VT		 3107 /* Disable both trigger and thresh interrupt masks */
3108 REG_CLR_BIT(ah, AR_IMR_S5,
3109 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3110 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3111
3112 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3113}
7322fd19 3114EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3115
3116void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3117{
3118 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3119
3120 /* free the hardware generic timer slot */
3121 timer_table->timers[timer->index] = NULL;
3122 kfree(timer);
3123}
7322fd19 3124EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3125
3126/*
3127 * Generic Timer Interrupts handling
3128 */
3129void ath_gen_timer_isr(struct ath_hw *ah)
3130{
3131 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3132 struct ath_gen_timer *timer;
c46917bb 3133 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3134 u32 trigger_mask, thresh_mask, index;
3135
3136 /* get hardware generic timer interrupt status */
3137 trigger_mask = ah->intr_gen_timer_trigger;
3138 thresh_mask = ah->intr_gen_timer_thresh;
3139 trigger_mask &= timer_table->timer_mask.val;
3140 thresh_mask &= timer_table->timer_mask.val;
3141
3142 trigger_mask &= ~thresh_mask;
3143
3144 while (thresh_mask) {
3145 index = rightmost_index(timer_table, &thresh_mask);
3146 timer = timer_table->timers[index];
3147 BUG_ON(!timer);
14335310 3148 ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
d2182b69 3149 index);
ff155a45
VT		 3150 timer->overflow(timer->arg);
3151 }
3152
3153 while (trigger_mask) {
3154 index = rightmost_index(timer_table, &trigger_mask);
3155 timer = timer_table->timers[index];
3156 BUG_ON(!timer);
14335310 3157 ath_dbg(common, BTCOEX,
226afe68 3158 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3159 timer->trigger(timer->arg);
3160 }
3161}
7322fd19 3162EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3163
05020d23
S		 3164/********/
3165/* HTC */
3166/********/
3167
2da4f01a
LR		 3168static struct {
3169 u32 version;
3170 const char * name;
3171} ath_mac_bb_names[] = {
3172 /* Devices with external radios */
3173 { AR_SREV_VERSION_5416_PCI, "5416" },
3174 { AR_SREV_VERSION_5416_PCIE, "5418" },
3175 { AR_SREV_VERSION_9100, "9100" },
3176 { AR_SREV_VERSION_9160, "9160" },
3177 /* Single-chip solutions */
3178 { AR_SREV_VERSION_9280, "9280" },
3179 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3180 { AR_SREV_VERSION_9287, "9287" },
3181 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3182 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3183 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3184 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3185 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3186 { AR_SREV_VERSION_9462, "9462" },
485124cb 3187 { AR_SREV_VERSION_9550, "9550" },
77fac465 3188 { AR_SREV_VERSION_9565, "9565" },
2da4f01a
LR		 3189};
3190
3191/* For devices with external radios */
3192static struct {
3193 u16 version;
3194 const char * name;
3195} ath_rf_names[] = {
3196 { 0, "5133" },
3197 { AR_RAD5133_SREV_MAJOR, "5133" },
3198 { AR_RAD5122_SREV_MAJOR, "5122" },
3199 { AR_RAD2133_SREV_MAJOR, "2133" },
3200 { AR_RAD2122_SREV_MAJOR, "2122" }
3201};
3202
3203/*
3204 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3205 */
f934c4d9 3206static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3207{
3208 int i;
3209
3210 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3211 if (ath_mac_bb_names[i].version == mac_bb_version) {
3212 return ath_mac_bb_names[i].name;
3213 }
3214 }
3215
3216 return "????";
3217}
2da4f01a
LR		 3218
3219/*
3220 * Return the RF name. "????" is returned if the RF is unknown.
3221 * Used for devices with external radios.
3222 */
f934c4d9 3223static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3224{
3225 int i;
3226
3227 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3228 if (ath_rf_names[i].version == rf_version) {
3229 return ath_rf_names[i].name;
3230 }
3231 }
3232
3233 return "????";
3234}
f934c4d9
LR		 3235
3236void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3237{
3238 int used;
3239
3240 /* chipsets >= AR9280 are single-chip */
7a37081e 3241 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3242 used = scnprintf(hw_name, len,
3243 "Atheros AR%s Rev:%x",
3244 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3245 ah->hw_version.macRev);
f934c4d9
LR		 3246 }
3247 else {
5e88ba62
ZK		 3248 used = scnprintf(hw_name, len,
3249 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3250 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3251 ah->hw_version.macRev,
3252 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3253 & AR_RADIO_SREV_MAJOR)),
3254 ah->hw_version.phyRev);
f934c4d9
LR		 3255 }
3256
3257 hw_name[used] = '\0';
3258}
3259EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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